CY2412 MPEG Clock Generator with VCXO Features Benefits • Integrated phase-locked loop (PLL) • Highest-performance PLL tailored for multimedia applications • Low-jitter, high-accuracy outputs • Meets critical timing requirements in complex system designs • VCXO with analog adjust • 3.3V operation • Large ± 150-ppm range, better linearity • 8-pin SOIC package • Enables application compatibility Part Number Outputs Input Frequency Range Output Frequencies CY2412-1 3 13.5-MHz pullable crystal input per Cypress specification Two 27 MHz outputs, one 54 MHz (3.3V) Linear CY2412-3 3 13.5-MHz pullable crystal input per Cypress specification 27 MHz, 13.5 MHz, 54 MHz (3.3V) Logic Block Diagram VCXO Profile Pin Configuration CY2412-1,-3 8-pin SOIC CLKC 13.5 XIN XOUT OSC Q Φ OUTPUT DIVIDERS VCO CLKB CLKA P VCXO Linear PLL VDD Cypress Semiconductor Corporation Document #: 38-07227 Rev. *D • XIN 1 8 XOUT VDD VCXO 2 7 3 6 CLKC CLKB VSS 4 5 CLKA VSS 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised December 13, 2004 CY2412 Pin Summary Pin Name Pin Number Pin Description XIN 1 Reference Crystal Input VDD 2 Voltage Supply VCXO 3 Input Analog Control for VCXO VSS 4 Ground CLKA 5 54-MHz clock output CLKB 6 13.5-MHz clock output CLKC 7 27-MHz clock output XOUT[2] 8 Reference Crystal Output Pullable Crystal Specifications[1] Parameter Description Condition Min. Typ. – 13.5 – – Max. Unit FNOM Nominal crystal frequency CLNOM Nominal load capacitance R1 Equivalent series resistance (ESR) R3/R1 Ratio of third overtone mode ESR to funda- Ratio used because typical R1 mental mode ESR values are much less than the maximum spec. DL Crystal drive level No external series resistor assumed F3SEPHI Third overtone separation from 3*FNOM High side F3SEPLO Third overtone separation from 3*FNOM Low side C0 Crystal shunt capacitance C0/C1 Ratio of shunt to motional capacitance 180 – 250 C1 Crystal motional capacitance 14.4 18 21.6 Parallel resonance, fundamental mode, AT cut Fundamental mode – MHz 14 – pF – 25 Ω 3 – – – 0.5 2.0 mW 300 – – ppm – – – – –150 ppm 7 pF pF Note: 1. Crystals that meet this specification includes: Ecliptek ECX-5788-13.500M,Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL,PDI HA13500XFSA14XC. Document #: 38-07227 Rev. *D Page 2 of 6 CY2412 Absolute Maximum Conditions Parameter Description Min. Max. Unit VDD Supply Voltage –0.5 7.0 V TS Storage Temperature[3] –65 125 °C TJ Junction Temperature – 125 °C Digital Inputs VSS – 0.3 VDD + 0.3 V Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 Electrostatic Discharge V 2 kV Recommended Operating Conditions Parameter Description VDD Operating Voltage TA Ambient Temperature CLOAD Max. Load Capacitance fREF Reference Frequency tPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Min. Typ. Max. Unit 3.14 3.3 3.47 V 0 70 °C 15 pF 13.5 MHz 0.05 500 ms DC Electrical Characteristics Parameter Description Test Conditions Min. Typ. Max. Unit IOH Output High Current VOH = VDD – 0.5, VDD = 3.3V 12 24 mA IOL Output Low Current VOL = 0.5, VDD = 3.3V 12 24 mA CIN Input Capacitance IIZ Input Leakage Current f∆XO VCXO pullability range VVCXO VCXO input range fVBW VCXO input bandwidth IDD Supply Current 7 pF µA 5 +150 ppm 0 VDD V DC to 200 Sum of Core and Output Current kHz 35 mA AC Electrical Characteristics Parameter[4] Min. Typ. Max. Unit DC Output Duty Cycle Description Duty Cycle is defined in Figure 1, 50% of VDD Test Conditions 45 50 55 % ER Rising Edge Rate Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. 0.8 1.4 V/ns EF Falling Edge Rate Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 2. 0.8 1.4 V/ns t9 Clock Jitter Peak to Peak period jitter t10 PLL Lock Time 100 200 ps 3 ms Notes: 2. Float XOUT if XIN is externally driven. 3. Rated for ten years. 4. Not 100% tested. Document #: 38-07227 Rev. *D Page 3 of 6 CY2412 t1 t2 CLK 50% 50% Figure 1. Duty Cycle Definition; DC = t2/t1 t3 t4 80% CLK 20% Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3 , EF = 0.6 x VDD / t4 Test Circuit VDD CLK out 0.1 µF CLOAD OUTPUTS GND Ordering Information Ordering Code Package Type Operating Range Operating Voltage CY2412SC-1 8-pin SOIC Commercial 3.3V CY2412SC-1T 8-pin SOIC–Tape and Reel Commercial 3.3V CY2412SC-3 8-pin SOIC Commercial 3.3V CY2412SC-3T 8-pin SOIC–Tape and Reel Commercial 3.3V CY2412SXC-1 8-pin SOIC Commercial 3.3V CY2412SXC-1T 8-pin SOIC–Tape and Reel Commercial 3.3V CY2412SXC-3 8-pin SOIC Commercial 3.3V CY2412SXC-3T 8-pin SOIC–Tape and Reel Commercial 3.3V Lead-free Document #: 38-07227 Rev. *D Page 4 of 6 CY2412 Package Diagram 8 Lead (150 Mil) SOIC S08 8-lead (150-Mil) SOIC S8 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 51-85066-*C 0.0138[0.350] 0.0192[0.487] All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07227 Rev. *D Page 5 of 6 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY2412 Document History Page Document Title: CY2412 MPEG Clock Generator with VCXO Document Number: 38-07227 REV. ECN NO. Orig. of Issue Date Change Description of Change ** 110492 10/28/01 SZV Change from Spec number: 38-00898 to 38-07227 *A 112457 03/14/02 CKN Added CY2412-2 to data sheet *B 116961 08/06/02 CKN Removed CY2412-2 from the datasheet. Added CY2412-3 to data sheet *C 121879 12/14/02 RBI Power-up requirements added to Operating Conditions Information *D 299735 See ECN RGL Added lead-free for CY2412-1 and CY2412-3 devices Document #: 38-07227 Rev. *D Page 6 of 6