CY26200 T1/E1 Clock Generator Features Benefits • High-performance PLL tailored for T1/E1 clock generation • Meets critical timing requirements in complex system designs • Enables application compatibility • Integrated phase-locked loop (PLL) • Low-jitter, high-accuracy outputs • 3.3V operation Part Number Outputs Input Frequency Range Output Frequencies CY26200 1 19.44 MHz 1.544 MHz/2.048 MHz (selectable) Logic Block Diagram 19.44 XIN OSC Q XOUT Φ VCO OUTPUT DIVIDERS P CLK1 PLL AVDD AVSS VDD VSS Pin Configuration CY26200 8-pin SOIC Table 1. CY26200 Frequency Select Option XIN 1 8 XOUT AVDD FS 2 7 3 6 VSS CLK1 AVSS 4 5 VDD Cypress Semiconductor Corporation Document #: 38-07335 Rev. *B • Frequency Select CLK1 Unit 0 1.544 MHz 1 2.048 MHz 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 3, 2005 CY26200 Pin Summary Pin Name Pin Number Pin Description XIN 1 19.44-MHz Reference Input AVDD 2 Analog Voltage Supply FS 3 Frequency Select – see Table 1 AVSS 4 Analog Ground VDD 5 Voltage Supply CLK1 6 1.544-MHz/2.048-MHz Clock Output VSS 7 Ground XOUT[1] 8 Reference Output Absolute Maximum Conditions Parameter VDD Description Supply Voltage Temperature[2] TS Storage TJ Junction Temperature Min. Max. Unit –0.5 7.0 V –65 125 °C 125 °C Digital Inputs VSS – 0.3 VDD + 0.3 V Digital Outputs Referred to VDD VSS – 0.3 VDD + 0.3 V Electrostatic Discharge 2000 V Recommended Operating Conditions Parameter Description VDD/AVDD Operating Voltage TA Ambient Temperature (Commercial) TA Ambient Temperature (Industrial) CLOAD Max. Load Capacitance fREF Reference Frequency tPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Min. Typ. Max. 3.135 3.3 Unit 3.465 V 0 70 °C –40 +85 °C 15 pF 19.44 MHz 0.05 500 ms DC Electrical Characteristics (Commercial) Parameter Description Conditions Min. Typ. Max. Unit IOH Output High Current VOH = VDD – 0.5, VDD = 3.3V 12 24 mA IOL Output Low Current VOL = 0.5, VDD = 3.3V 12 24 mA CIN Input Capacitance IIZ Input Leakage Current IDD Supply Current 7 Sum of Core and Output Current pF µA 5 20 mA Max. Unit DC Electrical Characteristics (Industrial) Parameter Description Conditions Min. Typ. IOH Output High Current VOH = VDD – 0.5, VDD = 3.3V 11 24 mA IOL Output Low Current VOL = 0.5, VDD = 3.3V 11 24 mA CIN Input Capacitance IIZ Input Leakage Current IDD Supply Current 7 Sum of Core and Output Current pF µA 5 25 mA Notes: 1. Float XOUT if XIN is externally driven 2. Rated for 10 years Document #: 38-07335 Rev. *B Page 2 of 5 CY26200 AC Electrical Characteristics (VDD = 3.3V, Commercial) Parameter[3] Min. Typ. Max. Unit DC Output Duty Cycle Description Duty Cycle is defined in Figure 1, 50% of VDD Conditions 45 50 55 % t3 Rising Edge Slew Rate Output Clock Rise Time, 20% - 80% of VDD 0.8 1.4 V/ns t4 Falling Edge Slew Rate Output Clock Fall Time, 80% - 20% of VDD 0.8 1.4 V/ns t9 Clock Jitter Peak to Peak period jitter t10 PLL Lock Time 200 ps 3 ms Typ. Max. Unit 55 AC Electrical Characteristics (VDD = 3.3V, Industrial) Parameter[3] Name Description Min. DC Output Duty Cycle Duty Cycle is defined in Figure 1, 50% of VDD 45 50 t3 Rising Edge Slew Rate Output Clock Rise Time, 20% - 80% of VDD 0.8 1.4 V/ns t4 Falling Edge Slew Rate Output Clock Fall Time, 80% - 20% of VDD 0.8 1.4 V/ns t9 Clock Jitter Peak to Peak period jitter 200 ps t10 PLL Lock Time % 3 ms Test Circuit V DD CLK out 0.1 mF C LOAD OUTPUTS GND t3 t1 t2 CLK t4 80% CLK 50% 50% 20% Figure 2. Rise and Fall Time Definitions Figure 1. Duty Cycle Definition; DC = t2/t1 Ordering Information Ordering Code Package Type Operating Range Operating Voltage CY26200SC 8-lead SOIC Commercial 3.3V CY26200SCT 8-lead SOIC - Tape and Reel Commercial 3.3V CY26200SI 8-lead SOIC Industrial 3.3V CY26200SIT 8-lead SOIC - Tape and Reel Industrial 3.3V CY26200SXC 8-lead SOIC Commercial 3.3V CY26200SXCT 8-lead SOIC - Tape and Reel Commercial 3.3V CY26200SXI 8-lead SOIC Industrial 3.3V CY26200SXIT 8-lead SOIC - Tape and Reel Industrial 3.3V Lead-free Notes: 3. Not 100% tested Document #: 38-07335 Rev. *B Page 3 of 5 CY26200 Package Diagram 8-lead (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07335 Rev. *B Page 4 of 5 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY26200 Document History Page Document Title: CY26200 T1/E1 Clock Generator Document Number: 38-07335 REV. ECN No. Issue Date Orig. of Change Description of Change ** 111745 05/06/02 CKN New Data Sheet *A 121890 12/14/02 RBI Power up requirements added to Operating Conditions Information *B 400148 See ECN RGL Added lead-free devices Document #: 38-07335 Rev. *B Page 5 of 5