CY24130 HOTLink II™ SMPTE Receiver Training Clock Features Benefits ■ Integrated phase-locked loop ■ Internal PLL with up to 400-MHz internal operation ■ Low-jitter, high-accuracy outputs ■ ■ 3.3V operation Meets critical timing requirements in complex system designs ■ Enables application compatibility Table 1. Frequency table Part Number Outputs Input Frequency CY24130-1 2 27 MHz (Driven Reference) 1 copy 27-MHz reference clock output 1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable) Output Frequency Range CY24130-2 2 27 MHz (Crystal Reference) 1 copy 27-MHz reference clock output 1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable) Logic Block Diagram XIN OSC. Φ Q VCO XOUT OUTPUT MULTIPLEXER AND DIVIDERS P CLKA PLL REFCLK S0 S1 S2 VDDL VDD AVDD AVSS VSS VSSL Table 2. Frequency Select Options S2 S1 S0 CLKA REFCLK Units 0 0 0 27 27 MHz 0 0 1 36 27 MHz 0 1 0 54 27 MHz 0 1 1 148.50 27 MHz 1 0 0 74.25 27 MHz 1 0 1 OFF, pulled low 27 MHz 1 1 0 OFF, pulled low 27 MHz 1 1 1 OFF, pulled low 27 MHz Cypress Semiconductor Corporation Document #: 38-07711 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 22, 2008 [+] Feedback CY24130 Pin Configuration Figure 1. CY24130-1, -2, 16-pin TSSOP XIN VDD 1 16 XOUT 2 15 AVDD S2 REFCLK VSS 3 14 S0 4 13 AVSS 5 12 N/C VSSL 6 11 VDDL N/C CLKA 7 10 8 9 S1 N/C Table 3. Pin Definition Name Pin Number Description XIN 1 Reference Crystal Input. VDD 2 Voltage Supply. AVDD 3 Analog Voltage Supply. S0 4 Frequency Select 0. AVSS 5 Analog Ground. VSSL 6 VDDL Ground. N/C 7 No Connect. CLKA 8 27-/36-/54-/148.50-/74.25-MHz Clock Output (frequency selectable). N/C 9 No Connect. S1 10 Frequency Select 1. VDDL 11 Voltage Supply. N/C 12 No Connect. VSS 13 Ground. REFCLK 14 Reference Clock Output. S2 15 Frequency Select 2. XOUT 16 Reference Crystal Output. Leave floating for -1. Absolute Maximum Conditions Parameter Description VDD, AVDD Supply Voltage VDDL I/O Supply Voltage TJ Junction Temperature Digital Inputs Min. Max. Unit –0.5 7.0 V – 7.0 V – 125 °C AVSS – 0.3 AVDD + 0.3 V 2 – kV Electro-Static Discharge Recommended Operating Conditions Parameter Description Min. Typ. Max. Unit 3.135 3.3 3.465 V 0 – 70 °C VDD/AVDDL/VDDL Operating Voltage TA Ambient Temperature CLOAD Max. Load Capacitance – – 15 pF fREF Reference Frequency – 27 – MHz CLNOM Nominal Parallel Crystal Load Capacitance for -2 – 18 – pF Document #: 38-07711 Rev. *A Page 2 of 6 [+] Feedback CY24130 DC Electrical Specifications Parameter[1] Name Description Min. Typ. Max. Unit IOH Output High Current VOH = VDD – 0.5, VDD/VDDL = 3.3V 12 24 – mA IOL Output Low Current VOL = 0.5, VDD/VDDL = 3.3V 12 24 – mA IIH Input High Current VIH = VDD – 5 10 μA IIL Input Low Current VIL = 0V – – 10 μA VIH Input High Voltage CMOS levels, 70% of VDD 0.7 – – V VIL Input Low Voltage CMOS levels, 30% of VDD – – 0.3 V IVDD Supply Current AVDD/VDD Current – 16 – mA IVDDL Supply Current VDDL Current – 14 – mA AC Electrical Specifications Parameter[1] Min. Typ. Max. Unit DC Output Duty Cycle Name Duty Cycle is defined in Figure 3; t1/t2, 50% of VDD Description 45 50 55 % ER Rising Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 4. 0.8 1.4 – V/ns EF Falling Edge Rate Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 4. 0.8 1.4 – V/ns t9 Clock Jitter CLKA Peak-Peak Period Jitter – 100 – ps t10 PLL Lock Time – – 3 ms Figure 2. Test and Measurement Setup VDDs 0.1 μF DUT Outputs CLOAD GND Voltage and Timing Definitions Figure 3. Duty Cycle Definitions t1 t2 VDD 50% of VDD Clock Output 0V Note 1. Not 100% tested. Document #: 38-07711 Rev. *A Page 3 of 6 [+] Feedback CY24130 Figure 4. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 t3 t4 V DD 80% of V DD Clock Output 20% of V DD 0V Ordering Information Ordering Code Package Type Operating Range Operating Voltage 16-Pin TSSOP Commercial 3.3V 16-Pin TSSOP – Tape and Reel Commercial 3.3V 16-Pin TSSOP Commercial 3.3V Pb-free CY24130ZXC-1[2] CY24130ZXC-1T [2] CY24130ZXC-2[2] CY24130ZXC-2T [2] 16-Pin TSSOP – Tape and Reel Commercial 3.3V CY24130KZXC-1 16-Pin TSSOP Commercial 3.3V CY24130KZXC-1T 16-Pin TSSOP – Tape and Reel Commercial 3.3V Note 2. Not recommended for new design. Document #: 38-07711 Rev. *A Page 4 of 6 [+] Feedback CY24130 Package Drawing and Dimensions Figure 5. 16-lead TSSOP 4.40 MM Body Z16.173 PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. MAX. 1 REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] PACKAGE WEIGHT 0.05 gms PART # 4.30[0.169] 4.50[0.177] Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG. 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091-*A Document #: 38-07711 Rev. *A Page 5 of 6 [+] Feedback CY24130 Document History Page Document Title: CY24130 HOTLink II™ SMPTE Receiver Training Clock Document Number: 38-07711 REV. ECN NO. Orig. of Change Submission Date ** 314514 RGL See ECN New Data Sheet *A 2442066 AESA See ECN Updated template. Added Note “Not recommended for new designs.” Added part number CY24130KZXC-1, and CY24130KZXC-1T in ordering information table. Description of Change Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers PSoC Solutions psoc.cypress.com clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog Memories memory.cypress.com LCD Drive psoc.cypress.com/lcd-drive image.cypress.com CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb Image Sensors psoc.cypress.com/precision-analog © Cypress Semiconductor Corporation, 2005-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07711 Rev. *A Revised May 22, 2008 Page 6 of 6 MediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback