CYPRESS CY29350AXI

CY29350
2.5 V or 3.3 V, 200-MHz,
9-Output Clock Driver
2.5 V or 3.3 V, 200-MHz, 9-Output Clock Driver
Features
Functional Description
■
Output frequency range: 25 MHz to 200 MHz
■
Input frequency range: 6.25 MHz to 31.25 MHz
■
2.5 V or 3.3 V operation
■
Split 2.5 V/3.3 V outputs
■
±2.5% max Output duty cycle variation
■
Nine Clock outputs: Drive up to 18 clock lines
■
Two reference clock inputs: Xtal or LVCMOS
■
150-ps max output-output skew
■
Phase-locked loop (PLL) bypass mode
■
Spread Aware™
■
Output enable/disable
■
Pin-compatible with MPC9350
■
Industrial temperature range: –40 °C to +85 °C
■
32-pin 1.0 mm TQFP package
The CY29350 is a low-voltage high-performance 200-MHz
PLL-based clock driver designed for high speed clock
distribution applications.
The CY29350 features Xtal and LVCMOS reference clock inputs
and provides nine outputs partitioned in four banks of 1, 1, 2, and
5 outputs. Bank A divides the VCO output by 2 or 4 while the
other banks divide by 4 or 8 per SEL(A:D) settings, see . These
dividers allow output to input ratios of 16:1, 8:1, 4:1, and 2:1.
Each LVCMOS compatible output can drive 50  series or
parallel terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces giving
the device an effective fanout of 1:18.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range of
output frequencies from 25 MHz to 200 MHz. The internal VCO
is running at multiples of the input reference clock set by the
feedback divider, see Table 1.
When PLL_EN is LOW, PLL is bypassed and the reference clock
directly feeds the output dividers. This mode is fully static and the
minimum input clock frequency specification does not apply.
Block Diagram
SELA
PLL_EN
REF_SEL
TCLK
XIN
XOUT
OSC
Phase
Detector
VCO
200 500MHz
LPF

QA

QB

FB_SEL
SELB

QC0
QC1
SELC

QD0
QD1
SELD
QD2
QD3
QD4
OE#
Cypress Semiconductor Corporation
Document Number: 38-07474 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 12, 2011
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CY29350
Contents
Pin Configuration ............................................................. 3
Pin Definitions .................................................................. 4
Absolute Maximum Conditions ....................................... 5
DC Electrical Specifications ............................................ 6
DC Electrical Specifications ............................................ 6
AC Electrical Specifications ............................................ 7
AC Electrical Specifications ............................................ 8
Ordering Information ...................................................... 10
Ordering Code Definitions ......................................... 10
Package Drawing and Dimension ................................. 10
Document Number: 38-07474 Rev. *C
Acronyms ........................................................................ 11
Document Conventions ................................................. 11
Units of Measure ....................................................... 11
Document History Page ................................................. 12
Sales, Solutions, and Legal Information ...................... 13
Worldwide Sales and Design Support ....................... 13
Products .................................................................... 13
PSoC Solutions ......................................................... 13
Page 2 of 13
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CY29350
32
31
30
29
28
27
26
25
REF_SEL
PLL_EN
TCLK
VSS
QA
VDDQB
QB
VSS
Pin Configuration
1
2
3
4
5
6
7
8
CY29350
24
23
22
21
20
19
18
17
QC0
VDDQC
QC1
VSS
QD0
VDDQD
QD1
VSS
XIN
OE#
VDD
QD4
VSS
QD3
VDDQD
QD2
9
10
11
12
13
14
15
16
AVDD
FB_SEL
SELA
SELB
SELC
SELD
AVSS
XOUT
Document Number: 38-07474 Rev. *C
Page 3 of 13
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CY29350
Pin Definitions[1]
Pin
8
Name
XOUT
9
XIN
30
TCLK
28
26
I/O
Type
O
Analog
Description
Oscillator Output. Connect to a crystal.
I
Analog
I, PD
LVCMOS
LVCMOS/LVTTL reference clock input
Oscillator Input. Connect to a crystal.
QA
O
LVCMOS
Clock output bank A
QB
O
LVCMOS
Clock output bank B
22, 24
QC(1:0)
O
LVCMOS
Clock output bank C
12, 14, 16, 18, 20
QD(4:0)
O
LVCMOS
Clock output bank D
2
FB_SEL
I, PD
LVCMOS
Internal Feedback Select Input. See Table 1.
10
OE#
I, PD
LVCMOS
Output enable/disable input. See Table 2.
31
PLL_EN
I, PU
LVCMOS
PLL enable/disable input. See Table 2.
32
REF_SEL
I, PD
LVCMOS
Reference select input. See Table 2.
3, 4, 5, 6
SEL(A:D)
I, PD
LVCMOS
27
VDDQB
Supply
VDD
2.5 V or 3.3 V Power supply for bank B output clock[2, 3]
Frequency select input, Bank (A:D). See Table 2.
23
VDDQC
Supply
VDD
2.5 V or 3.3 V Power supply for bank C output clocks[2, 3]
15, 19
VDDQD
Supply
VDD
2.5 V or 3.3 V Power supply for bank D output clocks[2, 3]
1
AVDD
Supply
VDD
2.5 V or 3.3 V Power supply for PLL[2, 3]
11
VDD
Supply
VDD
2.5 V or 3.3 V Power supply for core, inputs, and bank A
output clock[2, 3]
7
AVSS
Supply
Ground
Analog ground
13, 17, 21, 25, 29
VSS
Supply
Ground
Common ground
Table 1. Frequency Table
VCO
Input Frequency Range
(AVDD = 3.3 V)
Input Frequency Range
(AVDD = 2.5 V)
FB_SEL
Feedback Divider
0
32
Input Clock * 32
6.25 MHz to 15.625 MHz
6.25 MHz to 11.875 MHz
1
16
Input Clock * 16
12.5 MHz to 31.25 MHz
12.5 MHz to 23.75 MHz
Table 2. Function Table
Control
Default
0
1
REF_SEL
0
Xtal
TCLK
PLL_EN
1
Bypass mode, PLL disabled. The input
clock connects to the output dividers
PLL enabled. The VCO output connects to the
output dividers
OE#
0
Outputs enabled
Outputs disabled (three-state)
FB_SEL
0
SELA
0
Feedback divider  32
 2 (Bank A)
Feedback divider  16
 4 (Bank A )
SELB
0
 4 (Bank B)
 8 (Bank B)
SELC
0
 4 (Bank C)
 8 (Bank C)
SELD
0
 4 (Bank D)
 8 (Bank D)
Notes
1. PU = Internal pull-up, PD = Internal pull-down.
2. A 0.1F bypass capacitor should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their high
frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output power supply pins.
Document Number: 38-07474 Rev. *C
Page 4 of 13
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CY29350
Absolute Maximum Conditions
Parameter
VDD
VDD
VIN
VOUT
VTT
LU
RPS
TS
TA
TJ
ØJC
ØJA
ESDH
FIT
Description
DC Supply Voltage
DC Operating Voltage
DC Input Voltage
DC Output Voltage
Output termination Voltage
Latch Up Immunity
Power Supply Ripple
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Failure in Time
Document Number: 38-07474 Rev. *C
Condition
Functional
Relative to VSS
Relative to VSS
Functional
Ripple Frequency < 100 kHz
Non-functional
Functional
Functional
Functional
Functional
Manufacturing test
Min
–0.3
2.375
–0.3
–0.3
–
200
–
–65
–40
–
–
–
2000
Max
5.5
3.465
VDD + 0.3
VDD + 0.3
VDD  2
–
150
+150
+85
+150
42
105
–
10
Unit
V
V
V
V
V
mA
mVp-p
°C
°C
°C
°C/W
°C/W
Volts
ppm
Page 5 of 13
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CY29350
DC Electrical Specifications
(VDD = 2.5 V ± 5%, TA = –40 °C to +85 °C)
Parameter
VIL
VIH
VOL
VOH
IIL
IIH
IDDA
IDDQ
IDD
Description
Input Voltage, Low
Input Voltage, High
Output Voltage, Low[4]
Output Voltage, High[4]
Input Current, Low[5]
Input Current, High[5]
PLL Supply Current
Quiescent Supply Current
Dynamic Supply Current
CIN
ZOUT
Input Pin Capacitance
Output Impedance
Condition
LVCMOS
LVCMOS
IOL = 15mA
IOH = –15mA
VIL = VSS
VIL = VDD
AVDD only
All VDD pins except AVDD
Outputs loaded @ 100 MHz
Outputs loaded @ 200 MHz
Min
–
1.7
–
1.8
–
–
–
–
–
–
–
14
Typ
–
–
–
–
–
–
5
–
180
210
4
18
Max
0.7
VDD + 0.3
0.6
–
–100
100
10
7
–
–
–
22
Unit
V
V
V
V
A
A
mA
mA
mA
Min
–
2.0
–
–
2.4
––
–
–
–
–
–
–
12
Typ
–
–
–
–
–
–
–
5
–
270
300
4
15
Max
0.8
VDD + 0.3
0.55
0.30
–
–100
100
10
7
–
–
–
18
Unit
V
V
V
pF

DC Electrical Specifications
(VDD = 3.3 V ± 5%, TA = –40 °C to +85 °C)
Parameter
VIL
VIH
VOL
Description
Input Voltage, Low
Input Voltage, High
Output Voltage, Low[4]
VOH
IIL
IIH
IDDA
IDDQ
IDD
Output Voltage, High[4]
Input Current, Low[5]
Input Current, High[5]
PLL Supply Current
Quiescent Supply Current
Dynamic Supply Current
CIN
ZOUT
Input Pin Capacitance
Output Impedance
Condition
LVCMOS
LVCMOS
IOL = 24 mA
IOL = 12 mA
IOH = –24 mA
VIL = VSS
VIL = VDD
AVDD only
All VDD pins except AVDD
Outputs loaded @ 100 MHz
Outputs loaded @ 200 MHz
V
A
A
mA
mA
mA
pF

Notes
4. Driving one 50  parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50  series terminated transmission
lines.
5. Inputs have pull-up or pull-down resistors that affect the input current.
Document Number: 38-07474 Rev. *C
Page 6 of 13
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CY29350
AC Electrical Specifications
(VDD = 2.5 V ± 5%, TA = –40 °C to +85 °C) [6]
Parameter
Description
fVCO
VCO Frequency
fin
Input Frequency
Condition
Min
Typ
Max
Unit
200
–
380
MHz
16 Feedback
12.5
–
23.75
MHz
32 Feedback
6.25
–
11.87
0
–
200
Bypass mode (PLL_EN = 0)
fXTAL
Crystal Oscillator Frequency
10
–
23.75
MHz
frefDC
Input Duty Cycle
25
–
75
%
tr , tf
TCLK Input Rise/FallTime
0.7 V to 1.7 V
–
–
1.0
ns
fMAX
Maximum Output Frequency
2 Output
100
–
190
MHz
4 Output
50
–
95
8 Output
25
–
47.5
DC
Output Duty Cycle
fMAX < 100 MHz
47.5
–
52.5
fMAX > 100 MHz
45
–
55
0.6V to 1.8V
0.1
–
1.0
ns
–
–
150
ps
%
tr, tf
Output Rise/Fall times
tsk(O)
Output-to-Output Skew
tPLZ, HZ
Output Disable Time
–
–
10
ns
tPZL, ZH
Output Enable Time
–
–
10
ns
BW
PLL Closed Loop Bandwidth (–3 dB) 16 Feedback
–
0.7–0.9
–
MHz
32 Feedback
–
0.6–0.8
–
tJIT(CC)
tJIT(PER)
tLOCK
Cycle-to-Cycle Jitter
Period Jitter
Maximum PLL Lock Time
Same frequency
–
–
150
Multiple frequencies
–
–
250
Same frequency
–
–
100
Multiple frequencies
–
–
175
–
–
1
ps
ps
ms
Note
6. AC characteristics apply for parallel output termination of 50 to VTT. Parameters are guaranteed by characterization and are not 100% tested.
Document Number: 38-07474 Rev. *C
Page 7 of 13
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CY29350
AC Electrical Specifications
(VDD = 3.3 V ± 5%, TA = –40 °C to +85 °C) [7]
Parameter
Description
fVCO
VCO Frequency
fin
Input Frequency
Condition
Min
Typ
Max
Unit
200
–
500
MHz
16 Feedback
12.5
–
31.25
MHz
32 Feedback
6.25
–
15.625
200
0
–
fXTAL
Crystal Oscillator Frequency
Bypass mode (PLL_EN = 0)
10
–
25
MHz
frefDC
Input Duty Cycle
25
–
75
%
tr, tf
TCLK Input Rise/FallTime
0.8 V to 2.0 V
–
–
1.0
ns
fMAX
Maximum Output Frequency
2 Output
100
–
200
MHz
4 Output
50
–
125
8 Output
25
–
62.5
47.5
–
52.5
DC
Output Duty Cycle
fMAX < 100 MHz
fMAX > 100 MHz
45
–
55
tr , tf
Output Rise/Fall times
0.8 V to 2.4 V
0.1
–
1.0
ns
tsk(O)
Output-to-Output Skew
Banks at same voltage
–
–
150
ps
tsk(B)
Bank-to-Bank Skew
Banks at different voltages
–
–
350
ps
tPLZ, HZ
Output Disable Time
–
–
10
ns
%
tPZL, ZH
Output Enable Time
–
–
10
ns
BW
PLL Closed Loop Bandwidth (–3 dB) 16 Feedback
–
0.7–0.9
–
MHz
32 Feedback
–
0.6–0.8
–
Same frequency
–
–
150
Multiple frequencies
–
–
250
tJIT(CC)
tJIT(PER)
tLOCK
Cycle-to-Cycle Jitter
Period Jitter
Maximum PLL Lock Time
Same frequency
–
–
100
Multiple frequencies
–
–
150
–
–
1
ps
ps
ms
Note
7. AC characteristics apply for parallel output termination of 50 to VTT. Parameters are guaranteed by characterization and are not 100% tested.
Document Number: 38-07474 Rev. *C
Page 8 of 13
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CY29350
Figure 1. AC Test Reference for VDD = 3.3 V / 2.5 V
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
R T = 50 ohm
R T = 50 ohm
VTT
VTT
Figure 2. Output Duty Cycle (DC)
VDD
VDD/2
tP
GND
T0
DC = tP / T0 x 100%
Figure 3. Output-to-Output Skew , tsk(O)
VDD
VDD/2
GND
VDD
VDD/2
GND
tSK(O)
Table 3. Suggested Oscillator Crystal Parameters
Characteristic
Symbol
Conditions
Min
Typ
Max
Units
–
–
±100
ppm
–
–
±00
ppm
Frequency Tolerance
TC
Frequency Temperature Stability
TS
(TA –10 +60 °C)
Aging
TA
First three years @ 25 °C
–
–
5
ppm/yr
Load Capacitance
CL
Crystal’s rated load
–
20
–
pF
–
40
80

Effective Series Resistance
Document Number: 38-07474 Rev. *C
RESR
Page 9 of 13
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CY29350
Ordering Information
Part Number
Package Type
Product Flow
CY29350AXI
32-pin TQFP, Pb-free
Industrial, –40 °C to +85 °C
CY29350AXIT
32-pin TQFP – Tape and Reel, Pb-free
Industrial, –40 °C to 85 °C
Ordering Code Definitions
CY 29350 AX X
T
T = Tape and Reel
Temperature Range: X = C or I
C = Commercial; I = Industrial
Package Type:
AX = 32-pin TQFP
Base Device Part Number
Company ID: CY = Cypress
Package Drawing and Dimension
Figure 4. 32-pin TQFP 7 x 7 x 1.0 mm A3210
51-85063 *C
Document Number: 38-07474 Rev. *C
Page 10 of 13
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CY29350
Acronyms
Acronym
Description
CMOS
complementary metal oxide semiconductor
ESD
electrostatic discharge
I/O
Input/Output
LVCMOS
Low Voltage Complementary Metal Oxide
Semiconductor
LVTTL
Low Voltage Transistor-Transistor Logic
PLL
phase-locked loop
TQFP
thin quad flat pack
VCO
voltage-controlled oscillator
Document Conventions
Units of Measure
Symbol
Unit of Measure
°C
degree Celsius
Hz
Hertz
kHz
kilo Hertz
MHz
Mega Hertz
µF
micro Farads
µA
micro Amperes
mm
milli meter
mA
milli Amperes
ms
milli seconds
ns
nano seconds

ohms
%
percent
pF
pico Farads
ppm
parts per million
ps
pico seconds
kV
kilo Volts
mV
milli Volts
V
Volts
W
Watts
Document Number: 38-07474 Rev. *C
Page 11 of 13
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CY29350
Document History Page
Document Title:CY29350 2.5 V or 3.3 V, 200-MHz, 9-Output Clock Driver
Document Number: 38-07474
Rev.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
128104
07/07/03
RGL
New Data Sheet
*A
245393
See ECN
RGL
Re-worded Select Function Descriptions in table 2.
*B
2904632
04/05/2010
KVM
The existing part numbers are replaced with new ones: CY29350AXI and
CY29350AXIT with package type cells: [32-pin TQFP, Pb-free] [32-pin
TQFP – Tape and Reel, Pb-free].
*C
3223621
04/12/2011
BASH
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Updated in new template.
Document Number: 38-07474 Rev. *C
Page 12 of 13
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CY29350
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
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© Cypress Semiconductor Corporation, 2003-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07474 Rev. *C
Revised April 12, 2011
Page 13 of 13
Spread Aware is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.
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