CYPRESS CY2XP22ZXCT

CY2XP22
Crystal to LVPECL Clock Generator
Features
■
Pb-free 8-Pin TSSOP package
■
Supply voltage: 3.3 V or 2.5 V
■
Commercial and Industrial temperature ranges
■
One LVPECL output pair
■
Selectable frequency multiplication: x2.5 or x5
■
External crystal frequency: 25.0 MHz
Functional Description
■
Output frequency: 62.5 MHz or 125 MHz
■
Low RMS phase jitter at 125 MHz, using 25 MHz crystal
(1.875 MHz to 20 MHz): 0.4 ps (typical)
■
Phase noise at 125 MHz (typical):
The CY2XP22 is a PLL (Phase Locked Loop) based high
performance clock generator that uses an external reference
crystal. It is specifically targeted at FibreChannel and Gigabit
Ethernet applications. It produces a selectable output frequency
that is 2.5 or 5 times the crystal frequency. With a 25 MHz crystal,
the user can select either a 62.5 MHz or 125 MHz output. It uses
Cypress’s low noise VCO technology to achieve less than 1 ps
typical RMS phase jitter. The CY2XP22 has a crystal oscillator
interface input and one LVPECL output pair.
Offset
Noise Power
1 kHz
–117 dBc/Hz
10 kHz
–126 dBc/Hz
100 kHz
–131 dBc/Hz
1 MHz
–131 dBc/Hz
Logic Block Diagram
XIN
External
Crystal
CRYSTAL
OSCILLATOR
LOW -NOISE
PLL
OUTPUT
DIVIDER
CLK
CLK#
XOUT
F _SEL
Pinouts
Figure 1. Pin Diagram – 8-Pin TSSOP
VDD
VSS
XOUT
XIN
1
2
3
4
8
7
6
5
VDD
CLK
CLK#
F_SEL
Table 1. Pin Definitions – 8-Pin TSSOP
Pin Number
Pin Name
I/O Type
Power
Description
1, 8
VDD
2
VSS
Power
Ground
3, 4
XOUT, XIN
XTAL output and input
Parallel resonant crystal interface
5
F_SEL
CMOS input
Frequency Select: see Frequency Table
6,7
CLK#, CLK
LVPECL output
Differential clock output
Cypress Semiconductor Corporation
Document #: 001-10229 Rev. *F
3.3 V or 2.5 V power supply
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 11, 2011
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CY2XP22
Frequency Table
Inputs
PLL Multiplier Value
Output Frequency (MHz)
0
5
125
1
2.5
62.5
Crystal Frequency (MHz)
F_SEL
25
Absolute Maximum Conditions
Parameter
Description
Conditions
Min
Max
Unit
VDD
Supply Voltage
–0.5
4.4
V
VIN[1]
Input Voltage, DC
Relative to VSS
–0.5
VDD + 0.5
V
Non operating
–65
150
°C
–
135
°C
–
V
TS
Temperature, Storage
TJ
Temperature, Junction
ESDHBM
ESD Protection, Human Body Model
JEDEC STD 22-A114-B
UL–94
Flammability Rating
At 1/8 in.
V–0
ΘJA[2]
Thermal Resistance, Junction to Ambient
2000
0 m/s airflow
100
1 m/s airflow
91
2.5 m/s airflow
87
°C/W
Operating Conditions
Parameter
VDD
TA
TPU
Min
Max
Unit
3.3 V Supply Voltage
Description
3.135
3.465
V
2.5 V Supply Voltage
2.375
2.625
V
0
70
°C
Ambient Temperature, Commercial
Ambient Temperature, Industrial
–40
85
°C
Power up time for all VDD to reach minimum specified voltage (ensure power ramps
is monotonic)
0.05
500
ms
DC Electrical Characteristics
Parameter
IDD
IDDT
Description
Operating Supply Current with
output unterminated
Operating Supply Current with
output terminated
Min
Typ
Max
Unit
VDD = 3.465 V, FOUT = 125 MHz,
output unterminated
Test Conditions
–
–
125
mA
VDD = 2.625 V, FOUT = 125 MHz,
output unterminated
–
–
120
mA
VDD = 3.465 V, FOUT = 125 MHz,
output terminated
–
–
150
mA
VDD = 2.625 V, FOUT = 125 MHz,
output terminated
–
–
145
mA
VOH
LVPECL Output High Voltage
VDD = 3.3 V or 2.5 V, RTERM = 50Ω to VDD –1.15
VDD – 2.0 V
–
VDD –0.75
V
VOL
LVPECL Output Low Voltage
VDD = 3.3 V or 2.5 V, RTERM = 50Ω to
VDD – 2.0 V
VDD –2.0
–
VDD –1.625
V
Notes
1. The voltage on any input or IO pin cannot exceed the power pin during power up.
2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of
copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
Document #: 001-10229 Rev. *F
Page 2 of 10
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CY2XP22
DC Electrical Characteristics (continued)
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VOD1
LVPECL Peak-to-Peak Output
Voltage Swing
VDD = 3.3 V or 2.5 V, RTERM = 50Ω to
VDD – 2.0 V
600
–
1000
mV
VOD2
LVPECL Output Voltage Swing
(VOH - VOL)
VDD = 2.5 V, RTERM = 50Ω to VDD –
1.5 V
500
–
1000
mV
VOCM
LVPECL Output Common Mode VDD = 2.5 V, RTERM = 50Ω to VDD –
Voltage (VOH + VOL)/2
1.5 V
1.2
–
–
V
VIH
Input High Voltage, F_SEL
0.7*VDD
–
VDD + 0.3
V
VIL
Input Low Voltage, F_SEL
–0.3
–
0.3*VDD
V
IIH
Input High Current, F_SEL
F_SEL = VDD
–
–
115
µA
IIL
Input Low Current, F_SEL
F_SEL = VSS
–50
–
–
µA
CIN
[3]
CINX[3]
Input Capacitance, F_SEL
–
15
–
pF
Pin Capacitance, XIN & XOUT
–
4.5
–
pF
Min
Typ
Max
Unit
62.5
–
125
MHz
AC Electrical Characteristics[3]
Parameter
Description
Conditions
FOUT
Output Frequency
TR, TF
Output Rise or Fall Time
20% to 80% of full output swing
–
0.5
1.0
ns
TJitter(φ)
RMS Phase Jitter (Random)
125 MHz, (1.875–20 MHz)
–
0.4
–
ps
TDC
Output Duty Cycle
Measured at zero crossing point
48
50
52
%
TLOCK
Startup Time
Time for CLK to reach valid
frequency measured from the time
VDD = VDD(min.)
–
–
5
ms
TLFS
Re-lock Time
Time for CLK to reach valid
frequency from F_SEL pin change
–
–
1
ms
Min
Max
Unit
Recommended Crystal Specifications[4]
Parameter
Description
Mode
Mode of Oscillation
Fundamental
F
Frequency
25
25
MHz
ESR
Equivalent Series Resistance
–
50
Ω
C0
Shunt Capacitance
–
7
pF
Notes
3. Not 100% tested, guaranteed by design and characterization.
4. Characterized using an 18 pF parallel resonant crystal.
Document #: 001-10229 Rev. *F
Page 3 of 10
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CY2XP22
Parameter Measurements
Figure 2. 3.3 V Output Load AC Test Circuit
2V
VDD
SCOPE
Z = 50Ω
CLK
Z = 50Ω
CLK#
50Ω
LVPECL
VSS
50Ω
-1.3V +/- 0.165V
Figure 3. 2.5 V Output Load AC Test Circuit
2V
VDD
SCOPE
Z = 50Ω
CLK
Z = 50Ω
CLK#
50Ω
LVPECL
VSS
50Ω
-0.5V +/- 0.125V
Figure 4. Output DC Parameters
VA
CLK
VOD
VOCM = (V A + VB)/2
CLK#
VB
Figure 5. Output Rise and Fall Time
CLK#
CLK
80%
20%
20%
TR
Document #: 001-10229 Rev. *F
80%
TF
Page 4 of 10
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CY2XP22
Figure 6. RMS Phase Jitter
Phase noise
Noise
Power
Phase noise mask
Offset Frequency
f2
f1
RMS Jitter =
Area Under the Masked Phase Noise Plot
Figure 7. Output Duty Cycle
CLK
TDC =
TPW
TPERIOD
CLK#
TPW
TPERIOD
Document #: 001-10229 Rev. *F
Page 5 of 10
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CY2XP22
Application Information
Power Supply Filtering Techniques
As in any high speed analog circuitry, noise at the power supply
pins can degrade performance. To achieve optimum jitter performance, use good power supply isolation practices. Figure 8 illustrates a typical filtering scheme. Since all the current flows
through pin 1, the resistance and inductance between this pin
and the supply is minimized. A 0.01 or 0.1 µF ceramic chip
capacitor is also located close to this pin to provide a short and
low impedance AC path to ground. A 1 to 10 µF ceramic or
tantalum capacitor is located in the general vicinity of this device
and may be shared with other devices.
Figure 9. LVPECL Output Termination
3.3V
125Ω
125Ω
Z0 = 50Ω
CLK
CLK#
IN
Z0 = 50Ω
84Ω
84Ω
Figure 8. Power Supply Filtering
Crystal Interface
V DD
(Pin 8)
VDD
(Pin 1)
3.3V
0.1μF
0.01 µF
10µF
The CY2XP22 is characterized with 18 pF parallel resonant
crystals. The capacitor values shown in Figure 10 are determined using a 25 MHz 18 pF parallel resonant crystal and are
chosen to minimize the ppm error. Note that the optimal values
for C1 and C2 depend on the parasitic trace capacitance and are
thus layout dependent.
Figure 10. Crystal Input Interface
XIN
Termination for LVPECL Output
The CY2XP22 implements its LVPECL driver with a current
steering design. For proper operation, it requires a 50 ohm dc
termination on each of the two output signals. For 3.3 V
operation, this data sheet specifies output levels for termination
to VDD–2.0 V. This same termination voltage can also be used
for VDD = 2.5 V operation, or it can be terminated to VDD-1.5 V.
Note that it is also possible to terminate with 50 ohms to ground
(VSS), but the high and low signal levels differ from the data sheet
values. Termination resistors are best located close to the destination device. To avoid reflections, trace characteristic
impedance (Z0) should match the termination impedance.
Figure 9 shows a standard termination scheme.
Document #: 001-10229 Rev. *F
X1
18 pF Parallel
Crystal
C1
30 pF
Device
XOUT
C2
27 pF
Page 6 of 10
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CY2XP22
Ordering Information
Part Number
Package Type
Product Flow
CY2XP22ZXC
8-pin TSSOP
Commercial, 0°C to 70°C
CY2XP22ZXCT
8-pin TSSOP - Tape and Reel
Commercial, 0°C to 70°C
CY2XP22ZXI
8-pin TSSOP
Industrial, -40°C to 85°C
CY2XP22ZXIT
8-pin TSSOP - Tape and Reel
Industrial, -40°C to 85°C
Ordering Code Definitions
CY xx xxx Z X C/I T
T = Tape and Reel
Temperature Range: C = Commercial, I = Industrial
Pb-free
Package Type
Part Identifier
Family
Company ID: CY = Cypress
Package Drawing and Dimensions
Figure 11. 8-Pin Thin Shrunk Small Outline Package (4.40 MM Body) Z8
51-85093 *C
Document #: 001-10229 Rev. *F
Page 7 of 10
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CY2XP22
Acronyms
Document Conventions
Table 2. Acronyms Used
Table 3. Units of Measure
Acronym
Description
Symbol
Unit of Measure
CLKOUT
Clock output
°C
degrees Celsius
CMOS
Complementary metal oxide semiconductor
kHz
kilohertz
DPM
Die pick map
kΩ
kilohms
EPROM
Erasable programmable read only memory
MHz
megahertz
LVDS
Low-voltage differential signaling
MΩ
megaohms
LVPECL
Low voltage positive emitter coupled logic
µA
microamperes
NTSC
National television system committee
µs
microseconds
OE
Output enable
µV
microvolts
PAL
Phase alternate line
µVrms
microvolts root-mean-square
PD
Power-down
mA
milliamperes
PLL
Phase locked loop
mm
millimeters
PPM
Parts per million
ms
milliseconds
TTL
Transistor transistor logic
mV
millivolts
nA
nanoamperes
ns
nanoseconds
nV
nanovolts
Ω
ohms
Document #: 001-10229 Rev. *F
Page 8 of 10
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CY2XP22
Document History Page
Document Title: CY2XP22 Crystal to LVPECL Clock Generator
Document Number: 001-10229
Revision
ECN
Orig. of
Change
Submission
Date
**
506262
RGL
See ECN
Description of Change
New Data Sheet
*A
838060
RGL
See ECN
*B
2700242
KVM/PYRS
04/30/2009
*C
2718898
WWZ
06/15/09
Minor ECN to post data sheet to external web
*D
2767298
KVM
09/22/09
Add IDD spec for unterminated outputs
Change parameter name for IDD (terminated outputs) from IDD to IDDT
Remove IDD footnote about externally dissipated current
Add footnote reference to CIN and CINX:not 100% tested
Add max limit for TR, TF: 1.0 ns
Change TLOCK max from 10 ms to 5 ms
Split out parameter TLFS from TLOCK
*E
2896121
KVM
03/19/2010
*F
3219081
04/07/2011
BASH
Document #: 001-10229 Rev. *F
Changed status from Advance to Preliminary
Reformatted
Revised phase noise values
Replaced VCC with VDD; VEE with VSS; updated pin names
Removed pull-up resistor on F_SEL
Corrected temperature range, added industrial temperature range
Increased IDD from 120 / 100 mA to 150 / 140 mA
Added CINX parameter, revised CIN parameter
Revised LVPECL output specs
Added thermal resistance information
Changed VIL, VIH, IIL & IIH specs
Revised suggested crystal load capacitor values
Updated Package Diagram (Figure 11)
Changed status from preliminary to final.
Template and style updates as per current Cypress standards.
Added ordering code definitions, acronyms, and units of measure.
Updated package diagram to *C.
Page 9 of 10
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CY2XP22
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
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PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
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Touch Sensing
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© Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-10229 Rev. *F
Revised April 11, 2011
Page 10 of 10
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