SEMICONDUCTOR TECHNICAL DATA The MPC974 is a fully integrated PLL based clock generator and clock distribution chip which operates from a 3.3V supply. The MPC974 is ideally suited for high speed, timing critical designs which need a high level of clock fanout. The device features 15 high drive LVCMOS outputs, each output has the capability of driving a 50Ω parallel terminated transmission line or two 50Ω series terminated transmission lines on the incident edge. • • • • • • • • LOW VOLTAGE PLL CLOCK DRIVER Fully Integrated PLL Two Reference Clock Inputs for Redundant Clock Applications High Impedance Output Control Logic Enable on the Outputs 3.3V VCC Supply Output Frequency Configurable TQFP Packaging ±100ps Typical Cycle–to–Cycle Jitter The MPC974 features 3 independent frequency programmable banks of outputs. The frequency programmability offers the capability of establishing output frequency relationships of 1:1, 2:1, 3:1, 3:2 and 3:2:1. In addition, the device features a separate feedback output which allows for a wide variety of input/output frequency multiplication alternatives. FA SUFFIX The VCO_Sel pin provides an extended VCO lock range for added 52–LEAD TQFP PACKAGE flexibility and general purpose usage. CASE 848D-03 The TCLK0 and TCLK1 inputs provide a method for dynamically switching the PLL between two different clock sources. The PLL has been optimized to provide small deviations in output pulse width and well controlled, slow transition back to lock when the inputs are switched between two references that are equal in frequency but out of phase with each other. This feature makes the MPC974 an ideal solution for fault tolerant applications which require redundant clock sources. All of the control pins are LVTTL/LVCMOS level inputs. The Fsel pins control the VCO divide ratios that are applied to the various output banks and the feedback output. The MR input will reset the internal flip flops and place the outputs in high impedance when driven LOW. The OE pin will force all of the outputs except the feedback output LOW to allow for acquiring phase lock prior to providing clocks to the rest of the system. Note that the OE pin is not synchronized to the internal clock. As a result, the initial pulse after de–assertion of the OE pin may be distorted. The PLL_En pin allows the PLL to be bypassed for board level functional test. When bypassed the signal on the selected TCLK will be routed around the PLL and will drive the internal dividers directly. The MPC974 is packaged in the 52–lead TQFP package to provide optimum electrical performance as well as minimize board space requirements. The device is specified for 3.3V VCC. 1/97 Motorola, Inc. 1997 1 REV 2 GNDb Qb1 VCCb Qb2 GNDb Qb3 VCCb Qb4 Ext_FB GNDFB QFB VCCFB NC MPC974 39 38 37 36 35 34 33 32 31 30 29 28 27 Qb0 40 26 VCCa VCCb 41 25 Qa0 NC 42 24 GNDa GNDc 43 23 Qa1 Qc3 44 22 VCCa VCCc 45 21 Qa2 Qc2 46 20 fselFB1 GNDc 47 19 GNDa Qc1 48 18 Qa3 VCCc 49 17 VCCa Qc0 50 16 Qa4 GNDc 51 15 GNDa VCO_Sel 52 14 fselFB0 6 7 8 MR OE fselb fselc PLL_EN fsela TClk_Sel 9 10 11 12 13 VCCA 5 VCCI 4 NC 3 TClk1 2 TClk0 1 GNDI MPC974 Figure 1. 52–Lead Pinout (Top View) FUNCTION TABLE 1 fsela Qa fselb Qb fselc Qc 0 1 ÷2 ÷4 0 1 ÷2 ÷4 0 1 ÷4 ÷6 FUNCTION TABLE 2 FUNCTION TABLE 4 fselFB0 fselFB1 QFB Control Pin Logic ‘0’ Logic ‘1’ 0 0 1 1 0 1 0 1 ÷4 ÷6 ÷8 ÷12 MR PLL_EN TClk_Sel OE Master Reset/Output High Z Bypass PLL TCLK0 Qa, Qb, Qc Logic LOW – Enable PLL TCLK1 All Outputs Enabled FUNCTION TABLE 3 VCO_Sel fVCO 0 1 VCO/2 VCO/4 MOTOROLA 2 TIMING SOLUTIONS BR1333 — Rev 6 MPC974 fsela TCLK_Sel TCLK0 TCLK1 (Int. Pulldown) (Int. Pulldown) (Int. Pulldown) (Int. Pullup) 0 1 0 1 PLL FB_In PLL_EN VCO_Sel ÷2 0 1 ÷4 0 1 (Int. Pullup) Q ÷2 (Int. Pullup) ÷6 0 1 D Q (Int. Pulldown) MR fselFB0 OE D Q (Int. Pulldown) 5 Qb0:4 4 Qc0:3 R (Int. Pullup) 0 1 fselFB1 Qa0:4 R 0 1 fselc 5 R ÷4 (Int. Pulldown) R fselb D (Int. Pulldown) 0 1 ÷2 D QFB Q R (Int. Pulldown) (Int. Pullup) Figure 2. Logic Diagram ABSOLUTE MAXIMUM RATINGS* Symbol Parameter Min Max Unit V VCC Supply Voltage –0.3 5.6 VI Input Voltage –0.3 VDD + 0.3 V IIN Input Current 8 mA TStor Storage Temperature Range 125 °C –40 * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%) Symbol Characteristic VIH Input HIGH Voltage VIL Input LOW Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIN Min Typ 2.0 Max Unit VCC V 0.8 V 2.4 Condition V IOH = –20mA (Note 1.) 0.5 V IOL = 20mA (Note 1.) Input Current ±100 µA Note 2. ICC Maximum Quiescent Supply Current 120 mA CIN Input Capacitance 8 pF Cpd Power Dissipation Capacitance 25 pF Per Output 1. The MPC974 outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications Info section). 2. Inputs have either pull–up or pull–down resistors which affect input current. TIMING SOLUTIONS BR1333 — Rev 6 3 MOTOROLA MPC974 PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C) Symbol Characteristic Min Max Unit 3.0 ns tr, tf TCLK Input Rise/Falls fref Reference Input Frequency Note 3. Note 3. MHz frefDC Reference Input Duty Cycle 25 75 % Max Unit 1.5 ns tCYCLE/2 +800 ps Condition 3. Input reference frequency is limited by the divider selection and the VCO lock range. AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%) Symbol Characteristic Min Typ 0.15 Condition tr, tf Output Rise/Fall Time (Note 4.) tpw Output Duty Cycle (Note 4.) fVCO PLL VCO Lock Range fseln, fselFBn = ÷4 to ÷12 200 500 tpd SYNC to Feedback Propagation Delay –250 100 ps Notes 4., 6. tos Output-to-Output Skew 350 ps Note 4. fmax Maximum Output Frequency 125 63 42 MHz tPZL Output Enable Time 2 10 ns tPLZ, tPHZ Output Disable Time 2 10 ns tjitter Cycle–to–Cycle Jitter (Peak–to–Peak) tlock Maximum PLL Lock Time 10 ms tCYCLE/2 –800 tCYCLE/2 ±500 MHz Q (÷2) Q (÷4) Q (÷6) ±100 0.8 to 2.0V Note 5. VCO_Sel = 0 ps 4. 50Ω transmission lines terminated to VCC/2. 5. The PLL will be unstable if the total divide between the VCO and the feedback pin is less < 8. VCO_SEL = ‘0’, fsela or fselb = ‘0’ cannot be used for the PLL feedback signal. 6. tpd is specified for 50MHz input reference. The window will shrink/grow proportionally from the minimum limit with shorter/longer input reference periods. The tpd does not include jitter. APPLICATIONS INFORMATION which the PLL will be stable. The design of the PLL is such that for output frequencies between 10 and 125MHz the MPC974 can generally be configured into a stable region. The relationship between the input reference and the output frequency is also very flexible. The separate PLL feedback output allows for a wide range of output vs input frequency relationships. Function Table 1 can be used to identify the potential relationships available. Figure 3 illustrates several programming possibilities, although not exhaustive it is representative of the potential applications. Programming the MPC974 The MPC974 clock driver outputs can be configured into several frequency relationships, in addition the external feedback option allows for a great deal of flexibility in establishing unique input–to–output frequency relationships. The output dividers for the four output groups allows the user to configure the outputs into 1:1, 2:1, 3:2 and 3:2:1 frequency ratios. The use of even dividers ensures that the output duty cycle is always 50%. Function Table 1 illustrates the various output configurations, the table describes the outputs using the VCO frequency as a reference. As an example for a 3:2:1 relationship the Qa outputs would be set at VCO/2, the Qb’s and Qc’s at VCO/4 and the Qd’s at VCO/6. These settings will provide output frequencies with a 3:2:1 relationship. Using the MPC974 as a Zero Delay Buffer The external feedback option of the MPC974 clock driver allows for its use as a zero delay buffer. By using one of the outputs as a feedback to the PLL the propagation delay through the device is near zero. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The static phase offset is a function of the input reference frequency of the MPC974. The Tpd of the device is specified in the specification tables. The division settings establish the output relationship, but one must still ensure that the VCO will be stable given the frequency of the outputs desired. The VCO lock range can be found in the specification tables. The feedback frequency should be used to situate the VCO into a frequency range in MOTOROLA 4 TIMING SOLUTIONS BR1333 — Rev 6 MPC974 33MHz TCLK FB_In Qa Qb Qc 5 66MHz 5 33MHz TCLK 66MHz 4 FB_In Qa Qb 33MHz Qc QFB 5 100MHz 5 50MHz 4 33MHz QFB 33MHz 33MHz fsela fselb fselc fselFB VCO_Sel fsela fselb fselc fselFB VCO_Sel 0 0 0 00 0 0 1 1 10 0 TCLK Qa TCLK Qa 25MHz FB_In Qb Qc 5 100MHz 5 50MHz 50MHz 4 FB_In Qb 33MHz Qc QFB 5 50MHz 5 50MHz 4 50MHz QFB 25MHz 50MHz fsela fselb fselc fselFB VCO_Sel fsela fselb fselc fselFB VCO_Sel 0 1 1 01 0 1 1 0 00 0 Figure 3. MPC974 Programming Schemes To minimize part–to–part skew the external feedback option again should be used. The PLL in the MPC974 decouples the delay of the device from the propagation delay variations of the internal gates. From the specification table one sees a Tpd variation of only ±150ps, thus for multiple devices under identical configurations the part–to–part skew will be around 850ps (300ps for Tpd variation plus 350ps output–to–output skew plus 200ps for jitter). To minimize this value, the highest possible reference frequencies should be used. Higher reference frequencies will minimize both the tpd parameter as well as the input to output jitter. 3.3V RS=5–15Ω VCCA 22µF MPC974 0.01µF VCC 0.01µF Power Supply Filtering The MPC974 is a mixed analog/digital product and exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MPC974 provides separate power supplies for the output buffers (VCCO) and the internal PLL (VCCA) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase–locked loop. In a controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCCA pin for the MPC974. TIMING SOLUTIONS BR1333 — Rev 6 Figure 4. Power Supply Filter Figure 4 illustrates a typical power supply filter scheme. The MPC974 is most susceptible to noise with spectral content in the 1KHz to 1MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin of the MPC974. From the data sheet the IVCCA current (the current sourced through the VCCA pin) is typically 15mA (20mA maximum), assuming that a minimum of 3.0V must be maintained on the VCCA pin very little DC voltage drop can be tolerated when a 3.3V VCC supply is used. The resistor shown in Figure 4 must have a resistance of 10–15Ω to meet 5 MOTOROLA MPC974 When taken to its extreme the fanout of the MPC974 clock driver is effectively doubled due to its capability to drive multiple lines. the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20KHz. As the noise frequency crosses the series resonant point of an individual capacitor it’s overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. The waveform plots of Figure 6 show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the MPC974 output buffers is more than sufficient to drive 50Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output–to–output skew of the MPC974. The output waveform in Figure 6 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 43Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: Although the MPC974 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Driving Transmission Lines The MPC974 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 10Ω the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091 in the Timing Solutions brochure (BR1333/D). 3.0 VOLTAGE (V) 2.5 OutA tD = 3.8956 OutB tD = 3.9386 2.0 In 1.5 1.0 MPC974 OUTPUT BUFFER IN 7Ω 0.5 RS = 43Ω ZO = 50Ω OutA 0 2 MPC974 OUTPUT BUFFER IN 6 8 TIME (nS) 10 12 14 Figure 6. Single versus Dual Waveforms RS = 43Ω ZO = 50Ω OutB0 7Ω VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V RS = 43Ω ZO = 50Ω At the load end the voltage will double, due to the near unity reflection coefficient, to 2.8V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). OutB1 Figure 5. Single versus Dual Transmission Lines Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 7 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. In most high performance clock networks point–to–point distribution of signals is the method of choice. In a point–to–point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50Ω resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC974 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 5 illustrates an output driving a single series terminated line vs two series terminated lines in parallel. MOTOROLA 4 SPICE level output buffer models are available for engineers who want to simulate their specific interconnect schemes. In addition IV characteristics are in the process of being generated to support the other board level simulators in general use. 6 TIMING SOLUTIONS BR1333 — Rev 6 MPC974 MPC974 OUTPUT BUFFER RS = 36Ω ZO = 50Ω RS = 36Ω ZO = 50Ω 7Ω 7Ω + 36Ω k 36Ω = 50Ω k 50Ω 25Ω = 25Ω Figure 7. Optimized Dual Line Termination TIMING SOLUTIONS BR1333 — Rev 6 7 MOTOROLA MPC974 OUTLINE DIMENSIONS FA SUFFIX TQFP PACKAGE CASE 848D-03 ISSUE C –X– X=L, M, N CL 4X 4X TIPS 0.20 (0.008) H L–M N AB G 0.20 (0.008) T L–M N AB 52 40 1 VIEW Y 39 3X VIEW Y –L– –M– B B1 13 V V1 S1 A S 4X θ2 0.10 (0.004) T –H– –T– SEATING PLANE 4X θ3 S W θ1 2XR R1 0.25 (0.010) C2 θ GAGE PLANE K C1 E Z VIEW AA MOTOROLA S N S NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4 DATUMS –L–, –M– AND –N– TO BE DETERMINED AT DATUM PLANE –H–. 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –T–. 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). VIEW AA 0.05 (0.002) D T L–M SECTION AB–AB –N– C M U ROTATED 90_ CLOCKWISE 26 A1 ÇÇÇÇ ÉÉÉÉ ÉÉÉÉ ÇÇÇÇ J 0.13 (0.005) 27 14 BASE METAL F PLATING 8 DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z θ θ1 θ2 θ3 MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC ––– 1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0_ 7_ ––– 0_ 12 _ REF 5_ 13 _ INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC ––– 0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0_ 7_ ––– 0_ 12 _ REF 5_ 13 _ TIMING SOLUTIONS BR1333 — Rev 6 MPC974 Motorola reserves the right to make changes without further notice to any products herein. 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