CYPRESS CY8C24633

CY8C24633
PSoC® Programmable System-on-Chip
Features
■
Powerful Harvard Architecture Processor
❐ M8C processor speeds to 24 MHz
❐ 8x8 multiply, 32-bit accumulate
❐ Low power at high speed
❐ 3.0 to 5.25V operating voltage
❐ Industrial temperature range: -40°C to +85°C
■
Advanced Peripherals (PSoC® Blocks)
❐ 4 Rail-to-Rail analog PSoC Blocks provide:
• Up to 14-bit ADCs
• Up to 8-bit DACs
• Programmable gain amplifiers
• Programmable filters and comparators
❐ 4 Digital PSoC Blocks provide:
• 8 to 32-bit timers, counters, and PWMs
• CRC and PRS modules
• Full-duplex UART
• Multiple SPI™ masters or slaves
• Connectable to all GPIO pins
❐ Complex peripherals by combining blocks
❐ High speed 8-bit SAR ADC optimized for motor control
■
Precision, Programmable Clocking
❐ Internal ±5% 24/48 MHz oscillator
❐ High accuracy 24 MHz with optional 32 kHz crystal and PLL
❐ Optional external oscillator, up to 24 MHz
❐ Internal oscillator for watchdog and sleep
Cypress Semiconductor Corporation
Document Number: 001-20160 Rev. *B
•
■
Flexible On-Chip Memory
❐ 8K Bytes Flash program storage 50,000 erase/write cycles
❐ 256 Bytes SRAM data storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash updates
❐ Flexible protection modes
❐ EEPROM emulation in Flash
■
Programmable Pin Configurations
❐ 25 mA sink on all GPIO
❐ Pull up, pull down, high z, strong, or open drain drive modes
on all GPIO
❐ Up to 10 analog inputs on GPIO
❐ Two 30 mA analog outputs on GPIO
❐ Configurable interrupt on all GPIO
■
Additional System Resources
2
❐ I C slave, master, and multi-master to 400 kHz
❐ Watchdog and sleep timers
❐ User-configurable low voltage detection
❐ Integrated supervisory circuit
❐ On chip precision voltage reference
■
Complete Development Tools
❐ Free development software (PSoC Designer™)
❐ Full-featured in-circuit emulator and programmer
❐ Full speed emulation
❐ Complex breakpoint structure
❐ 128K Bytes trace memory
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 16, 2009
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CY8C24633
Block Diagram
Port 3
Port 2
Port 1 Port 0
Analog
Drivers
PSoC CORE
System Bus
Global Digital Interconnect
SRAM
256 Bytes
SROM
Global Analog Interconnect
Flash 8K
CPUCore (M8C)
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
Analog
Block Array
2 Columns
4 Blocks
1 Row
4 Blocks
Digital
Clocks
Multiply
Accum.
ANALOG SYSTEM
SAR8 ADC
Decimator
I2C
Analog
Ref
Analog
Input
Muxing
POR and LVD
System Resets
Internal
Voltage
Ref.
SYSTEM RESOURCES
PSoC Functional Overview
The PSoC family consists of many programmable
system-on-chip with on-chip Controller devices. These devices
are designed to replace multiple traditional MCU-based system
components with one, low cost single-chip programmable
device. PSoC devices include configurable blocks of analog and
digital logic, as well as programmable interconnects. This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM
data memory, and configurable I/O are included in a range of
convenient pinouts and packages.
The PSoC Core
The PSoC architecture, as illustrated in the Block Diagram, is
comprised of four main areas: PSoC Core, Digital System,
Analog System, and System Resources. Configurable global
buses allows all the device resources to be combined into a
complete custom system. The PSoC CY8C24x33 family can
have up to three I/O ports that connect to the global digital and
analog interconnects, providing access to four digital blocks and
four analog blocks.
Memory encompasses 8 KB of Flash for program storage, 256
bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the Flash. Program Flash uses four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
Document Number: 001-20160 Rev. *B
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose I/O).
The M8C CPU core is a powerful processor with speeds up to 24
MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with 11 vectors,
to simplify programming of real time embedded events. Program
execution is timed and protected using the included Sleep and
Watch Dog Timers (WDT).
Page 2 of 35
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The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to
±5% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
Sleep timer and WDT. If crystal accuracy is desired, the ECO
(32.768 kHz external crystal oscillator) is available for use as a
Real Time Clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system
interrupt on high level, low level, and change from last read.
■
SPI master and slave (up to 1)
■
I2C slave and master (1 available as a System Resource)
■
Cyclical Redundancy Checker/Generator (8 to 32 bit)
■
IrDA (up to 1)
■
Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks are connected to any GPIO through a series
of global buses that route any signal to any pin. The buses also
allow signal multiplexing and performing logic operations. This
configurability frees your designs from the constraints of a fixed
peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in Table 1 on page 4.
The Digital System
The Analog System
The Digital System is composed of four digital PSoC blocks.
Each block is an 8-bit resource that can be used alone or
combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references.
The Analog system is composed of an 8-bit SAR ADC and four
configurable blocks. The programmable 8-bit SAR ADC is an
optimized ADC that runs up to 300 Ksps, with monotonic
guarantee. It also has the features to support a motor control
application.
Figure 1. Digital System Block Diagram
Port 3
Port 2
Port 1
To System Bus
Digital Clocks
FromCore
Each analog block is comprised of an opamp circuit allowing the
creation of complex analog signal flows. Analog peripherals are
very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog
functions (most available as user modules) are listed below.
Port 0
ToAnalog
System
DIGITAL SYSTEM
8
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
Row Output
Configuration
8
Row Input
Configuration
Digital PSoC Block Array
8
8
GOE[7:0]
GOO[7:0]
Digital peripheral configurations include those listed below.
■
PWMs (8 to 32 bit)
■
PWMs with Dead Band (8 to 32 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
UART 8 bit with selectable parity (up to 1)
Document Number: 001-20160 Rev. *B
■
Filters (2 and 4 pole band pass, low-pass, and notch)
■
Amplifiers (up to 2, with selectable gain to 48x)
■
Instrumentation amplifiers (1 with selectable gain to 93x)
■
Comparators (up to 2, with 16 selectable thresholds)
■
DACs (up to 2, with 6- to 9-bit resolution)
■
Multiplying DACs (up to 2, with 6- to 9-bit resolution)
■
High current output drivers (two with 30 mA drive as a Core
Resource)
■
1.3V reference (as a System Resource)
■
DTMF dialer
■
Modulators
■
Correlators
■
Peak detectors
■
Many other topologies possible
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks. The Analog Column 0 contains the SAR8 ADC block
rather than the standard SC blocks.
Page 3 of 35
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CY8C24633
Additional System Resources
Figure 2. Analog System Block Diagram
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
AGNDIn RefIn
P0[7]
P2[3]
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include a multiplier, decimator, low voltage
detection, and power on reset. Brief statements describing the
merits of each system resource are presented below.
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■
A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math as well
as digital filters.
■
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
■
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■
Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.
■
An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
P2[6]
P2[4]
P2[1]
P2[2]
P2[0]
Array Input Configuration
ACI1[1:0]
Block Array
ACB01
PSoC Device Characteristics
ASD11
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
3 analog blocks. The following table lists the resources available
for specific PSoC device groups.
ASC21
P0[7:0]
ACI2[3:0]
PSoC Part
Number
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SAR8
ADC
8-Bit SAR ADC
Digital
Blocks
Table 1. PSoC Device Characteristics
Digital
Rows
ACB00
Digital
I/O
ACI0[1:0]
CY8C29x66
up to
64
4
16
12
4
4
12
No
CY8C27x43
up to
44
2
8
12
4
4
12
No
CY8C24x94
56
1
4
48
2
2
6
No
CY8C24633
up to
25
1
4
12
2
2
4
Yes
CY8C24x23A
up to
24
1
4
12
2
2
6
No
CY8C21x34
up to
28
1
4
28
0
2
4[1]
No
CY8C21x23
16
1
4
8
0
2
4[1]
No
CY8C20x34
up to
28
0
0
28
0
0
3[2]
No
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Notes
1. Limited analog functionality.
2. Two analog blocks and one CapSense®.
Document Number: 001-20160 Rev. *B
Page 4 of 35
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CY8C24633
Getting Started
Development Tools
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
PSoC Designer is a Microsoft® Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.
For in depth information, along with detailed programming
details, see the PSoC Programmable System-on-Chip Technical
Reference Manual for CY8C24xxx PSoC devices.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at www.cypress.com/psoc.
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops) is available online at www.cypress.com/training. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various application designs that include firmware and hardware design files
that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party
assemblers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
PSoC Designer Software Subsystems
System-Level View
A drag-and-drop visual embedded system design environment
based on PSoC Express. In the system level view you create a
model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state
based upon any or all other system devices. Based upon the
design, PSoC Designer automatically selects one or more PSoC
On-Chip Controllers that match your system requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.4. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
blocks. Examples of user modules are ADCs, DACs, Amplifiers,
and Filters. Configure the user modules for your chosen
application and connect them to each other and to the proper
pins. Then generate your project. This prepopulates your project
with APIs and libraries that you can use to program your
application.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder, and common debug, emulation, and programming
tools.
Code Generation Tools
PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
Document Number: 001-20160 Rev. *B
Page 5 of 35
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C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
Debugger commands allow the designer to read and program
and read and write data memory, read and write I/O registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process can be summarized in the
following four steps:
1. Select components
2. Configure components
3. Organize and Connect
4. Generate, Verify, and Debug
Select Components
Both the system-level and chip-level views provide a library of
prebuilt, pretested hardware peripheral components. In the
system-level view, these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces
(I2C-bus, for example), and the logic to control how they interact
with one another (called valuators).
In the chip-level view, the components are called “user modules”.
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and mixed signal
varieties.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in the PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
Document Number: 001-20160 Rev. *B
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Organize and Connect
You can build signal chains at the chip level by interconnecting
user modules to each other and the I/O pins, or connect system
level inputs, outputs, and communication interfaces to each
other with valuator functions.
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this
document.
In the system-level view, selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog to
digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
Table 2. Acronyms Used
In the chip-level view, perform the selection, configuration, and
routing so that you have complete control over the use of all
on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Application” step. This causes PSoC Designer to generate
source code that automatically configures the device to your
specification and provides the software for the system.
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
control and respond to hardware events at run-time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
Acronym
Description
AC
alternating current
ADC
analog-to-digital converter
API
application programming interface
CPU
central processing unit
CT
continuous time
DAC
digital-to-analog converter
DC
direct current
EEPROM
electrically erasable programmable read-only
memory
FSR
full scale range
GPIO
general purpose I/O
I/O
input/output
IPOR
imprecise power on reset
LSb
least-significant bit
LVD
low voltage detect
MSb
most-significant bit
PC
program counter
POR
power on reset
PPOR
precision power on reset
PSoC
Programmable System-on-Chip
PWM
pulse width modulator
RAM
random access memory
ROM
read only memory
SC
switched capacitor
Units of Measure
A units of measure table is located in the Electrical Specifications
section. Table 7 on page 13 lists all the abbreviations used to
measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, ‘01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.
Document Number: 001-20160 Rev. *B
Page 7 of 35
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Pinouts
The PSoC CY8C24633 is available in 28-pin SSOP and 56-pin SSOP OCD packages. Refer to the following information for details.
Every port pin (labeled with a “P”), except Vss, Vdd, and XRES in the following tables and illustrations, is capable of Digital I/O.
28-Pin Part Pinout
The 28-pin part is for the CY8C24633 PSoC device.
Table 3. 28-Pin Part Pinout (SSOP)
Pin
No. Digital Analog
Pin
Name
Description
AIO, P0[7]
1
28
Vdd
IO, P0[5]
2
27
P0[6], AIO, AnColMux and ADC IP
IO, P0[3]
3
26
P0[4], AIO, AnColMux and ADC IP
AIO, P0[1]
4
25
P0[2], AIO, AnColMux and ADC IP
Analog Col Mux IP and Column
O/P and ADC IP
IO, P2[7]
5
24
P0[0], AIO, AnColMux and ADC IP
IO, P2[5]
6
23
P2[6], IO
P0[1]
Analog Col Mux IP and ADC IP
AIO, P2[3]
7
22
AIO, P2[1]
8
21
P2[4], IO
P2[2], AIO
1
I/O
I
P0[7]
Analog Col Mux IP and ADC IP
2
I/O
I/O
P0[5]
Analog Col Mux IP and Column
O/P and ADC IP
3
I/O
I/O
I
Figure 3. CY8C24633 PSoC Device
P0[3]
4
I/O
5
I/O
P2[7]
GPIO
AVref, IO, P3[0]
9
20
P2[0], AIO
6
I/O
P2[5]
GPIO
I2C SCL, IO, P1[7]
10
19
XRES
7
I/O
I
P2[3]
Direct switched capacitor input
I2C SDA, IO, P1[5]
11
18
P1[6], IO
IO, P1[3]
12
17
P1[4], IO, EXTCLK
8
I/O
I
P2[1]
Direct switched capacitor input
I2C SCL, ISSP SCL, XTALin, IO, P1[1]
13
16
P1[2], IO
Vss
14
15
P1[0], IO, XTALout, ISSP SDA, I2CSDA
I/O
10
I/O
P1[7]
I2C SCL
11
I/O
P1[5]
I2C SDA
P1[3]
GPIO
I/O
13
I/O
14
P3[0]
GPIO/ADC Vref (optional)
9
12
AVref
[3]
P1[1][4] GPIO, Xtal input, I2C SCL, ISSP
SCL
Power
Vss
Ground pin
P1[0][4] GPIO, Xtal output, I2C SDA, ISSP
SDA
15
I/O
16
I/O
P1[2]
17
I/O
P1[4]
GPIO, external clock IP
18
I/O
P1[6]
GPIO
XRES
External reset
19
GPIO
20
I/O
I
P2[0]
Direct switched capacitor input
21
I/O
I
P2[2]
Direct switched capacitor input
22
I/O
P2[4]
GPIO
23
I/O
P2[6]
GPIO
24
I/O
I
P0[0]
Analog Col Mux IP and ADC IP
25
I/O
I
P0[2]
Analog Col Mux IP and ADC IP
26
I/O
I
P0[4]
Analog Col Mux IP and ADC IP
27
I/O
I
P0[6]
Analog Col Mux IP and ADC IP
Vdd
Supply voltage
28
SSOP
Power
LEGEND A = Analog, I = Input, and O = Output
Notes
3. Even though P3[0] is an odd port, it resides on the left side of the pinout.
4. ISSP pin, which is not High Z at POR.
Document Number: 001-20160 Rev. *B
Page 8 of 35
[+] Feedback
CY8C24633
56-Pin Part Pinout
The 56-pin OCD (On-Chip Debug) part is for the CY8C24633 (CY8C24033) PSoC device.
Note OCD parts are only used for in-circuit debugging. OCD parts are NOT available for production.
Table 4. 56-Pin OCD Part Pinout (SSOP)
Pin
No.
Name
1
NC
2
P0[7]
Analog column mux input: AI
3
P0[5]
Analog column mux input and column output: AIO
4
P0[3]
Analog column mux input and column output: AIO
5
P0[1]
Analog column mux input: AI
6
P2[7]
7
P2[5]
8
P2[3]
Direct switched capacitor block input: AI
9
P2[1]
Direct switched capacitor block input: AI
10
NC
No internal connection
11
P3[0]
NC
No internal connection
13
NC
GPIO/ADC Vref (optional)
No internal connection
14
OCDE OCD even data I/O
15
OCDO OCD odd data output
16
NC
No internal connection
17
NC
No internal connection
18
NC
No internal connection
19
NC
No internal connection
20
NC
No internal connection
21
NC
No internal connection
22
NC
No internal connection
23
P1[7]
I2C Serial Clock (SCL)
24
P1[5]
I2C Serial Data (SDA)
25
NC
No internal connection
27
OCD
SSOP
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Vdd
P0[6],AI
P0[4],AIO
P0[2],AIO
P0[0],AI
P2[6],External VRef
P2[4],External AGND
P2[2],AI
P2[0],AI
NC
NC
NC
NC
CCLK
HCLK
XRES
NC
NC
NC
P3[1]
NC
NC
P1[6]
P1[4],EXTCLK
P1[2]
P1[0],XTALout,I2CSDA,SDATA
NC
NC
Not For Production
P1[3]
Vss
Ground connection
29
NC
No internal connection
NC
No internal connection
31
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
P1[1][5] Crystal (XTALin), I2C Serial Clock (SCL)
28
30
NC
AI,P0[7]
AIO,P0[5]
AIO,P0[3]
AI,P0[1]
P2[7]
P2[5]
AI,P2[3]
AI,P2[1]
NC
GPIO/ADC VRef,P3[0]
NC
NC
OCDE
OCDO
NC
NC
NC
NC
NC
NC
NC
I2CSCL, P1[7]
I2CSDA, P1[5]
NC
P1[3]
SCLK, I2CSCL, XTALin,P1[1]
Vss
No internal connection
12
26
Figure 4. CY8C24033 OCD PSoC Device
Description
P1[0][5] Crystal (XTALout), I2C Serial Data (SDA)
32
P1[2]
33
P1[4]
34
P1[6]
35
NC
36
NC
37
P3[1]
38
Optional External Clock Input (EXTCLK)
Pin No. Name
Description
44
NC
No internal connection
45
NC
No internal connection
46
NC
No internal connection
47
NC
No internal connection
No internal connection
48
P2[0] Direct switched capacitor block input: AI
No internal connection
49
P2[2] Direct switched capacitor block input: AI
GPIO
50
P2[4] External Analog Ground (AGND)
NC
No internal connection
51
P2[6] External Voltage Reference (VRef)
39
NC
No internal connection
52
P0[0] Analog column mux input: AI
40
NC
No internal connection
53
P0[2] Analog column mux input and column output: AIO
41
XRES Active high pin reset with internal pull down
54
P0[4]
Analog column mux input and column output: AIO
42
HCLK
OCD high speed clock output
55
P0[6]
Analog column mux input: AI
43
CCLK
OCD CPU clock output
56
Vdd
Supply voltage
LEGEND A = Analog, I = Input, O = Output.
Note
5. ISSP pin, which is not High Z at POR.
Document Number: 001-20160 Rev. *B
Page 9 of 35
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CY8C24633
Register Reference
This section lists the registers of the CY8C24633 PSoC device by using mapping tables, in offset order.
Register Conventions
Register Mapping Tables
The register conventions specific to this section are listed in the
following table.
The PSoC device has a total register address space of 512
bytes. The register space is referred to as I/O space and is
divided into two banks. The XIO bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XIO bit
is set the user is in Bank 1.
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Document Number: 001-20160 Rev. *B
Note In the following register mapping tables, blank fields are
reserved and should not be accessed.
Page 10 of 35
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CY8C24633
Table 5. Register Map Bank 0 Table: User Space
Name
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
Addr (0,Hex) Access
Name
00
RW
01
RW
02
RW
03
RW
04
RW
05
RW
06
RW
07
RW
08
RW
09
RW
0A
RW
0B
RW
0C
RW
0D
RW
0E
RW
0F
RW
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
DBB00DR0
20
#
AMX_IN
DBB00DR1
21
W
DBB00DR2
22
RW
DBB00CR0
23
#
ARF_CR
DBB01DR0
24
#
CMP_CR0
DBB01DR1
25
W
ASY_CR
DBB01DR2
26
RW
CMP_CR1
DBB01CR0
27
#
SARADC_DL
DCB02DR0
28
#
DCB02DR1
29
W
SARADC_C0
DCB02DR2
2A
RW
SARADC_C1
DCB02CR0
2B
#
DCB03DR0
2C
#
TMP_DR0
DCB03DR1
2D
W
TMP_DR1
DCB03DR2
2E
RW
TMP_DR2
DCB03CR0
2F
#
TMP_DR3
30
ACB00CR3
31
ACB00CR0
32
ACB00CR1
33
ACB00CR2
34
ACB01CR3
35
ACB01CR0
36
ACB01CR1 *
37
ACB01CR2 *
38
39
3A
3B
3C
3D
3E
3F
Blank fields are reserved.
# Access is bit specific.
Document Number: 001-20160 Rev. *B
Addr (0,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
Name
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
#
#
RW
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
Addr (0,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
Access
Name
RW
RW
RW
RW
RW
RW
RW
RW
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR3
INT_MSK3
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL0_X
MUL0_Y
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
ACC0_DR3
ACC0_DR2
RW
RW
RW
RW
RW
RW
RW
CPU_F
CPU_SCR1
CPU_SCR0
Addr (0,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
#
#
Page 11 of 35
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CY8C24633
Table 6. Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
Addr (1,Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
Addr (1,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
Name
RW
RW
RW
RW
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
RW
RW
RW
RW
OSC_GO_E
N
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
VLT_CMP
Addr (1,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
Access
DD
RW
RW
RW
RW
RW
RW
RW
R
RW
RW
RW
RW
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
RW
IMO_TR
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
A9
RW
ILO_TR
E9
W
DCB02FN
RW
29
RW
69
DCB02OU
2A
RW
6A
RW
RW
RW
RW
RW
RW
CLK_CR0
CLK_CR1
ABF_CR0
AMD_CR0
AMD_CR1
ALT_CR0
2B
DCB03FN
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
Access
9D
DCB02IN
DCB03IN
DCB03OU
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
Addr (1,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
5D
5E
5F
60
61
62
63
64
65
66
67
68
DBB01FN
DBB01IN
DBB01OU
Name
1D
1E
1F
20
21
22
23
24
25
26
27
28
DBB00FN
DBB00IN
DBB00OU
Access
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
Blank fields are reserved.
RW
RW
RW
RW
RW
RW
SARADC_TRS
SARADC_TRC
L
SARADC_TRC
H
W
AA
RW
BDG_TR
EA
RW
6B
SARADC_C
2
AB
#
ECO_TR
EB
W
SARADC_LC
R
AC
RW
RW
TMP_DR0
6C
RW
RW
RW
TMP_DR1
TMP_DR2
TMP_DR3
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2 *
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
EC
RW
RW
RW
RW
RW
RW
RW
CPU_F
FLS_PR1
CPU_SCR1
CPU_SCR0
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RL
RW
#
#
# Access is bit specific.
Document Number: 001-20160 Rev. *B
Page 12 of 35
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CY8C24633
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C24633 PSoC device. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.
Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted.
Refer to Table 23 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.
Figure 5a. IMO Frequency Trim Options
5.25
SLIMO Mode = 0
Figure 5. Voltage versus CPU Frequency
5.25
4.75
Vdd Voltage
Vdd Voltage
l id g
Va ratin n
pe io
O Reg
4.75
SLIMO
Mode=1
SLIMO
Mode=0
SLIMO
Mode=1
SLIMO
Mode=0
3.60
3.00
3.00
93 kHz
12 MHz
3 MHz
93 kHz
24 MHz
6 MHz
12 MHz
24 MHz
IMO Frequency
CPU Frequency
The following table lists the units of measure that are used in this section.
Table 7. Units of Measure
Symbol
oC
dB
fF
Hz
KB
Kbit
kHz
kΩ
MHz
MΩ
μA
μF
μH
μs
μV
μVrms
Unit of Measure
degree Celsius
decibels
femto farad
hertz
1024 bytes
1024 bits
kilohertz
kilohm
megahertz
megaohm
micro ampere
micro farad
micro henry
microsecond
micro volts
micro volts root-mean-square
Document Number: 001-20160 Rev. *B
Symbol
μW
mA
ms
mV
nA
ns
nV
Ω
pA
pF
pp
ppm
ps
sps
σ
V
Unit of Measure
micro watts
milli-ampere
milli-second
milli-volts
nano ampere
nanosecond
nanovolts
ohm
pico ampere
pico farad
peak-to-peak
parts per million
picosecond
samples per second
sigma: one standard deviation
volts
Page 13 of 35
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CY8C24633
Absolute Maximum Ratings
Table 8. Absolute Maximum Ratings
Symbol
Description
TSTG
Storage Temperature
TA
Vdd
VIO
VIOZ
IMIO
ESD
LU
Ambient Temperature with Power Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
DC Voltage Applied to Tri-state
Maximum Current into any Port Pin
Electro Static Discharge Voltage
Latch Up Current
Min
-55
Typ
25
-40
-0.5
Vss - 0.5
Vss - 0.5
-25
2000
–
–
–
–
–
–
–
–
Max
+100
Units
Notes
o
C Higher storage temperatures reduce
data retention time. Recommended
storage temperature is +25oC ±
25oC. Extended duration storage
temperatures above 65oC degrade
reliability.
o
+85
C
+6.0
V
Vdd + 0.5
V
Vdd + 0.5
V
+50
mA
–
V
Human Body Model ESD.
200
mA
Operating Temperature
Table 9. Operating Temperature
Min
Typ
Max
Units
TA
Symbol
Ambient Temperature
Description
-40
–
+85
oC
TJ
Junction Temperature
-40
–
+100
oC
Document Number: 001-20160 Rev. *B
Notes
The temperature rise from ambient to
junction is package specific. See
Thermal Impedances by Package on
page 34. The user must limit the
power consumption to comply with
this requirement.
Page 14 of 35
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CY8C24633
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10. DC Chip-Level Specifications
Symbol
Description
Vdd
Supply Voltage
IDD
Supply Current
Min
3.0
–
Typ
–
5
Max
5.25
8
Units
V
mA
IDD3
Supply Current
–
3.3
6.0
mA
ISB
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT.[6]
–
3
6.5
μA
ISBH
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT at high temperature.[6]
–
4
25
μA
ISBXTL
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and external crystal.[6]
–
4
7.5
μA
ISBXTLH
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and external crystal at high
temperature.[6]
–
5
26
μA
VREF
Reference Voltage (Bandgap)
1.28
1.30
1.33
V
Notes
See Table 20 on page 21.
Conditions are Vdd = 5.0V, TA = 25 oC,
CPU = 3 MHz, SYSCLK doubler
disabled, VC1 = 1.5 MHz, VC2 = 93.75
kHz, VC3 = 93.75 kHz, analog power
= off. SLIMO mode = 0. IMO = 24 MHz.
Conditions are Vdd = 3.3V, TA = 25 oC,
CPU = 3 MHz, SYSCLK doubler
disabled, VC1 = 1.5 MHz, VC2 = 93.75
kHz, VC3 = 93.75 kHz, analog power
= off. SLIMO mode = 0. IMO = 24 MHz.
Conditions are with internal slow
speed oscillator, Vdd = 3.3V, -40 oC ≤
TA ≤ 55oC, analog power = off.
Conditions are with internal slow
speed oscillator, Vdd = 3.3V, 55 oC <
TA ≤ 85oC, analog power = off.
Conditions are with properly loaded, 1
μW max, 32.768 kHz crystal. Vdd =
3.3V, -40 oC ≤ TA ≤ 55oC, analog
power = off.
Conditions are with properly loaded,
1μW max, 32.768 kHz crystal. Vdd =
3.3 V, 55 oC < TA ≤ 85oC, analog power
= off.
Trimmed for appropriate Vdd.
Vdd > 3.0V.
Note
6. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have
similar functions enabled.
Document Number: 001-20160 Rev. *B
Page 15 of 35
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CY8C24633
DC General Purpose I/O Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 11. 5V and 3.3V DC GPIO Specifications
Symbol
Description
Pull Up Resistor
RPU
Pull Down Resistor
RPD
High Output Level
VOH
Min
4
4
Vdd - 1.0
Typ
5.6
5.6
–
Max
8
8
–
Units
kΩ
kΩ
V
VOL
Low Output Level
–
–
0.75
V
VIL
VIH
VH
IIL
CIN
Input Low Level
Input High Level
Input Hysterisis
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
–
2.1
–
–
–
–
–
60
1
3.5
0.8
–
–
10
V
V
mV
nA
pF
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF
Document Number: 001-20160 Rev. *B
Notes
IOH = 10 mA, Vdd = 4.75 to 5.25V
(maximum 40 mA on even port pins
(for example, P0[2], P1[4]), maximum
40 mA on odd port pins (for example,
P0[3], P1[5])). 80 mA maximum
combined IOH budget.
IOL = 25 mA, Vdd = 4.75 to 5.25V
(maximum 100 mA on even port pins
(for example, P0[2], P1[4]), maximum
100 mA on odd port pins (for example,
P0[3], P1[5])). 100 mA maximum
combined IOH budget.
Vdd = 3.0 to 5.25.
Vdd = 3.0 to 5.25.
Gross tested to 1 μA.
Package and pin dependent. Temp =
25oC.
Package and pin dependent. Temp =
25oC.
Page 16 of 35
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CY8C24633
DC Operational Amplifier Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at
25°C and are for design guidance only.
Table 12. 5V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Average Input Offset Voltage Drift
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
Min
Typ
Max
Units
–
–
–
–
–
–
1.6
1.3
1.2
7.0
20
4.5
10
8
7.5
35.0
–
9.5
VCMOA
Common Mode Voltage Range
Common Mode Voltage Range (high power
or high opamp bias)
0.0
0.5
–
–
Vdd
Vdd 0.5
GOLOA
Open Loop Gain
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
High Output Voltage Swing (internal
signals)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Low Output Voltage Swing (internal
signals)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Supply Current (including associated
AGND buffer)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
Supply Voltage Rejection Ratio
–
–
mV
mV
mV
μV/oC
pA
Gross tested to 1 μA.
pF
Package and pin dependent. Temp =
25oC.
V
The common-mode input voltage
range is measured through an
analog output buffer. The specification includes the limitations
imposed by the characteristics of the
analog output buffer.
dB
Specification is applicable at high
power. For all other bias modes
(except high power, high opamp
bias), minimum is 60 dB.
Vdd - 0.2
Vdd - 0.2
Vdd - 0.5
–
–
–
–
–
–
V
V
V
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
–
–
–
–
–
300
600
1200
2400
4600
400
800
1600
3200
6400
μA
μA
μA
μA
μA
52
80
–
dB
TCVOSOA
IEBOA
CINOA
VOHIGHOA
VOLOWOA
ISOA
PSRROA
Document Number: 001-20160 Rev. *B
60
60
80
Notes
Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd 1.25V) ≤ VIN ≤ Vdd.
Page 17 of 35
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CY8C24633
Table 13. 3.3V DC Operational Amplifier Specifications
Symbol
Min
Typ
Max
Units
–
–
1.65
1.32
10
8
mV
mV
TCVOSOA Average Input Offset Voltage Drift
–
7.0
35.0
μV/oC
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
20
–
pA
Gross tested to 1 μA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent. Temp
= 25oC.
VCMOA
Common Mode Voltage Range
0.2
–
Vdd 0.2
V
The common-mode input voltage
range is measured through an
analog output buffer. The specification includes the limitations
imposed by the characteristics of the
analog output buffer.
GOLOA
Open Loop Gain
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High, Opamp Bias = Low
–
–
dB
60
60
80
Specification is applicable at high
power. For all other bias modes
(except high power, high opamp
bias), minimum is 60 dB.
Vdd 0.2
Vdd 0.2
Vdd 0.2
–
–
–
–
–
–
V
V
V
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
VOSOA
Description
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
High Power is 5V Only
VOHIGHOA High Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High is 5V only
VOLOWOA Low Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High, Opamp Bias = Low
ISOA
Supply Current (including associated AGND
buffer)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
–
–
–
–
–
300
600
1200
2400
4600
400
800
1600
3200
6400
μA
μA
μA
μA
μA
PSRROA
Supply Voltage Rejection Ratio
52
80
–
dB
Notes
Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd 1.25V) ≤ VIN ≤ Vdd..
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 14. DC Low Power Comparator Specifications
Symbol
VREFLPC
ISLPC
VOSLPC
Description
Low power comparator (LPC) reference
voltage range
LPC supply current
LPC voltage offset
Document Number: 001-20160 Rev. *B
Min
0.2
Typ
–
Max
Vdd - 1
Units
V
–
–
10
2.5
40
30
μA
mV
Notes
Page 18 of 35
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CY8C24633
DC Analog Output Buffer Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 15. 5V DC Analog Output Buffer Specifications
Symbol
VOSOB
TCVOSOB
VCMOB
ROUTOB
Description
Input Offset Voltage (Absolute Value)
Average Input Offset Voltage Drift
Common-Mode Input Voltage Range
Output Resistance
Power = Low
Power = High
VOHIGHOB High Output Voltage Swing (Load = 32Ω to
Vdd/2)
Power = Low
Power = High
VOLOWOB Low Output Voltage Swing (Load = 32Ω to
Vdd/2)
Power = Low
Power = High
ISOB
PSRROB
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
Supply Voltage Rejection Ratio
Min
–
–
0.5
Typ
3
+6
–
Max
12
–
Vdd - 1.0
Units
mV
μV/°C
V
–
–
1
1
–
–
W
W
0.5 x Vdd +
1.1
0.5 x Vdd +
1.1
–
–
–
–
V
V
–
–
–
–
0.5 x Vdd 1.3
0.5 x Vdd 1.3
V
V
–
–
52
1.1
2.6
64
5.1
8.8
–
mA
mA
dB
Min
–
–
0.5
Typ
3
+6
-
Max
12
–
Vdd - 1.0
Units
mV
μV/°C
V
–
–
1
1
–
–
W
W
0.5 x Vdd +
1.0
0.5 x Vdd +
1.0
–
–
–
–
V
V
Notes
VOUT > (Vdd - 1.25).
Table 16. 3.3V DC Analog Output Buffer Specifications
Symbol
VOSOB
TCVOSOB
VCMOB
ROUTOB
VOHIGHOB
Description
Input Offset Voltage (Absolute Value)
Average Input Offset Voltage Drift
Common-Mode Input Voltage Range
Output Resistance
Power = Low
Power = High
High Output Voltage Swing (Load = 1 kΩ to
Vdd/2)
Power = Low
Power = High
VOLOWOB
Low Output Voltage Swing (Load = 1 kΩ to
Vdd/2)
Power = Low
Power = High
–
–
–
–
0.5 x Vdd 1.0
0.5 x Vdd 1.0
V
V
ISOB
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
Supply Voltage Rejection Ratio
–
–
52
0.8
2.0
64
2.0
4.3
–
mA
mA
dB
PSRROB
Document Number: 001-20160 Rev. *B
Notes
VOUT > (Vdd - 1.25).
Page 19 of 35
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CY8C24633
DC Analog Reference Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 17. 5V DC Analog Reference Specifications
Symbol
BG
–
–
–
–
–
–
–
–
–
Description
Bandgap Voltage Reference
AGND = Vdd/2
AGND = 2 x BandGap
AGND = P2[4] (P2[4] = Vdd/2)
AGND = BandGap
AGND = 1.6 x BandGap
AGND Block to Block Variation (AGND = Vdd/2)
RefHi = Vdd/2 + BandGap
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
–
–
–
–
–
–
–
–
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
RefHi = 3.2 x BandGap
RefLo = Vdd/2 – BandGap
RefLo = BandGap
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
Min
1.28
Vdd/2 - 0.04
2 x BG - 0.048
P2[4] - 0.011
BG - 0.009
1.6 x BG - 0.022
-0.034
Vdd/2 + BG - 0.10
3 x BG - 0.06
2 x BG + P2[6] - 0.113
Typ
1.30
Vdd/2 - 0.01
2 x BG - 0.030
P2[4]
BG + 0.008
1.6 x BG - 0.010
0.000
Vdd/2 + BG
3 x BG
2 x BG + P2[6] - 0.018
Max
1.33
Vdd/2 + 0.007
2 x BG + 0.024
P2[4] + 0.011
BG + 0.016
1.6 x BG + 0.018
0.034
Vdd/2 + BG + 0.10
3 x BG + 0.06
2 x BG + P2[6] +
0.077
P2[4] + BG - 0.130
P2[4] + BG - 0.016
P2[4] + BG + 0.098
P2[4] + P2[6] - 0.133 P2[4] + P2[6] - 0.016 P2[4] + P2[6]+ 0.100
3.2 x BG - 0.112
3.2 x BG
3.2 x BG + 0.076
Vdd/2 - BG - 0.04
Vdd/2 - BG + 0.024
Vdd/2 - BG + 0.04
BG - 0.06
BG
BG + 0.06
2 x BG - P2[6] - 0.084 2 x BG - P2[6] + 0.025 2 x BG - P2[6] + 0.134
P2[4] - BG - 0.056
P2[4] - BG + 0.026
P2[4] - BG + 0.107
P2[4] - P2[6] - 0.057 P2[4] - P2[6] + 0.026 P2[4] - P2[6] + 0.110
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Table 18. 3.3V DC Analog Reference Specifications
Symbol
BG
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Description
Bandgap Voltage Reference
AGND = Vdd/2
AGND = 2 x BandGap
AGND = P2[4] (P2[4] = Vdd/2)
AGND = BandGap
AGND = 1.6 x BandGap
AGND Column to Column Variation (AGND = Vdd/2)
RefHi = Vdd/2 + BandGap
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
RefHi = 3.2 x BandGap
RefLo = Vdd/2 - BandGap
RefLo = BandGap
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
Document Number: 001-20160 Rev. *B
Min
1.28
Vdd/2 - 0.03
Not Allowed
P2[4] - 0.008
BG - 0.009
1.6 x BG - 0.027
-0.034
Not Allowed
Not Allowed
Not Allowed
Not Allowed
P2[4] + P2[6] - 0.075
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
P2[4] - P2[6] - 0.048
Typ
1.30
Vdd/2 - 0.01
Max
1.33
Vdd/2 + 0.005
V
V
Units
P2[4] + 0.001
BG + 0.005
1.6 x BG - 0.010
0.000
P2[4] + 0.009
BG + 0.015
1.6 x BG + 0.018
0.034
V
V
V
mV
P2[4] + P2[6] - 0.009 P2[4] + P2[6] + 0.057 V
P2[4]- P2[6] + 0.022
P2[4] - P2[6] + 0.092 V
Page 20 of 35
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CY8C24633
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 19. DC Analog PSoC Block Specifications
Symbol
RCT
Description
Resistor Unit Value (Continuous Time)
Min
–
Typ
12.2
Max
–
Units
kΩ
Notes
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register.
Table 20. DC POR and LVD Specifications
Symbol
Description
VPPOR0
VPPOR1
VPPOR2
Vdd Value for PPOR Trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
Min
Typ
Max
Units
Notes
Vdd must be greater than or equal
to 2.5V during startup, reset from
the XRES pin, or reset from
Watchdog.
–
2.36
2.82
4.55
2.40
2.95
4.70
V
V
V
2.40
2.85
2.95
3.06
4.37
4.50
4.62
4.71
2.45
2.92
3.02
3.13
4.48
4.64
4.73
4.81
2.51[7]
2.99[8]
3.09
3.20
4.55
4.75
4.83
4.95
V
V
V
V
V
V
V
V
Notes
7. Always greater than 50 mV above VPPOR (PORLEV=00) for falling supply.
8. Always greater than 50 mV above VPPOR (PORLEV=01) for falling supply.
Document Number: 001-20160 Rev. *B
Page 21 of 35
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CY8C24633
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 21. DC Programming Specifications
Symbol
VddIWRITE
IDDP
VILP
VIHP
IILP
IIHP
VOLV
VOHV
FlashENPB
FlashENT
FlashDR
Description
Min
Supply Voltage for Flash Write Operations
3.3
Supply Current During Programming or Verify
–
Input Low Voltage During Programming or
–
Verify
Input High Voltage During Programming or
2.1
Verify
Input Current when Applying Vilp to P1[0] or
–
P1[1] During Programming or Verify
Input Current when Applying Vihp to P1[0] or
–
P1[1] During Programming or Verify
Output Low Voltage During Programming or
–
Verify
Output High Voltage During Programming or Vdd - 1.0
Verify
Flash Endurance (per block)
50,000
Flash Endurance (total)[9]
1,800,0
00
Flash Data Retention
10
Typ
–
5
–
Max
–
25
0.8
Units
V
mA
V
–
–
V
–
0.2
mA
–
1.5
mA
–
V
–
Vss +
0.75
Vdd
–
–
–
–
–
–
–
–
Years
Notes
Driving internal pull down
resistor.
Driving internal pull down
resistor.
V
Erase/write cycles per block.
Erase/write cycles.
SAR8 ADC DC Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 22. SAR8 ADC DC Specifications
Symbol
VADCVREF
Description
Reference voltage at pin P3[0] when
configured as ADC reference voltage
IADCVREF
Current when P3[0] is configured as ADC VREF
INL
R-2R Integral Non-linearity[10]
DNL
R-2R Differential Non-linearity[11]
Min
Typ
Max
Units
Notes
3.0
–
5.25
V
The voltage level at P3[0]
(when configured as ADC
reference voltage) should
always be maintained to be
less than chip supply voltage
level on Vdd pin. VADCVREF <
Vdd.
3
–
–
mA
-1.2
–
+1.2
LSB
The maximum LSB is over a
sub-range not exceeding
1/16 of the full-scale range.
-1
–
+1
LSB
Output is monatonic.
Notes
9. A maximum of 36 x 50,000 block endurance cycles is allowed. This can be balanced between operations on 36x1 blocks of 50,000 maximum cycles each,
36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no
single block ever sees more than 50,000 cycles).
For the full industrial range, use a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the
Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
10. At the 7F and 80 points, the maximum INL is 1.5 LSB.
11. For the 7F to 80 transition, the DNL specification is waived.
Document Number: 001-20160 Rev. *B
Page 22 of 35
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CY8C24633
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 23. 5V and 3.3V AC Chip-Level Specifications
Symbol
FIMO24
Description
Internal Main Oscillator Frequency for 24 MHz
Min
22.8
Typ
24
Max
25.2[12],[13],[14]
Units
MHz
FIMO6
Internal Main Oscillator Frequency for 6 MHz
5.75
6
6.35[12],[13],[14]
MHz
FCPU1
FCPU2
F48M
F24M
F32K1
F32K2
CPU Frequency (5V Nominal)
CPU Frequency (3.3V Nominal)
Digital PSoC Block Frequency
Digital PSoC Block Frequency
Internal Low Speed Oscillator Frequency
External Crystal Oscillator
0.093
0.093
0
0
15
–
24
12
48
24
32
32.768
24.6[12],[13]
12.3[13],[14]
49.2[12],[13],[15]
24.6[13],[15]
75
–
MHz
MHz
MHz
MHz
kHz
kHz
FPLL
PLL Frequency
–
23.986
–
MHz
–
0.5
0.5
–
–
–
600
10
50
ps
ms
ms
Jitter24M2
24 MHz Period Jitter (PLL)
TPLLSLEW
PLL Lock Time
TPLLSLEWSL PLL Lock Time for Low Gain Setting
Notes
Trimmed for 5V or 3.3V operation
using factory trim values. See Figure
5b on page 13. SLIMO mode = 0.
Trimmed for 5V or 3.3V operation
using factory trim values. See Figure
5b on page 13. SLIMO mode = 1.
Refer to the Table 28 on page 28.
Accuracy is capacitor and crystal
dependent. 50% duty cycle.
Is a multiple (x732) of crystal
frequency.
OW
TOS
TOSACC
External Crystal Oscillator Startup to 1%
External Crystal Oscillator Startup to 100 ppm
–
–
1700
2800
2620
3800
ms
ms
Jitter32k
TXRST
DC24M
Step24M
Fout48M
Jitter24M1R
FMAX
32 kHz Period Jitter
External Reset Pulse Width
24 MHz Duty Cycle
24 MHz Trim Step Size
48 MHz Output Frequency
24 MHz Period Jitter (IMO) Root Mean Squared
Maximum frequency of signal on row input or
row output.
Supply Ramp Time
–
10
40
–
46.8
–
–
100
–
50
50
48.0
–
–
–
60
–
49.2[12],[14]
600
12.3
ns
μs
%
kHz
MHz
ps
MHz
0
–
–
μs
TRAMP
The crystal oscillator frequency is
within 100 ppm of its final value by the
end of the Tosacc period. Correct
operation assumes a properly loaded
1 uW maximum drive level 32.768
kHz crystal. 3.0V ≤ Vdd ≤ 5.5V, -40 oC
≤ TA ≤ 85 oC.
Trimmed. Utilizing factory trim values.
Notes
12. 4.75V < Vdd < 5.25V.
13. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
14. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for
operation at 3.3V.
15. See the individual user module data sheets for information on maximum frequencies for user modules.
Document Number: 001-20160 Rev. *B
Page 23 of 35
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CY8C24633
Figure 6. PLL Lock Timing Diagram
PLL
Enable
TPLLSLEW
24 MHz
FPLL
PLL
Gain
0
Figure 7. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
TPLLSLEWLOW
24 MHz
FPLL
PLL
Gain
1
Figure 8. External Crystal Oscillator Startup Timing Diagram
32K
Select
32 kHz
TOS
F32K2
Figure 9. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F 24M
Figure 10. 32 kHz Period Jitter (ECO) Timing Diagram
Jitter32k
F 32K2
Document Number: 001-20160 Rev. *B
Page 24 of 35
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CY8C24633
AC General Purpose I/O Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 24. 5V and 3.3V AC GPIO Specifications
Symbol
FGPIO
TRiseF
TFallF
TRiseS
TFallS
Description
GPIO Operating Frequency
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
Min
0
3
2
10
10
Typ
–
–
–
27
22
Max
12
18
18
–
–
Units
MHz
ns
ns
ns
ns
Notes
Normal Strong Mode
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Figure 11. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
Document Number: 001-20160 Rev. *B
TFallF
TFallS
Page 25 of 35
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CY8C24633
AC Operational Amplifier Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.
Table 25. 5V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
Description
Rising Settling Time from 80% of ΔV to 0.1% of
ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Settling Time from 20% of ΔV to 0.1%
of ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Rising Slew Rate (20% to 80%)(10 pF load,
Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Slew Rate (20% to 80%)(10 pF load,
Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Min
Typ
Max
Units
–
–
–
–
–
–
3.9
0.72
0.62
μs
μs
μs
–
–
–
–
–
–
5.9
0.92
0.72
μs
μs
μs
0.15
1.7
6.5
–
–
–
–
–
–
V/μs
V/μs
V/μs
0.01
0.5
4.0
–
–
–
–
–
–
V/μs
V/μs
V/μs
0.75
3.1
5.4
–
–
–
–
–
–
MHz
MHz
MHz
Min
Typ
Max
Units
–
–
–
–
3.92
0.72
μs
μs
–
–
–
–
5.41
0.72
μs
μs
0.31
2.7
–
–
–
–
V/μs
V/μs
0.24
1.8
–
–
–
–
V/μs
V/μs
0.67
2.8
–
–
–
–
MHz
MHz
Notes
Table 26. 3.3V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
Description
Rising Settling Time from 80% of ΔV to 0.1% of
ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Falling Settling Time from 20% of ΔV to 0.1%
of ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Rising Slew Rate (20% to 80%)(10 pF load,
Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Falling Slew Rate (20% to 80%)(10 pF load,
Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Document Number: 001-20160 Rev. *B
Notes
Page 26 of 35
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CY8C24633
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 12. Typical AGND Noise with P2[4] Bypass
dBV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 13. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
Document Number: 001-20160 Rev. *B
0.01
0.1
Freq (kHz)
1
10
100
Page 27 of 35
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CY8C24633
AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 27. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Min
–
Typ
–
Max
50
Units
μs
Notes
≥ 50 mV overdrive comparator
reference set within VREFLPC.
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 28. 5V and 3.3V AC Digital Block Specifications
Symbol
Min
Typ
Max
Units
50[16]
–
–
ns
Maximum Frequency, No Capture
–
–
49.2
MHz
Maximum Frequency, With Capture
–
–
24.6
MHz
50[16]
–
–
ns
Maximum Frequency, No Enable Input
–
–
49.2
MHz
Maximum Frequency, Enable Input
–
–
24.6
MHz
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50[16]
–
–
ns
Disable Mode
50[16]
–
–
ns
Maximum Frequency
–
–
49.2
MHz
4.75V < Vdd < 5.25V.
CRCPRS Maximum Input Clock Frequency
(PRS
Mode)
–
–
49.2
MHz
4.75V < Vdd < 5.25V.
CRCPRS Maximum Input Clock Frequency
(CRC
Mode)
–
–
24.6
MHz
SPIM
Maximum Input Clock Frequency
–
–
8.2
MHz
SPIS
Maximum Input Clock Frequency
–
–
4.1
MHz
Width of SS_ Negated Between Transmissions
[16]
–
–
ns
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum Input Clock Frequency with Vdd Š
4.75V, 2 Stop Bits
–
–
49.2
MHz
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum Input Clock Frequency with Vdd Š
4.75V, 2 Stop Bits
–
–
49.2
MHz
Timer
Counter
Dead
Band
Transmitter
Receiver
Description
Capture Pulse Width
Enable Pulse Width
Notes
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
Kill Pulse Width:
50
Maximum data rate at 4.1 MHz due to
2 x over clocking.
Maximum data rate at 3.08 MHz due
to 8 x over clocking.
Maximum data rate at 6.15 MHz due
to 8 x over clocking.
Maximum data rate at 3.08 MHz due
to 8 x over clocking.
Maximum data rate at 6.15 MHz due
to 8 x over clocking.
Note
16. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-20160 Rev. *B
Page 28 of 35
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CY8C24633
AC Analog Output Buffer Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 29. 5V AC Analog Output Buffer Specifications
Symbol
Description
TROB
Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
TSOB
Falling Settling Time to 0.1%, 1V Step, 100 pF
Load
Power = Low
Power = High
SRROB Rising Slew Rate (20% to 80%), 1V Step, 100 pF
Load
Power = Low
Power = High
SRFOB
Falling Slew Rate (80% to 20%), 1V Step, 100 pF
Load
Power = Low
Power = High
BWOB
Small Signal Bandwidth, 20 mVpp, 3dB BW, 100
pF Load
Power = Low
Power = High
BWOB
Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF
Load
Power = Low
Power = High
Min
Typ
Max
Units
–
–
–
–
2.5
2.5
μs
μs
–
–
–
–
2.2
2.2
μs
μs
0.65
0.65
–
–
–
–
V/μs
V/μs
0.65
0.65
–
–
–
–
V/μs
V/μs
0.8
0.8
–
–
–
–
MHz
MHz
300
300
–
–
–
–
kHz
kHz
Min
Typ
Max
Units
–
–
–
–
3.8
3.8
μs
μs
–
–
–
–
2.6
2.6
μs
μs
0.5
0.5
–
–
–
–
V/μs
V/μs
0.5
0.5
–
–
–
–
V/μs
V/μs
0.7
0.7
–
–
–
–
MHz
MHz
200
200
–
–
–
–
kHz
kHz
Notes
Table 30. 3.3V AC Analog Output Buffer Specifications
Symbol
Description
TROB
Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
TSOB
Falling Settling Time to 0.1%, 1V Step, 100 pF
Load
Power = Low
Power = High
SRROB Rising Slew Rate (20% to 80%), 1V Step, 100 pF
Load
Power = Low
Power = High
SRFOB
Falling Slew Rate (80% to 20%), 1V Step, 100 pF
Load
Power = Low
Power = High
BWOB
Small Signal Bandwidth, 20 mVpp, 3dB BW, 100 pF
Load
Power = Low
Power = High
BWOB
Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF
Load
Power = Low
Power = High
Document Number: 001-20160 Rev. *B
Notes
Page 29 of 35
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CY8C24633
AC External Clock Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 31. 5V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency
0.093
–
24.6
MHz
–
High Period
20.6
–
5300
ns
–
Low Period
20.6
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Notes
Table 32. 3.3V AC External Clock Specifications
Min
Typ
Max
Units
FOSCEXT
Symbol
Frequency with CPU Clock divide by 1[17]
Description
0.093
–
12.3
MHz
FOSCEXT
Frequency with CPU Clock divide by 2 or
greater[18]
0.186
–
24.6
MHz
–
High Period with CPU Clock divide by 1
41.7
–
5300
ns
–
Low Period with CPU Clock divide by 1
41.7
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Notes
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 33. AC Programming Specifications
Symbol
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
TERASEB
TWRITE
TDSCLK
TDSCLK3
Description
Rise Time of SCLK
Fall Time of SCLK
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Min
1
1
40
40
0
–
–
–
–
Typ
–
–
–
–
–
20
20
–
–
Max
20
20
–
–
8
–
–
45
50
Units
ns
ns
ns
ns
MHz
ms
ms
ns
ns
Notes
Vdd > 3.6
3.0 ≤ Vdd ≤ 3.6
Notes
17. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle
requirements.
18. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that
the fifty percent duty cycle requirement is met.
Document Number: 001-20160 Rev. *B
Page 30 of 35
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CY8C24633
SAR8 ADC AC Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 34. SAR8 ADC AC Specifications
Symbol
Description
Min
Typ
Max
Units
Freq3
Input clock frequency 3V
–
–
3.0
MHz
Freq5
Input clock frequency 5V
–
–
3.0
MHz
Notes
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 35. AC Characteristics of the I2C SDA and SCL Pins for Vdd > 3.0V
Symbol
Description
SCL Clock Frequency
FSCLI2C
THDSTAI2C Hold Time (repeated) START Condition. After
this period, the first clock pulse is generated.
LOW Period of the SCL Clock
TLOWI2C
HIGH Period of the SCL Clock
THIGHI2C
TSUSTAI2C Set-up Time for a Repeated START Condition
THDDATI2C Data Hold Time
TSUDATI2C Data Set-up Time
TSUSTOI2C Set-up Time for STOP Condition
TBUFI2C
Bus Free Time Between a STOP and START
Condition
Pulse Width of spikes are suppressed by the
TSPI2C
input filter.
Standard Mode
Min
Max
0
100
4.0
–
Fast Mode
Min
Max
0
400
0.6
–
Units
Notes
kHz
μs
4.7
4.0
4.7
0
250
4.0
4.7
–
–
–
–
–
–
–
1.3
0.6
0.6
0
100[19]
0.6
1.3
–
–
–
–
–
–
–
μs
μs
μs
μs
ns
μs
μs
–
–
0
50
ns
Table 36. AC Characteristics of the I2C SDA and SCL Pins for Vdd < 3.0V (Fast Mode Not Supported)
Symbol
Description
SCL Clock Frequency
FSCLI2C
THDSTAI2C Hold Time (repeated) START Condition. After
this period, the first clock pulse is generated.
LOW Period of the SCL Clock
TLOWI2C
HIGH Period of the SCL Clock
THIGHI2C
TSUSTAI2C Set-up Time for a Repeated START Condition
THDDATI2C Data Hold Time
Standard Mode
Min
Max
0
100
4.0
–
4.7
4.0
4.7
0
–
–
–
–
Fast Mode
Min
Max
–
–
–
–
–
–
–
–
–
–
–
–
Units
Notes
kHz
μs
μs
μs
μs
μs
Note
19. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement TSUDATI2C ≥ 250 ns must then be met. This is automatically
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line trmax + TSUDATI2C = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-20160 Rev. *B
Page 31 of 35
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Table 36. AC Characteristics of the I2C SDA and SCL Pins for Vdd < 3.0V (Fast Mode Not Supported)
Symbol
Description
TSUDATI2C Data Set-up Time
TSUSTOI2C Set-up Time for STOP Condition
Bus Free Time Between a STOP and START
TBUFI2C
Condition
TSPI2C
Pulse Width of spikes are suppressed by the
input filter.
Standard Mode
Min
Max
250
–
4.0
–
4.7
–
–
–
Fast Mode
Min
Max
–
–
–
–
–
–
–
–
Units
Notes
ns
μs
μs
ns
Figure 14. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
Document Number: 001-20160 Rev. *B
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Page 32 of 35
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CY8C24633
Packaging Information
This section illustrates the packaging specifications for the CY8C24633 PSoC device, along with the thermal impedances for each
package, solder reflow peak temperature, and the typical package capacitance on crystal pins.
Figure 15. 28-Pin (210-Mil) SSOP
51-85079 *C
Figure 16. 56-Pin (300-Mil) SSOP
32
51-85062 *C
Document Number: 001-20160 Rev. *B
Page 33 of 35
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CY8C24633
Thermal Impedances
Table 37. Thermal Impedances by Package
Typical θJA [20]
95 oC/W
67 oC/W
Package
28 SSOP
56 SSOP
Capacitance on Crystal Pins
Table 38. Typical Package Capacitance on Crystal Pins
Package
Package Capacitance
28 SSOP
2.8 pF
56 SSOP
Pin 27 0.33 pF
Pin 31 0.35 pF
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 39. Solder Reflow Peak Temperature
Package
28 SSOP
56 SSOP
Minimum Peak Temperature [21]
240oC
240oC
Maximum Peak Temperature
260oC
260oC
Ordering Information
The following table lists the CY8C24633 PSoC device family key package features and ordering codes.
Temperature
Range
Digital Blocks
(Rows of 4)
Analog Blocks
(Columns of 3)
Digital I/O Pins
Analog Inputs
Analog Outputs
XRES Pin
28 Pin (210 Mil) SSOP
28 Pin (210 Mil) SSOP
(Tape and Reel)
56 Pin OCD SSOP
RAM
(Bytes)
Package
Flash
(Kbytes)
Table 40. CY8C24x33 PSoC Device Family Key Features and Ordering Information
CY8C24633-24PVXI
CY8C24633-24PVXIT
8
8
256
256
-40oC to +85oC
-40oC to +85oC
4
4
4
4
25
25
12
12
2
2
Yes
Yes
CY8C24033-24PVXI[22]
8
256
-40oC to +85oC
4
4
24
12
2
Yes
Ordering Code
Notes
20. TJ = TA + POWER x θJA.
21. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu
paste. Refer to the solder manufacturer specifications.
22. This part may be used for in-circuit debugging. It is NOT available for production.
Document Number: 001-20160 Rev. *B
Page 34 of 35
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CY8C24633
Document History Page
Document Title: CY8C24633 PSoC® Programmable-System-on-Chip
Document Number: 001-20160
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
1411003
HMT
See ECN
New spec. Separate device from 001-14643.
*A
1648723
HMT
See ECN
Update SAR ADC electrical specs. Update INL, DNL, and VOL specs. Finetune
specs. Add 56 SSOP package capacitance data. Change title. Make data sheet Final.
*B
2763970 POA/AESA
09/16/09
Updated Getting Started, Development Tools, and Designing with PSoC Designer
sections
Description of Change
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at www.cypress.com/sales.
Products
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psoc.cypress.com
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wireless.cypress.com
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image.cypress.com
© Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-20160 Rev. *B
Revised September 16, 2009
Page 35 of 35
PSoC Designer™ is a trademark and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective
corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C
system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their
respective holders.
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