CYPRESS CY8CLED04

CY8CLED04
EZ-Color™ HB LED Controller
Features
■
HB LED Controller
❐ Configurable Dimmers Support up to 4
Independent LED Channels
❐ 8-32 Bits of Resolution per Channel
❐ Dynamic Reconfiguration Enables LED
Controller plus other Features; CapSense, Battery Charging,
Motor Control…
■
Visual Embedded Design, PSoC Express
❐ LED Based Express Drivers
• Binning Compensation
• Temperature Feedback
• DMX512
■
■
■
PrISM Modulation Technology
❐ Reduces Radiated EMI
❐ Reduces Low Frequency Blinking
■ Advanced Peripherals (PSoC Blocks)
❐ 4 Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• Up to 2 Full-Duplex UART
• Multiple SPI™ Masters or Slaves
• Connectable to all GPIO Pins
❐ 6 Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ Complex Peripherals by Combining Blocks
❐ Capacitive Sensing Application Capability
Cypress Semiconductor Corporation
Document Number: 001-13108 Rev. **
•
■
■
198 Champion Court
Complete Development Tools
❐ Free Development Software
• PSoC Designer™
• PSoC Express™
❐ Full-Featured, In-Circuit Emulator and
Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128 KBytes Trace Memory
Programmable Pin Configurations
❐ 25 mA Sink on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive
Modes on all GPIO
❐ Up to 12 Analog Inputs on GPIO
❐ Four 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on all GPIO
Flexible On-Chip Memory
❐ 16K Flash Program Storage 50,000 Erase/Write Cycles
❐ 1K SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
Full-Speed USB (12 Mbps)
❐ Four Uni-Directional Endpoints
❐ One Bi-Directional Control Endpoint
❐ USB 2.0 Compliant
❐ Dedicated 256 Byte Buffer
❐ No External Crystal Required
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 13, 2007
CY8CLED04
Overview
Block Diagram
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
System Bus
Port 7
Global Digital Interconnect
Analog
Drivers
Global Analog Interconnect
PSoC CORE
SRAM
1K
SROM
Flash 16K
CPU Core (M8C)
Interrupt
Controller
Sleep and
Watchdog
Clock Sources
(Includes IMO and ILO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref.
Digital
Block
Array
Digital
2
Decimator
Clocks MACs
Type 2
Analog
Block
Array
I2C
Internal
POR and LVD
Voltage
System Resets
Ref.
USB
Analog
Input
Muxing
SYSTEM RESOURCES
Document Number: 001-13108 Rev. **
Page 2 of 33
CY8CLED04
EZ-Color Functional Overview
Cypress' EZ-Color family of devices offers the ideal control
solution for High Brightness LED applications requiring intelligent dimming control. EZ-Color devices combine the power and
flexibility of PSoC (Programmable System-on-Chip™); with
Cypress' PrISM (precise illumination signal modulation)
modulation technology providing lighting designers a fully
customizable and integrated lighting solution platform.
The EZ-Color family support up to 16 independent LED channels
with up to 32 bits of resolution per channel, enabling lighting
designers the flexibility to choose the LED array size and color
quality. PSoC Express software, with lighting specific drivers,
can significantly cut development time and simplify implementation of fixed color points through temperature and LED binning
compensation. EZ-Color's virtually limitless analog and digital
customization allow for simple integration of features in addition
to intelligent lighting, such as CapSense, Battery Charging,
Image Stabilization, and Motor Control during the development
process. These features, along with Cypress' best-in-class
quality and design support, make EZ-Color the ideal choice for
intelligent HB LED control applications.
The EZ-Color family incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate
to 8% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
Sleep timer and WDT. The clocks, together with programmable
clock dividers (as a System Resource), provide the flexibility to
integrate almost any timing requirement into the EZ-Color
device. In USB systems, the IMO will self-tune to ± 0.25%
accuracy for USB communication.
EZ-Color GPIOs provide connection to the CPU, digital and
analog resources of the device. Each pin’s drive mode may be
selected from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
The Digital System
The Digital System is composed of 4 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references.
Target Applications
Digital peripheral configurations include those listed below.
■
LCD Backlight
■
PrISM (8 to 32 bit)
■
Large Signs
■
Full-Speed USB (12 Mbps)
■
General Lighting
■
PWMs (8 to 32 bit)
■
Architectural Lighting
■
PWMs with Dead band (8 to 24 bit)
■
Camera/Cell Phone Flash
■
Counters (8 to 32 bit)
■
Flashlights
■
Timers (8 to 32 bit)
■
UART 8 bit with selectable parity
■
SPI master and slave
■
I2C slave and multi-master
■
Cyclical Redundancy Checker/Generator (8 to 32 bit)
■
IrDA
■
Generators (8 to 32 bit)
The PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to 68
MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with up to 20
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory encompasses 16K of Flash for program storage, 1K of
SRAM for data storage, and up to 2K of EEPROM emulated
using the Flash. Program Flash utilizes four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
Document Number: 001-13108 Rev. **
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by EZ-Color device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in the table titled EZ-Color Device Characteristics.
Page 3 of 33
CY8CLED04
Figure 2. Analog System Block Diagram
Figure 1. Digital System Block Diagram
Port 7
Port 5
Port 3
Port 4
Port 1
Port 2
To System Bus
Digital Clocks
From Core
All IO
(Except Port 7)
Port 0
To Analog
System
DIGITAL SYSTEM
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
Digital PSoC Block Array
DBB01
DCB02
DCB03
4
8
AGNDIn RefIn
DBB00
4
Analog
Mux Bus
Row Input
Configuration
8
Row 0
Row Output
Configuration
8
8
P2[3]
P2[6]
P2[4]
P2[1]
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
P2[2]
GOE[7:0]
P2[0]
GOO[7:0]
The Analog System
The Analog System is composed of 6 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common EZ-Color analog functions (most
available as user modules) are listed below.
■
Analog-to-digital converters (up to 2, with 6- to 14-bit resolution,
selectable as Incremental, Delta Sigma, and SAR)
■
Filters (2 and 4 pole band-pass, low-pass, and notch)
■
Amplifiers (up to 2, with selectable gain to 48x)
■
Instrumentation amplifiers (1 with selectable gain to 93x)
■
Comparators (up to 2, with 16 selectable thresholds)
■
DACs (up to 2, with 6- to 9-bit resolution)
■
Multiplying DACs (up to 2, with 6- to 9-bit resolution)
■
High current output drivers (two with 30 mA drive as a PSoC
Core Resource)
■
1.3V reference (as a System Resource)
■
DTMF Dialer
■
Modulators
■
Correlators
■
Peak Detectors
■
Many other topologies possible
ACI0[1:0]
ACI1[1:0]
Array Input
Configuration
Block
Array
ACB00
ACB01
ASC10
ASD11
ASD20
ASC21
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in the figure below.
Document Number: 001-13108 Rev. **
Page 4 of 33
CY8CLED04
The Analog Multiplexer System
Additional System Resources
The Analog Mux Bus can connect to every GPIO pin in ports 0-5.
Pins can be connected to the bus individually or in any combination. The bus also connects to the analog system for analysis
with comparators and analog-to-digital converters. It can be split
into two sections for simultaneous dual-channel processing. An
additional 8:1 analog input multiplexer provides a second path to
bring Port 0 pins to the analog array.
System Resources, provide additional capability useful to
complete systems. Additional resources include a multiplier,
decimator, low voltage detection, and power on reset. Brief statements describing the merits of each resource follow.
Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■
Track pad, finger sensing.
■
Chip-wide mux that allows analog input from up to 48 IO pins.
■
Crosspoint connection between any IO pin combinations.
When designing capacitive sensing applications, refer to the
latest signal-to-noise signal level requirements Application
Notes, which can be found under http://www.cypress.com >>
DESIGN RESOURCES >> Application Notes. In general, and
unless otherwise noted in the relevant Application Notes, the
minimum signal-to-noise ratio (SNR) for CapSense applications
is 5:1.
■
Full-Speed USB (12 Mbps) with 5 configurable endpoints and
256 bytes of RAM. No external components required except
two series resistors. Wider than commercial temperature USB
operation (-10°C to +85°C).
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■
Two multiply accumulates (MACs) provide fast 8-bit multipliers
with 32-bit accumulate, to assist in both general math as well
as digital filters.
■
Decimator provides a custom hardware filter for digital signal
processing apps. including creation of Delta Sigma ADCs.
■
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, multi-master are supported.
■
Low Voltage Detection (LVD) interrupts signal the application
of falling voltage levels, while the advanced POR (Power On
Reset) circuit eliminates the need for a system supervisor.
■
An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■
Versatile analog multiplexer system.
EZ-Color Device Characteristics
Depending on your EZ-Color device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4
analog blocks. The following table lists the resources available for specific EZ-Color device groups. The device covered by this data
sheet is shown in the highlighted row of the table
SRAM
Size
Flash
Size
CapSense
48
2
2
6
1K
16K
Yes
8
12
4
4
12
256 Bytes
16K
No
CY8CLED16
16
64
4
16
12
4
4
12
2K
32K
No
Document Number: 001-13108 Rev. **
Analog
Blocks
4
2
Analog
Columns
1
44
Analog
Outputs
56
8
Analog
Inputs
4
Digital
Blocks
Digital
IO
CY8CLED04
CY8CLED08
PSoC Part
Number
Digital
Rows
LED
Channels
Table 1. EZ-Color Device Characteristics
Page 5 of 33
CY8CLED04
Getting Started
Development Tools
The quickest path to understanding the EZ-Color silicon is by
reading this data sheet and using the PSoC Express Integrated
Development Environment (IDE). This data sheet is an overview
of the EZ-Color integrated circuit and presents specific pin,
register, and electrical specifications.
PSoC Express is a high-level design tool for creating embedded
systems using Cypress's PSoC mixed-signal technology. With
PSoC Express you create a complete embedded solution
including all necessary on-chip peripherals, block configuration,
interrupt handling and application software without writing a
single line of assembly or C code.
For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest device data sheets on the web
at http://www.cypress.com/ez-color.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com, click the Online Store shopping cart
icon at the bottom of the web page, and click EZ-Color to view
a current list of available items.
PSoC Express solves design problems the way you think about
the system:
■
Select input and output devices based upon system requirements.
■
Add a communications interface and define its interface to
system (using registers).
■
Define when and how an output device changes state based
upon any and all other system devices.
Based upon the design, automatically select one or more PSoC
Mixed-Signal Controllers that match system requirements.
Figure 3. PSoC Express
Technical Training Modules
Free PSoC technical training modules are available for users
new to PSoC. Training modules cover designing, debugging,
advanced
analog
and
CapSense.
Go
to
http://www.cypress.com/techtrain.
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com, click on Design
Support located on the left side of the web page, and select
CYPros Consultants.
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support/login.cfm.
Application Notes
A long list of application notes will assist you in every aspect of
your design effort. To view the PSoC application notes, go to the
http://www.cypress.com web site and select Application Notes
under the Design Resources list located in the center of the web
page. Application notes are listed by date as default.
PSoC Express Subsystems
Express Editor
The Express Editor allows you to create designs visually by
dragging and dropping inputs, outputs, communication interfaces, and other design elements, and then describing the logic
that controls them.
Project Manager
The Project Manager allows you to work with your applications
and projects in PSoC Express. A PSoC Express application is a
top level container for projects and their associated files. Each
project contains a design that uses a single PSoC device. An
application can contain multiple projects so if you are creating an
application that uses multiple PSoC devices you can keep all of
the projects together in a single application.
Most of the files associated with a project are automatically
generated by PSoC Express during the build process, but you
can make changes directly to the custom.c and custom.h files
Document Number: 001-13108 Rev. **
Page 6 of 33
CY8CLED04
and also add your own custom code to the project in the Project
Manager.
Document Conventions
Application Editor
The Application Editor allows you to edit custom.c and custom.h
as well as any C or assembly language source code that you add
to your project. With PSoC Express you can create application
software without writing a single line of assembly or C code, but
you have a full featured application editor at your finger tips if you
want it.
Units of Measure
Build Manager
The Build Manager gives you the ability to build the application
software, assign pins, and generate the data sheet, schematic,
and BOM for your project.
Hexidecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’ or ‘b’ are decimal.
Board Monitor
The Board Monitor is a debugging tool designed to be used
while attached to a prototype board through a communication
interface that allows you to monitor changes in the various
design elements in real time.
2C.
It uses
The default communication for the board monitor is I
the CY3240-I2USB I2C to USB Bridge Debugging/Communication Kit.
A units of measure table is located in the Electrical Specifications
section. Table 6 on page 12 lists all the abbreviations used to
measure the PSoC devices.
Numeric Naming
Acronyms Used
The following table lists the acronyms that are used in this
document.
Table 2. Acronyms
Acronym
Description
AC
alternating current
ADC
analog-to-digital converter
API
application programming interface
CPU
central processing unit
CT
continuous time
DAC
digital-to-analog converter
DC
direct current
ECO
external crystal oscillator
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
EEPROM
electrically erasable programmable read-only memory
FSR
full scale range
GPIO
general purpose IO
GUI
graphical user interface
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and will operate
with all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
HBM
human body model
ICE
in-circuit emulator
ILO
internal low speed oscillator
IMO
internal main oscillator
IO
input/output
IPOR
imprecise power on reset
LSb
least-significant bit
LVD
low voltage detect
MSb
most-significant bit
PC
program counter
PLL
phase-locked loop
POR
power on reset
PPOR
precision power on reset
PSoC®
Programmable System-on-Chip™
PWM
pulse width modulator
SC
switched capacitor
SRAM
static random access memory
Tuners
A Tuner is a visual interface for the Board Monitor that allows you
to view the performance of the HB LED drivers on your test board
while your program is running, and manually override values and
see the results.
Hardware Tools
Document Number: 001-13108 Rev. **
Page 7 of 33
CY8CLED04
Pin Information
68-Pin Part Pinout
This Section describes, lists, and illustrates the CY8CLED04 EZ-Color device pins and pinout configuration. The CY8CLED04 device
is available in the following package. Every port pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, and XRES are
not capable of Digital IO.
Table 3. 68-Pin Part Pinout (QFN**)
44
45
46
M
M
M
M
M
M
M
M
M
Input
NC
NC
XRES
P2[1], M, AI
P2[3], M, AI
P2[5], M
P2[7], M
P0[1], M, AI
P0[3], M, AIO
P0[5], M, AIO
P0[7], M, AI
Vss
Vdd
P0[6], M, AI
P0[4], M, AI
P0[2], M, AI
P0[0], M, AI
P2[6], M, Ext. VREF
P2[4], M, Ext. AGND
P2[2], M, AI
P1[6]
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
IO
IO
IO
IO
IO
IO
IO
IO
IO
No connection.
No connection.
Ground connection.
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
NC
NC
Vss
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
I2C SCL, M, P1[7]
I2C SDA, M, P1[5]
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
I2C Serial Clock (SCL) ISSP SCLK*.
Ground connection.
Supply voltage.
Type
Pin
No. Digital Analog
50
IO
M
I2C Serial Data (SDA), ISSP SDATA*. 51
IO
I,M
52
IO
I,M
Optional External Clock Input (EXT53
IO
M
CLK).
54
IO
M
55
IO
I,M
56
IO
I,M
57
IO
I,M
58
IO
I,M
59
Power
60
Power
61
IO
I,M
62
IO
IO,M
No connection.
No connection.
Active high pin reset with internal pull
down.
Document Number: 001-13108 Rev. **
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
35
36
37
38
39
40
41
42
43
68-Pin Device
Description
51
50
QFN
(Top View)
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
P4[7]
P4[5]
P4[3]
P4[1]
NC
NC
Vss
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
D+
DVdd
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
P1[0]
P1[2]
P1[4]
Name
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
P2[0], M, AI
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
NC
NC
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
P1[6], M
M, P1[3]
I2C SCL, M, P1[1]
Vss
D+
DVdd
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
I2C SDA, M, P1[0]
M, P1[2]
M, P1[4]
Type
Pin
No. Digital Analog
1
IO
M
2
IO
M
3
IO
M
4
IO
M
5
6
7
Power
8
IO
M
9
IO
M
10
IO
M
11
IO
M
12
IO
M
13
IO
M
14
IO
M
15
IO
M
16
IO
M
17
IO
M
18
IO
M
19
IO
M
20
Power
21
USB
22
USB
23
Power
24
IO
25
IO
26
IO
27
IO
28
IO
29
IO
30
IO
31
IO
32
IO
M
33
IO
M
34
IO
M
63
64
65
IO
IO
IO
IO,M
I,M
M
Name
P4[6]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Vss
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
Description
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND) input.
External Voltage Reference (VREF) input.
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Supply voltage.
Ground connection.
Analog column mux input, integration input #1
Analog column mux input and column output, integration input #2.
Analog column mux input and column output.
Analog column mux input.
Page 8 of 33
CY8CLED04
Table 3. 68-Pin Part Pinout (QFN**) (continued)
47
48
49
IO
IO
IO
M
M
M
P4[0]
P4[2]
P4[4]
66
67
68
IO
IO
IO
M
I,M
I,M
P2[5]
P2[3]
P2[1]
Direct switched capacitor block input.
Direct switched capacitor block input.
LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input.
* These are the ISSP pins, which are not High Z at POR.
** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal.
Register Conventions
This section lists the registers of the CY8CLED04 EZ-Color device.
Abbreviations Used
The register conventions specific to this section are listed in the following table.
Convention
R
Description
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Register Mapping Tables
The device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks.
The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1.
Note In the following register mapping tables, blank fields are Reserved and should not be accessed.
Table 4. Register Map Bank 0 Table: User Space
Name
PRT0DR
Addr (0,Hex)
00
Access
RW
Name
PMA0_DR
Addr (0,Hex)
40
Access
RW
Name
ASC10CR0
Addr (0,Hex)
80
Access
RW
PRT0IE
01
RW
PMA1_DR
41
RW
ASC10CR1
81
RW
C1
PRT0GS
02
RW
PMA2_DR
42
RW
ASC10CR2
82
RW
C2
PRT0DM2
03
RW
PMA3_DR
43
RW
ASC10CR3
83
RW
C3
PRT1DR
04
RW
PMA4_DR
44
RW
ASD11CR0
84
RW
C4
PRT1IE
05
RW
PMA5_DR
45
RW
ASD11CR1
85
RW
C5
PRT1GS
06
RW
PMA6_DR
46
RW
ASD11CR2
86
RW
C6
PRT1DM2
07
RW
PMA7_DR
47
RW
ASD11CR3
87
RW
C7
PRT2DR
08
RW
USB_SOF0
48
R
88
C8
PRT2IE
09
RW
USB_SOF1
49
R
89
C9
PRT2GS
0A
RW
USB_CR0
4A
RW
8A
CA
PRT2DM2
0B
RW
USBIO_CR0
4B
#
8B
CB
PRT3DR
0C
RW
USBIO_CR1
4C
RW
8C
CC
PRT3IE
0D
RW
8D
CD
PRT3GS
0E
RW
EP1_CNT1
4E
#
8E
CE
PRT3DM2
0F
RW
EP1_CNT
4F
RW
8F
PRT4DR
10
RW
EP2_CNT1
50
#
ASD20CR0
90
RW
CUR_PP
D0
RW
PRT4IE
11
RW
EP2_CNT
51
RW
ASD20CR1
91
RW
STK_PP
D1
RW
PRT4GS
12
RW
EP3_CNT1
52
#
ASD20CR2
92
RW
PRT4DM2
13
RW
EP3_CNT
53
RW
ASD20CR3
93
RW
IDX_PP
D3
RW
PRT5DR
14
RW
EP4_CNT1
54
#
ASC21CR0
94
RW
MVR_PP
D4
RW
PRT5IE
15
RW
EP4_CNT
55
RW
ASC21CR1
95
RW
MVW_PP
D5
RW
PRT5GS
16
RW
EP0_CR
56
#
ASC21CR2
96
RW
I2C_CFG
D6
RW
PRT5DM2
17
RW
EP0_CNT
57
#
ASC21CR3
97
RW
I2C_SCR
D7
#
18
EP0_DR0
58
RW
98
I2C_DR
D8
RW
19
EP0_DR1
59
RW
99
I2C_MSCR
D9
#
4D
Blank fields are Reserved and should not be accessed.
Document Number: 001-13108 Rev. **
Name
Addr (0,Hex)
C0
Access
CF
D2
# Access is bit specific.
Page 9 of 33
CY8CLED04
Table 4. Register Map Bank 0 Table: User Space (continued)
Name
Addr (0,Hex)
1A
Access
1B
Name
EP0_DR2
Addr (0,Hex)
5A
Access
RW
Name
Addr (0,Hex)
9A
Access
Name
INT_CLR0
Addr (0,Hex)
DA
Access
RW
EP0_DR3
5B
RW
9B
INT_CLR1
DB
RW
PRT7DR
1C
RW
EP0_DR4
5C
RW
9C
INT_CLR2
DC
RW
PRT7IE
1D
RW
EP0_DR5
5D
RW
9D
INT_CLR3
DD
RW
PRT7GS
1E
RW
EP0_DR6
5E
RW
9E
INT_MSK3
DE
RW
PRT7DM2
1F
RW
EP0_DR7
5F
RW
9F
INT_MSK2
DF
RW
DBB00DR0
20
#
AMX_IN
60
RW
A0
INT_MSK0
E0
RW
DBB00DR1
21
W
AMUXCFG
61
RW
A1
INT_MSK1
E1
RW
DBB00DR2
22
RW
A2
INT_VC
E2
RC
DBB00CR0
23
#
ARF_CR
63
RW
A3
RES_WDT
E3
W
DBB01DR0
24
#
CMP_CR0
64
#
A4
DEC_DH
E4
RC
DBB01DR1
25
W
ASY_CR
65
#
A5
DEC_DL
E5
RC
DBB01DR2
26
RW
CMP_CR1
66
RW
A6
DEC_CR0
E6
RW
DBB01CR0
27
#
67
A7
DEC_CR1
E7
RW
DCB02DR0
28
#
68
MUL1_X
A8
W
MUL0_X
E8
W
DCB02DR1
29
W
69
MUL1_Y
A9
W
MUL0_Y
E9
W
DCB02DR2
2A
RW
6A
MUL1_DH
AA
R
MUL0_DH
EA
R
DCB02CR0
2B
#
6B
MUL1_DL
AB
R
MUL0_DL
EB
R
DCB03DR0
2C
#
TMP_DR0
6C
RW
ACC1_DR1
AC
RW
ACC0_DR1
EC
RW
DCB03DR1
2D
W
TMP_DR1
6D
RW
ACC1_DR0
AD
RW
ACC0_DR0
ED
RW
DCB03DR2
2E
RW
TMP_DR2
6E
RW
ACC1_DR3
AE
RW
ACC0_DR3
EE
RW
DCB03CR0
2F
#
TMP_DR3
6F
RW
ACC1_DR2
AF
RW
ACC0_DR2
EF
RW
30
ACB00CR3
70
RW
RDI0RI
B0
RW
F0
31
ACB00CR0
71
RW
RDI0SYN
B1
RW
F1
32
ACB00CR1
72
RW
RDI0IS
B2
RW
F2
33
ACB00CR2
73
RW
RDI0LT0
B3
RW
F3
34
ACB01CR3
74
RW
RDI0LT1
B4
RW
F4
35
ACB01CR0
75
RW
RDI0RO0
B5
RW
F5
36
ACB01CR1
76
RW
RDI0RO1
B6
RW
37
ACB01CR2
77
RW
62
B7
F6
F7
CPU_F
RL
38
78
B8
F8
39
79
B9
F9
3A
7A
BA
FA
3B
7B
BB
FB
3C
7C
BC
3D
7D
BD
DAC_D
FD
3E
7E
BE
CPU_SCR1
FE
#
3F
7F
BF
CPU_SCR0
FF
#
Blank fields are Reserved and should not be accessed.
FC
RW
# Access is bit specific.
Table 5. Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
Addr (1,Hex)
00
Access
RW
Name
PMA0_WA
Addr (1,Hex)
40
Access
RW
Name
ASC10CR0
Addr (1,Hex)
80
Access
RW
Name
USBIO_CR2
Addr (1,Hex)
C0
Access
RW
PRT0DM1
01
RW
PMA1_WA
41
RW
ASC10CR1
81
RW
USB_CR1
C1
#
PRT0IC0
02
RW
PMA2_WA
42
RW
ASC10CR2
82
RW
PRT0IC1
03
RW
PMA3_WA
43
RW
ASC10CR3
83
RW
PRT1DM0
04
RW
PMA4_WA
44
RW
ASD11CR0
84
RW
EP1_CR0
C4
#
PRT1DM1
05
RW
PMA5_WA
45
RW
ASD11CR1
85
RW
EP2_CR0
C5
#
PRT1IC0
06
RW
PMA6_WA
46
RW
ASD11CR2
86
RW
EP3_CR0
C6
#
PRT1IC1
07
RW
PMA7_WA
47
RW
ASD11CR3
87
RW
EP4_CR0
C7
#
PRT2DM0
08
RW
48
88
C8
PRT2DM1
09
RW
49
89
C9
PRT2IC0
0A
RW
4A
8A
CA
PRT2IC1
0B
RW
4B
8B
CB
PRT3DM0
0C
RW
4C
8C
CC
PRT3DM1
0D
RW
4D
8D
CD
PRT3IC0
0E
RW
4E
8E
CE
PRT3IC1
0F
RW
4F
8F
PRT4DM0
10
RW
PMA0_RA
50
RW
PRT4DM1
11
RW
PMA1_RA
51
RW
ASD20CR1
91
PRT4IC0
12
RW
PMA2_RA
52
RW
ASD20CR2
PRT4IC1
13
RW
PMA3_RA
53
RW
ASD20CR3
14
PRT5DM0
RW
PMA4_RA
Blank fields are Reserved and should not be accessed.
54
RW
ASC21CR0 94
# Access is bit specific.
Document Number: 001-13108 Rev. **
CF
90
GDI_O_IN
D0
RW
RW
GDI_E_IN
D1
RW
92
RW
GDI_O_OU
D2
RW
93
RW
GDI_E_OU
D3
RW
RW
D4
Page 10 of 33
CY8CLED04
Table 5. Register Map Bank 1 Table: Configuration Space (continued)
Name
PRT5DM1
Addr (1,Hex)
15
Access
RW
Name
PMA5_RA
Addr (1,Hex)
55
Access
RW
Name
ASC21CR1
Addr (1,Hex)
95
Access
RW
PRT5IC0
16
RW
PMA6_RA
56
RW
ASC21CR2
96
RW
PRT5IC1
17
RW
PMA7_RA
57
RW
ASC21CR3
97
RW
Name
Addr (1,Hex)
D5
Access
D6
D7
18
58
98
MUX_CR0
D8
RW
19
59
99
MUX_CR1
D9
RW
1A
5A
9A
MUX_CR2
DA
RW
1B
5B
9B
MUX_CR3
DB
RW
PRT7DM0
1C
RW
5C
9C
PRT7DM1
1D
RW
5D
9D
OSC_GO_EN
DD
RW
PRT7IC0
1E
RW
5E
9E
OSC_CR4
DE
RW
PRT7IC1
1F
RW
5F
9F
OSC_CR3
DF
RW
DBB00FN
20
RW
CLK_CR0
60
RW
A0
OSC_CR0
E0
RW
DBB00IN
21
RW
CLK_CR1
61
RW
A1
OSC_CR1
E1
RW
DBB00OU
22
RW
ABF_CR0
62
RW
A2
OSC_CR2
E2
RW
AMD_CR0
63
RW
A3
VLT_CR
E3
RW
VLT_CMP
E4
R
23
DC
DBB01FN
24
RW
CMP_GO_EN
64
RW
A4
DBB01IN
25
RW
CMP_GO_EN1
65
RW
A5
E5
26
RW
AMD_CR1
66
RW
A6
E6
ALT_CR0
67
RW
A7
DBB01OU
27
E7
DCB02FN
28
RW
68
A8
IMO_TR
E8
W
DCB02IN
29
RW
69
A9
ILO_TR
E9
W
DCB02OU
2A
RW
6A
AA
BDG_TR
EA
RW
6B
AB
ECO_TR
EB
W
2B
DCB03FN
2C
RW
TMP_DR0
6C
RW
AC
MUX_CR4
EC
RW
DCB03IN
2D
RW
TMP_DR1
6D
RW
AD
MUX_CR5
ED
RW
DCB03OU
2E
RW
TMP_DR2
6E
RW
AE
2F
TMP_DR3
6F
RW
30
ACB00CR3
70
RW
RDI0RI
B0
RW
F0
31
ACB00CR0
71
RW
RDI0SYN
B1
RW
F1
32
ACB00CR1
72
RW
RDI0IS
B2
RW
F2
33
ACB00CR2
73
RW
RDI0LT0
B3
RW
F3
34
ACB01CR3
74
RW
RDI0LT1
B4
RW
F4
35
ACB01CR0
75
RW
RDI0RO0
B5
RW
F5
36
ACB01CR1
76
RW
RDI0RO1
B6
RW
37
ACB01CR2
77
RW
EE
AF
B7
EF
F6
CPU_F
F7
RL
38
78
B8
F8
39
79
B9
F9
3A
7A
BA
FA
3B
7B
BB
FB
3C
7C
BC
3D
7D
BD
DAC_CR
FD
RW
3E
7E
BE
FE
3F
7F
BF
CPU_SCR1
CPU_SCR0
#
#
Blank fields are Reserved and should not be accessed.
Document Number: 001-13108 Rev. **
FC
FF
# Access is bit specific.
Page 11 of 33
CY8CLED04
Electrical Specifications
This section presents the DC and AC electrical specifications of
the CY8CLED04 EZ-Color device. For the most up to date
electrical specifications, confirm that you have the most recent
data sheet by going to the web at
http://www.cypress.com/ez-color.
Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC,
except where noted. Specifications for devices running at greater
than 12 MHz are valid for -40oC ≤ TA ≤ 70oC and TJ ≤ 82oC.
Figure 4. Voltage versus CPU Frequency
5.25
Vdd Voltage
lid ng
Va rati n
e io
Op Reg
4.75
3.00
The following table lists the units of measure that are used in this
chapter.
Table 6. Units of Measure
Symbol
12 MHz
Symbol
Unit of Measure
μW
microwatts
dB
decibels
mA
milli-ampere
fF
femto farad
ms
milli-second
Hz
hertz
mV
milli-volts
KB
1024 bytes
nA
nanoampere
Kbit
1024 bits
ns
nanosecond
kHz
kilohertz
nV
nanovolts
kΩ
kilohm
Ω
ohm
MHz
megahertz
pA
picoampere
MΩ
megaohm
pF
picofarad
μA
microampere
pp
peak-to-peak
μF
microfarad
ppm
μH
microhenry
ps
picosecond
μs
microsecond
sps
samples per second
μV
microvolts
σ
sigma: one standard
deviation
microvolts
root-mean-square
V
volts
C
μVrms
93 kHz
Unit of Measure
degree Celsius
o
parts per million
24 MHz
CPU Frequency
Document Number: 001-13108 Rev. **
Page 12 of 33
CY8CLED04
Absolute Maximum Ratings
Table 7. Absolute Maximum Ratings
Symbol
Description
Min
Typ
Max
Units
TSTG
Storage Temperature
-55
25
+100
o
C
TA
Ambient Temperature with Power Applied
-40
–
+85
o
C
Vdd
Supply Voltage on Vdd Relative to Vss
-0.5
–
+6.0
V
VIO
DC Input Voltage
Vss - 0.5
–
Vdd + 0.5 V
VIO2
DC Voltage Applied to Tri-state
Vss - 0.5
–
Vdd + 0.5 V
IMIO
Maximum Current into any Port Pin
-25
–
+50
mA
IMAIO
Maximum Current into any Port Pin Configured as Analog
Driver
-50
–
+50
mA
ESD
Electro Static Discharge Voltage
2000
–
–
V
LU
Latch-up Current
–
–
200
mA
Notes
Higher storage temperatures will reduce data
retention time. Recommended storage temperature is +25oC ± 25oC. Extended duration storage temperatures above 65oC will degrade
reliability.
Human Body Model ESD.
Operating Temperature
Table 8. Operating Temperature
Symbol
Description
Min
Typ
Max
Units
TA
Ambient Temperature
-40
–
+85
oC
TAUSB
Ambient Temperature using USB
-10
–
+85
o
TJ
Junction Temperature
-40
–
+100
oC
Notes
C
The temperature rise from ambient to junction
is package specific. See “Thermal Impedance”
on page 30. The user must limit the power consumption to comply with this requirement.
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 9. DC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Vdd
Supply Voltage
3.0
–
5.25
V
See DC POR and LVD specifications, Table 20
on page 20.
IDD5
Supply Current, IMO = 24 MHz (5V)
–
14
27
mA
Conditions are Vdd = 5.0V, TA = 25 oC, CPU = 3
MHz, SYSCLK doubler disabled, VC1 = 1.5
MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off.
IDD3
Supply Current, IMO = 24 MHz (3.3V)
–
8
14
mA
Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3
MHz, SYSCLK doubler disabled, VC1 = 1.5
MHz, VC2 = 93.75 kHz, VC3 = 0.367 kHz, analog power = off.
ISB
Sleep (Mode) Current with POR, LVD, Sleep Timer, and
WDT.a
–
3
6.5
μA
Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC ≤ TA ≤ 55 oC, analog
power = off.
ISBH
Sleep (Mode) Current with POR, LVD, Sleep Timer, and
WDT at high temperature.a
–
4
25
μA
Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 oC < TA ≤ 85 oC, analog
power = off.
a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar functions
enabled.
Document Number: 001-13108 Rev. **
Page 13 of 33
CY8CLED04
DC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10. DC GPIO Specifications
Symbol
Description
Min
Typ
5.6
Max
8
Units
Notes
RPU
Pull-Up Resistor
4
kΩ
RPD
Pull-Down Resistor
4
5.6
8
kΩ
VOH
High Output Level
Vdd - 1.0
–
–
V
IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total
loads, 4 on even port pins (for example, P0[2],
P1[4]), 4 on odd port pins (for example, P0[3],
P1[5])). 80 mA maximum combined IOH budget.
VOL
Low Output Level
–
–
0.75
V
IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total
loads, 4 on even port pins (for example, P0[2],
P1[4]), 4 on odd port pins (for example, P0[3],
P1[5])). 200 mA maximum combined IOL budget.
0.8
V
Vdd = 3.0 to 5.25.
V
Vdd = 3.0 to 5.25.
VIL
Input Low Level
–
–
VIH
Input High Level
2.1
–
VH
Input Hysterisis
–
60
–
mV
IIL
Input Leakage (Absolute Value)
–
1
–
nA
Gross tested to 1 μA.
CIN
Capacitive Load on Pins as Input
–
3.5
10
pF
Package and pin dependent. Temp = 25oC.
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF
Package and pin dependent. Temp = 25oC.
DC Full-Speed USB Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -10°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -10°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 11. DC Full-Speed (12 Mbps) USB Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
USB Interface
VDI
Differential Input Sensitivity
0.2
–
–
V
VCM
Differential Input Common Mode Range
0.8
–
2.5
V
VSE
Single Ended Receiver Threshold
0.8
–
2.0
V
CIN
Transceiver Capacitance
–
–
20
pF
| (D+) - (D-) |
IIO
High-Z State Data Line Leakage
-10
–
10
μA
0V < VIN < 3.3V.
REXT
External USB Series Resistor
23
–
25
Ω
In series with each USB pin.
VUOH
Static Output High, Driven
2.8
–
3.6
V
15 kΩ ± 5% to Ground. Internal pull-up enabled.
VUOHI
Static Output High, Idle
2.7
–
3.6
V
15 kΩ ± 5% to Ground. Internal pull-up enabled.
VUOL
Static Output Low
–
–
0.3
V
15 kΩ ± 5% to Ground. Internal pull-up enabled.
ZO
USB Driver Output Impedance
28
–
44
Ω
Including REXT Resistor.
VCRS
D+/D- Crossover Voltage
1.3
–
2.0
V
Document Number: 001-13108 Rev. **
Page 14 of 33
CY8CLED04
DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.
Table 12. 5V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Min
Typ
Max
Units
Notes
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
–
1.6
10
mV
Power = Medium, Opamp Bias = High
–
1.3
8
mV
Power = High, Opamp Bias = High
–
1.2
7.5
mV
TCVOSOA
Average Input Offset Voltage Drift
–
7.0
35.0
μV/oC
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
20
–
pA
Gross tested to 1 μA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent. Temp = 25oC.
VCMOA
Common Mode Voltage Range
0.0
–
Vdd
V
Common Mode Voltage Range (high power or high
opamp bias)
0.5
–
Vdd - 0.5
The common-mode input voltage range is measured through an analog output buffer. The
specification includes the limitations imposed
by the characteristics of the analog output
buffer.
–
–
dB
GOLOA
VOHIGHOA
VOLOWOA
ISOA
PSRROA
Open Loop Gain
Power = Low, Opamp Bias = High
60
Power = Medium, Opamp Bias = High
60
Power = High, Opamp Bias = High
80
High Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = High
Vdd - 0.2
–
–
V
Power = Medium, Opamp Bias = High
Vdd - 0.2
–
–
V
Power = High, Opamp Bias = High
Vdd - 0.5
–
–
V
Power = Low, Opamp Bias = High
–
–
0.2
V
Power = Medium, Opamp Bias = High
–
–
0.2
V
Power = High, Opamp Bias = High
–
–
0.5
V
Power = Low, Opamp Bias = Low
–
400
800
μA
Power = Low, Opamp Bias = High
–
500
900
μA
Power = Medium, Opamp Bias = Low
–
800
1000
μA
Power = Medium, Opamp Bias = High
–
1200
1600
μA
Power = High, Opamp Bias = Low
–
2400
3200
μA
Power = High, Opamp Bias = High
–
4600
6400
μA
Supply Voltage Rejection Ratio
65
80
–
dB
Low Output Voltage Swing (internal signals)
Supply Current (including associated AGND buffer)
Document Number: 001-13108 Rev. **
Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤ VIN
≤ Vdd.
Page 15 of 33
CY8CLED04
Table 13. 3.3V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Min
Typ
Max
Units
Notes
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
–
1.65
10
mV
Power = Medium, Opamp Bias = High
–
1.32
8
mV
–
7.0
35.0
μV/oC
High Power is 5 Volts Only
TCVOSOA
Average Input Offset Voltage Drift
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
20
–
pA
Gross tested to 1 μA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent. Temp = 25oC.
VCMOA
Common Mode Voltage Range
0.2
–
Vdd - 0.2
V
The common-mode input voltage range is measured through an analog output buffer. The
specification includes the limitations imposed
by the characteristics of the analog output
buffer.
GOLOA
Open Loop Gain
–
–
dB
VOHIGHOA
VOLOWOA
ISOA
PSRROA
Power = Low, Opamp Bias = Low
60
Power = Medium, Opamp Bias = Low
60
Power = High, Opamp Bias = Low
80
High Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = Low
Vdd - 0.2
–
–
V
Power = Medium, Opamp Bias = Low
Vdd - 0.2
–
–
V
Power = High is 5V only
Vdd - 0.2
–
–
V
Power = Low, Opamp Bias = Low
–
–
0.2
V
Power = Medium, Opamp Bias = Low
–
–
0.2
V
Power = High, Opamp Bias = Low
–
–
0.2
V
Power = Low, Opamp Bias = Low
–
400
800
μA
Power = Low, Opamp Bias = High
–
500
900
μA
Power = Medium, Opamp Bias = Low
–
800
1000
μA
Power = Medium, Opamp Bias = High
–
1200
1600
μA
Power = High, Opamp Bias = Low
–
2400
3200
μA
Power = High, Opamp Bias = High
–
4600
6400
μA
Supply Voltage Rejection Ratio
65
80
–
dB
Low Output Voltage Swing (internal signals)
Supply Current (including associated AGND buffer)
Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤ VIN
≤ Vdd.
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.
Table 14. DC Low Power Comparator Specifications
Symbol
Description
Min
Typ
Max
Units
VREFLPC
Low power comparator (LPC) reference voltage range
0.2
–
Vdd - 1
ISLPC
LPC supply current
–
10
40
μA
VOSLPC
LPC voltage offset
–
2.5
30
mV
Document Number: 001-13108 Rev. **
Notes
V
Page 16 of 33
CY8CLED04
DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 15. 5V DC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
VOSOB
Input Offset Voltage (Absolute Value)
–
3
12
mV
TCVOSOB
Average Input Offset Voltage Drift
–
+6
–
μV/°C
VCMOB
Common-Mode Input Voltage Range
0.5
–
Vdd - 1.0
V
ROUTOB
Output Resistance
Power = Low
–
0.6
–
Ω
Power = High
–
0.6
–
Ω
High Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
0.5 x Vdd
–
–
V
Power = High
+ 1.1
–
–
V
VOHIGHOB
Notes
0.5 x Vdd
+ 1.1
VOLOWOB
Low Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
–
–
0.5 x Vdd
V
Power = High
–
–
- 1.3
V
0.5 x Vdd
- 1.3
ISOB
PSRROB
Supply Current Including Bias Cell (No Load)
Power = Low
–
1.1
5.1
mA
Power = High
–
2.6
8.8
mA
Supply Voltage Rejection Ratio
53
64
–
dB
(0.5 x Vdd - 1.3) ≤ VOUT ≤ (Vdd - 2.3).
Table 16. 3.3V DC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
VOSOB
Input Offset Voltage (Absolute Value)
–
3
12
mV
TCVOSOB
Average Input Offset Voltage Drift
–
+6
–
μV/°C
VCMOB
Common-Mode Input Voltage Range
0.5
-
Vdd - 1.0
V
ROUTOB
Output Resistance
Power = Low
–
1
–
Ω
Power = High
–
1
–
Ω
Power = Low
0.5 x Vdd
–
–
V
Power = High
+ 1.0
–
–
V
VOHIGHOB
Notes
High Output Voltage Swing (Load = 1K ohms to Vdd/2)
0.5 x Vdd
+ 1.0
VOLOWOB
Low Output Voltage Swing (Load = 1K ohms to Vdd/2)
Power = Low
–
–
0.5 x Vdd
V
Power = High
–
–
- 1.0
V
0.5 x Vdd
- 1.0
ISOB
Supply Current Including Bias Cell (No Load)
Power = Low
PSRROB
0.8
2.0
mA
Power = High
–
2.0
4.3
mA
Supply Voltage Rejection Ratio
34
64
–
dB
Document Number: 001-13108 Rev. **
(0.5 x Vdd - 1.0) ≤ VOUT ≤ (0.5 x Vdd + 0.9).
Page 17 of 33
CY8CLED04
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 17. 5V DC Analog Reference Specifications
Symbol
Description
Min
Typ
Max
Units
BG
Bandgap Voltage Reference
1.28
1.30
1.32
V
–
AGND = Vdd/2a
Vdd/2 0.04
Vdd/2 0.01
Vdd/2 +
0.007
V
–
AGND = 2 x BandGapa
2 x BG 0.048
2 x BG 0.030
2 x BG +
0.024
V
–
AGND = P2[4] (P2[4] = Vdd/2)a
P2[4] 0.011
P2[4]
P2[4] +
0.011
V
–
AGND = BandGapa
BG 0.009
BG +
0.008
BG +
0.016
V
–
AGND = 1.6 x BandGapa
1.6 x BG
- 0.022
1.6 x BG
- 0.010
1.6 x BG
+ 0.018
V
–
AGND Block to Block Variation (AGND = Vdd/2)a
-0.034
0.000
0.034
V
–
RefHi = Vdd/2 + BandGap
Vdd/2 +
Vdd/2 +
Vdd/2 +
V
BG - 0.10 BG
BG +
0.10
–
RefHi = 3 x BandGap
3 x BG 0.06
3 x BG
3 x BG +
0.06
V
–
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
2 x BG +
P2[6] 0.113
2 x BG +
P2[6] 0.018
2 x BG +
P2[6] +
0.077
V
–
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
P2[4] +
BG 0.130
P2[4] +
BG 0.016
P2[4] +
BG +
0.098
V
–
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
P2[4] +
P2[6] 0.133
P2[4] +
P2[6] 0.016
P2[4] +
P2[6]+
0.100
V
–
RefHi = 3.2 x BandGap
3.2 x BG
- 0.112
3.2 x BG
3.2 x BG
+ 0.076
V
–
RefLo = Vdd/2 – BandGap
Vdd/2 -
Vdd/2 BG - 0.04 BG +
0.024
Vdd/2 -
V
BG +
0.04
–
RefLo = BandGap
BG - 0.06 BG
BG +
0.06
V
–
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
2 x BG P2[6] 0.084
2 x BG P2[6] +
0.025
2 x BG P2[6] +
0.134
V
–
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
P2[4] BG 0.056
P2[4] BG +
0.026
P2[4] BG +
0.107
V
–
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
P2[4] P2[6] 0.057
P2[4] P2[6] +
0.026
P2[4] P2[6] +
0.110
V
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.
Document Number: 001-13108 Rev. **
Page 18 of 33
CY8CLED04
Table 18. 3.3V DC Analog Reference Specifications
Symbol
Description
Min
Typ
Max
Units
BG
Bandgap Voltage Reference
1.28
1.30
1.32
V
–
AGND = Vdd/2a
Vdd/2 0.03
Vdd/2 0.01
Vdd/2 +
0.005
V
–
AGND = 2 x BandGapa
Not Allowed
–
AGND = P2[4] (P2[4] = Vdd/2)
P2[4] 0.008
P2[4] +
0.001
P2[4] +
0.009
V
–
AGND = BandGapa
BG 0.009
BG +
0.005
BG +
0.015
V
–
AGND = 1.6 x BandGapa
1.6 x BG
- 0.027
1.6 x BG
- 0.010
1.6 x BG
+ 0.018
V
–
AGND Column to Column Variation (AGND = Vdd/2)a
-0.034
0.000
0.034
V
–
RefHi = Vdd/2 + BandGap
Not Allowed
–
RefHi = 3 x BandGap
Not Allowed
–
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)
Not Allowed
–
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
Not Allowed
–
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
P2[4] +
P2[6] 0.075
P2[4] +
P2[6] +
0.057
V
–
RefHi = 3.2 x BandGap
Not Allowed
–
RefLo = Vdd/2 - BandGap
Not Allowed
–
RefLo = BandGap
Not Allowed
–
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)
Not Allowed
–
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
Not Allowed
–
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
P2[4] P2[6] 0.048
P2[4] P2[6] +
0.092
V
P2[4] +
P2[6] 0.009
P2[4]P2[6] +
0.022
Notes
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 19. DC Analog PSoC Block Specifications
Symbol
Description
Min
Typ
Max
Units
RCT
Resistor Unit Value (Continuous Time)
–
12.2
–
kΩ
CSC
Capacitor Unit Value (Switched Capacitor)
–
80
–
fF
Notes
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V or 3.3V at 25°C and are
for design guidance only.
Document Number: 001-13108 Rev. **
Page 19 of 33
CY8CLED04
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register.
Table 20. DC POR and LVD Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Vdd Value for PPOR Trip (positive ramp)
VPPOR0R
PORLEV[1:0] = 00b
VPPOR1R
PORLEV[1:0] = 01b
VPPOR2R
PORLEV[1:0] = 10b
2.91
–
4.39
V
–
V
4.55
V
Vdd Value for PPOR Trip (negative ramp)
VPPOR0
PORLEV[1:0] = 00b
VPPOR1
PORLEV[1:0] = 01b
VPPOR2
PORLEV[1:0] = 10b
2.82
–
4.39
V
–
V
4.55
V
PPOR Hysteresis
VPH0
PORLEV[1:0] = 00b
–
92
–
mV
VPH1
PORLEV[1:0] = 01b
–
0
–
mV
VPH2
PORLEV[1:0] = 10b
–
0
–
mV
Vdd Value for LVD Trip
VLVD0
VM[2:0] = 000b
2.86
2.92
2.98a
V
VLVD1
VM[2:0] = 001b
2.96
3.02
3.08
VLVD2
VM[2:0] = 010b
3.07
3.13
3.20
VLVD3
VM[2:0] = 011b
3.92
4.00
4.08
VLVD4
VM[2:0] = 100b
4.39
4.48
4.57
VLVD5
VM[2:0] = 101b
4.55
4.64
4.74b
VLVD6
VM[2:0] = 110b
4.63
4.73
VLVD7
VM[2:0] = 111b
4.72
4.81
V
V
V
V
V
V
V
V
4.82
4.91
a. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
b. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 21. DC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
IDDP
Supply Current During Programming or Verify
–
15
30
mA
VILP
Input Low Voltage During Programming or Verify
–
–
0.8
V
VIHP
Input High Voltage During Programming or Verify
2.1
–
–
V
IILP
Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify
–
–
0.2
mA
Driving internal pull-down resistor.
IIHP
Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify
–
–
1.5
mA
Driving internal pull-down resistor.
VOLV
Output Low Voltage During Programming or Verify
–
–
Vss +
0.75
V
VOHV
Output High Voltage During Programming or Verify
Vdd - 1.0
–
Vdd
V
FlashENPB
Flash Endurance (per block)
50,000
–
–
–
Erase/write cycles per block.
1,800,00
0
–
–
–
Erase/write cycles.
10
–
–
Years
FlashENT
Flash Endurance
FlashDR
Flash Data Retention
(total)a
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of
25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than
50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to
the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
Document Number: 001-13108 Rev. **
Page 20 of 33
CY8CLED04
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 22. AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FIMO245V
Internal Main Oscillator Frequency for 24 MHz (5V)
23.04
24
24.96a,b
MHz
Trimmed for 5V operation using factory trim
values.
FIMO243V
Internal Main Oscillator Frequency for 24 MHz (3.3V)
22.08
24
25.92b,c
MHz
Trimmed for 3.3V operation using factory trim
values.
FIMOUSB5V
Internal Main Oscillator Frequency with USB (5V)
Frequency locking enabled and USB traffic present.
23.94
24
24.06b
MHz
-10°C ≤ TA ≤ 85°C
4.35 ≤ Vdd ≤ 5.15
FIMOUSB3V
Internal Main Oscillator Frequency with USB (3.3V)
Frequency locking enabled and USB traffic present.
23.94
24
24.06b
MHz
-0°C ≤ TA ≤ 70°C
3.15 ≤ Vdd ≤ 3.45
FCPU1
CPU Frequency (5V Nominal)
0.93
24
24.96a,b
MHz
FCPU2
CPU Frequency (3.3V Nominal)
0.93
12
12.96b,c
MHz
FBLK5
Digital PSoC Block Frequency (5V Nominal)
0
48
49.92
FBLK3
Digital PSoC Block Frequency (3.3V Nominal)
0
24
25.92b, d
MHz
F32K1
Internal Low Speed Oscillator Frequency
15
32
64
kHz
Jitter32k
32 kHz Period Jitter
–
100
Step24M
24 MHz Trim Step Size
–
50
Fout48M
48 MHz Output Frequency
46.08
48.0
Jitter24M1
24 MHz Period Jitter (IMO) Peak-to-Peak
–
300
FMAX
Maximum frequency of signal on row input or row output. –
–
12.96
MHz
TRAMP
Supply Ramp Time
–
–
μs
a.
b.
c.
d.
0
a,b,d
MHz
Refer to the AC Digital Block Specifications.
ns
–
kHz
a,c
49.92
MHz
Trimmed. Utilizing factory trim values.
ps
4.75V < Vdd < 5.25V.
Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.
See the individual user module data sheets for information on maximum frequencies for user modules.
Figure 5. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F24M
AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 23. AC GPIO Specifications
Symbol
Description
Min
–
Max
12
Units
MHz
Notes
GPIO Operating Frequency
TRiseF
Rise Time, Normal Strong Mode, Cload = 50 pF
3
–
18
ns
Vdd = 4.5 to 5.25V, 10% - 90%
TFallF
Fall Time, Normal Strong Mode, Cload = 50 pF
2
–
18
ns
Vdd = 4.5 to 5.25V, 10% - 90%
TRiseS
Rise Time, Slow Strong Mode, Cload = 50 pF
10
27
–
ns
Vdd = 3 to 5.25V, 10% - 90%
TFallS
Fall Time, Slow Strong Mode, Cload = 50 pF
10
22
–
ns
Vdd = 3 to 5.25V, 10% - 90%
Document Number: 001-13108 Rev. **
0
Typ
FGPIO
Normal Strong Mode
Page 21 of 33
CY8CLED04
Figure 6. GPIO Timing Diagram
90%
G PIO
Pin
O utput
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
AC Full-Speed USB Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -10°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -10°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 24. AC Full-Speed (12 Mbps) USB Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
TRFS
Transition Rise Time
4
–
20
TFSS
Transition Fall Time
4
–
20
ns
For 50 pF load.
TRFMFS
Rise/Fall Time Matching: (TR/TF)
90
–
111
%
For 50 pF load.
12 0.25%
12
12 +
0.25%
Mbps
TDRATEFS Full-Speed Data Rate
ns
For 50 pF load.
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.
Table 25. 5V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
Description
Min
Typ
Max
Units
Notes
Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10
pF load, Unity Gain)
Power = Low, Opamp Bias = Low
–
–
3.9
μs
Power = Medium, Opamp Bias = High
–
–
0.72
μs
Power = High, Opamp Bias = High
–
–
0.62
μs
Power = Low, Opamp Bias = Low
–
–
5.9
μs
Power = Medium, Opamp Bias = High
–
–
0.92
μs
Power = High, Opamp Bias = High
–
–
0.72
μs
Power = Low, Opamp Bias = Low
0.15
–
–
V/μs
Power = Medium, Opamp Bias = High
1.7
–
–
V/μs
Power = High, Opamp Bias = High
6.5
–
–
V/μs
Power = Low, Opamp Bias = Low
0.01
–
–
V/μs
Power = Medium, Opamp Bias = High
0.5
–
–
V/μs
Power = High, Opamp Bias = High
4.0
–
–
V/μs
Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10
pF load, Unity Gain)
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Document Number: 001-13108 Rev. **
Page 22 of 33
CY8CLED04
Table 25. 5V AC Operational Amplifier Specifications (continued)
Symbol
BWOA
ENOA
Description
Min
Typ
Max
Units
Notes
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
0.75
–
–
MHz
Power = Medium, Opamp Bias = High
3.1
–
–
MHz
Power = High, Opamp Bias = High
5.4
–
–
MHz
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
100
–
nV/rt-Hz
Table 26. 3.3V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Min
Typ
Max
Units
Notes
Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10
pF load, Unity Gain)
Power = Low, Opamp Bias = Low
–
–
3.92
μs
Power = Medium, Opamp Bias = High
–
–
0.72
μs
Power = Low, Opamp Bias = Low
–
–
5.41
μs
Power = Medium, Opamp Bias = High
–
–
0.72
μs
Power = Low, Opamp Bias = Low
0.31
–
–
V/μs
Power = Medium, Opamp Bias = High
2.7
–
–
V/μs
Power = Low, Opamp Bias = Low
0.24
–
–
V/μs
Power = Medium, Opamp Bias = High
1.8
–
–
V/μs
Power = Low, Opamp Bias = Low
0.67
–
–
MHz
Power = Medium, Opamp Bias = High
2.8
–
–
MHz
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
100
–
nV/rt-Hz
Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10
pF load, Unity Gain)
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Gain Bandwidth Product
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 7. Typical AGND Noise with P2[4] Bypass
dBV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
Document Number: 001-13108 Rev. **
0.01
0.1 Freq (kHz)
1
10
100
Page 23 of 33
CY8CLED04
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 8. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
0.01
0.1
Freq (kHz)
1
10
100
AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.
Table 27. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Document Number: 001-13108 Rev. **
Min
–
Typ
–
Max
50
Units
μs
Notes
≥ 50 mV overdrive comparator reference set
within VREFLPC.
Page 24 of 33
CY8CLED04
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 28. AC Digital Block Specifications
Function
Timer
Counter
Dead Band
Description
Min
Typ
Max
Units
Capture Pulse Width
50a
–
–
ns
Maximum Frequency, No Capture
–
–
49.92
MHz
Maximum Frequency, With Capture
–
–
25.92
MHz
Enable Pulse Width
50a
–
–
ns
Maximum Frequency, No Enable Input
–
–
49.92
MHz
Maximum Frequency, Enable Input
–
–
25.92
MHz
Notes
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
Kill Pulse Width:
Asynchronous Restart Mode
–
–
ns
Synchronous Restart Mode
50
a
–
–
ns
Disable Mode
50a
–
–
ns
–
–
49.92
MHz
4.75V < Vdd < 5.25V.
CRCPRS
Maximum Input Clock Frequency
(PRS Mode)
–
–
49.92
MHz
4.75V < Vdd < 5.25V.
CRCPRS
Maximum Input Clock Frequency
(CRC Mode)
–
–
24.6
MHz
SPIM
Maximum Input Clock Frequency
–
–
8.2
MHz
SPIS
Maximum Input Clock Frequency
–
–
4.1
MHz
Width of SS_ Negated Between Transmissions
50a
–
–
ns
Transmitter
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at 3.08 MHz due to 8 x over
clocking.
Receiver
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at 3.08 MHz due to 8 x over
clocking.
Maximum Frequency
20
Maximum data rate at 4.1 MHz due to 2 x over
clocking.
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 29. AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency for USB Applications
23.94
24
24.06
MHz
–
Duty Cycle
47
50
53
%
–
Power up to IMO Switch
150
–
–
μs
Document Number: 001-13108 Rev. **
Notes
Page 25 of 33
CY8CLED04
AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 30. 5V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOBSS
BWOBLS
Description
Min
Typ
Max
Units
Notes
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
–
–
2.5
μs
Power = High
–
–
2.5
μs
Power = Low
–
–
2.2
μs
Power = High
–
–
2.2
μs
Power = Low
0.65
–
–
V/μs
Power = High
0.65
–
–
V/μs
Power = Low
0.65
–
–
V/μs
Power = High
0.65
–
–
V/μs
Power = Low
0.8
–
–
MHz
Power = High
0.8
–
–
MHz
Power = Low
300
–
–
kHz
Power = High
300
–
–
kHz
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
Table 31. 3.3V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOBSS
BWOBLS
Description
Min
Typ
Max
Units
Notes
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
–
–
3.8
μs
Power = High
–
–
3.8
μs
Power = Low
–
–
2.6
μs
Power = High
–
–
2.6
μs
Power = Low
0.5
–
–
V/μs
Power = High
0.5
–
–
V/μs
Power = Low
0.5
–
–
V/μs
Power = High
0.5
–
–
V/μs
Power = Low
0.7
–
–
MHz
Power = High
0.7
–
–
MHz
Power = Low
200
–
–
kHz
Power = High
200
–
–
kHz
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
Document Number: 001-13108 Rev. **
Page 26 of 33
CY8CLED04
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 32. AC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
TRSCLK
Rise Time of SCLK
1
–
20
ns
TFSCLK
Fall Time of SCLK
1
–
20
ns
TSSCLK
Data Set up Time to Falling Edge of SCLK
40
–
–
ns
THSCLK
Data Hold Time from Falling Edge of SCLK
40
–
–
ns
FSCLK
Frequency of SCLK
0
–
8
MHz
TERASEB
Flash Erase Time (Block)
–
10
–
ms
TWRITE
Flash Block Write Time
–
30
–
ms
TDSCLK
Data Out Delay from Falling Edge of SCLK
–
–
45
ns
Vdd > 3.6
TDSCLK3
Data Out Delay from Falling Edge of SCLK
–
–
50
ns
3.0 ≤ Vdd ≤ 3.6
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 33. AC Characteristics of the I2C SDA and SCL Pins for Vdd
Standard Mode
Symbol
Description
Min
Fast Mode
Max
Min
Max
Units
FSCLI2C
SCL Clock Frequency
0
100
0
400
kHz
THDSTAI2C
Hold Time (repeated) START Condition. After this
period, the first clock pulse is generated.
4.0
–
0.6
–
μs
TLOWI2C
LOW Period of the SCL Clock
4.7
–
1.3
–
μs
THIGHI2C
HIGH Period of the SCL Clock
4.0
–
0.6
–
μs
TSUSTAI2C
Set-up Time for a Repeated START Condition
4.7
–
0.6
–
μs
THDDATI2C
Data Hold Time
0
–
0
–
μs
TSUDATI2C
Data Set-up Time
250
–
100
–
ns
TSUSTOI2C
Set-up Time for STOP Condition
4.0
–
0.6
–
μs
TBUFI2C
Bus Free Time Between a STOP and START Condition
4.7
–
1.3
–
μs
TSPI2C
Pulse Width of spikes are suppressed by the input filter.
–
–
0
50
ns
a
Notes
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if
the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-13108 Rev. **
Page 27 of 33
CY8CLED04
Figure 9. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
TLOWI2C
TSPI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
Document Number: 001-13108 Rev. **
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Page 28 of 33
CY8CLED04
Packaging Information
Packaging Dimensions
This section illustrates the package specification for the CY8CLED04 EZ-Color device, along with the thermal impedance for the
package and solder reflow peak temperatures.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Figure 10. 68-Lead (8x8 mm x 0.89 mm) QFN
51-85214 *C
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
Important Note Pinned vias for thermal conduction are not required for the low-power PSoC device.
Document Number: 001-13108 Rev. **
Page 29 of 33
CY8CLED04
Thermal Impedance
Table 34. Thermal Impedance for the Package
Package
Typical θJA *
68 QFN**
13.05 oC/W
* TJ = TA + POWER x θJA
** To achieve the thermal impedance specified for the QFN
package, the center thermal pad should be soldered to the PCB
ground plane.
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to
achieve good solderability.
Table 35. Solder Reflow Peak Temperature
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer or PSoC Express. PSoC
Programmer software is compatible with both PSoC ICE-Cube
In-Circuit Emulator and PSoC MiniProg. PSoC programmer is
available free ofcharge at http://www.cypress.com/psocprogrammer.
CY3202-C iMAGEcraft C Compiler
CY3202 is the optional upgrade to PSoC Designer that enables
the iMAGEcraft C compiler. It can be purchased from the
Cypress Online Store. At http://www.cypress.com, click the
Online Store shopping cart icon at the bottom of the web page,
and click PSoC (Programmable System-on-Chip) to view a
current list of available items.
Evaluation Tools
Package
Minimum Peak
Temperature*
Maximum Peak
Temperature
All evaluation tools can be purchased from the Cypress Online
Store.
68 QFN
240oC
260oC
CY3261A-RGB EZ-Color RGB Kit
The CY3261A-RGB board is a preprogrammed HB LED color
mix board with seven pre-set colors using the CY8CLED16
EZ-Color HB LED Controller. The board is accompanied by a
CD containing the color selector software application, PSoC
Express 3.0 Beta 2, PSoC Programmer, and a suite of
documents, schematics, and firmware examples. The color
selector software application can be installed on a host PC and
is used to control the EZ-Color HB LED controller using the
included USB cable. The application enables you to select colors
via a CIE 1931 chart or by entering coordinates. The kit includes:
*Higher temperatures may be required based on the solder melting
point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or
245 ± 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer
specifications.
Development Tools
Software
This section presents the development tools available for all
current PSoC device families including the CY8CLED04
EZ-Color.
PSoC Express™
As the newest addition to the PSoC development software suite,
PSoC Express is the first visual embedded system design tool
that allows a user to create an entire PSoC project and generate
a schematic, BOM, and data sheet without writing a single line
of code. Users work directly with application objects such as
LEDs, switches, sensors, and fans. PSoC Express is available
free of charge at http://www.cypress.com/psocexpress.
PSoC Designer™
At the core of the PSoC development software suite is PSoC
Designer. Utilized by thousands of PSoC developers, this robust
software has been facilitating PSoC designs for half a decade.
PSoC Designer is available free of charge at
http://www.cypress.com under DESIGN RESOURCES >>
Software and Drivers.
Document Number: 001-13108 Rev. **
■
Training Board (CY8CLED16)
■
One mini-A to mini-B USB Cable
■
PSoC Express CD-ROM
■
Design Files and Application Installation CD-ROM
To program and tune this kit via PSoC Express 3.0 you must use
a Mini Programmer Unit (CY3217 Kit) and a CY3240-I2CUSB kit.
CY3210-MiniProg1
The CY3210-MiniProg1 kit allows a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■
MiniProg Programming Unit
■
MiniEval Socket Programming and Evaluation Board
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■
28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
Page 30 of 33
CY8CLED04
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit
includes:
■
USB 2.0 Cable
■
Evaluation Board with LCD Module
CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
Note: CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
■
MiniProg Programming Unit
■
CY3207 Programmer Unit
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■
PSoC ISSP Software CD
■
PSoC Designer Software CD
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
Getting Started Guide
■
USB 2.0 Cable
■
USB 2.0 Cable
3rd-Party Tools
Device Programmers
All device programmers can be purchased from the Cypress
Online Store.
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■
Modular Programmer Base
■
3 Programming Module Cards
■
MiniProg Programming Unit
■
PSoC Designer Software CD
■
Getting Started Guide
Document Number: 001-13108 Rev. **
Several tools have been specially designed by the following
3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools
can be found at http://www.cypress.com under DESIGN
RESOURCES >> Evaluation Boards.
Build a PSoC Emulator into Your Board
For details on how to emulate your circuit before going to volume
production using an on-chip debug (OCD) non-production PSoC
device, see Application Note “Debugging - Build a PSoC
Emulator into Your Board - AN2323” at
http://www.cypress.com/an2323.
The following table lists the CY8CLED04 EZ-Color device key
package features and ordering codes.
Page 31 of 33
CY8CLED04
Ordering Information
Key Device Features
SRAM
(Bytes)
Temperature
Range
Digital Blocks
Analog Blocks
Digital IO Pins
Analog Inputs
Analog Outputs
XRES Pin
CY8CLED04-68LFXI
16K
1K
-40C to +85C
4
6
56
48
2
Yes
CY8CLED04-68LFXIT
16K
1K
-40C to +85C
4
6
56
48
2
Yes
Package
Ordering
Code
Flash
(Bytes)
Table 36. Device Key Features and Ordering Information
68 Pin (8x8 mm) QFN
68 Pin (8x8 mm) QFN
(Tape and Reel)
Ordering Code Definitions
CY 8 C LED
xx - xx xxxx
Package Type:
Thermal Rating:
PX = PDIP Pb-Free
C = Commercial
SX = SOIC Pb-Free
I = Industrial
PVX = SSOP Pb-Free
E = Extended
LFX/LKX = QFN Pb-Free
AX = TQFP Pb-Free
Pin Count
Part Number
LED Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number: 001-13108 Rev. **
Page 32 of 33
CY8CLED04
Revision History
Table 37. CY8CLED04 Data Sheet Revision History
Document Title:
CY8CLED04 EZ-Color HB LED Controller
Document Number: 001-13108
Revision
**
ECN #
1148504
Issue Date
Origin of Change
See ECN
SFVTMP3
Distribution: External/Public
Description of Change
New document (revision **).
Posting: None
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for
use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works
of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with
a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is
prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems
where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-13108 Rev. **
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