CYPRESS CY8CLED08

CY8CLED08
EZ-Color™ HB LED Controller
Features
■
HB LED Controller
❐ Configurable Dimmers Support up to 8
Independent LED Channels
❐ 8-32 Bits of Resolution per Channel
❐ Dynamic Reconfiguration Enables LED
❐ Controller plus other Features; Battery
❐ Charging, Motor Control
■
Visual Embedded Design, PSoC Express
❐ LED Based Express Drivers
• Binning Compensation
• Temperature Feedback
• DMX512
■
PrISM Modulation Technology
❐ Reduces Radiated EMI
❐ Reduces Low Frequency Blinking
■
Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ 3.0 to 5.25V Operating Voltage
❐ Operating Voltages down to 1.0V using
On-Chip Switch Mode Pump (SMP)
❐ Industrial Temperature Range: -40°C to +85°C
■
Flexible On-Chip Memory
❐ 16K Flash Program Storage 50,000 Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
Cypress Semiconductor Corporation
Document Number: 001-12981 Rev. **
•
■
Advanced Peripherals (PSoC Blocks)
❐ 8 Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• Up to 2 Full-Duplex UART
• Multiple SPI™ Masters or Slaves
• Connectable to all GPIO Pins
❐ 12 Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ Complex Peripherals by Combining Blocks
■
Flexible On-Chip Memory
❐ 16K Flash Program Storage 50,000 Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■
Programmable Pin Configurations
❐ 25 mA Sink on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive
Modes on all GPIO
❐ Up to 12 Analog Inputs on GPIO
❐ Four 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on all GPIO
■
Complete Development Tools
❐ Free Development Software
• PSoC Designer™
• PSoC Express™
❐ Full featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128 KBytes Trace Memory
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 12, 2007
CY8CLED08
Overview
Block Diagram
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
Analog
Drivers
PSoC
CORE
System Bus
Global Digital Interconnect
SRAM
256 Bytes
Global Analog Interconnect
SROM
Flash 16K
CPU Core (M8C)
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref.
Digital
Block
Array
Digital
Clocks
Multiply
Accum.
Analog
Block
Array
POR and LVD
Decimator
I 2C
System Resets
Analog
Input
Muxing
Internal
Voltage
Ref.
Switch
Mode
Pump
SYSTEM RESOURCES
Document Number: 001-12981 Rev. **
Page 2 of 37
CY8CLED08
EZ-Color Functional Overview
Resource), provide the flexibility to integrate almost any timing
requirement into the EZ-Color device.
Cypress' EZ-Color family of devices offers the ideal control
solution for High Brightness LED applications requiring intelligent dimming control. EZ-Color devices combine the power and
flexibility of PSoC (Programmable System-on-Chip™); with
Cypress' PrISM (precise illumination signal modulation)
modulation technology providing lighting designers a fully
customizable and integrated lighting solution platform.
EZ-Color GPIOs provide connection to the CPU, digital and
analog resources of the device. Each pin’s drive mode may be
selected from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
The EZ-Color family supports up to 16 independent LED
channels with up to 32 bits of resolution per channel, enabling
lighting designers the flexibility to choose the LED array size and
color quality. PSoC Express software, with lighting specific
drivers, can significantly cut development time and simplify
implementation of fixed color points through temperature and
LED binning compensation. EZ-Color's virtually limitless analog
and digital customization allow for simple integration of features
in addition to intelligent lighting, such as Battery Charging, Image
Stabilization, and Motor Control during the development
process. These features, along with Cypress' best-in-class
quality and design support, make EZ-Color the ideal choice for
intelligent HB LED control applications.
The Digital System
The Digital System is composed of 8 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references.
Figure 1. Digital System Block Diagram
Port 5
Port 3
Port 1
Port 4
Port 2
Digital Clocks
From Core
To System Bus
Port 0
To Analog
System
Target Applications
■
Large Signs
■
General Lighting
■
Architectural Lighting
■
Camera/Cell Phone Flash
Document Number: 001-12981 Rev. **
DCB02
DCB03
8
Row Input
Configuration
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose IO).
The EZ-Color family incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate
to 2.5% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
Sleep timer and WDT. If crystal accuracy is desired, the ECO
(32.768 kHz external crystal oscillator) is available for use as a
Real Time Clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
DBB01
4
8
The PSoC Core
Memory encompasses 16K of Flash for program storage, 256
bytes of SRAM for data storage, and up to 2K of EEPROM
emulated using the Flash. Program Flash utilizes four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
DBB00
4
8
Flashlights
The M8C CPU core is a powerful processor with speeds up to 48
MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with 17 vectors,
to simplify programming of real time embedded events. Program
execution is timed and protected using the included Sleep and
Watch Dog Timers (WDT).
Row 0
Row 1
DBB10
DBB11
DCB12
8
4
Row Output
Configuration
■
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input
Configuration
LCD Backlight
Row Output
Configuration
■
DCB13
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Digital peripheral configurations include those listed below.
■
PrISM (8 to 32 bit)
■
PWMs (8 to 32 bit)
■
PWMs with Dead band (8 to 32 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
UART 8 bit with selectable parity (up to 2)
■
SPI slave and master (up to 2)
■
I2C slave and multi-master (1 available as a System Resource)
■
Cyclical Redundancy Checker/Generator (8 to 32 bit)
■
IrDA (up to 2)
■
Generators (8 to 32 bit)
Page 3 of 37
CY8CLED08
Digital blocks are provided in rows of four, where the number of
blocks varies by EZ-Color device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in the table titled EZ-Color Device Characteristics.
Figure 2. Analog System Block Diagram
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
AGNDIn RefIn
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
P2[3]
The Analog System
The Analog System is composed of 12 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common EZ-Color analog functions (most
available as user modules) are listed below.
■
P2[1]
P2[0]
Array Input Configuration
■
Filters (2, 4, 6, and 8 pole band-pass, low-pass, and notch)
■
Amplifiers (up to 4, with selectable gain to 48x)
■
Instrumentation amplifiers (up to 2, with selectable gain to 93x)
■
Comparators (up to 4, with 16 selectable thresholds)
■
DACs (up to 4, with 6- to 9-bit resolution)
■
Multiplying DACs (up to 4, with 6- to 9-bit resolution)
ACB00
ACB01
ACB02
ACB03
■
High current output drivers (four with 30 mA drive as a Core
Resource)
ASC10
ASD11
ASC12
ASD13
■
1.3V reference (as a System Resource)
ASD20
ASC21
ASD22
ASC23
■
DTMF Dialer
■
Modulators
■
Correlators
■
Peak detectors
■
Many other topologies possible
Document Number: 001-12981 Rev. **
P2[4]
P2[2]
Analog-to-digital converters (up to 4, with 6- to 14-bit resolution,
selectable as Incremental, Delta Sigma, and SAR)
Analog blocks are provided in columns of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in the figure below.
P2[6]
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
Block Array
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Page 4 of 37
CY8CLED08
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include a multiplier, decimator, switch mode
pump, low voltage detection, and power on reset. Statements
describing the merits of each system resource are below.
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■
Multiply accumulate (MAC) provides fast 8-bit multiplier with
32-bit accumulate, to assist in general math and digital filters.
■
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
■
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■
Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.
■
An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■
An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
EZ-Color Device Characteristics
Depending on your EZ-Color device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4
analog blocks. The following table lists the resources available for specific EZ-Color device groups. The device covered by this data
sheet is shown in the highlighted row of the table
CapSense
6
1K
16K
Yes
4
12
256 Bytes
16K
No
CY8CLED16
16
64
4
16
12
4
4
12
2K
32K
No
Document Number: 001-12981 Rev. **
SRAM
Size
2
4
Analog
Blocks
2
12
Analog
Columns
48
8
Analog
Outputs
4
2
Analog
Inputs
1
44
Digital
Blocks
56
8
Digital
Rows
4
CY8CLED08
Digital
IO
CY8CLED04
PSoC Part
Number
LED
Channels
Flash
Size
Table 1. EZ-Color Device Characteristics
Page 5 of 37
CY8CLED08
Getting Started
Development Tools
The quickest path to understanding the EZ-Color silicon is by
reading this data sheet and using the PSoC Express Integrated
Development Environment (IDE). This data sheet is an overview
of the EZ-Color integrated circuit and presents specific pin,
register, and electrical specifications.
PSoC Express is a high-level design tool for creating embedded
systems with devices using Cypress's PSoC Mixed-Signal
technology. With PSoC Express you create a complete
embedded solution including all necessary on-chip peripherals,
block configuration, interrupt handling and application software
without writing a single line of assembly or C code.
For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest device data sheets on the web
at http://www.cypress.com/ez-color.
PSoC Express solves design problems the way you think about
the system:
■
Select input and output devices based upon system requirements.
■
Add a communications interface and define its interface to
system (using registers).
■
Define when and how an output device changes state based
upon any and all other system devices.
■
Based upon the design, automatically select one or more PSoC
Mixed-Signal Controllers that match system requirements.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com, click the Online Store shopping cart
icon at the bottom of the web page, and click EZ-Color to view
a current list of available items.
Figure 3. PSoC Express
Technical Training Modules
Free PSoC technical training modules are available for users
new to PSoC. Training modules cover designing, debugging,
advanced analog and CapSense. Go to
http://www.cypress.com/techtrain.
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com, click on Design
Support located on the left side of the web page, and select
CYPros Consultants.
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support/login.cfm.
PSoC Express Subsystems
Application Notes
Express Editor
A long list of application notes will assist you in every aspect of
your design effort. To view the PSoC application notes, go to the
http://www.cypress.com web site and select Application Notes
under the Design Resources list located in the center of the web
page. Application Notes are sorted by date by default.
The Express Editor allows you to create designs visually by
dragging and dropping inputs, outputs, communication interfaces, and other design elements, and then describing the logic
that controls them.
Project Manager
The Project Manager allows you to work with your applications
and projects in PSoC Express. A PSoC Express application is a
top level container for projects and their associated files. Each
project contains a design that uses a single PSoC device. An
application can contain multiple projects so if you are creating an
application that uses multiple PSoC devices you can keep all of
the projects together in a single application.
Most of the files associated with a project are automatically
generated by PSoC Express during the build process, but you
can make changes directly to the custom.c and custom.h files
Document Number: 001-12981 Rev. **
Page 6 of 37
CY8CLED08
and also add your own custom code to the project in the Project
Manager.
Application Editor
The Application Editor allows you to edit custom.c and custom.h
as well as any C or assembly language source code that you add
to your project. With PSoC Express you can create application
software without writing a single line of assembly or C code, but
you have a full featured application editor at your finger tips if you
want it.
Build Manager
The Build Manager gives you the ability to build the application
software, assign pins, and generate the data sheet, schematic,
and BOM for your project.
Board Monitor
The Board Monitor is a debugging tool designed to be used while
attached to a prototype board through a communication interface
that allows you to monitor changes in the various design
elements in real time.
The default communication for the board monitor is I2C. It uses
the CY3240-I2USB I2C to USB Bridge Debugging/Communication Kit.
Tuners
A Tuner is a visual interface for the Board Monitor that allows you
to view the performance of the HB LED drivers on your test board
while your program is running, and manually override values and
see the results.
Document Conventions
Units of Measure
A units of measure table is located in the Electrical Specifications
section. Table 6 on page 13 lists all the abbreviations used to
measure the PSoC devices.
Acronyms Used
The following table lists the acronyms that are used in this
document.
Acronym
Description
AC
alternating current
ADC
analog-to-digital converter
API
application programming interface
CPU
central processing unit
CT
continuous time
DAC
digital-to-analog converter
DC
direct current
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only memory
FSR
full scale range
GPIO
general purpose IO
GUI
graphical user interface
HBM
human body model
ICE
in-circuit emulator
ILO
internal low speed oscillator
IMO
internal main oscillator
IO
input/output
IPOR
imprecise power on reset
LSb
least-significant bit
LVD
low voltage detect
MSb
most-significant bit
PC
program counter
PLL
phase-locked loop
POR
power on reset
PPOR
precision power on reset
PSoC®
Programmable System-on-Chip™
PWM
pulse width modulator
SC
switched capacitor
SLIMO
slow IMO
SMP
switch mode pump
SRAM
static random access memory
Numeric Naming
Hexidecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’ or ‘b’ are decimal.
Document Number: 001-12981 Rev. **
Page 7 of 37
CY8CLED08
Pin Information
Pinouts
48-Pin Part Pinout SSOP
Table 2. 48-Pin Part Pinout (SSOP)
Pin
No.
Type
Digital
Analog
Pin
Name
1
IO
I
P0[7]
Analog column mux input.
2
IO
IO
P0[5]
Analog column mux input and column output.
3
IO
IO
P0[3]
Analog column mux input and column output.
4
IO
I
P0[1]
Analog column mux input.
5
IO
6
IO
7
IO
I
8
IO
I
9
IO
P4[7]
10
IO
P4[5]
11
IO
P4[3]
12
IO
13
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
P2[7]
P2[5]
P2[3]
Direct switched capacitor block input.
P2[1]
Direct switched capacitor block input.
P4[1]
Power
SMP
Switch Mode Pump (SMP) connection to external components required.
14
IO
P3[7]
15
IO
P3[5]
16
IO
P3[3]
17
IO
P3[1]
18
IO
P5[3]
19
IO
P5[1]
20
IO
P1[7]
I2C Serial Clock (SCL).
21
IO
P1[5]
I2C Serial Data (SDA).
22
IO
P1[3]
23
IO
P1[1]
Crystal Input (XTALin), I2C Serial Clock (SCL),
ISSP SCLK*.
24
48-Pin Device
Description
Power
A, I, P0[1]
P2[7]
P2[5]
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
SSOP
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Vdd
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6], External VRef
P2[4], External AGND
P2[2], A, I
P2[0], A, I
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P5[2]
P5[0]
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
Vss
Ground connection.
25
IO
P1[0]
Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP SDATA.*
26
IO
P1[2]
27
IO
P1[4]
28
IO
P1[6]
39
IO
29
IO
P5[0]
39
IO
30
IO
P5[2]
40
IO
I
P2[0]
Direct switched capacitor block input.
31
IO
P3[0]
41
IO
I
P2[2]
Direct switched capacitor block input.
32
IO
P3[2]
42
IO
P2[4]
External Analog Ground (AGND).
33
IO
P3[4]
43
IO
P2[6]
External Voltage Reference (VRef).
34
IO
35
Optional External Clock Input (EXTCLK).
P3[6]
Input
XRES
Pin
No.
Digital
Analog
Pin
Name
Description
P4[6]
P4[6]
44
IO
I
P0[0]
Analog column mux input.
Active high external reset with internal pull down. 45
IO
IO
P0[2]
Analog column mux input and column output.
Analog column mux input and column output.
36
IO
P4[0]
46
IO
IO
P0[4]
37
IO
P4[2]
47
IO
I
P0[6]
Analog column mux input.
38
IO
P4[4]
48
Vdd
Supply voltage.
Power
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset).
Document Number: 001-12981 Rev. **
Page 8 of 37
CY8CLED08
48-Pin Part Pinout QFN
Table 3. 48-Pin Part Pinout (QFN**)
Pin
Name
IO
I
P2[3]
Direct switched capacitor block input.
2
IO
I
P2[1]
Direct switched capacitor block input.
3
IO
P4[7]
4
IO
P4[5]
5
IO
P4[3]
6
IO
P2[5]
P2[7]
P0[1], A, I
P0[3], A, IO
P0[5], A, IO
P0[7], A, I
1
8
IO
P3[7]
9
IO
P3[5]
10
IO
P3[3]
11
IO
P3[1]
12
IO
P5[3]
13
IO
P5[1]
14
IO
P1[7]
I2C Serial Clock (SCL).
15
IO
P1[5]
I2C Serial Data (SDA).
16
IO
P1[3]
17
IO
P1[1]
18
Power
Crystal Input (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK*.
Vss
Ground connection.
19
IO
P1[0]
Crystal Output (XTALout), I2C Serial Data (SDA),
ISSP-SDATA*.
20
IO
P1[2]
21
IO
P1[4]
22
IO
P1[6]
23
IO
P5[0]
24
IO
P5[2]
25
IO
P3[0]
26
IO
P3[2]
27
IO
P3[4]
28
IO
29
Optional External Clock Input (EXTCLK).
1
2
3
4
5
6
7
8
9
10
11
12
QFN
(Top View)
36
35
34
33
32
31
30
29
28
27
26
25
P2[4], External AGND
P2[2], A, I
P2[0], A, I
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P3[6]
Input
XRES
Active high external reset with internal pull down.
30
IO
P4[0]
31
IO
P4[2]
32
IO
P4[4]
33
IO
34
IO
I
P2[0]
Direct switched capacitor block input.
35
IO
I
P2[2]
Direct switched capacitor block input.
36
IO
P2[4]
External Analog Ground (AGND).
37
IO
P2[6]
External Voltage Reference (VRef).
38
IO
I
P0[0]
Analog column mux input.
39
IO
IO
P0[2]
Analog column mux input and column output.
40
IO
IO
P0[4]
Analog column mux input and column output.
41
IO
I
P0[6]
Analog column mux input.
42
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
I2C SCL, XTALin, P1[1]
Vss
I2C SDA, XTALout, P1[0]
P1[2]
EXTCLK, P1[4]
P1[6]
P5[0]
P5[2]
Switch Mode Pump (SMP) connection to external
components required.
I2C SDA, P1[5]
P1[3]
SMP
48
47
46
45
44
43
42
41
40
39
38
37
P4[1]
Power
13
14
15
16
17
18
19
20
21
22
23
24
7
48-Pin PSoC Device
Description
Analog
Vdd
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6], External VRef
Type
Digital
P5[1]
I2C SCL, P1[7]
Pin
No.
P4[6]
Vdd
Supply voltage.
43
IO
Power
I
P0[7]
Analog column mux input.
44
IO
IO
P0[5]
Analog column mux input and column output.
45
IO
IO
P0[3]
Analog column mux input and column output.
46
IO
I
P0[1]
Analog column mux input.
47
IO
P2[7]
48
IO
P2[5]
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset).
** The QFN package has a center pad that must be connected to ground (Vss).
Document Number: 001-12981 Rev. **
Page 9 of 37
CY8CLED08
Register Reference
This chapter lists the registers of the CY8CLED08 EZ-Color
device.
Register Conventions
The register conventions specific to this section are listed in the
following table. Register Mapping Tables
Convention
R
Register Mapping Tables
The device has a total register address space of 512 bytes. The
register space is referred to as IO space and is divided into two
banks. The XOI bit in the Flag register (CPU_F) determines
which bank the user is currently in. When the XOI bit is set the
user is in Bank 1.
Note In the following register mapping tables, blank fields are
reserved and should not be accessed.
Description
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Table 4. Register Map Bank 0 Table: User Space
Addr (0,Hex)
Access
PRT0DR
Name
00
RW
Name
40
ASC10CR0
80
RW
C0
PRT0IE
01
RW
41
ASC10CR1
81
RW
C1
PRT0GS
02
RW
42
ASC10CR2
82
RW
C2
PRT0DM2
03
RW
43
ASC10CR3
83
RW
C3
PRT1DR
04
RW
44
ASD11CR0
84
RW
C4
PRT1IE
05
RW
45
ASD11CR1
85
RW
C5
PRT1GS
06
RW
46
ASD11CR2
86
RW
C6
PRT1DM2
07
RW
47
ASD11CR3
87
RW
C7
PRT2DR
08
RW
48
ASC12CR0
88
RW
C8
PRT2IE
09
RW
49
ASC12CR1
89
RW
C9
PRT2GS
0A
RW
4A
ASC12CR2
8A
RW
CA
PRT2DM2
0B
RW
4B
ASC12CR3
8B
RW
CB
PRT3DR
0C
RW
4C
ASD13CR0
8C
RW
CC
PRT3IE
0D
RW
4D
ASD13CR1
8D
RW
CD
PRT3GS
0E
RW
4E
ASD13CR2
8E
RW
CE
PRT3DM2
0F
RW
4F
ASD13CR3
8F
RW
CF
PRT4DR
10
RW
50
ASD20CR0
90
RW
D0
PRT4IE
11
RW
51
ASD20CR1
91
RW
D1
PRT4GS
12
RW
52
ASD20CR2
92
RW
D2
PRT4DM2
13
RW
53
ASD20CR3
93
RW
D3
PRT5DR
14
RW
54
ASC21CR0
94
RW
D4
PRT5IE
15
RW
55
ASC21CR1
95
RW
PRT5GS
16
RW
56
ASC21CR2
96
RW
I2C_CFG
D6
RW
PRT5DM2
17
RW
57
ASC21CR3
97
RW
I2C_SCR
D7
#
18
58
ASD22CR0
98
RW
I2C_DR
D8
RW
19
59
ASD22CR1
99
RW
I2C_MSCR
D9
#
1A
5A
ASD22CR2
9A
RW
INT_CLR0
DA
RW
1B
5B
ASD22CR3
9B
RW
INT_CLR1
DB
RW
1C
5C
ASC23CR0
9C
RW
1D
5D
ASC23CR1
9D
RW
INT_CLR3
DD
RW
1E
5E
ASC23CR2
9E
RW
INT_MSK3
DE
RW
1F
5F
ASC23CR3
9F
RW
AMX_IN
Addr (0,Hex)
60
Access
Addr (0,Hex)
Access
Name
Addr (0,Hex)
Access
D5
DC
DF
DBB00DR0
20
#
A0
INT_MSK0
E0
RW
DBB00DR1
21
W
61
A1
INT_MSK1
E1
RW
DBB00DR2
22
RW
62
A2
INT_VC
E2
RC
DBB00CR0
23
#
ARF_CR
63
RW
A3
RES_WDT
E3
W
DBB01DR0
24
#
CMP_CR0
64
#
A4
DEC_DH
E4
RC
Blank fields are Reserved and should not be accessed.
Document Number: 001-12981 Rev. **
RW
Name
# Access is bit specific.
Page 10 of 37
CY8CLED08
Table 4. Register Map Bank 0 Table: User Space (continued)
Addr (0,Hex)
Access
DBB01DR1
Name
25
W
ASY_CR
Name
65
Addr (0,Hex)
#
Access
Name
A5
Addr (0,Hex)
Access
DEC_DL
Name
E5
Addr (0,Hex)
RC
Access
DBB01DR2
26
RW
CMP_CR1
66
RW
A6
DEC_CR0
E6
RW
DBB01CR0
27
#
67
A7
DEC_CR1
E7
RW
DCB02DR0
28
#
68
A8
MUL_X
E8
W
DCB02DR1
29
W
69
A9
MUL_Y
E9
W
DCB02DR2
2A
RW
6A
AA
MUL_DH
EA
R
DCB02CR0
2B
#
6B
AB
MUL_DL
EB
R
DCB03DR0
2C
#
6C
AC
ACC_DR1
EC
RW
DCB03DR1
2D
W
6D
AD
ACC_DR0
ED
RW
DCB03DR2
2E
RW
6E
AE
ACC_DR3
EE
RW
DCB03CR0
2F
#
6F
AF
ACC_DR2
EF
RW
DBB10DR0
30
#
ACB00CR3
70
RW
RDI0RI
B0
RW
F0
DBB10DR1
31
W
ACB00CR0
71
RW
RDI0SYN
B1
RW
F1
DBB10DR2
32
RW
ACB00CR1
72
RW
RDI0IS
B2
RW
F2
DBB10CR0
33
#
ACB00CR2
73
RW
RDI0LT0
B3
RW
F3
DBB11DR0
34
#
ACB01CR3
74
RW
RDI0LT1
B4
RW
F4
DBB11DR1
35
W
ACB01CR0
75
RW
RDI0RO0
B5
RW
F5
DBB11DR2
36
RW
ACB01CR1
76
RW
RDI0RO1
B6
RW
DBB11CR0
37
#
ACB01CR2
77
RW
DCB12DR0
38
#
ACB02CR3
78
RW
RDI1RI
B8
RW
F8
DCB12DR1
39
W
ACB02CR0
79
RW
RDI1SYN
B9
RW
F9
DCB12DR2
3A
RW
ACB02CR1
7A
RW
RDI1IS
BA
RW
FA
DCB12CR0
3B
#
ACB02CR2
7B
RW
RDI1LT0
BB
RW
FB
DCB13DR0
3C
#
ACB03CR3
7C
RW
RDI1LT1
BC
RW
FC
DCB13DR1
3D
W
ACB03CR0
7D
RW
RDI1RO0
BD
RW
DCB13DR2
3E
RW
ACB03CR1
7E
RW
RDI1RO1
BE
RW
DCB13CR0
3F
#
ACB03CR2
7F
RW
F6
B7
CPU_F
F7
RL
FD
BF
CPU_SCR1
FE
#
CPU_SCR0
FF
#
# Access is bit specific.
Blank fields are Reserved and should not be accessed.
Table 5. Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
Add (1,Hex)
00
Access
RW
PRT0DM1
01
RW
PRT0IC0
02
RW
PRT0IC1
03
PRT1DM0
Name
Addr (1,Hex)
40
Access
Name
ASC10CR0
Addr (1,Hex)
80
Access
RW
Name
Addr (1,Hex)
C0
Access
41
ASC10CR1
81
RW
C1
42
ASC10CR2
82
RW
C2
RW
43
ASC10CR3
83
RW
C3
04
RW
44
ASD11CR0
84
RW
C4
PRT1DM1
05
RW
45
ASD11CR1
85
RW
C5
PRT1IC0
06
RW
46
ASD11CR2
86
RW
C6
PRT1IC1
07
RW
47
ASD11CR3
87
RW
C7
PRT2DM0
08
RW
48
ASC12CR0
88
RW
C8
PRT2DM1
09
RW
49
ASC12CR1
89
RW
C9
PRT2IC0
0A
RW
4A
ASC12CR2
8A
RW
CA
PRT2IC1
0B
RW
4B
ASC12CR3
8B
RW
CB
PRT3DM0
0C
RW
4C
ASD13CR0
8C
RW
CC
PRT3DM1
0D
RW
4D
ASD13CR1
8D
RW
CD
PRT3IC0
0E
RW
4E
ASD13CR2
8E
RW
CE
PRT3IC1
0F
RW
4F
ASD13CR3
8F
RW
PRT4DM0
10
RW
50
ASD20CR0
90
RW
GDI_O_IN
D0
RW
PRT4DM1
11
RW
51
ASD20CR1
91
RW
GDI_E_IN
D1
RW
PRT4IC0
12
RW
52
ASD20CR2
92
RW
GDI_O_OU
D2
RW
PRT4IC1
13
RW
53
ASD20CR3
93
RW
GDI_E_OU
D3
RW
PRT5DM0
14
RW
54
ASC21CR0
94
RW
D4
CF
PRT5DM1
15
RW
55
ASC21CR1
95
RW
D5
PRT5IC0
16
RW
56
ASC21CR2
96
RW
D6
PRT5IC1
17
RW
57
ASC21CR3
97
RW
D7
18
58
ASD22CR0
98
RW
D8
19
59
ASD22CR1
99
RW
D9
1A
5A
ASD22CR2
9A
RW
DA
1B
5B
ASD22CR3
9B
RW
DB
1C
5C
ASC23CR0
9C
RW
1D
5D
ASC23CR1
9D
RW
OSC_GO_EN
DD
RW
1E
5E
ASC23CR2
9E
RW
OSC_CR4
DE
RW
1F
5F
ASC23CR3
9F
RW
OSC_CR3
DF
RW
Blank fields are Reserved and should not be accessed.
Document Number: 001-12981 Rev. **
DC
# Access is bit specific.
Page 11 of 37
CY8CLED08
Table 5. Register Map Bank 1 Table: Configuration Space (continued)
Name
DBB00FN
Add (1,Hex)
20
Access
RW
Name
CLK_CR0
Addr (1,Hex)
60
Access
RW
DBB00IN
21
RW
CLK_CR1
61
RW
DBB00OU
22
RW
ABF_CR0
62
RW
AMD_CR0
63
RW
23
Name
Addr (1,Hex)
A0
Access
Name
OSC_CR0
Addr (1,Hex)
E0
Access
RW
A1
OSC_CR1
E1
RW
A2
OSC_CR2
E2
RW
A3
VLT_CR
E3
RW
VLT_CMP
E4
R
DBB01FN
24
RW
64
A4
DBB01IN
25
RW
65
A5
E5
DBB01OU
26
RW
E6
27
AMD_CR1
66
RW
A6
ALT_CR0
67
RW
A7
E7
DCB02FN
28
RW
ALT_CR1
68
RW
A8
IMO_TR
E8
W
DCB02IN
29
RW
CLK_CR2
69
RW
A9
ILO_TR
E9
W
DCB02OU
2A
RW
6A
AA
BDG_TR
EA
RW
6B
AB
ECO_TR
EB
W
2B
DCB03FN
2C
RW
6C
AC
EC
DCB03IN
2D
RW
6D
AD
ED
DCB03OU
2E
RW
6E
AE
EE
6F
AF
2F
EF
DBB10FN
30
RW
ACB00CR3
70
RW
RDI0RI
B0
RW
F0
DBB10IN
31
RW
ACB00CR0
71
RW
RDI0SYN
B1
RW
F1
DBB10OU
32
RW
ACB00CR1
72
RW
RDI0IS
B2
RW
F2
ACB00CR2
73
RW
RDI0LT0
B3
RW
F3
33
DBB11FN
34
RW
ACB01CR3
74
RW
RDI0LT1
B4
RW
F4
DBB11IN
35
RW
ACB01CR0
75
RW
RDI0RO0
B5
RW
F5
DBB11OU
36
RW
ACB01CR1
76
RW
RDI0RO1
B6
RW
ACB01CR2
77
RW
37
B7
F6
CPU_F
F7
DCB12FN
38
RW
ACB02CR3
78
RW
RDI1RI
B8
RW
F8
DCB12IN
39
RW
ACB02CR0
79
RW
RDI1SYN
B9
RW
F9
DCB12OU
3A
RW
ACB02CR1
7A
RW
RDI1IS
BA
RW
FA
ACB02CR2
7B
RW
RDI1LT0
BB
RW
FB
FC
3B
DCB13FN
3C
RW
ACB03CR3
7C
RW
RDI1LT1
BC
RW
DCB13IN
3D
RW
ACB03CR0
7D
RW
RDI1RO0
BD
RW
DCB13OU
3E
RW
ACB03CR1
7E
RW
RDI1RO1
BE
RW
ACB03CR2
7F
RW
3F
Blank fields are Reserved and should not be accessed.
Document Number: 001-12981 Rev. **
BF
RL
FD
CPU_SCR1
FE
#
CPU_SCR0
FF
#
# Access is bit specific.
Page 12 of 37
CY8CLED08
Electrical Specifications
This section presents the DC and AC electrical specifications of
the CY8CLED08 EZ-Color device. For the most up to date
electrical specifications, confirm that you have the most recent
data sheet by going to the web at
http://www.cypress.com/ez-color.
The following table lists the units of measure that are used in this
section.
Table 6. Units of Measure
Symbol
Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC,
except where noted. Specifications for devices running at greater
than 12 MHz are valid for -40oC ≤ TA ≤ 70oC and TJ ≤ 82oC.
Figure 4. Voltage versus CPU Frequency
5.25
Vdd Voltage
lid ng
Va rati n
pe io
O eg
R
4.75
3.00
CPU Frequency
12 MHz
Symbol
Unit of Measure
μW
microwatts
dB
decibels
mA
milli-ampere
fF
femto farad
ms
milli-second
Hz
hertz
mV
milli-volts
KB
1024 bytes
nA
nanoampere
Kbit
1024 bits
ns
nanosecond
kHz
kilohertz
nV
nanovolts
kΩ
kilohm
Ω
ohm
MHz
megahertz
pA
picoampere
MΩ
megaohm
pF
picofarad
μA
microampere
pp
peak-to-peak
μF
microfarad
ppm
μH
microhenry
ps
picosecond
μs
microsecond
sps
samples per second
μV
microvolts
σ
sigma: one standard deviation
microvolts
root-mean-square
V
volts
C
μVrms
93 kHz
Unit of Measure
degree Celsius
o
parts per million
24 MHz
Absolute Maximum Ratings
Table 7. Absolute Maximum Ratings
Symbol
Description
Min
Typ
Max
Units
TSTG
Storage Temperature
-55
25
+100
o
TA
Ambient Temperature with Power Applied
-40
–
+85
o
Vdd
Supply Voltage on Vdd Relative to Vss
-0.5
–
+6.0
V
VIO
DC Input Voltage
Vss- 0.5
–
Vdd + 0.5
V
VIOZ
DC Voltage Applied to Tri-state
Vss - 0.5
–
Vdd + 0.5
V
IMIO
Maximum Current into any Port Pin
-25
–
+50
mA
IMAIO
Maximum Current into any Port Pin Configured as Analog Driver
-50
–
+50
mA
ESD
Electro Static Discharge Voltage
2000
–
–
V
LU
Latch-up Current
–
–
200
mA
Document Number: 001-12981 Rev. **
C
Notes
Higher storage temperatures will reduce data
retention time. Recommended storage temperature is +25oC ± 25oC. Extended duration storage temperatures above 65oC will degrade
reliability.
C
Human Body Model ESD.
Page 13 of 37
CY8CLED08
Operating Temperature
Table 8. Operating Temperature
Symbol
Description
Min
Typ
Max
Units
TA
Ambient Temperature
-40
–
+85
o
TJ
Junction Temperature
-40
–
+100
oC
Notes
C
The temperature rise from ambient to junction is
package specific. See “Thermal Impedances”
on page 34. The user must limit the power consumption to comply with this requirement.
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 9. DC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Vdd
Supply Voltage
3.00
–
5.25
V
IDD
Supply Current
–
5
8
mA
Conditions are Vdd = 5.0V, TA = 25 oC, CPU = 3
MHz, SYSCLK doubler disabled. VC1 = 1.5
MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz.
IDD3
Supply Current
–
3.3
6.0
mA
Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3
MHz, SYSCLK doubler disabled. VC1 = 1.5
MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz.
ISB
Sleep (Mode) Current with POR, LVD, Sleep Timer, and
WDT.a
–
3
6.5
μA
Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC ≤ TA ≤ 55 oC.
ISBH
Sleep (Mode) Current with POR, LVD, Sleep Timer, and
WDT at high temperature.a
–
4
25
μA
Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 oC < TA ≤ 85 oC.
ISBXTL
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and external crystal.a
–
4
7.5
μA
Conditions are with properly loaded, 1 μW max,
32.768 kHz crystal. Vdd = 3.3V, -40 oC ≤ TA ≤
55 oC.
ISBXTLH
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and external crystal at high temperature.a
–
5
26
μA
Conditions are with properly loaded, 1 μW max,
32.768 kHz crystal. Vdd = 3.3V, 55 oC < TA ≤ 85
o
C.
VREF
Reference Voltage (Bandgap) for Silicon A b
1.275
1.300
1.325
V
Trimmed for appropriate Vdd.
VREF
Reference Voltage (Bandgap) for Silicon B b
1.280
1.300
1.320
V
Trimmed for appropriate Vdd.
a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar functions
enabled.
b. Refer to the “Ordering Information” on page 36.
Document Number: 001-12981 Rev. **
Page 14 of 37
CY8CLED08
DC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10. DC GPIO Specifications
Symbol
Description
Min
Typ
Max
5.6
Units
Notes
kΩ
RPU
Pull up Resistor
4
8
RPD
Pull down Resistor
4
5.6
8
kΩ
VOH
High Output Level
Vdd - 1.0
–
–
V
IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads,
4 on even port pins (for example, P0[2], P1[4]),
4 on odd port pins (for example, P0[3], P1[5])).
VOL
Low Output Level
–
–
0.75
V
IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads,
4 on even port pins (for example, P0[2], P1[4]),
4 on odd port pins (for example, P0[3], P1[5])).
0.8
V
Vdd = 3.0 to 5.25.
V
Vdd = 3.0 to 5.25.
VIL
Input Low Level
–
–
VIH
Input High Level
2.1
–
VH
Input Hysterisis
–
60
–
mV
IIL
Input Leakage (Absolute Value)
–
1
–
nA
Gross tested to 1 μA.
CIN
Capacitive Load on Pins as Input
–
3.5
10
pF
Package and pin dependent. Temp = 25oC.
COUT
Capacitive Load on Pins as Output –
3.5
10
pF
Package and pin dependent. Temp = 25oC.
DC Operational Amplifier Specifications
The Operational Amplifier is a component of both the Analog
Continuous Time PSoC blocks and the Analog Switched Cap
PSoC blocks. The guaranteed specifications are measured in
the Analog Continuous Time PSoC block. Typical parameters
apply to 5V at 25°C and are for design guidance only.
The following tables list guaranteed maximum and minimum
specifications for the voltage and temperature ranges: 4.75V to
5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤
85°C, respectively. Typical parameters apply to 5V and 3.3V at
25°C and are for design guidance only.
Table 11. 5V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Min
Typ
Max
Units
Notes
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
–
1.6
10
mV
Power = Medium, Opamp Bias = High
–
1.3
8
mV
Power = High, Opamp Bias = High
–
1.2
7.5
mV
TCVOSOA
Average Input Offset Voltage Drift
–
7.0
35.0
μV/oC
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
20
–
pA
Gross tested to 1 μA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent. Temp = 25oC.
VCMOA
Common Mode Voltage Range
0.0
–
Vdd
V
Common Mode Voltage Range (high power or high
opamp bias)
0.5
–
Vdd - 0.5
The common-mode input voltage range is measured through an analog output buffer. The
specification includes the limitations imposed
by the characteristics of the analog output
buffer.
–
–
dB
Specification is applicable at high power. For all
other bias modes (except high power, high
opamp bias), minimum is 60 dB.
–
–
dB
Specification is applicable at high power. For all
other bias modes (except high power, high
opamp bias), minimum is 60 dB.
CMRROA
GOLOA
VOHIGHOA
Common Mode Rejection Ratio
Power = Low
60
Power = Medium
60
Power = High
60
Open Loop Gain
Power = Low
60
Power = Medium
60
Power = High
80
High Output Voltage Swing (internal signals)
Power = Low
Vdd - 0.2
–
–
V
Power = Medium
Vdd - 0.2
–
–
V
Power = High
Vdd - 0.5
–
–
V
Document Number: 001-12981 Rev. **
Page 15 of 37
CY8CLED08
Table 11. 5V DC Operational Amplifier Specifications (continued)
Symbol
VOLOWOA
ISOA
PSRROA
Description
Min
Typ
Max
Units
Notes
Low Output Voltage Swing (internal signals)
Power = Low
–
–
0.2
V
Power = Medium
–
–
0.2
V
Power = High
–
–
0.5
V
Power = Low, Opamp Bias = Low
–
150
200
μA
Power = Low, Opamp Bias = High
–
300
400
μA
Power = Medium, Opamp Bias = Low
–
600
800
μA
Power = Medium, Opamp Bias = High
–
1200
1600
μA
Power = High, Opamp Bias = Low
–
2400
3200
μA
Power = High, Opamp Bias = High
–
4600
6400
μA
Supply Voltage Rejection Ratio
60
–
–
dB
Min
Typ
Supply Current (including associated AGND buffer)
Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤ VIN
≤ Vdd.
Table 12. 3.3V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Max
Units
Notes
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
–
1.65
10
mV
Power = Medium, Opamp Bias = High
–
1.32
8
mV
High Power is 5 Volts Only
TCVOSOA
Average Input Offset Voltage Drift
–
7.0
35.0
μV/oC
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
20
–
pA
Gross tested to 1 μA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent. Temp = 25oC.
VCMOA
Common Mode Voltage Range
0.2
–
Vdd - 0.2
V
The common-mode input voltage range is
measured through an analog output buffer.
The specification includes the limitations
imposed by the characteristics of the analog
output buffer.
CMRROA
Common Mode Rejection Ratio
–
–
dB
Specification is applicable at high power. For
all other bias modes (except high power, high
opamp bias), minimum is 60 dB.
–
–
dB
Specification is applicable at high power. For
all other bias modes (except high power, high
opamp bias), minimum is 60 dB.
GOLOA
VOHIGHOA
VOLOWOA
ISOA
PSRROA
Power = Low
50
Power = Medium
50
Power = High
50
Open Loop Gain
Power = Low
60
Power = Medium
60
Power = High
80
High Output Voltage Swing (internal signals)
Power = Low
Vdd - 0.2
–
–
V
Power = Medium
Vdd - 0.2
–
–
V
Power = High is 5V only
Vdd - 0.2
–
–
V
Power = Low
–
–
0.2
V
Power = Medium
–
–
0.2
V
Power = High
–
–
0.2
V
Power = Low, Opamp Bias = Low
–
150
200
μA
Power = Low, Opamp Bias = High
–
300
400
μA
Power = Medium, Opamp Bias = Low
–
600
800
μA
Power = Medium, Opamp Bias = High
–
1200
1600
μA
Power = High, Opamp Bias = Low
–
2400
3200
μA
Power = High, Opamp Bias = High
–
4600
6400
μA
Supply Voltage Rejection Ratio
50
80
–
dB
Low Output Voltage Swing (internal signals)
Supply Current (including associated AGND buffer)
Document Number: 001-12981 Rev. **
Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤
VIN ≤ Vdd.
Page 16 of 37
CY8CLED08
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.
Table 13. DC Low Power Comparator Specifications
Symbol
Description
Min
Typ
Max
Units
VREFLPC
Low power comparator (LPC) reference voltage range
0.2
–
Vdd - 1
ISLPC
LPC supply current
–
10
40
μA
VOSLPC
LPC voltage offset
–
2.5
30
mV
Notes
V
DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 14. 5V DC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
VOSOB
Input Offset Voltage (Absolute Value)
–
3
12
mV
TCVOSOB
Average Input Offset Voltage Drift
–
+6
–
μV/°C
VCMOB
Common-Mode Input Voltage Range
0.5
–
Vdd - 1.0
V
ROUTOB
Output Resistance
Power = Low
–
1
–
Ω
Power = High
–
1
–
Ω
High Output Voltage Swing (Load = 32
ohms to Vdd/2)
Power = Low
0.5 x
Vdd +
–
–
V
Power = High
–
–
V
1.3
VOHIGHOB
Notes
0.5 x
Vdd +
1.3
VOLOWOB
Low Output Voltage Swing (Load = 32
ohms to Vdd/2)
–
–
0.5 x Vdd -
V
Power = Low
–
–
1.3
V
Power = High
0.5 x Vdd 1.3
ISOB
Supply Current Including Bias Cell (No
Load)
–
1.1
5.1
mA
Power = Low
–
2.6
8.8
mA
60
64
–
dB
Power = High
PSRROB
Supply Voltage Rejection Ratio
Document Number: 001-12981 Rev. **
Page 17 of 37
CY8CLED08
Table 15. 3.3V DC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
VOSOB
Input Offset Voltage (Absolute Value)
–
3
12
mV
TCVOSOB
Average Input Offset Voltage Drift
–
+6
–
μV/°C
VCMOB
Common-Mode Input Voltage Range
0.5
-
Vdd - 1.0
V
ROUTOB
Output Resistance
Power = Low
–
1
–
Ω
Power = High
–
1
–
Ω
Power = Low
0.5 x Vdd + 1.0 –
–
V
Power = High
0.5 x Vdd + 1.0 –
–
V
Power = Low
–
–
0.5 x Vdd - 1.0
V
Power = High
–
–
0.5 x Vdd - 1.0
V
VOHIGHOB
VOLOWOB
ISOB
High Output Voltage Swing (Load = 1k ohms to Vdd/2)
Low Output Voltage Swing (Load = 1k ohms to Vdd/2)
Supply Current Including Bias Cell (No Load)
Power = Low
PSRROB
Notes
0.8
2.0
mA
Power = High
–
2.0
4.3
mA
Supply Voltage Rejection Ratio
60
64
–
dB
DC Switch Mode Pump Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 16. DC Switch Mode Pump (SMP) Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VPUMP 5V
5V Output Voltage
4.75
5.0
5.25
V
Configuration of footnote.a Average, neglecting
ripple. SMP trip voltage is set to 5.0V.
VPUMP 3V
3V Output Voltage
3.00
3.25
3.60
V
Configuration of footnote.a Average, neglecting
ripple. SMP trip voltage is set to 3.25V.
IPUMP
Available Output Current
VBAT = 1.5V, VPUMP = 3.25V
8
–
–
mA
VBAT = 1.8V, VPUMP = 5.0V
5
–
–
mA
SMP trip voltage is set to 5.0V.
VBAT5V
Input Voltage Range from Battery
1.8
–
5.0
V
Configuration of footnote.a SMP trip voltage is
set to 5.0V.
VBAT3V
Input Voltage Range from Battery
1.0
–
3.3
V
Configuration of footnote.a SMP trip voltage is
set to 3.25V.
Configuration of footnote.a
SMP trip voltage is set to 3.25V.
VBATSTART
Minimum Input Voltage from Battery to Start Pump
1.1
–
–
V
Configuration of footnote.a
ΔVPUMP_Line
Line Regulation (over VBAT range)
–
5
–
%VO
Configuration of footnote.a VO is the “Vdd Value
for PUMP Trip” specified by the VM[2:0] setting
in the DC POR and LVD Specification, Table 20
on page 21.
ΔVPUMP_Load
Load Regulation
–
5
–
%VO
Configuration of footnote.a VO is the “Vdd Value
for PUMP Trip” specified by the VM[2:0] setting
in the DC POR and LVD Specification, Table 20
on page 21.
ΔVPUMP_Ripple
Output Voltage Ripple (depends on capacitor/load)
–
100
–
mVpp
Configuration of footnote.a Load is 5mA.
E3
Efficiency
35
50
–
%
Configuration of footnote.a Load is 5 mA. SMP
trip voltage is set to 3.25V.
FPUMP
Switching Frequency
–
1.3
–
MHz
DCPUMP
Switching Duty Cycle
–
50
–
%
a. L1 = 2 μH inductor, C1 = 10 μF capacitor, D1 = Schottky diode.
Document Number: 001-12981 Rev. **
Page 18 of 37
CY8CLED08
Figure 5. Basic Switch Mode Pump Circuit
D1
Vdd
L1
V BAT
+
V PUMP
C1
SMP
Battery
PSoC
Vss
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum
specifications for the voltage and temperature ranges: 4.75V to
5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤
85°C, respectively. Typical parameters apply to 5V and 3.3V at
25°C and are for design guidance only.
to the power of the Analog Continuous Time PSoC block. The
power levels for RefHi and RefLo refer to the Analog Reference
Control register. The limits stated for AGND include the offset
error of the AGND buffer local to the Analog Continuous Time
PSoC block. Reference control power is high.
The guaranteed specifications are measured through the Analog
Continuous Time PSoC blocks. The power levels for AGND refer
Table 17. 5V DC Analog Reference Specifications
Symbol
Description
Min
Typ
Max
Units
BG
Bandgap Voltage Reference
1.28
1.30
1.32
V
–
AGND = Vdd/2a
Vdd/2 - 0.030
Vdd/2
Vdd/2 + 0.007
V
2 x BG - 0.043
2 x BG
2 x BG + 0.024
V
P2[4] - 0.011
P2[4]
P2[4] + 0.011
V
BG - 0.009
BG
BG + 0.009
V
1.6 x BG - 0.018
1.6 x BG
1.6 x BG + 0.018
V
-0.034
0.000
0.034
V
–
–
AGND = 2 x
BandGapa
AGND = P2[4] (P2[4] = Vdd/2)
–
AGND =
–
AGND = 1.6 x BandGapa
a
BandGapa
–
AGND Block to Block Variation (AGND =
–
RefHi = Vdd/2 + BandGap
Vdd/2 + BG - 0.1
Vdd/2 + BG - 0.01
Vdd/2 + BG + 0.1
V
–
RefHi = 3 x BandGap
3 x BG - 0.06
3 x BG - 0.01
3 x BG + 0.06
V
–
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
2 x BG + P2[6] - 0.06
2 x BG + P2[6] - 0.01
2 x BG + P2[6] + 0.06
V
–
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
P2[4] + BG - 0.06
P2[4] + BG - 0.01
P2[4] + BG + 0.06
V
–
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
P2[4] + P2[6] - 0.06
P2[4] + P2[6] - 0.01
P2[4] + P2[6] + 0.06
V
–
RefHi = 3.2 x BandGap
3.2 x BG - 0.06
3.2 x BG - 0.01
3.2 x BG + 0.06
V
–
RefLo = Vdd/2 – BandGap
Vdd/2 - BG - 0.051
Vdd/2 - BG + 0.01
Vdd/2 - BG + 0.06
V
–
RefLo = BandGap
BG - 0.06
BG + 0.01
BG + 0.06
V
–
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
2 x BG - P2[6] - 0.04
2 x BG - P2[6] + 0.01
2 x BG - P2[6] + 0.04
V
–
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
P2[4] - BG - 0.056
P2[4] - BG + 0.01
P2[4] - BG + 0.056
V
–
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
P2[4] - P2[6] - 0.056
P2[4] - P2[6] + 0.01
P2[4] - P2[6] + 0.056
V
Vdd/2)a
a. AGND tolerance includes the offsets of the local buffer in the PSoC block.
Document Number: 001-12981 Rev. **
Page 19 of 37
CY8CLED08
Table 18. 3.3V DC Analog Reference Specifications
Symbol
Description
Min
Typ
Max
Units
BG
Bandgap Voltage Reference
1.28
1.30
1.32
V
–
AGND = Vdd/2a
Vdd/2 - 0.027
Vdd/2
Vdd/2 + 0.005
V
–
AGND = 2 x BandGapa
Not Allowed
–
AGND = P2[4] (P2[4] = Vdd/2)
P2[4] - 0.008
P2[4]
P2[4] + 0.009
V
–
AGND = BandGapa
BG - 0.009
BG
BG + 0.009
V
–
AGND = 1.6 x BandGapa
1.6 x BG - 0.018
1.6 x BG
1.6 x BG + 0.018
V
-0.034
0.000
0.034
mV
P2[4] + P2[6] - 0.01
P2[4] + P2[6] + 0.057
V
P2[4] - P2[6] + 0.01
P2[4] - P2[6] + 0.048
V
–
AGND Block to Block Variation (AGND =
–
RefHi = Vdd/2 + BandGap
Not Allowed
–
RefHi = 3 x BandGap
Not Allowed
–
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)
Not Allowed
–
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
Not Allowed
–
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
P2[4] + P2[6] - 0.06
–
RefHi = 3.2 x BandGap
Not Allowed
–
RefLo = Vdd/2 - BandGap
Not Allowed
–
RefLo = BandGap
Not Allowed
–
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)
Not Allowed
–
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
Not Allowed
–
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
P2[4] - P2[6] - 0.048
Vdd/2)a
a. AGND tolerance includes the offsets of the local buffer in the PSoC block.
Note See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 19. DC Analog PSoC Block Specifications
Symbol
Description
Min
Typ
Max
Units
RCT
Resistor Unit Value (Continuous Time)
–
12.2
–
kΩ
CSC
Capacitor Unit Value (Switch Cap)
–
80
–
fF
Document Number: 001-12981 Rev. **
Notes
Page 20 of 37
CY8CLED08
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register.
Table 20. DC POR and LVD Specifications
Symbol
Description
Min
Typ
Max
Units
Vdd Value for PPOR Trip (positive ramp)
VPPOR0R
PORLEV[1:0] = 00b
VPPOR1R
PORLEV[1:0] = 01b
VPPOR2R
PORLEV[1:0] = 10b
2.91
–
4.39
V
–
4.55
V
Notes
Vdd must be greater than or equal to 2.5V
during startup, reset from the XRES pin, or
reset from Watchdog.
V
Vdd Value for PPOR Trip (negative ramp)
VPPOR0
PORLEV[1:0] = 00b
VPPOR1
PORLEV[1:0] = 01b
VPPOR2
PORLEV[1:0] = 10b
2.82
–
4.39
V
–
4.55
V
V
PPOR Hysteresis
VPH0
PORLEV[1:0] = 00b
–
92
–
mV
VPH1
PORLEV[1:0] = 01b
–
0
–
mV
VPH2
PORLEV[1:0] = 10b
–
0
–
mV
Vdd Value for LVD Trip
VLVD0
VM[2:0] = 000b
2.86
2.92
2.98a
V
VLVD1
VM[2:0] = 001b
2.96
3.02
3.08
VLVD2
VM[2:0] = 010b
3.07
3.13
3.20
VLVD3
VM[2:0] = 011b
3.92
4.00
4.08
VLVD4
VM[2:0] = 100b
4.39
4.48
4.57
VLVD5
VM[2:0] = 101b
4.55
4.64
4.74b
VLVD6
VM[2:0] = 110b
4.63
4.73
VLVD7
VM[2:0] = 111b
4.72
4.81
V
V
V
V
V
V
V
V
4.82
4.91
Vdd Value for PUMP Trip
VPUMP0
VM[2:0] = 000b
2.96
3.02
3.08
VPUMP1
VM[2:0] = 001b
3.03
3.10
3.16
VPUMP2
VM[2:0] = 010b
3.18
3.25
3.32
VPUMP3
VM[2:0] = 011b
4.11
4.19
4.28
VPUMP4
VM[2:0] = 100b
4.55
4.64
4.74
VPUMP5
VM[2:0] = 101b
4.63
4.73
4.82
VPUMP6
VM[2:0] = 110b
4.72
4.82
4.91
VPUMP7
VM[2:0] = 111b
4.90
5.00
5.10
V
V
V
V
V
V
V
V
V
a. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
b. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
Document Number: 001-12981 Rev. **
Page 21 of 37
CY8CLED08
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 21. DC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
IDDP
Supply Current During Programming or Verify
–
5
25
mA
VILP
Input Low Voltage During Programming or Verify
–
–
0.8
V
VIHP
Input High Voltage During Programming or Verify
2.2
–
–
V
IILP
Input Current when Applying Vilp to P1[0] or P1[1] During
Programming or Verify
–
–
0.2
mA
Driving internal pull-down resistor.
IIHP
Input Current when Applying Vihp to P1[0] or P1[1] During
Programming or Verify
–
–
1.5
mA
Driving internal pull-down resistor.
VOLV
Output Low Voltage During Programming or Verify
–
–
Vss + 0.75 V
VOHV
Output High Voltage During Programming or Verify
Vdd - 1.0
–
Vdd
V
FlashENPB
Flash Endurance (per block)
50,000
–
–
–
Erase/write cycles per block.
1,800,000
–
–
–
Erase/write cycles.
10
–
–
Years
FlashENT
Flash Endurance
FlashDR
Flash Data Retention
(total)a
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks
of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees
more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer
to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
Document Number: 001-12981 Rev. **
Page 22 of 37
CY8CLED08
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 22. AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FIMO
Internal Main Oscillator Frequency
23.4
24
24.6a
MHz
Trimmed. Utilizing factory trim values.
FCPU1
CPU Frequency (5V Nominal)
0.93
24
24.6a,b
MHz
Trimmed. Utilizing factory trim values.
FCPU2
CPU Frequency (3.3V Nominal)
0.93
12
12.3
b,c
MHz
Trimmed. Utilizing factory trim values.
F48M
Digital PSoC Block Frequency
0
48
49.2a,b,d
MHz
Refer to the AC Digital Block Specifications
below.
F24M
Digital PSoC Block Frequency
0
24
24.6b, d
MHz
F32K1
Internal Low Speed Oscillator Frequency
15
32
64
kHz
F32K2
External Crystal Oscillator
–
32.768
–
kHz
Accuracy is capacitor and crystal dependent.
50% duty cycle.
FPLL
PLL Frequency
–
23.986
–
MHz
Multiple (x732) of crystal frequency.
Jitter24M2
24 MHz Period Jitter (PLL)
–
–
600
ps
TPLLSLEW
PLL Lock Time
0.5
–
10
ms
TPLLSLEWS-
PLL Lock Time for Low Gain Setting
0.5
–
50
ms
TOS
External Crystal Oscillator Startup to 1%
–
1700
2620
ms
TOSACC
External Crystal Oscillator Startup to 100 ppm
–
2800
3800
ms
Jitter32k
32 kHz Period Jitter
–
100
TXRST
External Reset Pulse Width
10
–
–
μs
DC24M
24 MHz Duty Cycle
40
50
60
%
Step24M
24 MHz Trim Step Size
–
50
–
kHz
Fout48M
48 MHz Output Frequency
46.8
48.0
49.2a,c
MHz
Jitter24M1
24 MHz Period Jitter (IMO)
–
600
FMAX
Maximum frequency of signal on row input or row output.
–
–
12.3
MHz
TRAMP
Supply Ramp Time
0
–
–
μs
LOW
a.
b.
c.
d.
The crystal oscillator frequency is within 100 ppm of its
final value by the end of the Tosacc period. Correct
operation assumes a properly loaded 1 uW maximum
drive level 32.768 kHz crystal. 3.0V ≤ Vdd ≤ 5.5V, -40
o
C ≤ TA ≤ 85 oC.
ns
Trimmed. Utilizing factory trim values.
ps
4.75V < Vdd < 5.25V.
Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.
See the individual user module data sheets for information on maximum frequencies for user modules.
Figure 6. PLL Lock Timing Diagram
PLL
Enable
TPLLSLEW
24 MHz
FPLL
PLL
Gain
0
Document Number: 001-12981 Rev. **
Page 23 of 37
CY8CLED08
Figure 7. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
TPLLSLEWLOW
24 MHz
FPLL
PLL
Gain
1
Figure 8. External Crystal Oscillator Startup Timing Diagram
32K
Select
32 kHz
TOS
F32K2
Figure 9. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F 24M
Figure 10. 32 kHz Period Jitter (ECO) Timing Diagram
Jitter32k
F 32K2
AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 23. AC GPIO Specifications
Symbol
Description
Min
0
Typ
–
Max
12
Units
MHz
Notes
FGPIO
GPIO Operating Frequency
Normal Strong Mode
TRiseF
Rise Time, Normal Strong Mode, Cload = 50 pF
3
–
18
ns
Vdd = 4.5 to 5.25V, 10% - 90%
TFallF
Fall Time, Normal Strong Mode, Cload = 50 pF
2
–
18
ns
Vdd = 4.5 to 5.25V, 10% - 90%
TRiseS
Rise Time, Slow Strong Mode, Cload = 50 pF
10
27
–
ns
Vdd = 3 to 5.25V, 10% - 90%
TFallS
Fall Time, Slow Strong Mode, Cload = 50 pF
10
22
–
ns
Vdd = 3 to 5.25V, 10% - 90%
Document Number: 001-12981 Rev. **
Page 24 of 37
CY8CLED08
Figure 11. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.
Table 24. 5V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Min
Typ
Max
Units
Notes
Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10 pF
load, Unity Gain)
Power = Low, Opamp Bias = Low
–
–
3.9
μs
Power = Medium, Opamp Bias = High
–
–
0.72
μs
Power = High, Opamp Bias = High
–
–
0.62
μs
Power = Low, Opamp Bias = Low
–
–
5.9
μs
Power = Medium, Opamp Bias = High
–
–
0.92
μs
Power = High, Opamp Bias = High
–
–
0.72
μs
Power = Low, Opamp Bias = Low
0.15
–
–
V/μs
Power = Medium, Opamp Bias = High
1.7
–
–
V/μs
Power = High, Opamp Bias = High
6.5
–
–
V/μs
Power = Low, Opamp Bias = Low
0.01
–
–
V/μs
Power = Medium, Opamp Bias = High
0.5
–
–
V/μs
Power = High, Opamp Bias = High
4.0
–
–
V/μs
Power = Low, Opamp Bias = Low
0.75
–
–
MHz
Power = Medium, Opamp Bias = High
3.1
–
–
MHz
Power = High, Opamp Bias = High
5.4
–
–
MHz
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
100
–
nV/rt-Hz
Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10 pF
load, Unity Gain)
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Gain Bandwidth Product
Document Number: 001-12981 Rev. **
Page 25 of 37
CY8CLED08
Table 25. 3.3V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Min
Typ
Max
Units
Notes
Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10 pF
load, Unity Gain)
Power = Low, Opamp Bias = Low
–
–
3.92
μs
Power = Low, Opamp Bias = High
–
–
0.72
μs
Power = Low, Opamp Bias = Low
–
–
5.41
μs
Power = Medium, Opamp Bias = High
–
–
0.72
μs
Power = Low, Opamp Bias = Low
0.31
–
–
V/μs
Power = Medium, Opamp Bias = High
2.7
–
–
V/μs
Power = Low, Opamp Bias = Low
0.24
–
–
V/μs
Power = Medium, Opamp Bias = High
1.8
–
–
V/μs
Power = Low, Opamp Bias = Low
0.67
–
–
MHz
Power = Medium, Opamp Bias = High
2.8
–
–
MHz
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
100
–
nV/rt-Hz
Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10 pF
load, Unity Gain)
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Gain Bandwidth Product
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 12. Typical AGND Noise with P2[4] Bypass
dBV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
Document Number: 001-12981 Rev. **
0.01
0.1 Freq (kHz)
1
10
100
Page 26 of 37
CY8CLED08
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 13. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
0.01
0.1
Freq (kHz)
1
10
100
AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.
Table 26. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Document Number: 001-12981 Rev. **
Min
–
Typ
–
Max
50
Units
μs
Notes
≥ 50 mV overdrive comparator reference set
within VREFLPC.
Page 27 of 37
CY8CLED08
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 27. AC Digital Block Specifications
Function
Description
Min
Typ
Max
Units
All
Functions
Maximum Block Clocking Frequency (> 4.75V)
Timer
Capture Pulse Width
50a
–
–
ns
Maximum Frequency, No Capture
–
–
49.2
MHz
Maximum Frequency, With Capture
–
–
24.6
MHz
Enable Pulse Width
50a
–
–
ns
Maximum Frequency, No Enable Input
–
–
49.2
MHz
Maximum Frequency, Enable Input
–
–
24.6
MHz
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50a
–
–
ns
a
–
–
ns
Counter
Dead Band
49.2
Maximum Block Clocking Frequency (< 4.75V)
Notes
4.75V < Vdd < 5.25V.
24.6
3.0V < Vdd < 4.75V.
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
Kill Pulse Width:
Disable Mode
Maximum Frequency
50
–
–
49.2
MHz
4.75V < Vdd < 5.25V.
CRCPRS
Maximum Input Clock Frequency
(PRS Mode)
–
–
49.2
MHz
4.75V < Vdd < 5.25V.
CRCPRS
Maximum Input Clock Frequency
(CRC Mode)
–
–
24.6
MHz
SPIM
Maximum Input Clock Frequency
–
–
8.2
MHz
SPIS
Maximum Input Clock Frequency
–
–
4.1
ns
Width of SS_ Negated Between Transmissions
50a
–
–
ns
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at 3.08 MHz due to 8 x over
clocking.
Maximum Input Clock Frequency with Vdd ≥ 4.75V, 2
Stop Bits
–
–
49.2
MHz
Maximum data rate at 6.15 MHz due to 8 x over
clocking.
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at 3.08 MHz due to 8 x over
clocking.
Maximum Input Clock Frequency with Vdd ≥ 4.75V, 2
Stop Bits
–
–
49.2
MHz
Maximum data rate at 6.15 MHz due to 8 x over
clocking.
Transmitter
Receiver
Maximum data rate at 4.1 MHz due to 2 x over
clocking.
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-12981 Rev. **
Page 28 of 37
CY8CLED08
AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 28. 5V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
Description
Min
Typ
Max
Units
Notes
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
–
–
2.5
μs
Power = High
–
–
2.5
μs
Power = Low
–
–
2.2
μs
Power = High
–
–
2.2
μs
Power = Low
0.65
–
–
V/μs
Power = High
0.65
–
–
V/μs
Power = Low
0.65
–
–
V/μs
Power = High
0.65
–
–
V/μs
0.8
–
–
MHz
0.8
–
–
MHz
Power = Low
300
–
–
kHz
Power = High
300
–
–
kHz
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF
Load
Power = Low
Power = High
BWOB
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
Table 29. 3.3V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
BWOB
Description
Min
Typ
Max
Units
Notes
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
–
–
3.8
μs
Power = High
–
–
3.8
μs
Power = Low
–
–
2.6
μs
Power = High
–
–
2.6
μs
Power = Low
0.5
–
–
V/μs
Power = High
0.5
–
–
V/μs
Power = Low
0.5
–
–
V/μs
Power = High
0.5
–
–
V/μs
Power = Low
0.7
–
–
MHz
Power = High
0.7
–
–
MHz
Power = Low
200
–
–
kHz
Power = High
200
–
–
kHz
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
Document Number: 001-12981 Rev. **
Page 29 of 37
CY8CLED08
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 30. 5V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency
0.093
–
24.6
MHz
–
High Period
20.6
–
5300
ns
–
Low Period
20.6
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Notes
Table 31. 3.3V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency with CPU Clock divide by 1a
0.093
–
12.3
MHz
FOSCEXT
Frequency with CPU Clock divide by 2 or greaterb
0.186
–
24.6
MHz
–
High Period with CPU Clock divide by 1
41.7
–
5300
ns
–
Low Period with CPU Clock divide by 1
41.7
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Notes
a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met.
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 32. AC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
TRSCLK
Rise Time of SCLK
1
–
20
ns
TFSCLK
Fall Time of SCLK
1
–
20
ns
TSSCLK
Data Set up Time to Falling Edge of SCLK
40
–
–
ns
THSCLK
Data Hold Time from Falling Edge of SCLK
40
–
–
ns
FSCLK
Frequency of SCLK
0
–
8
MHz
TERASEB
Flash Erase Time (Block)
–
10
–
ms
TWRITE
Flash Block Write Time
–
10
–
ms
TDSCLK
Data Out Delay from Falling Edge of SCLK
–
–
45
ns
Vdd > 3.6
TDSCLK3
Data Out Delay from Falling Edge of SCLK
–
–
50
ns
3.0 ≤ Vdd ≤ 3.6
Document Number: 001-12981 Rev. **
Page 30 of 37
CY8CLED08
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 33. AC Characteristics of the I2C SDA and SCL Pins
Standard Mode
Symbol
Description
Min
Fast Mode
Max
Min
Max
Units
FSCLI2C
SCL Clock Frequency
0
100
0
400
kHz
THDSTAI2C
Hold Time (repeated) START Condition. After this period, the
first clock pulse is generated.
4.0
–
0.6
–
μs
TLOWI2C
LOW Period of the SCL Clock
4.7
–
1.3
–
μs
THIGHI2C
HIGH Period of the SCL Clock
4.0
–
0.6
–
μs
TSUSTAI2C
Set-up Time for a Repeated START Condition
4.7
–
0.6
–
μs
THDDATI2C
Data Hold Time
0
–
0
–
μs
TSUDATI2C
Data Set-up Time
250
–
100a
–
ns
TSUSTOI2C
Set-up Time for STOP Condition
4.0
–
0.6
–
μs
TBUFI2C
Bus Free Time Between a STOP and START Condition
4.7
–
1.3
–
μs
TSPI2C
Pulse Width of spikes are suppressed by the input filter.
–
–
0
50
ns
Notes
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if
the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Figure 14. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
TLOWI2C
TSPI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
Document Number: 001-12981 Rev. **
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Page 31 of 37
CY8CLED08
Packaging Information
This section illustrates the packaging specifications for the CY8CLED08 EZ-Color device, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Packaging Dimensions
Figure 15. 48-Lead (300-Mil) SSOP
Document Number: 001-12981 Rev. **
Page 32 of 37
CY8CLED08
Figure 16. 48-Lead (7x7 mm) QFN
001-12919 *A
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
Important Note Pinned vias for thermal conduction are not required for the low-power PSoC device.
Document Number: 001-12981 Rev. **
Page 33 of 37
CY8CLED08
Thermal Impedances
Development Tool Selection
Table 34. Thermal Impedances per Package
This section presents the development tools available for all
current PSoC device families including the CY8CLED08
EZ-Color family.
Package
Typical θJA *
48 SSOP
69 oC/W
48 QFN**
18 oC/W
Software Tools
* TJ = TA + POWER x θJA
PSoC Express™
** To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB
ground plane.
Capacitance on Crystal Pins
Table 35. Typical Package Capacitance on Crystal Pins
Package
Package Capacitance
48 SSOP
3.3 pF
48 QFN
2.3 pF
As the newest addition to the PSoC development software suite,
PSoC Express is the first visual embedded system design tool
that allows a user to create an entire PSoC project and generate
a schematic, BOM, and data sheet without writing a single line
of code. Users work directly with application objects such as
LEDs, switches, sensors, and fans. PSoC Express is available
free of charge at http://www.cypress.com/psocexpress.
PSoC Designer™
Utilized by thousands of PSoC developers, this robust software
has been facilitating PSoC designs for half a decade. PSoC
Designer is available free of charge at http://www.cypress.com
under DESIGN RESOURCES >> Software and Drivers.
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to
achieve good solderability.
Table 36. Solder Reflow Peak Temperature
Package
Minimum Peak
Temperature*
Maximum Peak
Temperature
48 SSOP
220oC
260oC
48 QFN
240oC
260oC
*Higher temperatures may be required based on the solder melting
point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or
245 ± 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer
specifications.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer or PSoC Express. PSoC
Programmer software is compatible with both PSoC ICE-Cube
In-Circuit Emulator and PSoC MiniProg. PSoC programmer is
available free ofcharge at http://www.cypress.com/psocprogrammer.
CY3202-C iMAGEcraft C Compiler
CY3202 is the optional upgrade to PSoC Designer that enables
the iMAGEcraft C compiler. It can be purchased from the
Cypress Online Store. At http://www.cypress.com, click the
Online Store shopping cart icon at the bottom of the web page,
and click PSoC (Programmable System-on-Chip) to view a
current list of available items.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of the USB port. The base unit is universal and will operate
with all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
I2C to USB Bridge
The I2C to USB Bridge is a quick and easy link from any design
or application’s I2C bus to a PC via USB for design testing,
debugging and communication.
Document Number: 001-12981 Rev. **
Page 34 of 37
CY8CLED08
PSoC Programmer
CY3210-PSoCEval1
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer or PSoC Express. PSoC
Programmer software is compatible with both PSoC ICE-Cube
In-Circuit Emulator and PSoC MiniProg. PSoC programmer is
available free ofcharge at http://www.cypress.com/psocprogrammer.
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit
includes:
■
Evaluation Board with LCD Module
■
MiniProg Programming Unit
CY3202-C iMAGEcraft C Compiler
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
CY3202 is the optional upgrade to PSoC Designer that enables
the iMAGEcraft C compiler. It can be purchased from the
Cypress Online Store. At http://www.cypress.com, click the
Online Store shopping cart icon at the bottom of the web page,
and click PSoC (Programmable System-on-Chip) to view a
current list of available items.
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
Device Programmers
Evaluation Tools
All evaluation tools can be purchased from the Cypress Online
Store.
CY3261A-RGB EZ-Color RGB Kit
The CY3261A-RGB board is a preprogrammed HB LED color
mix board with seven pre-set colors using the CY8CLED16
EZ-Color HB LED Controller. The board is accompanied by a
CD containing the color selector software application, PSoC
Express 3.0 Beta 2, PSoC Programmer, and a suite of
documents, schematics, and firmware examples. The color
selector software application can be installed on a host PC and
is used to control the EZ-Color HB LED controller using the
included USB cable. The application enables you to select colors
via a CIE 1931 chart or by entering coordinates. The kit includes:
■
Training Board (CY8CLED16)
■
One mini-A to mini-B USB Cable
■
PSoC Express CD-ROM
■
Design Files and Application Installation CD-ROM
To program and tune this kit via PSoC Express 3.0 you must use
a Mini Programmer Unit (CY3217 Kit) and a CY3240-I2CUSB kit.
All device programmers can be purchased from the Cypress
Online Store.
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■
Modular Programmer Base
■
3 Programming Module Cards
■
MiniProg Programming Unit
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
Note: CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
CY3210-MiniProg1
■
CY3207 Programmer Unit
The CY3210-MiniProg1 kit allows a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■
PSoC ISSP Software CD
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
USB 2.0 Cable
■
MiniProg Programming Unit
■
MiniEval Socket Programming and Evaluation Board
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■
28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
Document Number: 001-12981 Rev. **
Page 35 of 37
CY8CLED08
Accessories (Emulation and Programming)
Third Party Tools
Table 37. Emulation and Programming Accessories
Part #
Pin
Package
Flex-Pod Kita
Foot Kitb
CY8CLED08-48PVXI
48 SSOP CY3250-27XXX
CY8CLED08-48LFXI
48 QFN
CY3250-27XXX
QFN
Adapterc
CY3250-48 Adapters
SSOP-FK
can be
found at
CY3250-48
http://www.e
QFN-FK
mulation.com.
a. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two
flex-pods.
b. Foot kit includes surface mount feet that can be soldered to the target PCB.
c. Programming adapter converts non-DIP package to DIP footprint. Specific
details and ordering information for each of the adapters can be found at
http://www.emulation.com.
Several tools have been specially designed by the following
3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools
can be found at http://www.cypress.com under DESIGN
RESOURCES >> Evaluation Boards.
Build a PSoC Emulator into Your Board
For details on how to emulate your circuit before going to volume
production using an on-chip debug (OCD) non-production PSoC
device, see Application Note “Debugging - Build a PSoC
Emulator into Your Board - AN2323” at
http://www.cypress.com/an2323. The following table lists the
CY8CLED08 EZ-Color devices’ key package features and
ordering codes.
Ordering Information
Key Device Features
Analog
Outputs
XRES Pin
Analog
Inputs
CY8CLED08-48PVXI
16K
256
Yes
-40C to +85C
8
12
44
12
4
Yes
48 Pin (300 Mil) SSOP (Tape and Reel)
CY8CLED08-48PVXIT 16K
256
Yes
-40C to +85C
8
12
44
12
4
Yes
48 Pin (7x7) QFN
CY8CLED08-48LFXI
16K
256
Yes
-40C to +85C
8
12
44
12
4
Yes
48 Pin (7x7) QFN (Tape and Reel)
CY8CLED08-48LFXIT
16K
256
Yes
-40C to +85C
8
12
44
12
4
Yes
RAM
(Bytes)
48 Pin (300 Mil) SSOP
Ordering
Code
Package
Flash
(Bytes)
Digital IO
Pins
(Columns of 3)
Analog Blocks
Digital Blocks
(Rows of 4)
Temperature
Range
Switch Mode
Pump
Table 38. Device Key Features and Ordering Information
Ordering Code Definitions
CY 8 C LED
xx - xx xxxx
Package Type:
Thermal Rating:
PX = PDIP Pb-Free
C = Commercial
SX = SOIC Pb-Free
I = Industrial
PVX = SSOP Pb-Free
E = Extended
LFX/LKX = QFN Pb-Free
AX = TQFP Pb-Free
Pin Count
Part Number
LED Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number: 001-12981 Rev. **
Page 36 of 37
CY8CLED08
Document History
Table 39. CY8CLED08 Data Sheet Revision History
Document Title:
CY8CLED08 EZ-Color HB LED Controller
Document Number: 001-12981
Revision
ECN #
Issue Date Origin of Change
New document (revision **).
**
1148504
See ECN SFVTMP3
Distribution: External Public
Description of Change
Posting: None
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for
use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works
of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with
a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is
prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems
where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-12981 Rev. **
Page 37 of 37