CY23FS08-04 FailSafe™ 1.8V Zero Delay Buffer Features Functional Description ■ Internal DCXO for continuous glitch free operation ■ Zero input-output propagation delay ■ Low output cycle-to-cycle jitter (<46 ps RMS) ■ Low output-output skew (<200 ps) The CY23FS08-04 is a FailSafe Zero Delay Buffer with two reference clock inputs and eight phase aligned outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. ■ 3.84 MHz reference input ■ Supports industry standard input crystals ■ Up to 133 MHz (industrial) outputs ■ Phase-locked loop (PLL) bypass mode ■ Dual reference inputs ■ 28-pin SSOP ■ 1.8V output power supplies ■ 3.3V core power supply ■ Industrial temperature Continuous, glitch free operation is achieved by using a DCXO that serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and phase information of the reference clock. The unique feature of the CY23FS08-04 is that the DCXO is in fact, the primary clocking source, that is synchronized (phase aligned) to the external reference clock. When this external clock is restored, the DCXO automatically resynchronizes to the external clock. The frequency of the crystal that is connected to the DCXO is chosen as an integer factor of the frequency of the reference clock. This factor is set by four select lines: S[4:1]. For more information, see Table 2 on page 3. The CY23FS08-04 has three split power supplies; one for core, another for Bank A outputs, and the third for Bank B outputs. Each output power supply, except VDDC is connected to 1.8V. VDDC is the power supply pin for internal circuits and is connected to 3.3V. Logic Block Diagram XIN XOUT REFSEL DCXO REF1 4 FailsafeTM Block REF2 PLL 4 CLKA[1:4] CLKB[1:4] FBK Decoder FAIL# /SAFE S[4:1] 4 Cypress Semiconductor Corporation Document Number: 001-17042 Rev. ** • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 20, 2007 [+] Feedback CY23FS08-04 Pinouts REF1 REF2 VSSB CLKB1 CLKB2 S2 S3 VDDB VSSB CLKB3 CLKB4 VDDB VDDC XIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CY23FS08 - 04 Figure 1. Pin Diagram - 28 Pin SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 REFSEL FBK VSSA CLKA1 CLKA2 S1 S4 VDDA VSSA CLKA3 CLKA4 VDDA FAIL#/SAFE XOUT 28-pin SSOP Table 1. Pin Definition - 28 Pin SSOP Pin Number Pin Name Description [3]. 1,2 REF1,REF2 5V Tolerant. Reference clock inputs 4,5,10,11 CLKB[1:4] Bank B Clock Outputs.[1] CLKB3 and CLKB4 are differential signals when terminated as shown in Figure 8 on page 6. CLKB3 is negtive output, CLKB4 is positive output. 25,24,19,18 CLKA[1:4] Bank A Clock Outputs.[1] 27 FBK No Connect, Internal Feedback. 23,6,7,22 S[1:4] Frequency Select Pins.[2] 14 XIN Reference Crystal Input. 15 XOUT Reference Crystal Output. 16 FAIL#/SAFE Valid Reference Indicator. A high level indicates a valid reference input. 13 VDDC 3.3V Power Supply for the Internal Circuitry. 8,12 VDDB 1.8V Power Supply for Bank B Outputs. 3,9 VSSB Ground. 17,21 VDDA 1.8V Power Supply for Bank A Outputs. 20,26 VSSA Ground. 28 REFSEL Reference Select. Selects the active reference clock from either REF1 or REF2. REFSEL = 1, REF1 is selected, REFSEL = 0, REF2 is selected.[3] Notes 1. Weak pull downs on all outputs. 2. Weak pull ups on these inputs. 3. Weak pull downs on these inputs. Document Number: 001-17042 Rev. ** Page 2 of 11 [+] Feedback CY23FS08-04 Table 2. Configuration Table S[4:1] XTAL (MHz) REF(MHz) OUT/REF Ratio Xtal/REF Ratio CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 CLKB2 CLKB3 CLKB4 Min Max Min Max 0000 15.36 16.384 3.84 4.096 4 32 32 0001 15.36 16.384 3.84 4.096 4 Off Off 0010 15.36 16.384 3.84 4.096 4 Off Off 0011 15.36 16.384 3.84 4.096 4 Off Off 16 16 0100 15.36 16.384 3.84 4.096 4 Off Off Off Off 32 32 32 32 32 32 32 32 32 32 32 32 Off Off 32 32 32 32 32 32 32 32 Off Off 32 32 0101 15.36 16.384 3.84 4.096 4 8 8 16 16 32 32 32 32 0110 15.36 16.384 3.84 4.096 4 8 8 8 8 16 16 16 16 0111 15.36 16.384 3.84 4.096 4 1 1 10 10 20 20 20 20 1xxx - - - - - Off Off Off Off Off Off Off Off FailSafe Function The CY23FS08-04 is targeted at clock distribution applications that can or currently require continued operation, if the main reference clock fail. Existing approaches to this requirement have used multiple reference clocks with either internal or external methods for switching between references. The problem with this technique is that it leads to interruptions (or glitches) when transitioning from one reference to another. This often requires complex external circuitry or software to maintain system stability. The technique implemented in this design completely eliminates any switching of references to the PLL that greatly simplifies the system design. The CY23FS08-04 PLL is driven by the crystal oscillator that is phase aligned to an external reference clock. It is aligned in a way that the output of the device is effectively phase aligned to reference via the external feedback loop. This is accomplished by using a digitally controlled capacitor array to pull the crystal frequency over an approximate range of ±100 ppm from its nominal frequency. In this mode, if the reference frequency fails (that is, stop or disappear), the DCXO maintains its last setting. Then a flag signal (FAIL#/SAFE) is set to indicate failure of the reference clock. The CY23FS08-04 provides four select bits, S1 through S4 to control the reference to crystal frequency ratio. The DCXO is internally tuned to the phase and frequency of the external reference only when the reference frequency divided by this ratio is within the DCXO capture range. If the frequency is out of range, a flag is set on the FAIL#/SAFE pin notifying the system that the selected reference is not valid. If the reference moves in range, then the flag is cleared indicating the system that the selected reference is valid. Figure 2. Fail#/safe timing for input reference failing catastrophically Missing REF Detected Valid REF but not Phase Aligned Phase Aligned REF Feedback(Internal) =CLKOUT * 1/32 Keeping Frequency for all CLKOUTs FAIL#/SAFE Trying to align phase between REF and Feedback tFSL tFSH Figure 3. Fail#/safe Timing formula tFSL(max) = tREF + 25ns t FSH(min) = tREF + 25ns Document Number: 001-17042 Rev. ** Page 3 of 11 [+] Feedback CY23FS08-04 Table 3. FailSafe Timing Table Parameter Description Conditions Min tFSL Fail#/Safe Assert Delay Measured at 80% to 20%, Load = 15 pF tFSH Fail#/Safe Deassert Delay Measured at 80% to 20%, Load = 15 pF Max See Figure 3 See Figure 3 Unit ns ns DCXO and capture range Failsafe has DCXO for tracking to incoming reference clock. The CY23FS08-04 is configured its capture range of approx +/- 100ppm with using pullable crystal that specified in Table 7. Figure 4. FailSafe Timing Diagram: Input Reference Slowly Drifting Out of FailSafe Capture Range Reference + 100 ppm Reference Reference - 100 ppm Frequency Reference Off Output + 100 ppm Output Output - 100 ppm Volt Fail#/Safe tFSH tFSL Document Number: 001-17042 Rev. ** Time Page 4 of 11 [+] Feedback CY23FS08-04 Figure 5. FailSafe Reference Switching Behavior Failsafe typical frequency settling time OUTPUT FREQUENCY DELTA (ppm) Initial valid Ref1 = 20 MHz +100 ppm, then switching to REF2 = 20 MHz 150 100 50 0 0 0.45 1.3 2.5 SETTLING TIME (ms) Figure 6. FailSafe Effective Loop Bandwidth (Min) Document Number: 001-17042 Rev. ** Page 5 of 11 [+] Feedback CY23FS08-04 Figure 7. Sample Timing of Muxing Between Two Reference Clocks 180°C Out of Phase and Resulting Output Phase Offset Typical Settling Time (105 MHz) REF1 REF2 REFSEL 0 ms 0 d eg -1 8 0 d e g 0 ms 1 .4 m s Figure 8. Output Termination for Differential Output and Measurement Setup for Single-Ended Outputs R UP RS TP CLKB3 D if f e r e n t ia l D R IV E R V D D (1 .8 V ) R DN R UP RS CLKB4 TP R DN D if f e r e n t ia l O u t p u t T e r m in a t io n N e t w o r k f o r C L K B 3 a n d C L K B 4 Document Number: 001-17042 Rev. ** M e a s u r e m e n t p o in t f o r s in g le - e n d e d c lo c k s Page 6 of 11 [+] Feedback CY23FS08-04 Figure 9. Waveforms for Timing Parameters D u ty C y c le - t D C V D D /2 V D D /2 V D D /2 V DD 0V t1 t2 S le w R a te - t (S R ) 80% V DD 80% 20% 20% 0V t S R (O ) t S R (O ) O u tp u t-O u tp u t S k e w - t S K (O ) V D D /2 V D D /2 t S K (O ) P a rt to P a rt S k e w - t S K (P P ) FBK, P a rt 1 V D D /2 FBK, P a rt 2 V D D /2 t S K (P P ) S ta tic P h a s e O ffs e t - t (φ ) REF V D D /2 FBK V D D /2 t (φ ) Document Number: 001-17042 Rev. ** Page 7 of 11 [+] Feedback CY23FS08-04 Absolute Maximum Conditions Parameter Description Condition Min Max Unit VDD Supply Voltage –0.5 4.6 V VIN Input Voltage Relative to VSS –0.5 VDD+0.5 VDC TS Temperature, Storage Non-functional –65 +150 °C TA Temperature, Operating Ambient Industrial Grade –40 85 °C 125 °C TJ Temperature, Junction Functional ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 V ØJC Dissipation, Junction to Case Mil-Specification 883E Method 1012.1 36.17 °C/W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) 100.6 °C/W UL–94 Flammability Rating At 1/8 in. MSL Moisture Sensitivity Level V–0 1 Multiple Supplies: The voltage on any input or IO pin cannot exceed the power pin during power up. Power supply sequencing is NOT required. Table 4. Operating Conditions for FailSafe Industrial Temperature Devices Parameter Description Min Max Unit VDDC 3.3V Supply Voltage 3.135 3.465 V VDDA, VDDB 1.8V Supply Voltage Range 1.70 1.90 V TA Ambient Operating Temperature, Industrial –40 85 °C CL Output Load Capacitance 15 pF CIN Input Capacitance (Except XIN) CXIN Crystal Input Capacitance (All internal caps off) TPU Power Up Time for all VDDs to Reach Minimum Specified Voltage (Power ramps are monotonic) 7 pF 10 13 pF 0.05 500 ms Table 5. Electrical Characteristics for FailSafe Industrial Temperature Devices Parameter Description Test Conditions VIL Input Low Voltage VIH Input High Voltage CMOS Levels, 70% of VDD IIL Input Low Current VIN = VSS (100k pull up only) IIH Input High Current VIN = VDD (100k pull down only) IOL Output Low Current VOL = 0.5V, VDD = 1.8V Min CMOS Levels, 30% of VDD Typ Max Unit 0.3xVDD V 50 µA 0.7xVDD V 50 10 µA mA IOH Output High Current VOH = VDD – 0.5V, VDD = 1.8V 10 mA IDD Dynamic Current VDDA, VDDB, and VDDC are all at the maximum values, IOUT = 0mA, output frequency = maximum 75 mA IDDQ Quiescent Current All inputs are grounded, PLL and DCXO are in bypass mode, Reference input = 0 250 µA Document Number: 001-17042 Rev. ** Page 8 of 11 [+] Feedback CY23FS08-04 Table 6. Switching Characteristics for FailSafe Industrial Temperature Devices Parameter [5] Description Test Conditions Min Typ Max Unit fREF Reference Frequency Industrial Grade 1.0 – 4.1 MHz fOUT Output Frequency 15 pF Load 1.0 – 133 MHz fXIN DCXO Frequency 15 – 25 MHz tDC Duty Cycle Measured at VDD/2 40 – 60 % tSR(I) Input Slew Rate Measured on REF1 Input, 30% to 70% of VDD 0.5 – 4.0 V/ns tSR(O) Output Slew Rate Measured from 20% to 80% of VDD = 1.8V, 15 pF Load 0.3 – 3.0 V/ns tSK(O) Output to Output Skew All outputs equally loaded, measured at VDD/2 – 110 200 ps tSK(IB) Intrabank Skew All outputs equally loaded, measured at VDD/2 – – 75 ps t(φ)[4] Static Phase Offset Measured at VDD/2 – – 250 ps tD(φ)[4] Dynamic Phase Offset Measured at VDD/2 – 150 200 ps tJ(CC) Cycle-to-Cycle Jitter Load = 15 pF, fOUT ≥ 6.25 MHz – 200 250 ps – 18 46 psRMS Min Typ Max Unit Table 7. Pullable Crystal Specifications Parameter Description CR load Crystal Load Capacitance 16 C0 / C1 C0 / C1 Ratio 240 ESR Equivalent Series Resistance pF 50 Ω Notes 4. The t(φ) reference feedback input delay is guaranteed for a maximum 4:1 input edge ratio between the two signals as long as tSR(I) is maintained. 5. Parameters are guaranteed by design and characterization. Not 100% tested in production. Document Number: 001-17042 Rev. ** Page 9 of 11 [+] Feedback CY23FS08-04 Ordering Information Part Number Package Type Product Flow Pb-Free CY23FS08OXI-04 28-pin SSOP Industrial, –40°C to 85°C CY23FS08OXI-04T 28-pin SSOP – Tape and Reel Industrial, –40°C to 85°C Package Drawing and Dimensions Figure 10. 28-Pin (5.3 mm) Shrunk Small Outline Package O28 51-85079-*C Document Number: 001-17042 Rev. ** Page 10 of 11 [+] Feedback CY23FS08-04 Document History Page Document Title: CY23FS08-04 FailSafe™ 1.8V Zero Delay Buffer Document Number: 001-17042 REV. ECN NO. Issue Date ** 1493204 See ECN Orig. of Change Description of Change XHT/WWZ/ New data sheet AESA © Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. 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The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-17042 Rev. ** Revised September 20, 2007 Page 11 of 11 PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. FailSafe is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback