Datasheet, V2.0, 1 May 1996 PWM-FF IC TDA4916GG SMPS IC with MOSFET Driver Output Power Management & Supply N e v e r s t o p t h i n k i n g . TDA4916GG Revision History: 1996-05-01 Datasheet Previous Version: Page Subjects (major changes since last revision) For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http:// www.infineon.com Edition 1996-05-01 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München © Infineon Technologies AG 1999. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. SMPS-IC with MOSFET Driver Output TDA 4916 GG Features • • • • High clock frequency Low current drain High reference accuracy All monitoring functions P-DSO-24-1 Type Ordering Code Package TDA 4916 GG Q67000-A9230 P-DSO-24-1 Functional Description and Application The general-purpose single-ended switch-mode power supply device for the direct control of SIPMOS power transistors incorporates both digital and analog functions. These are required for the construction of high-quality flyback, forward and choke converters. The device can be likewise used for transformer-less voltage multipliers and variable-speed motors. Faults occurring during operation of the switch-mode power supply are detected by comparators integrated in the device which initiate protective functions. In addition, pairs of power supplies can be synchronized in antiphase. In-phase or antiphase synchronization is possible when more than two power supplies are involved. Version 2.0 3 1 May 1996 TDA 4916 GG Pin Configuration (top view) P-DSO-24-1 Figure 1 Version 2.0 4 1 May 1996 TDA 4916 GG Pin Definitions and Functions Pin No. Symbol Function 1 0V GND GND 2 VS Supply voltage 3 0V QSIP Ground QSIP 4 Q SIP SIPMOS driver 5 VS QSIP Supply voltage driver 6 SF Series feed 7 – I K5/– I K6 Current sensor negative input 8 + I K5 Current sensor K5 9 + I K6 Current turn-OFF K6 10 Q K6 Output K6 11 PO Pulse omission 12 CSS Soft start 13 I SYN Input synchronization 14 Q SYN Output synchronization 15 Frequency generator 17 RT CT CR 18 I K4 Input undervoltage 19 I K3 Input overvoltage 20 I K1 Input K1 21 Q OP Output operational amplifier 22 – I OP Input operational amplifier 23 + I OP Input operational amplifier 24 VREF Reference voltage 16 Version 2.0 Frequency generator Ramp generator 5 1 May 1996 TDA 4916 GG Figure 2 Block Diagram TDA 4916 GG Circuit Description The individual functional sections of the device and their interactions are described below. Power Supply at VS The device does not enable the output until the turn-ON threshold of VS is exceeded. The duty factor (active time/period) can then rise from zero to the value set with K1 in the time determined by the soft start. The turn-OFF threshold lies below the turn-ON threshold. Below the turn-OFF threshold the output Q SIP is reliably low. Frequency Generator The frequency is mainly determined by close-tolerance external components and the calibrated reference voltage. The switching frequency at the output can be set by suitable choice of Rt and Ct. The maximum possible duty factor can be reduced by a defined amount by means of a resistor from CT to 0V GND. The maximum possible duty factor can be increased by a defined amount by means of a resistor from CT to VS. Ramp Generator The ramp generator is controlled by the frequency generator and operates with the same frequency. Capacitor Cr on the ramp generator is discharged by an internally-set current and charged via a current set externally. The duration of the falling edge of the ramp generator output must be shorter than its rise time. Only then do the upper and lower switching levels of the ramp generator signal have their nominal values. In “voltage mode control” operation, the rising edge of the ramp generator signal is compared with an externally set dc voltage in comparator K1 for pulse-width control at the output. The slope of the rising edge is set by the current through Rr. The voltage source connected to Rr can be the SMPS input voltage. This makes it possible to control the duty factor for a constant volt-second product at the output. This control option (precontrol) permits equalization of known disturbances (e.g. input voltage ripple). Superimposed load current control (current mode control) can also be implemented. For this purpose the actual current at the source of the SIPMOS transistor is sensed and compared with the specified value in comparator K5. Version 2.0 7 1 May 1996 TDA 4916 GG Comparator K1 (duty factor setting for voltage mode control) The two plus inputs of the comparator are so connected that the lower plus level is always compared with the minus input level. As soon as the voltage of the rising edge of the sawtooth (minus input) exceeds the lower of the two plus input levels, the output is inhibited via the turn-OFF Flip-Flop, that is to say the High time of the output can be continuously varied. Since the frequency remains constant, this corresponds to a duty factor change. Comparator K2 The comparator has a switching threshold at 1.5 V. Its output sets the fault Flip-Flop when the voltage on capacitor Ca lies below 1.5 V. However, the fault Flip-Flop accepts the setting pulse only if no reset pulse (fault) is applied. This prevents resetting of the output as long as a fault signal is present. Comparators K3 (overvoltage), K4 (undervoltage), VS Undervoltage, VREF Overcurrent These are fault detectors which cause the output to be inhibited immediately by the fault Flip-Flop when faults occur. When faults are no longer present, the duty factor is reestablished via the soft start CSS. In the event of undervoltage, a current is injected at the input of K4 with the aid of which an adjustable hysteresis or latching is made possible. The value of the hysteresis is determined by the internal resistance of the external drive source and the current injected internally at the input of K4. In the event of undervoltage at K4, the injected current flows into the device. Comparator K5 (duty factor setting for current mode control) K5 is used to sense the source current at the switching transistor. The plus input of the comparator is fed out. Enabling of output Q SIP after cessation of the fault is effected with an H signal at the turn-OFF Flip-Flop output. Comparator K6 (overcurrent turn-OFF) The turn-OFF Flip-Flop is reset when overcurrent is detected by K6. In combination with the pulse-omission facility, individual pulses can then be omitted. This then results in a limited rise in the output current with a rising overload at the output. Version 2.0 8 1 May 1996 TDA 4916 GG Operational Amplifier OP Opamp OP is a high-quality operational amplifier. It can be used in the control circuit to transfer the variations in the voltage to be regulated in amplified form to the free plus input of comparator K1. As a result, a voltage change is converted into a duty factor change. The output of OP is an open collector. The frequency response of OP is already corrected. The plus input is connected internally via a capacitor to ground. This gives the inverting amplifier a more favorable phase response. Turn-OFF Flip-Flop AFF A pulse is fed to the set input of the turn-OFF Flip-Flop with the falling edge of the frequency generator signal. However, it can only really be set if no reset signal is applied. With a set turn-OFF Flip-Flop, the output is enabled and can be active. The Flip-Flop inhibits the output in the event of a turn-OFF signal from K1, K5, K6 or K7. Fault Flip-Flop Fault signals fed to the reset input of the fault Flip-Flop cause the output to be immediately disabled (Low), and to be turned on again via the soft start CSS after removing fault-condition. Soft Start CSS The smaller of the two voltages at the plus inputs of K1 - compared with the ramp generator voltage - is a measure of the duty factor at the output. At the instant the device is turned-ON, the voltage on capacitor CSS equals zero. Provided no fault exists, the capacitor is charged up to its maximum value. CSS is discharged in the event of a fault. However, the fault Flip-Flop inhibits the output immediately. Below a charging voltage of approx. 1.5 V, a set signal is applied to the fault Flip-Flop and the output is enabled, provided a reset signal is not applied simultaneously. However, since the minimum ramp generator voltage is about 1.8 V, the duty factor at the output is not actually slowly and continuously increased until the voltage on CSS exceeds a value of 1.8 V. The Z-diode limits the voltage on capacitor CSS. The voltage at the ramp generator can reach a higher level than the Zener voltage. With a suitable ramp generator rising edge slope, the duty factor can be limited to a wanted maximum value. Pulse Omission PO In the event of overcurrent in the SIPMOS transistors it is frequently necessary to omit pulses even with minimum duty factor. Only this measure ensures that the SIPMOS transistors cannot be overloaded. This wanted function can be achieved with Pulse Omission PO and Overcurrent Comparator K7 by means of a suitable external circuit. Version 2.0 9 1 May 1996 TDA 4916 GG Reference Voltage VREF The reference voltage source makes available a source with a high-stability temperature characteristic which can be used for external connection to the operational amplifier, the fault comparators, the frequency generator, or to other external units. The voltage source is short-circuit-proof to ground. Synchronization I SYN, Q SYN The device has an input and an output for synchronization. In the case of a synchronized device (slave), its output Q SIP is in phase opposition to the output Q SIP of the synchronizing device (master). In the case of an unconnected input I SYN, or with connection to VREF, or also when a series capacitor (without switching transitions) is connected, the device receives its clock from the internal frequency generator in accordance with the circuit connected to it. As soon as switching transitions appear at I SYN, switchover to external synchronization and vice versa takes place after a delay. After a switchover process, a few clock cycles must elapse in addition to the delay before the frequency and phase achieve their steady states. Series Feed SF The Series Feed circuit section is used to turn-OFF the external series-feed transistor when energy recovery commences. As a result there is minimum power loss in the supply to the device. With the series-feed transistor turned-OFF, its drive current flows via VS to VS. SIPMOS Driver Output Q SIP The output is High active. The time during which the output is active can be continuously varied. The duration of the rising edge of the frequency generator signal is the minimum time during which the output can be Low. The duration of the falling edge of the frequency generator signal is the maximum time during which the output can be High. The output driver is designed as a push-pull stage. The output current is limited internally to the specified values. Output Q SIP is connected via diodes to the supply VS QSIP and 0V QSIP. A protection circuit SS lies between Q SIP and GND to clamp the output to ground at low impedance in the event of undervoltage at VS. Version 2.0 10 1 May 1996 TDA 4916 GG When the supply to the switch-mode power supply is switched on, the capacitive displacement current from the gate of the SIPMOS transistor is conducted to the smoothing capacitor at VS QSIP by the diode connected to VS QSIP. The voltage at VS QSIP may reach about 2.3 V in the process without the SIPMOS transistor being turned-ON. The diode connected to ground clamps negative voltages at Q SIP to minus 0.7 V. Capacitive currents which occur with voltage dips at the drain terminal of the SIPMOS transistor can then flow away unimpeded. The output is active Low with supply voltages at VS and VS QSIP from about 4 V on. The function of the diode connected to VS QSIP and the resistor are then taken over by the pull-down source. The two ground terminals 0V SQIP and 0V GND can lie at different levels. This permits connections to be made to the SIPMOS transistor in such a way that the drive currents for the gate do not flow to the source via the current-sensing resistor. The maximum permissible level differences between 0V GND and 0V SQIP are given under Functional Range. If greater level differences are anticipated, it is better to join the two terminals. Version 2.0 11 1 May 1996 TDA 4916 GG Absolute Maximum Ratings TA = – 40 to 85 °C Parameter Symbol Limit Values Unit Test Condition min. VS,VVS QSIP – 0.3 Supply voltage; VS,VS QSIP – 0.3 I OP, I K1, I K3, I K4, I K5, I K6, VI 0 I SYN VI SYN –3 II SYN Q SYN Frequency Generator; CT, RT Ramp Generator; CR Reference voltage; VREF Output Opamp; Q OP Inhibited Conducting Output Overcurrent Turn-OFF; Q K6 Inhibited Conducting Driver output; Q SIP Q SIP clamping diodes Soft start; CSS Pulse omission; PO Series feed; SF Junction temperature Storage temperature Thermal resistance system - ambient max. 17 17 5 3 V V V mA VI SYN > 5 V or VI SYN < 0 V VQ SYN VCT, RT ICT, RT VCR ICR VREF IREF – 0.3 5 V – 0.3 0 5 3 V mA – 0.3 0 VCRH 3 V mA – 0.3 – 10 6 10 V mA VQ OP IQ OP – 0.3 0 17 5 V mA VQ K6 IQ K6 VQ SIP IQ SIP – 0.3 0 17 5 V mA – 0.3 VS V 1) – 10 10 mA VCSS ICSS VPO IPO VSF Tj Ts Rth S/A – 0.3 0 VSSH V µA – 0.3 0 VPOH 3 V mA VQ SIP > VS or VQ SIP < – 0.3 V VSSH (see charact.) VSS > VSSH VPOH (see charact.) VPO > VPOH – 0.3 17 V – 65 150 °C – 65 150 °C 60 K/W 100 VCT > 5 V VCRH (see charact.) VCR > VCRH VREF > 6 V or VREF < – 0.3 V The values refer to the two connected ground terminals. 1) Important: observe max. power loss or junction temperature. Version 2.0 12 1 May 1996 TDA 4916 GG Operating Range Function Symbol Limit Values min. max. Unit Supply voltage VS VVS QSIP 0 0 15 15 V V Frequency generator f 0.05 400 kHz Ramp generator f TA V0V QSIP RRT 0.05 400 kHz – 40 + 100 °C Ambient temperature Ground Q SIP Resistor at RT GND – 300 mV GND + 2 V V 27 kΩ 1000 Characteristics VSon < VS < 15 V, – 25 °C < TA < 85 °C; VSon means that VS has exceeded VSH, but has not gone below VSL. Parameter Symbol Limit Values min. Current in VS IVS Current in VS QSIP IVS QSIP Current in VS + VS QSIP ISum Version 2.0 typ. Unit Test Condition 7 8 mA1) mA1) FG at 100 kHz FG at 300 kHz Q SYN unconnected 8 9 mA1) mA1) FG at 100 kHz FG at 300 kHz Q SYN to 0V GND mA1) mA1) FG at 100 kHz FG at 300 kHz 9 13 mA1) mA1) FG at 100 kHz FG at 300 kHz Q SYN unconnected 10 14 mA1) mA1) FG at 100 kHz FG at 300 kHz Q SYN to 0 V GND max. 2.5 5.5 13 1 May 1996 TDA 4916 GG Characteristics (cont’d) VSon < VS < 15 V, – 25 °C < TA < 85 °C; VSon means that VS has exceeded VSH, but has not gone below VSL. Parameter Symbol Limit Values Unit min. typ. max. VSH 8.0 9.1 10 V VSL 7.9 9.0 9.9 V Test Condition Current Drain2) Hysteresis at VS Turn-ON threshold for VS rising Turn-OFF threshold for VS falling 1) 2) CT; RT (see oscillator nomogram). The currents as VS and VS QSIP are in each case without loads and without internal discharge to CR, as well as with active output Q SIP. Reference Voltage Voltage VREF 2.460 Load current – IREF 0 Voltage change 2.500 2.540 V 3 mA ∆VREF 5 mV Voltage change ∆VREF 3 mV Temperature response Operate threshold VREF overcurrent ∆VREF/ ∆T – IREFO 0.1 3 6 IREF = 250 µA; VS = 12 V ∆VREF < 30 mV 0 mA < IREF < 500 µA 12 V < VS < 14 V mV/K 10 mA Frequency Generator ∆fF/fO –4 4 % 20 kHz < fO < 150 kHz; Q SYN to GND; VS = 12 V; TA = 25 °C Voltage dependence ∆fV/fO of nominal frequency –1 1 % 10 V < VS < 14.4 V; TA = 25 °C; Nominal frequency spread relative to fO at 12 V; 20 kHz < fO < 150 kHz Version 2.0 14 1 May 1996 TDA 4916 GG Characteristics (cont’d) VSon < VS < 15 V, – 25 °C < TA < 85 °C; VSon means that VS has exceeded VSH, but has not gone below VSL. Parameter Symbol Limit Values min. Temperaturedependence of nominal frequency ∆fτ/fO –3 Nominal frequency f20150 f150250 f250300 0.92 fO Nominal frequency Nominal frequency 0.88 fO 0.85 fO typ. Test Condition % – 25 °C < TA < + 85 °C; VS = 12 V; relative to fO at 25 °C; 20 kHz < fO < 150 kHz max. 3 fO fO fO Unit 1.08 fO kHz1) 20 kHz to 150 kHz 1.12 fO kHz1),2) 150 kHz to 250 kHz 1.15 fO kHz1),2) 250 kHz to 300 kHz Maximum duty cycle ν20150 48 52 %2) 20 kHz to 150 kHz Maximum duty cycle ν150200 46 54 %2) 150 kHz to 250 kHz Maximum duty cycle ν250300 44 56 %2) 250 kHz to 300 kHz 0.05 300 kHz Ramp Generator Frequency range f Maximum voltage at VCRH CR Minimum voltage VCRL at CR Discharge current at Idis CR Capacitance at CR CR ON-time spread ∆tOt/tOt (limited by CSS) 4.8 5.8 6.8 V 1.4 1.8 2.2 V 0.75 1.00 1.25 mA 10 internally fixed pF –9 9 % Cr = 200 pF; VIK1 > VSSH; IRr = 150 µA; TA = 25 °C; relative to tOt = 4.0 µs 1) 2) CT; RT (see oscillator nomogram). See diagram: Tolerance of oscillator frequency, duty cycle. Version 2.0 15 1 May 1996 TDA 4916 GG Characteristics (cont’d) VSon < VS < 15 V, – 25 °C < TA < 85 °C; VSon means that VS has exceeded VSH, but has not gone below VSL. Parameter Symbol Limit Values min. ON-time drift ∆tOt/tOt typ. –2 Unit Test Condition % Cr = 200 pF; VIK1 > VCAH; IRr = 150 µA; max. 2 relative to tOt = 25 °C ON-time spread tOt 3.6 4.0 4.4 µs Cr = 200 pF; VIK1 > VCAH; IRr = 150 µA 60 80 100 dB IQ OP = 100 µA +5 mV IQ OP = 100 µA 1 µA 4 V Operational Amplifier OP Open-loop gain Go Input offset voltage Vio Input current – Ii Input common-mode Vcm –5 – 0.2 range –3 Transit frequency IQ OP VQ OP ft 2 Transit phase φt 90 Temp. coeff. of Vio Tc – 10 Rate of rise of voltage at output ∆V/∆t 1 Output current Output voltage mA 0.5 < VQ OP < 15 V 15 V 0 mA < IQ OP < 2 mA 5 8 MHz 120 150 Deg. + 10 µV/K 6 V/µs 1 µA VCAH V 400 ns1) 0.5 ±3 IQ OP = 100 µA Comparator K1 Input current – IK1 Input common-mode Vcm range Turn-OFF delay 1) tOFF Step function ∆V – 100 mV Version 2.0 0 200 Nominal load 1 nF at Q SIP ∆V + 100 mV (for delay from comparator input to Q SIP). 16 1 May 1996 TDA 4916 GG Characteristics (cont’d) VSon < VS < 15 V, – 25 °C < TA < 85 °C; VSon means that VS has exceeded VSH, but has not gone below VSL. Parameter Symbol Limit Values min. typ. Unit Test Condition max. Overvoltage K3 Input current – Ii Switching voltage VSW VREF – 5 mV Turn-OFF delay tOFF 1 0.2 µA VREF + V 5 mV 2 4 µs 0.2 µA Undervoltage K4 Input current at K4 – Ii Switching voltage at K4 VSW VREF – 5 mV Hysteresis current Ihy4H Ihy4L to 5 10 15 0.1 µA µA 1 2 4 µs1) 1 µA –5 +5 mV 0 4 V 300 400 ns2) ns3) Load 1 nF at Q SIP 2 µA 1.2 V VQK6 = 5 V IQK6 = 1 mA Turn-OFF delay VREF + V 5 mV V+ IK4 < Vsw V+ IK4 > Vsw Current Sensor K5; Overcurrent Turn-OFF K6 Input current – Idyn Input offset voltage Vio Vcm Input common-mode range Turn-OFF delay tOFF Output K6 inhibited IQK6 VQK6 Conducting 1) 2) 3) Step function VREF – 100 mV Step function ∆V – 100 mV Step function ∆V – 10 mV Version 2.0 150 250 VREF + 100 mV (for delay from comparator input to Q SIP). ∆V + 100 mV (for delay from comparator input to Q SIP). ∆V + 10 mV (for delay from comparator input to Q SIP). 17 1 May 1996 TDA 4916 GG Characteristics (cont’d) VSon < VS < 15 V, – 25 °C < TA < 85 °C; VSon means that VS has exceeded VSH, but has not gone below VSL. Parameter Symbol Limit Values Unit min. typ. max. 4 5 8 µA 0.8 1.5 3.0 µA 4.8 5.2 V Test Condition Soft Start CSS Charging current at CSS – Ich Discharge current at Idis CSS Upper clamping voltage VSSH 4.4 Difference VCRH – VSSH VDSS 0.1 Switching voltage of VK2 K2 V 1.1 1.4 1.7 V 4 6 9 µA 1 mA VS/3 V VCRH – VSSH Pulse Omission PO Charging current at PO int. – Ich Charging current at PO ext. Ich Voltage at – K7 V– K7 VS/3 VS/3 –5% Upper clamping voltage at + K7 VPOH Minimum voltage applied to PO VPOM 1 Input I SYN II SYN – 70 Switching threshold at I SYN Open Rising edge Falling edge VI SYNO VI SYNR VI SYNF 1.5 2.5 1.0 +5% V-K7 V-K7 V-K7 + 0.2 + 0.7 + 1.2 V 0 mA < IPO < 1 mA V Synchronization Version 2.0 2.7 3.4 2.0 18 200 µA 3.5 4.0 3.0 V V V 0 V< VI SYN < 4.5 V 1 May 1996 TDA 4916 GG Characteristics (cont’d) VSon < VS < 15 V, – 25 °C < TA < 85 °C; VSon means that VS has exceeded VSH, but has not gone below VSL. Parameter Symbol Switchover delay int. tdf-s free-running synchronized synchronized tds-f free-running Limit Values typ. max. 15 35 60 µs 9 18 35 µs 2 2 mA mA VI SYN < 1 V VI SYN > 5 V V – 500 µA < IQ SYN < 0 µA 0 µA< IQ SYN < 500 µA 0 0 Output Q SYN High VQ SYNH 4.1 Low VQ SYNL Fan-out of Q SYN for control I SYN Test Condition min. – II SYN II SYN Limiting diodes Unit 0.6 V 2 Q SYN to 0V GND allowed Series Feed Series Feed Threshold at VS VSFTH 9.0 10.0 10.5 V Maximum current VSFGAP ISF max 500 500 – – – – mV µA Voltage at Z1 VZ11 5 – – V Voltage at Z1 VZ12 – – 8 V VSH to VSFTH Gap ISF > 5 µA; VSF = 13 V VS = 11.5 V; VSF = 12.5 V IZ1 = 20 µA; 0 ≤ VS ≤ 8 V IZ1 = 500 µA 0 ≤ VS ≤ 8 V Output Driver Q SIP Saturation voltage source VQ SIPH VQ SIPH VQ SIPH 1.8 2.2 2.5 2.0 2.5 3.0 V V V Saturation voltage sink VQ SIPL VQ SIPL 0.1 1.7 0.5 2.2 V V Version 2.0 19 IQ SIP = 0 mA IQ SIP = – 1 mA IQ SIP = – 200 mA VS = VQ SIP > VSon IQ SIP = 10 mA IQ SIP = 200 mA VS = VQ SIP > VSon 1 May 1996 TDA 4916 GG Characteristics (cont’d) VSon < VS < 15 V, – 25 °C < TA < 85 °C; VSon means that VS has exceeded VSH, but has not gone below VSL. Parameter Symbol Limit Values min. Saturation voltage sink typ. VQ SIPP Unit Test Condition 1.5 V IQ SIP = + 5 mA IC passive CQ SIP = 10 nF; VS = VQ SIP = 12 V CQ SIP = 10 nF; VS = VQ SIP = 12 V max. Output current Falling edge IQ SIP 0.7 1.0 1.5 A1) Rising edge – IQ SIP 0.7 1.0 1.5 A1) Output voltage Fall time tQ SIPF 200 ns2) Rise time tQ SIPR 200 ns2) 1) 2) CQ SIP = 10 nF; VS = VQ SIP = 12 V CQ SIP = 10 nF; VS = VQ SIP = 12 V Maximum dynamic current during rising or falling edge. Voltage level 10 %/90 %. Version 2.0 20 1 May 1996 TDA 4916 GG Figure 3 Application Circuit 1: Forward Converter with Output Regulation Version 2.0 21 1 May 1996 TDA 4916 GG Figure 4 Application Circuit 2: Flyback Converter with EMF Regulation Version 2.0 22 1 May 1996 TDA 4916 GG Figure 5 Timing Diagram Version 2.0 23 1 May 1996 TDA 4916 GG Figure 6 Soft Start CSS / Fault/ON - OFF Version 2.0 24 1 May 1996 TDA 4916 GG Nomogram for FG fo = 97.5 kHz @ Tj = 25 °C; RT = 40.2 kΩ; CT = 560 pF Version 2.0 25 1 May 1996 TDA 4916 GG Instructions for the Approximate Calculation of the Maximum Duty Cycle of the FG when RVS or RGND is Connected to Input CT. 1. General remarks Duty cycle ν = ON time/period Time t = CT ∆VCT/ICT ∆VCT = approx. 0.6 V Current IRGND = 2.2 V/RGND Current IRT = 2.5 V/RT Current IRVS = (12 V − 2.2 V)/RVS Mean value VCT Mean = approx. 2.2 V To facilitate better general understanding, the equations are not abbreviated in the following. The wanted quantity can be isolated using the rules of arithmetic. 2. Calculation for connection of RVS (ν > 0.5) CT ⋅ 0.6 V -----------------------------I RT – I RVS ν max = -------------------------------------------------------------------- CT ⋅ 0.6 V C T ⋅ 0.6 V ------------------------------ + -----------------------------I RT – I RVS I RT + I RVS 3. Calculation for connection of RGND (ν < 0.5) CT ⋅ 0.6 V I RT + I RGND ------------------------------------ ν max = ------------------------------------------------------------------------------CT ⋅ 0.6 V C T ⋅ 0.6 V ------------------------------------ + ------------------------------------ I RT + I RGND I RT – I RGND Version 2.0 26 1 May 1996 TDA 4916 GG Duty Cycle Limiting fFG = 100 kHz Example for νmax = 44 %: Step ➀ to get 44 % a resistor RGND = 220 kΩ is found Step ➁ for the same ν we get RT = 39 kΩ to set fFG to 100 kHz Version 2.0 27 1 May 1996 TDA 4916 GG Tolerance of Osc. Frequency ∆fmax versus Osc. Frequency f Tolerance of Duty Cycle ∆νmax versus Osc. Frequency f Version 2.0 28 1 May 1996 TDA 4916 GG Package Outlines GPS05144 P-DSO-24-1 (SMD) (Plastic Dual Small Outline Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” SMD = Surface Mounted Device Version 2.0 29 Dimensions in mm 1 May 1996 Total Quality Management Qualität hat für uns eine umfassende Bedeutung. Wir wollen allen Ihren Ansprüchen in der bestmöglichen Weise gerecht werden. Es geht uns also nicht nur um die Produktqualität – unsere Anstrengungen gelten gleichermaßen der Lieferqualität und Logistik, dem Service und Support sowie allen sonstigen Beratungs- und Betreuungsleistungen. Quality takes on an allencompassing significance at Semiconductor Group. For us it means living up to each and every one of your demands in the best possible way. So we are not only concerned with product quality. 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