Version 2.0, 5 May 2010 CCM-PFC ICE3PCS02G Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM) Pow e r M a na ge m e nt & S upply CCM-PFC Revision History: Datasheet Edition 2010-05-05 Published by Infineon Technologies AG 81726 Munich, Germany © Infineon Technologies AG 05/05/10. All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. CCM-PFC ICE3PCS02G Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM) Product Highlights • • • • • • • High efficiency over the whole load range Lowest count of external components Accurate and adjustable switching frequency Integrated digital voltage loop compensation Fast output dynamic response during load jump External synchronization Low peak current limitation ICE3PCS02G PG-DSO-8 Features Description • • • The ICE3PCS02G is a 8-pins wide input range controller IC for active power factor correction converters. It is designed for converters in boost topology, and requires few external components. Its power supply is recommended to be provided by an external auxiliary supply which will switch on and off the IC. • • • • Continuous current operation mode PFC Wide input range of Vcc up to 25V Enhanced dynamic response without input current distortion External current loop compensation for greater user flexibility Open loop protection Second over bulk voltage protection Maximum duty cycle of 95% (typical) D BYP DB L Boos t 90 ~ 270 Vac Line Filter R GATE CE R SHUNT R BVS 1 CB R GS R BVS 4 R BVS 2 R BVS 5 R BVS 3 R BVS 6 RCS ISENSE GATE VSENSE OVP GND FREQ ICOMP VCC V CC R FREQ Type Package ICE3PCS02G PG-DSO-8 Version 2.0 3 CICOMP C VCC 5 May 2010 CCM-PFC ICE3PCS02G 1 1.1 1.2 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.5 3.5.1 3.5.2 3.6 3.6.1 3.6.2 3.6.3 3.7 3.8 3.8.1 3.8.2 3.8.3 3.8.4 3.9 3.10 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Frequency Setting and External Synchronization . . . . . . . . . . . . . . . . . . . . .8 Frequency Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 External Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Voltage Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Notch Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Voltage Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Average Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Complete Current Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Current Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 PWM Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 System Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Peak Current Limit (PCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Open Loop Protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 First Over-Voltage Protection (OVP1) . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Second Over Voltage Protection (OVP2) . . . . . . . . . . . . . . . . . . . . . . . .12 Output Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Protection Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.3.9 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Variable Frequency Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 External Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 System Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Current Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Voltage Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Gate Drive Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 5 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Notes: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Version 2.0 4 5 May 2010 CCM-PFC Preliminary Datasheet ICE3PCS02G Pin Configuration and Functionality 1 Pin Configuration and Functionality 1.1 Pin Configuration ratings. Therefore a series resistor (RCS) of around 50Ω is recommended in order to limit this current into the IC. GND (IC Ground) The ground potential of the IC. Pin Symbol Function 1 ISENSE Current Sense Input 2 GND 3 ICOMP Current Loop Compensation 4 FREQ Switching Frequency Setting 5 OVP 6 VSENSE 7 VCC IC Supply Voltage 8 GATE Gate Drive ICOMP (Current Loop Compensation) Low pass filter and compensation of the current control loop. The capacitor which is connected at this pin integrates the output current of OTA6 and averages the current sense signal. IC Ground Over Voltage Protection Bulk Voltage Sense FREQ (Frequency Setting) This pin allows the setting of the operating switching frequency by connecting a resistor to ground. The frequency range is from 21kHz to 250kHz. OVP A resistive voltage divider from bulk voltage to GND can set the over voltage protection threshold. This additional OVP is able to ensure system safety operation. Package PG-DSO-8 ISENSE VSENSE VSENSE is connected via a resistive divider to the bulk voltage. The voltage of VSENSE relative to GND represents the output voltage. The bulk voltage is monitored for voltage regulation, over voltage protection and open loop protection. GATE GND VCC P-DSO-8 ICOMP VSENSE FREQ Figure 1 1.2 VCC VCC provides the power supply of the ground related to IC section. OVP GATE GATE is the output for driving the PFC MOSFET.Its gate drive voltage is clamped at 15V (typically). Pin Configuration (top view) Pin Functionality ISENSE (Current Sense Input) The ISENSE Pin senses the voltage drop at the external sense resistor (RSHUNT). This is the input signal for the average current regulation in the current loop. It is also fed to the peak current limitation block. During power up time, high inrush currents cause high negative voltage drop at RSHUNT, driving currents out of pin 1 which could be beyond the absolute maximum Version 2.0 5 5 May 2010 90 ~ 270 Vac Line Filter CE Figure 2 Version 2.0 6 R Shunt QB R FREQ RGATE Auxiliary Supply FREQ GATE VCC C ISENSE C ICOMP ICOMP GND Nonlinear Gain Current Loop Compensation/ PCL Oscillator/ Synchronization ISENSE Voltage Loop Compensation Second OVP Ramp Generator Protection Unit PWM Logic Driver VCC Unit ICE3PCS02G DB VSENSE OVP R BVS3 R BVS5 R BVS2 R BVS6 CB R BVS4 R BVS1 2 R CS LBoost DBYP CCM-PFC ICE3PCS02G Block Diagram Block Diagram A functional block diagram is given in Figure 2. Note that the figure only shows the brief functional block and does not represent the implementation of the IC. Block Diagram 5 May 2010 CCM-PFC ICE3PCS02G Block Diagram Table 1 Bill Of Material Component Parameters Rectifier Bridge GBU8J CE 100nF/X2/275V LBoost 750uH QB IPP60R199CP DBYP MUR360 DB IDT04S60C CB 220µF/450V Rshunt 60mΩ Cisense 1nF RCS 50Ω RGATE 3.3Ω RFREQ 67kΩ CICOMP 4.7nF/25V RBVS1...2 1.5MΩ RBVS3 18.85kΩ RBVS4...5 2MΩ RBVS6 23kΩ Version 2.0 7 5 May 2010 CCM-PFC ICE3PCS02G Functional Description 3 3.1 Functional Description VBULK 100% 95% General 20% VCC The ICE3PCS02G is a 8-pins control IC for power factor correction converters. It is suitable for wide range line input applications from 85 to 265 VAC with overall efficiency above 90%. The IC supports converters in boost topology and it operates in continuous conduction mode (CCM) with average current control. The IC operates with a cascaded control; the inner current loop and the outer voltage loop. The inner current loop of the IC controls the sinusoidal profile for the average input current. It uses the dependency of the PWM duty cycle on the line input voltage to determine the corresponding input current. This means the average input current follows the input voltage as long as the device operates in CCM. Under light load condition, depending on the choke inductance, the system may enter into discontinuous conduction mode (DCM) resulting in a higher harmonics but still meeting the Class D requirement of IEC 1000-3-2. The outer voltage loop controls the output bulk voltage, integrated digitally within the IC. Depending on the load condition, internal PI compensation output is converted to an appropriate DC voltage which controls the amplitude of the average input current. The IC is equipped with various protection features to ensure safe operating condition for both the system and device. 3.2 26V 12V IVCC <6.4mA with 1nF external cap. at gate drive pin UVLO Figure 3 3.3 Bulk voltage rises to 95% rated value within 200ms Normal operation Standby mode (V VSENSE < 0.5V) State of Operation respect to VCC Start-up During power up when the Vout is less than 95% of the rated level, internal voltage loop output increases from initial voltage under the soft-start control. This results in a controlled linear increase of the input current from 0A thus reducing the stress in the external components. Once Vout has reached 95% of the rated level, the softstart control is released to achieve good regulation and dynamic response in normal operation. 3.4 Power Supply Frequency Setting and External Synchronization The IC can provide external switching frequency setting by an external resistor RFREQ and the online synchronization by external pulse signal at FREQ pin. An internal under voltage lockout (UVLO) block monitors the VCC power supply. As soon as it exceeds 12.0V and voltage at pin 6 (VSENSE) >0.5V, the IC begins operating its gate drive and performs its startup as shown in Figure 3. If VCC drops below 11V, the IC is off. The IC will then be consuming typically 1.4mA, whereas consuming 6.4mA during normal operation The IC can be turned off and forced into standby mode by pulling down the voltage at pin 6 (VSENSE) below 0.5V. Version 2.0 3.5mA 1.4 mA 3.4.1 Frequency Setting The switching frequency of the PFC converter can be set with an external resistor RFREQ at FREQ pin as shown Figure 2. The pin voltage at VFREQ is typical 1V. The corresponding capacitor for the oscillator is integrated in the device and the RFREQ/frequency is given in Figure 4. The recommended operating frequency range is from 21kHz to 250kHz. As an example, a RFREQ of 67kΩ at pin FREQ will set a switching frequency FSW of 65kHz typically. 8 5 May 2010 CCM-PFC ICE3PCS02G Functional Description 3.5 The voltage loop is the outer loop of the cascaded control scheme which controls the PFC output bus voltage VOUT. This loop is closed by the feedback sensing voltage at VSENSE which is a resistive divider tapping from VOUT. The pin VSENSE is the input of sigma-delta ADC which has an internal reference of 2.5V and sampling rate of 3.55kHz (typical). The voltage loop compensation is integrated digitally for better dynamic response and saving design effort. Figure 6 shows the important blocks of this voltage loop. Frequency vs Resistance 260 240 Resistance /kohm Frequency /kHz Resistance /kohm Frequency /kHz 220 15 278 110 40 17 249 120 20 211 130 34 30 141 140 31.5 160 40 106 150 29.5 140 50 86 169 26.2 120 60 74 191 70 62 200 23 80 55 210 21.2 80 90 49 221 20.2 60 100 43 232 19.2 200 Frequency/kHz 180 100 Voltage Loop 36 25 40 20 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 Resistance/kohm Figure 4 L Boost DB R BVS1 Frequency Versus RFREQ QB Rectified Input Voltage 3.4.2 External Synchronization The switching frequency can be synchronized to the external pulse signal after 6 external pulses delay once the voltage at the FREQ pin is higher than 2.5V. The synchronization means two points. Firstly, the PFC switching frequency is tracking the external pulse signal frequency. Secondly, the falling edge of the PFC signal is triggered by the rising edge of the external pulse signal. Figure 5 shows the blocks of frequency setting and synchronization. The external RSYN combined with RFREQ and the external diode DSYN can ensure pin voltage to be kept between 1.0V (clamped externally) and 5V (maximum pin voltage). If the external pulse signal has disappeared longer than 108µs (typical) the switching frequency will be synchronized to internal clock set by the external resistor RFREQ. R GATE R BVS2 CB R BVS3 Gate Driver Current Loop + PWM Generation GATE VIN Av(IIN ) Nonlinear Gain Sigmadelta ADC Notch Filter PI Filter 2.5V VSENSE t 500 ns OLP C2 a C1 a OVP OVP Q R Q S 0.5V 2.5V 2.7V C1 b Syn. clock IOSC Figure 6 1.0V DSYN OTA7 3.5.1 Notch Filter In the PFC converter, an averaged current through the output diode of rectified sine waveform charges the output capacitor and results in a ripple voltage at the output capacitor with a frequency two times of the line frequency. In this digital PFC, a notch filter is used to remove the ripple of the sensed output voltage while keeping the rest of the signal almost uninfluenced. In this way, an accurate and fast output voltage regulation without influence of the output voltage ripple is achieved. RSYN C9 RFREQ FREQ Figure 5 Version 2.0 Voltage Loop SYN 2.5V/1.25V Frequency Setting and Synchronization 3.5.2 Voltage Loop Compensation The Proportion-Integration (PI) compensation of the voltage loop is integrated digitally inside the IC. The digital data out of the PI compensator is converted to analog voltage for current loop control. 9 5 May 2010 CCM-PFC ICE3PCS02G Functional Description The nonlinear gain block controls the amplitude of the regulated inductor current. The input of this block is the output voltage of integrated PI compensator. This block has been designed to reduce the voltage loop dependency on the input voltage in order to support the wide input voltage range (85VAC-265VAC). Figure 7 gives the relative output power transfer curve versus the digital word from the integrated PI compensator. The output power at the input voltage of 85VAC and maximum digital word of 256 from PI compensator is set as the normative power and the power curves at different input voltage present the relative power to the normative one. power at 85V LBoost QB Rectified Input Voltage RGATE CB Rshunt GATE RCS Current Loop ISENSE power at 265V Current Loop Compensation ICOMP 10.00000 1.00000 relative output power DB CICOMP OTA6 voltage proportional to averaged Inductor current Gate Driver PWM Comparator R Q S C10 PWM Logic 5.0mS +/-50uA (linear range) S2 0.10000 5V Nonlinear Gain Input From Voltage Loop Fault 0.01000 0.00100 Figure 8 Complete System Current Loop 0.00010 3.6.2 Current Loop Compensation The compensation of the current loop is implemented at the ICOMP pin. This is OTA6 output and a capacitor CICOMP has to be installed at this node to ground (see Figure 8). Under normal mode of the operation, this pin gives a voltage which is proportional to the averaged inductor current. This pin is internally shorted to 5V in the event of standby mode. 0.00001 0 18 37 55 73 91 110 128 146 165 183 201 219 238 256 PI digital output Figure 7 3.6 Power Transfer Curve Average Current Control The choke current is sensed through the voltage across the shunt resistor and averaged by the ICOMP pin capacitor so that the IC can control the choke current to track the instant variation of the input voltage. 3.6.3 Pulse Width Modulation (PWM) The IC employs an average current control scheme in continuous mode (CCM) to achieve the power factor correction. Assuming the loop voltage is working and output voltage is kept constant, the off duty cycle DOFF for a CCM PFC system is given as: 3.6.1 Complete Current Loop The complete system current loop is shown in Figure 8. It consists of the current loop block which averages the voltage at ISENSE pin resulted from the inductor current flowing across Rshunt. The averaged waveform is compared with an internal ramp in the ramp generator and PWM block. Once the ramp crosses the average waveform, the comparator C10 turns on the driver stage through the PWM logic block. The Nonlinear Gain block defines the amplitude of the inductor current. The following sections describe the functionality of each individual blocks. Version 2.0 DOFF=VIN/VOUT From the above equation, DOFF is proportional to VIN. The objective of the current loop is to regulate the average inductor current such that it is proportional to the off duty cycle DOFF, and thus to the input voltage VIN. Figure 9 shows the scheme to achieve the objective. 10 5 May 2010 CCM-PFC ICE3PCS02G Functional Description Ramp Profile immediately and maintained in off state for the current PWM cycle. The signal TOFFMIN resets (highest priority, overriding other input signals) both the current limit latch and the PWM on latch as illustrated in Figure 11. Ave(Iin) at ICOMP Current limit Latch Toff _min 600ns R Peak current limit Gate Drive t Figure 9 Average Current Control in CCM Current loop PWM on signal The PWM is performed by the intersection of a ramp signal with the averaged inductor current at pin 3 (ICOMP). The PWM cycles starts with the Gate turn off for a duration of TOFFMIN (600ns typ.) and the ramp is kept discharged. The ramp is allowed to rise after the TOFFMIN expires. The off time of the boost transistor ends at the intersection of the ramp signal and the averaged current waveform. This results in the proportional relationship between the average current and the off duty cycle DOFF. Figure 10 shows the timing diagrams of the TOFFMIN and the gate waveforms. PWM on Latch R Q S Q PWM LOGIC System Protection The IC provides numerous protection features in order to ensure the PFC system in safe operation. 3.8.1 Peak Current Limit (PCL) The IC provides a cycle by cycle peak current limitation (PCL). It is active when the voltage at pin 1 (ISENSE) reaches -0.4V. This voltage is amplified by a factor of 2.5 and connected to comparator with a reference voltage of 1.0V as shown in Figure 12. A deglitcher with 200ns after the comparator improves noise immunity to the activation of this protection. Toff _min 600 ns Clock PWM Cycle VC,ref High = turn on Gate S Q Figure 11 3.8 Q (1) Vram p Full-wave rectifier Ramp Released ISENSE R CS GATE t G=-2.5 200ns AO2 Rshunt C5 (1) V c,ref is a function of V ICOMP Figure 10 3.7 Iin Ramp and PWM waveforms PCL 1V SGND PWM Logic The PWM logic block prioritizes the control input signal and generates the final logic signal to turn on the driver stage. The speed of the logic gates in this block, together with the width of the reset pulse TOFFMIN, are designed to meet a maximum duty cycle DMAX of 95% at the GATE output under 65kHz of operation. In case of high input currents which results in Peak Current Limitation, the GATE will be turned off Version 2.0 Figure 12 Peak Current Limit (PCL) 3.8.2 Open Loop Protection (OLP) Whenever VSENSE voltage falls below 0.5V, or equivalently VOUT falls below 20% of its rated value, it indicates an open loop condition (i.e. VSENSE pin not connected) or an insufficient input voltage VIN for normal operation. It is implemented using comparator 11 5 May 2010 CCM-PFC ICE3PCS02G Functional Description C2a with a threshold of 0.5V as shown in the IC block diagram in Figure 6. VCC Reg (17V) 3.8.3 First Over-Voltage Protection (OVP1) Whenever VOUT exceeds the rated value by 8%, the over-voltage protection OVP1 is active as shown in Figure 6. This is implemented by sensing the voltage at VSENSE pin with respect to a reference voltage of 2.7V. A VSENSE voltage higher than 2.7V will immediately turn off the gate, thereby preventing damage to bus capacitor. After bulk voltage falls below the rated value, gate drive resumes switching again. PWM Logic HIGH to turn on LV Z1 External MOS GATE 3.8.4 Second Over Voltage Protection (OVP2) The second OVP is provided in case that the first one fails due to the aging or incorrect resistors connected to the VSENSE pin. This is implemented by sensing the voltage at pin OVP with respect to a reference voltage of 2.5V. When voltage at OVP pin is higher than 2.5V, the IC will immediately turn off the gate, thereby preventing damage to bus capacitor. When the bulk voltage drops out of the hysteresis the IC will begin auto soft-start. In normal operation the trigger level of second OVP should be designed higher than the first OVP. However in the condition of mains transient overshoot the bulk voltage may be pulled up to the peak value of mains that is higher than the threshold of OVP1 and OVP2. In this case the OVP1 and OVP2 are triggered in the same time the IC will shut down the gate drive until bulk voltage falls out of the two protection hysteresis, then resume the gate drive again. 3.9 Gate Driver * LV: Level Shift Figure 13 Gate Driver Output Gate Driver The output gate driver is a fast totem pole gate drive. It has an in-built cross conduction currents protection and a Zener diode Z1 (see Figure 13) to protect the external transistor switch against undesirable over voltages. The maximum voltage at pin 8 (GATE) is typically clamped at 15V. The output is active HIGH and at VCC voltages below the under voltage lockout threshold VCCUVLO, the gate drive is internally pull low to maintain the off state. Version 2.0 12 5 May 2010 CCM-PFC ICE3PCS02G Functional Description 3.10 Protection Function Description of Fault Fault-Type Min. Duration of Effect Consequence Voltage at Pin ISENSE < -400mV PCL 200 ns Gate Driver is turned off immediately during current switching cycle Voltage at Pin VSENSE < 0.5V OLP 1 µs Power down. Soft-restart after VSENSE voltage > 0.5V Voltage at Pin VSENSE > 108% of rated level OVP1 12 µs Gate Driver is turned off until VSENSE voltage < 2.5V. Voltage at Pin OVP > 2.5V and Voltage at Pin VSENSE > 108% of rated level OVP1 and OVP2 12 µs Gate Driver is turned off until bulk voltage drops out of both OVP hysteresis Voltage at Pin OVP > 2.5V OVP2 (autorestart mode) 12 µs Gate Driver is turned off. Soft-restart after OVP voltage < 2.3V Version 2.0 13 5 May 2010 CCM-PFC ICE3PCS02G Electrical Characteristics 4 Electrical Characteristics All voltages are measured with respect to ground (pin 2). The voltage levels are valid if other ratings are not violated. 4.1 Absolute Maximum Ratings Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7 (VCC) is discharged before assembling the application circuit. Parameter Symbol Values Min. Typ. Unit Note / Test Condition Max. VCC Supply Voltage VVCC -0.3 26 V GATE Voltage VGATE -0.3 17 V Clamped at 15V if driven internally. ISENSE Voltage VISENSE -20 5.3 V 1) ISENSE Current IISENSE -1 1 mA VSENSE Voltage VVSENSE -0.3 5.3 V VSENSE Current IVSENSE -1 1 mA ICOMP Voltage VICOMP -0.3 5.3 V FREQ Voltage VFREQ -0.3 5.3 V OVP Voltage VOVP -0.3 5.3 V Junction Temperature TJ -40 150 °C Storage Temperature TA,STO -55 150 °C Thermal Resistance RTHJA 185 K/W Soldering Temperature TSLD 260 °C Wave Soldering2) ESD Capability VESD 2 kV Human Body Model3) 1) 2) 3) Junction to Air Absolute ISENSE current should not be exceeded According to JESD22A111 According to EIA/JESD22-A114-B (discharging an 100 pF capacitor through an 1.5kΩ series resistor) Version 2.0 14 5 May 2010 CCM-PFC ICE3PCS02G Electrical Characteristics 4.2 Note: Operating Range Within the operating range the IC operates as described in the functional description. Parameter Symbol Values Min. 25 V TJ -25 125 °C FPFC 21 250 kHz VVCC Junction Temperature PFC switching frequency Note: 4.3.1 Note / Test Condition Max. VVCC,OFF VCC Supply Voltage @ 25°C 4.3 Typ. Unit TJ=25°C Characteristics The electrical Characteristics involve the spread of values given within the specified supply voltage and junction temperature range TJ from -25 °C to 125 °C. Typical values represent the median values, which are related to 25 °C. If not otherwise stated, a supply voltage of VVCC = 18V, a typical switching frequency of ffreq=65kHz are assumed and the IC operates in active mode. Furthermore, all voltages are referring to GND if not otherwise mentioned. Supply Section Parameter Symbol Limit Values Min. Unit Note/Test Condition Typ. Max. VCC Turn-On Threshold VCCon 11.5 12 12.9 V VCC Turn-Off Threshold/ Under Voltage Lock Out VCCUVLO 10.5 11.0 11.9 V VCC Turn-On/Off Hysteresis VCChy 0.7 1 1.45 V Start Up Current Before VCCon ICCstart1 - 380 680 µA VCCon-1.2V Start Up Current Before VCCon ICCstart2 - 1.4 2.4 mA VCCon-0.2V Operating Current with active GATE ICCHG - 6.4 8.5 mA CL= 1nF Operating Current during Standby ICCStdby - 3.5 4.7 mA VVSENSE= 0.4V VICOMP= 4V Version 2.0 15 5 May 2010 CCM-PFC ICE3PCS02G Electrical Characteristics 4.3.2 Variable Frequency Section Parameter Symbol Limit Values Min. Unit Test Condition Typ. Max. Switching Frequency (Typical) FSWnom 62.5 65 67.5 kHz R5 = 67kΩ Switching Frequency (Min.) FSWmin - 21 - kHz R5 = 212kΩ Switching Frequency (Max.) FSWmax - 250 - kHz R5 = 17kΩ Voltage at FREQ pin VFREQ - 1 - V Max. Duty Cycle Dmax 93 95 98.5 % 4.3.3 PWM Section Parameter Symbol Limit Values Min. Min. Duty Cycle DMIN Min. Off Time TOFFMIN 4.3.4 fSW=fSWnom (RFRE=67kΩ) 310 Typ. 600 Unit Test Condition Max. 0 % VVSENSE= 2.5V VICOMP= 4.3V 920 ns VVSENSE= 2.5V VISENSE= 0V (R5 = 67kΩ) External Synchronization Parameter Symbol Values Min. Detection threshold of external clock Vthr_EXT Synchronization range fEXT_range Synchronization frequency ratio fEXT:fPFC propagation delay from rising edge of external clock to falling edge of PFC gate drive TEXT2GATE Allowable external duty on time TD_on Version 2.0 Typ. Unit Max. 2.5 50 Note / Test Condition V 150 kHz 500 ns 70 % 1:1 10 16 fEXT=65kHz 5 May 2010 CCM-PFC ICE3PCS02G Electrical Characteristics 4.3.5 System Protection Section Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Over Voltage Protection (OVP1) Low to High VOVP1_L2H 2.65 2.7 2.77 V Over Voltage Protection (OVP1) High to Low VOVP1_H2L 2.45 2.5 2.55 V Over Voltage Protection (OVP1) Hysteresis VOVP1_HYS 150 200 270 mV Blanking time for OVP1 TOVP1 Over Voltage Protection (OVP2) Low to High VOVP2_L2H 2.45 2.5 2.55 V Over Voltage Protection (OVP2) High to Low IOVP2_H2L 2.25 2.3 2.35 V Blanking time for OVP2 TOVP2 12 µs OVP2 mode detection threshold VOVP2_mode 0.5 V comparator at VBTHL pin Current source for OVP2 mode detection1) IOVP2_mode current source at VBTHL pin Peak Current Limitation (PCL) ISENSE Threshold VPCL Blanking time for PCL turn_on TPCLon 1) 4.3.6 4 5 6 µA -365 -400 -435 mV 200 ns Current Loop Section Symbol OTA6 Transconductance Gain 1) GmOTA6 OTA6 Output Linear Range IOTA6 ICOMP Voltage during OLP VICOMPF 4.3.7 µs 12 The parameter is not subject to production test - verified by design/characterization Parameter 1) 108%VBULKRated Values Unit Note / Test Condition Min. Typ. Max. 3.5 5.0 6.35 5.0 At Temp = 25°C µA ± 50 4.8 mS 5.2 V VVSENSE= 0.4V The parameter is not subject to production test - verified by design/characterization Voltage Loop Section Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Trimmed Reference Voltage VVSREF 2.47 2.5 2.53 V Open Loop Protection (OLP) VSENSE Threshold VVS_OLP 0.45 0.5 0.55 V VSENSE Input Bias Current IVSENSE -1 - 1 µA Version 2.0 17 ±1.2% VVSENSE= 2.5V 5 May 2010 CCM-PFC ICE3PCS02G Electrical Characteristics 4.3.8 Driver Section Parameter GATE Low Voltage GATE High Voltage 4.3.9 Symbol Values Unit Note / Test Condition Min. Typ. Max. - - 1.2 V VCC =10V IGATE = 5 mA - 0.4 - V IGATE = 0 A - - 1.4 V IGATE = 20 mA -0.2 0.8 - V IGATE = -20 mA - 15 - V VCC = 25V CL = 1nF - 12.4 - V VCC = 15V CL = 1nF 8.0 - - V VCC = VVCCoff + 0.2V CL = 1nF VGATEL VGATEH Gate Drive Section Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. GATE Rise Time tr - 30 - ns VGate = 20% - 80% VGATEH CL = 1nF GATE Fall Time tf - 25 - ns VGate = 80% - 20% VGATEH CL = 1nF Version 2.0 18 5 May 2010 CCM-PFC ICE3PCS02G Outline Dimension 5 Outline Dimension PG-DSO-8 Outline Dimension 1.27 0.1 0.41 +0.1 -0.05 .01 0.2 +0.05 -0 C 0.2 M A C x8 8 5 Index Marking 1 4 5 -0.21) 8˚ MAX. 4 -0.21) 1.75 MAX. 0.1 MIN. (1.5) 0.33 ±0.08 x 45˚ 0.64 ±0.25 6 ±0.2 A Index Marking (Chamfer) 1) Does not include plastic or metal protrusion of 0.15 max. per side Notes: 1. You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. 2. Dimensions in mm. Version 2.0 19 5 May 2010 Total Quality Management Qualität hat für uns eine umfassende Bedeutung. Wir wollen allen Ihren Ansprüchen in der bestmöglichen Weise gerecht werden. Es geht uns also nicht nur um die Produktqualität – unsere Anstrengungen gelten gleichermaßen der Lieferqualität und Logistik, dem Service und Support sowie allen sonstigen Beratungs- und Betreuungsleistungen. Quality takes on an allencompassing significance at Semiconductor Group. For us it means living up to each and every one of your demands in the best possible way. So we are not only concerned with product quality. We direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. Dazu gehört eine bestimmte Geisteshaltung unserer Mitarbeiter. Total Quality im Denken und Handeln gegenüber Kollegen, Lieferanten und Ihnen, unserem Kunden. Unsere Leitlinie ist jede Aufgabe mit „Null Fehlern“ zu lösen – in offener Sichtweise auch über den eigenen Arbeitsplatz hinaus – und uns ständig zu verbessern. Part of this is the very special attitude of our staff. Total Quality in thought and deed, towards co-workers, suppliers and you, our customer. Our guideline is “do everything with zero defects”, in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve. Unternehmensweit orientieren wir uns dabei auch an „top“ (Time Optimized Processes), um Ihnen durch größere Schnelligkeit den entscheidenden Wettbewerbsvorsprung zu verschaffen. Geben Sie uns die Chance, hohe Leistung durch umfassende Qualität zu beweisen. Wir werden Sie überzeugen. http://www.infineon.com Published by Infineon Technologies AG Throughout the corporation we also think in terms of Time Optimized Processes (top), greater speed on our part to give you that decisive competitive edge. Give us the chance to prove the best of performance through the best of quality – you will be convinced.