CYPRESS CY7C133-55JC

CY7C133
CY7C143
2K x 16 Dual-Port Static RAM
Features
Functional Description
• True dual-ported memory cells which allow
simultaneous reads of the same memory location
• 2K x 16 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 25/35/55 ns
• Low operating power: ICC = 150 mA (typ.)
• Fully asynchronous operation
• Master CY7C133 expands data bus width to 32 bits or
more using slave CY7C143
• BUSY output flag on CY7C133; BUSY input flag on
CY7C143
• Available in 68-pin PLCC
The CY7C133 and CY7C143 are high-speed CMOS 2K by 16
dual-port static RAMs. Two ports are provided permitting
independent access to any location in memory. The CY7C133
can be utilized as either a stand-alone 16-bit dual-port static
RAM or as a master dual-port RAM in conjunction with the
CY7C143 slave dual-port device in systems requiring 32-bit or
greater word widths. It is the solution to applications requiring
shared or buffered data, such as cache memory for DSP,
bit-slice, or multiprocessor designs.
Each port has independent control pins; Chip Enable (CE),
Write Enable (R/WUB, R/WLB), and Output Enable (OE).
BUSY signals that the port is trying to access the same
location currently being accessed by the other port. An
automatic power-down feature is controlled independently on
each port by the Chip Enable (CE) pin.
The CY7C133 and CY7C143 are available in 68-pin PLCC.
Logic Block Diagram
CEL
R/WLUB
CER
R/WLLB
R/WRLB
OER
R/WRUB
OEL
I/O8L – I/O15L
I/O
CONTROL
I/O8R – I/O15R
I/O
CONTROL
I/O0L – I/O7L
I/O0R – I/O7R
[ ]
BUSYL[1]
A10L
BUSYR
ADDRESS
DECODER
ADDRESS
DECODER
MEMORY
ARRAY
A0L
1
A10R
A0R
CE L
OE L
R/WLUB
ARBITRATION
LOGIC
CER
OER
(CY7C133 ONLY)
R/WRUB
R/WRLB
R/WLLB
Note:
1. CY7C133 (Master): BUSY is open drain output and requires pull-up resistor. CY7C143 (Slave): BUSY is input.
Cypress Semiconductor Corporation
Document #: 38-06036 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised June 22, 2004
CY7C133
CY7C143
Pin Configuration
9 8 7 6
I/O9L
I/O10L
I/O11L
I/O12L
I/O13L
I/O14L
I/O15L
VCC
GND
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
A8L
A7L
A10L
A9L
R/WLUB
R/WLLB
OEL
I/O 3L
I/O 2L
I/O 1L
I/O 0L
V CC
I/O 4L
I/O 6L
I/O 5L
I/O 8L
I/O 7L
68-Pin LCC/PLCC
Top View
5 4 3 2 1 68 67 66 65 64 63 62 61
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
7C133
7C143
21
22
23
24
25
26
47
46
45
44
A6L
A5L
A4L
A3L
A2L
A1L
A0L
BUSYL
CEL
CER
BUSYR
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A
8R
A7R
I/O8R
I/O9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
I/O
15R
GND
R/W
RUB
R/W
RLB
OE R
A
10R
A9R
2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43
Selection Guide
7C133-25
7C143-25
7C133-35
7C143-35
7C133-55
7C143-55
Unit
Maximum Access Time
25
35
55
ns
Typical Operating Current ICC
170
160
150
mA
Typical Standby Current for ISB1
40
30
20
mA
Document #: 38-06036 Rev. *B
Page 2 of 13
CY7C133
CY7C143
Architecture
The CY7C133 (master) and CY7C143 (slave) consist of an
array of 2K words of 16 bits each of dual-port RAM cells, I/O
and address lines, and control signals (CE, OE, R/W). These
control pins permit independent access for reads or writes to any
location in memory. To handle simultaneous writes/reads to the same
location, a BUSY pin is provided on each port. The CY7C133 and
CY7C143 have an automatic power-down feature controlled by CE.
Each port is provided with its own output enable control (OE), which
allows data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1 waveform) or
the CE pin (see Write Cycle No. 2 waveform). Two R/W pins (R/WUB
and R/WLB) are used to separate the upper and lower bytes of IO.
Required inputs for non-contention operations are summarized in
Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flow-through
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port tDDD after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after OE is
asserted.
Busy
The CY7C133 (master) provides on-chip arbitration to resolve
simultaneous memory location access (contention). Table 2
shows a summery of conditions where BUSY is asserted. If both
ports’ CEs are asserted and an address match occurs within tPS of
each other, the busy logic will determine which port has access. If tPS
is violated, one port will definitely gain permission to the location, but
which one is not predictable. BUSY will be asserted tBLA after an
address match or tBLC after CE is taken LOW. The results of all eight
arbitration possibilities are summarized in Table 3. BUSY is an open
drain output and requires a pull-up resistor.
One master and as many slaves as necessary may be
connected in parallel to expand the data bus width in 16 bit
increments. The BUSY output of the master is connected to the
BUSY input of the slave. Writing to slave devices must be delayed
until after the BUSY input has settled (tBLC or tBLA). Otherwise, the
slave chip may begin a write cycle during a contention
situation.
Flow-Through Operation
The CY7C133/143 has a flow-through architecture that facilitates repeating (actually extending) an operation when a
BUSY is received by a losing port. The BUSY signal should be
interpreted as a NOT READY. If a BUSY to a port is active, the
port should wait for BUSY to go inactive, and then extend the
operation it was performing for another cycle. The timing
diagram titled, “Timing waveform with port to port delay” illustrates the case where the right port is writing to an address and
the left port reads the same address. The data that the right
port has just written flows through to the left, and is valid either
tDDD after the falling edge of the write strobe of the left port, or
tDDD after the data being written becomes stable.
Data Retention Mode
The CY7C133/143 is designed with battery backup in mind.
Data retention voltage and supply current are guaranteed over
temperature. The following rules insure data retention:
1. Chip enable (CE) must be held HIGH during data retention, within VCC to VCC – 0.2V.
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (4.5V).
Timing
Data Retention Mode
VCC
4.5V
VCC > 2.0V
4.5V
VCC to VCC – 0.2V
CE
Parameter
ICCDR1
Test Conditions[2]
@ VCCDR = 2V
tRC
V
IH
Max.
Unit
1.5
mA
Note:
2. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
Document #: 38-06036 Rev. *B
Page 3 of 13
CY7C133
CY7C143
Table 1. Non-Contending Read/Write Control
Control
I/O
R/WLB
R/WUB
CE
OE
I/O0–I/O8
I/O9–I/O17
Operation
X
X
H
X
High Z
High Z
Deselected: Power-Down
L
L
L
X
Data In
Data In
Write to Both Bytes
L
H
L
L
Data In
Data Out
Write Lower Byte, Read Upper Byte
H
L
L
L
Data Out
Data In
Read Lower Byte, Write Upper Byte
L
H
L
H
Data In
High Z
Write to Lower Byte
H
L
L
H
High Z
Data In
Write to Upper Byte
H
H
L
L
Data Out
Data Out
Read to Both Bytes
H
H
L
H
High Z
High Z
High Impedance Outputs
Table 2. Address BUSY Arbitration
Inputs
Outputs
CEL
CER
AddressL
AddressR
BUSYL
BUSYR
X
X
No Match
H
H
Normal
H
X
Match
H
H
Normal
X
H
Match
H
H
Normal
L
L
Match
Note 3
Note 3
Function
Write Inhibit[4]
32-Bit Master/Slave Dual-Port Memory Systems
R/W
LEFT
RIGHT
R/W
CY7C133
BUSY
BUSY
5V
5V
R/W
R/W
CY7C143
BUSY
BUSY
Table 3. Arbitration Results
Port
Case
Left
Right
Winning Port
Result
1
Read
Read
L
Both ports read
2
Read
Read
R
Both ports read
3
Read
Write
L
L port reads OK R port write inhibited
4
Read
Write
R
R port writes OK L port data may be invalid
5
Write
Read
L
L port writes OK R port data may be invalid
6
Write
Read
R
R port reads OK L port write inhibited
7
Write
Write
L
L port writes OK R port write inhibited
8
Write
Write
R
R port writes OK L port write inhibited
Notes:
3. The loser of the port arbitration will receive BUSY = “L” (BUSYL or BUSYR = “L”). BUSYL and BUSYR cannot both be LOW simultaneously.
4. Writes are inhibited to the left port when BUSYL is LOW. Writes are inhibited to the right port when BUSYR is LOW.
Document #: 38-06036 Rev. *B
Page 4 of 13
CY7C133
CY7C143
DC Input Voltage ................................................. −3.5V to +7.0V
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................... −65°C to +150°C
Latch-up Current..................................................... >200 mA
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Operating Range
Supply Voltage to Ground Potential
(Pin 48 to Pin 24).................................................−0.5V to +7.0V
Range
Ambient Temperature
VCC
0°C to +70°C
5V ± 10%
−40°C to +85°C
5V ± 10%
Commercial
DC Voltage Applied to Outputs
in High-Z State .....................................................−0.5V to +7.0V
Industrial
Electrical Characteristics Over the Operating Range
7C133-25
7C143-25
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
IOL = 4.0 mA
IOL = 16.0
Min.
mA[5]
Input LOW Voltage
IIX
Input Leakage Current
GND < VI < VCC
−5
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
−5
IOS
Output Short Circuit Current[6, 7]
VCC = Max., VOUT = GND
ICC
VCC Operating Supply Current
CE = VIL,
Outputs Open, f = fMAX[8]
ISB4
V
0.5
VIL
ISB3
Unit
V
0.4
Input HIGH Voltage
ISB2
Max.
2.4
VIH
ISB1
Typ.
2.2
V
0.8
V
+5
µA
+5
µA
−200
mA
mA
Com’l
170
250
Ind.
170
290
Standby Current Both Ports, TTL CEL and CER > VIH, f = fMAX[8]
Inputs
Com’l
40
60
Ind.
40
75
Standby Current One Port, TTL
Inputs
CEL or CER > VIH, Active Port
Outputs Open, f = fMAX[8]
Com’l
100
140
Ind.
100
160
Standby Current Both Ports,
CMOS Inputs
Both Ports CEL and CER > VCC –
0.2V, VIN > VCC – 0.2V or VIN <
0.2V, f = 0
Com’l
3
15
Ind.
3
15
Standby Current One Port,
CMOS Inputs
One Port CEL or CER > VCC – 0.2V, Com’l
VIN > VCC – 0.2V or
Ind.
VIN < 0.2V, Active Port Outputs Open,
[8]
f = fMAX
90
120
90
140
mA
mA
mA
mA
Electrical Characteristics Over the Operating Range (continued)
7C133-35
7C143-35
Parameter
Description
Test Conditions
Min.
Typ.
7C133-55
7C143-55
Max.
Typ.
Max.
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
IOL = 4.0 mA
0.4
0.4
IOL = 16.0 mA[5]
0.5
0.5
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
2.4
Min.
VOH
2.4
2.2
V
2.2
0.8
Unit
V
V
0.8
V
Input Leakage Current GND < VI < VCC
−5
+5
−5
+5
µA
Notes:
5. BUSY pin only.
6. Duration of the short circuit should not exceed 30 seconds.
7. Tested initially and after any design or process changes that may affect these parameters.
8. At f=fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/tRC and using AC Test Waveforms input levels of GND to 3V.
IIX
Document #: 38-06036 Rev. *B
Page 5 of 13
CY7C133
CY7C143
Electrical Characteristics Over the Operating Range (continued)
7C133-35
7C143-35
Parameter
Description
Test Conditions
Min.
IOZ
Output Leakage
Current
GND < VO < VCC, Output Disabled
IOS
Output Short Circuit
Current[6, 7]
VCC = Max., VOUT = GND
ICC
VCC Operating Supply CE = VIL,
Outputs Open, f = fMAX[8]
Current
ISB1
Standby Current Both
Ports, TTL Inputs
CEL and CER > VIH, f = fMAX[8] Com’l
ISB2
Standby Current One
Port, TTL Inputs
CEL or CER > VIH, Active Port Com’l
Outputs Open, f = fMAX[8]
Ind.
ISB3
Standby Current Both
Ports, CMOS Inputs
Both Ports CEL and CER >
Com’l
VCC - 0.2V, VIN > VCC – 0.2V Ind.
or VIN < 0.2V, f = 0
Standby Current One
Port, CMOS Inputs
One Port CEL or CER > VCC – Com’l
0.2V, VIN > VCC – 0.2V or
VIN < 0.2V, Active Port
Ind.
Outputs Open, f = fMAX[8]
ISB4
Typ.
−5
7C133-55
7C143-55
Max.
Min.
+5
−5
Typ.
−200
Max.
Unit
−5
µA
−200
mA
mA
Com’l
160
230
150
220
Ind.
160
260
150
250
30
50
20
40
30
65
20
55
85
125
75
110
85
140
75
125
3
15
3
15
3
15
3
15
80
105
70
90
80
120
70
105
Ind.
mA
mA
mA
mA
Capacitance[7]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
10
pF
10
pF
TA = 25°C, f = 1 MHz, VCC = 5.0V
AC Test Loads and Waveforms
R1893Ω
5V
OUTPUT
5V
R1893Ω
5V
OUTPUT
R2
347Ω
30 pF
INCLUDING
JIG AND
SCOPE
R2
347Ω
5 pF
INCLUDING
JIG AND
SCOPE
(a)
BUSY
OR
INT
30 pF
(b)
BUSY Output Load
(CY7C133 ONLY)
ALL INPUT PULSES
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
Document #: 38-06036 Rev. *B
3.0V
10%
250Ω
1.40V
281Ω
GND
< 3 ns
90%
90%
10%
< 3 ns
Page 6 of 13
CY7C133
CY7C143
Switching Characteristics Over the Operating Range[9]
Parameter
Description
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid[10]
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid[10]
tDOE
OE LOW to Data Valid[10]
tLZOE
OE LOW to Low Z[11, 12,13]
tHZOE
OE HIGH to High Z[11, 12,13]
tLZCE
CE LOW to Low Z[11, 12,13]
tHZCE
CE HIGH to High Z[11, 12,13]
tPU
CE LOW to Power-Up[13]
tPD
CE HIGH to Power-Down[13]
Write Cycle[14]
tWC
Write Cycle Time
tSCE
CE LOW to Write End
tAW
Address Set-up to Write End
tHA
Address Hold from Write End
tSA
Address Set-up to Write Start
tPWE
R/W Pulse Width
tSD
Data Set-up to Write End
tHD
Data Hold from Write End
tHZWE
R/W LOW to High Z[12,13]
tLZWE
R/W HIGH to Low Z[12,13]
Busy/Interrupt Timing (for master CY7C133)
tBLA
BUSY Low from Address Match
tBHA
BUSY High from Address Mismatch
tBLC
BUSY Low from CE LOW
tBHC
BUSY High from CE HIGH
tWDD
Write Pulse to Data Delay[15]
tDDD
Write Data Valid to Read Data Valid[15]
tBDD
BUSY High to Valid Data[16]
tPS
Arbitration Priority Set Up Time[17]
Busy Timing (for slave CY7C143)
tWB
Write to BUSY[18]
tWH
Write Hold After BUSY[19]
tWDD
Write Pulse to Data Delay[20]
tDDD
Write Data Valid to Read Data Valid[20]
7C133-25
7C143-25
Min.
Max.
25
7C133-35
7C143-35
Min.
Max.
35
25
0
55
35
0
25
20
3
0
3
15
3
20
25
20
0
25
35
25
25
2
0
25
20
0
15
0
25
5
0
25
20
20
2
0
20
15
0
55
30
20
5
0
55
35
25
15
3
7C133-55
7C143-55
Min.
Max.
25
55
40
40
2
0
35
20
0
20
0
25
20
20
20
50
35
Note 16
20
0
35
30
25
20
60
45
Note 16
50
40
35
30
80
55
Note 16
5
5
5
0
20
0
25
0
30
50
35
60
45
80
55
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
9. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
IOL/IOH, and 30-pF load capacitance.
10. AC Test Conditions use VOH = 1.6V and VOL = 1.4V.
11. At any given temperature and voltage condition for any given device, tLZCE is less than tHZCE and tLZOE is less than tHZOE.
12. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tested with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
13. This parameter is guaranteed but not tested.
14. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal
can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
15. Port-to-port delay through RAM cells from writing port to reading port. Refer to timing waveform of “Read with BUSY, Master: CY7C133.”
16. tBDD is a calculated parameter and is greater of 0,tWDD–tWP (actual) or tDDD–tDW (actual).
17. To ensure that the earlier of the two ports wins.
18. To ensure that write cycle is inhibited during contention.
19. To ensure that a write cycle is completed after contention.
20. Port-to-port delay through RAM cells from writing port to reading port. Refer to timing waveform of “Read with Port-to-port Delay.”
Document #: 38-06036 Rev. *B
Page 7 of 13
CY7C133
CY7C143
Switching Waveforms
Read Cycle No.1 [21, 22]
Either Port Address Access
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 [21, 23]
Either Port CE/OE Access
CE
tHZCE
tACE
OE
tLZOE
tHZOE
tDOE
tLZCE
DATA VALID
DATA OUT
tPU
tPD
ICC
ISB
Read Cycle No. 3 [22]
Read with BUSY (for master CY7C133)
tRC
ADDRESS R
ADDRESS MATCH
tPWE
R/WR
tHD
DINR
VALID
ADDRESS MATCH
ADDRESS L
tPS
tBHA
BUSYL
tBLA
tBDD
DOUTL
VALID
tWDD
tDDD
Note:
21. R/W is HIGH for read cycle.
22. Device is continuously selected, CE = VIL and OE = VIL.
23. Address valid prior to or coincidence with CE transition LOW.
Document #: 38-06036 Rev. *B
Page 8 of 13
CY7C133
CY7C143
Switching Waveforms (continued)
Timing Waveform of Read with Port-to-port Delay No. 4 (for slave CY7C143) [24, 25, 26]
tWC
ADDRESSR
MATCH
tWP
R/WR
tDH
tDW
VALID
DINR
MATCH
ADDRESSL
tWDD
DOUTL
VALID
tDDD
Write Cycle No. 1 (OE Three-States Data I/Os - Either Port) [17, 27]
Either Port
tWC
ADDRESS
tSCE
CE
tSA
tAW
tPWE
tHA
R/W
tSD
DATAIN
tHD
DATA VALID
OE
tHZOE
HIGH IMPEDANCE
DOUT
Notes:
24. Assume BUSY input at VIH for the writing port and at VIL for the reading port.l
25. Write cycle parameters should be adhered to in order to ensure proper writing.
26. Device is continuously enabled for both ports.
27. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high
impedance and for data to be placed on the bus for the required tSD.
Document #: 38-06036 Rev. *B
Page 9 of 13
CY7C133
CY7C143
Switching Waveforms (continued)
Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port) [23, 28]
Either Port
tWC
ADDRESS
tSCE
tHA
CE
tAW
tSA
tPWE
R/W
tSD
DATAIN
tHD
DATA VALID
tLZWE
tHZWE
HIGH IMPEDANCE
DATAOUT
Busy Timing Diagram No. 1 (CE Arbitration)
CEL Valid First:
ADDRESS L,R
ADDRESS MATCH
CEL
tPS
CER
tBLC
tBHC
BUSYR
CER Valid First:
ADDRESS L,R
ADDRESS MATCH
CER
tPS
CEL
tBLC
tBHC
BUSYL
Note:
28. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Document #: 38-06036 Rev. *B
Page 10 of 13
CY7C133
CY7C143
Switching Waveforms (continued)
Busy Timing Diagram No. 2 (Address Arbitration)
Left Address Valid First:
tRC or tWC
ADDRESS MATCH
ADDRESSL
ADDRESS MISMATCH
tPS
ADDRESSR
tBLA
tBHA
BUSYR
Right Address Valid First:
tRC or tWC
ADDRESS MATCH
ADDRESSR
ADDRESS MISMATCH
tPS
ADDRESS L
tBLA
tBHA
BUSY L
Busy Timing Diagram No. 3
Write with BUSY (For Slave CY7C143)
CE
tPWE
R/W
tWB
tWH
BUSY
Document #: 38-06036 Rev. *B
Page 11 of 13
CY7C133
CY7C143
Ordering Information
2K x 16 Master Dual-Port SRAM
Speed
(ns)
25
35
55
Ordering Code
Package
Name
Operating
Range
Package Type
CY7C133-25JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7C133-25JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
CY7C133-35JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7C133-35JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
CY7C133-55JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
Package Diagram
68-Lead Plastic Leaded Chip Carrier J81
51-85005-*A
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-06036 Rev. *B
Page 12 of 13
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C133
CY7C143
Document History Page
Document Title: CY7C133/CY7C143 2K x 16 Dual-Port Static RAM
Document Number: 38-06036
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110178
09/22/01
SZV
Change from Spec number: 38-00414 to 38-06036
*A
127954
08/27/03
FSG
Logic Block Diagram: fixed busy I/O flag on devices (typo)
Removed obsolete parts from ordering information table:
–CY7C133-55JI
–CY7C143-25JC
–CY7C143-25JI
–CY7C143-35JC
–CY7C143-35JI
–CY7C143-55JC
–CY7C143-55JI
*B
236761
See ECN
YDT
Removed cross information from features section
Document #: 38-06036 Rev. *B
Page 13 of 13