CY7C1302CV25 PREMILINARY 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth — 2.5 ns clock-to-Valid access time • 2-word burst on all accesses • Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 333 MHz) @ 167 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two output clocks (C and C) account for clock skew and flight time mismatching • Single multiplexed address input bus latches address inputs for both Read and Write ports • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • 2.5V core power supply with HSTL Inputs and Outputs • 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball (11 x 15 matrix) • Variable drive HSTL output buffers • Expanded HSTL output voltage (1.4V–1.9V) The CY7C1302CV25 is a 2.5V Synchronous Pipelined SRAM equipped with QDR™ architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated data outputs to support Read operations and the Write Port has dedicated data inputs to support Write operations. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of K clock. QDR has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Accesses to the CY7C1302CV25 Read and Write ports are completely independent of one another. All accesses are initiated synchronously on the rising edge of the positive input clock (K). In order to maximize data throughput, both Read and Write ports are equipped with DDR interfaces. Therefore, data can be transferred into the device on every rising edge of both input clocks (K and K) and out of the device on every rising edge of the output clock (C and C, or K and K in a single clock domain) thereby maximizing performance while simplifying system design. Each address location is associated with two 18-bit words that burst sequentially into or out of the device. Depth expansion is accomplished with a Port Select input for each port. Each Port Select allows each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. • JTAG Interface Configurations CY7C1302CV25 – 512K x 18 Logic Block Diagram (CY7C1302CV25) Write Data Reg Address Register Write Add. Decode A(17:0) 18 18 K K CLK Gen. Write Data Reg Read Add. Decode D[17:0] 256Kx18 256Kx18 Memory Memory Array Array Address Register Control Logic Read Data Reg. 36 Vref WPS BWS0 18 Reg. Control Logic 18 Cypress Semiconductor Corporation Document #: 38-05491 Rev. *A RPS C C Reg. 18 Reg. BWS1 18 • 3901 North First Street • A(17:0) 18 San Jose, CA 95134 18 Q[17:0] • 408-943-2600 Revised June 1, 2004 CY7C1302CV25 PREMILINARY Selection Guide CY7C1302CV25 -167 CY7C1302CV25 -133 CY7C1302CV25 -100 Unit Maximum Operating Frequency 167 133 100 MHz Maximum Operating Current 750 650 550 mA Pin Configuration–CY7C1302CV25 (Top View) 1 2 3 4 5 6 7 8 WPS BWS1 K NC RPS D9 A NC K BWS0 A NC NC Q8 D10 VSS A A A VSS NC Q7 D8 VSS VSS NC NC D7 VSS VDDQ NC D6 Q6 A NC Gnd/144M NC/36M B NC Q9 C NC NC D NC D11 Q10 VSS VSS VSS E NC NC Q11 VDDQ VSS VSS 9 10 11 NC/18M Gnd/72M NC F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H NC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4 K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS A A A VSS NC NC D1 P NC NC Q17 A A C A A NC D0 Q0 R TDO TCK A A A C A A A TMS TDI Pin Definitions Name I/O Description D[17:0] InputSynchronous Data input signals, sampled on the rising edge of K and K clocks during valid Write operations. WPS InputSynchronous Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D[17:0] to be ignored. BWS0, BWS1 InputSynchronous Byte Write Select 0, 1, active LOW. Sampled on the rising edge of the K and K clocks during Write operations. Used to select which byte is written into the device during the current portion of the Write operations. Bytes not written remain unaltered. BWS0 controls D[8:0] and BWS1 controls D[17:9]. All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device. A InputSynchronous Address Inputs. Sampled on the rising edge of the K (read address) and K (write address) clocks for active Read and Write operations. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 512K x 18 (2 arrays each of 256K x 18). These inputs are ignored when the appropriate port is deselected. Q[17:0] OutputsSynchronous Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode. When the Read port is deselected, Q[17:0] are automatically three-stated. RPS InputSynchronous Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K). When active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically three-stated following the next rising edge of the C clock. Each read access consists of a burst of two sequential transfers. InputClock Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. C Document #: 38-05491 Rev. *A Page 2 of 18 PREMILINARY CY7C1302CV25 Pin Definitions (continued) I/O Description C Name Input-Clock Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board cack to the controller. See application example for further details. K Input-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[17:0] when in single clock mode. All accesses are initiated on the rising edge of K. K Input-Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[17:0] when in single clock mode. Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[17:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDD, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. ZQ TDO Output TCK Input TCK pin for JTAG. TDI Input TDI pin for JTAG. TMS Input TMS pin for JTAG. NC/18M N/A Address expansion for 18M. This is not connected to the die and so can be tied to any voltage level. NC/36M N/A Address expansion for 36M. This is not connected to the die and so can be tied to any voltage level. GND/72M Input Address expansion for 72M. This must be tied LOW. GND/144M Input Address expansion for 144M. This must be tied LOW. N/A Not connected to the die. Can be tied to any voltage level. NC VREF VDD VSS VDDQ InputReference TDO for JTAG. Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points. Power Supply Power supply inputs to the core of the device. Ground Ground for the device. Power Supply Power supply inputs for the outputs of the device. Introduction Functional Overview The CY7C1302CV25 is a synchronous pipelined Burst SRAM equipped with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write port is dedicated to Write operations. Data flows into the SRAM through the Write port and out through the Read port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate Read and Write ports, the QDR-I completely eliminates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. Accesses for both ports are initiated on the rising edge of the Positive Input Clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the output clocks (C and C, or K and K when in single clock mode). All synchronous data inputs (D[17:0]) pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[17:0]) pass through output registers controlled by the rising edge of the output clocks (C and C, or K and K when in single clock mode). Document #: 38-05491 Rev. *A All synchronous control (RPS, WPS, BWS[1:0]) inputs pass through input registers controlled by the rising edge of input clocks (K and K). Read Operations The CY7C1302CV25 is organized internally as 2 arrays of 256K x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the positive input clock (K). The address is latched on the rising edge of the K clock. Following the next K clock rise the corresponding lower order 18-bit word of data is driven onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C the higher order data word is driven onto the Q[17:0]. The requested data will be valid 2.5 ns from the rising edge of the output clock (C and C, or K and K when in single clock mode, 167-MHz device). Synchronous internal circuitry will automatically three-state the outputs following the next rising edge of the positive output clock (C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory. Page 3 of 18 PREMILINARY Write Operations Write operations are initiated by asserting WPS active at the rising edge of the positive input clock (K). On the same K clock rise the data presented to D[17:0] is latched into the lower 18-bit Write Data register provided BWS[1:0] are both asserted active. On the subsequent rising edge of the negative input clock (K), the address is latched and the information presented to D[17:0] is stored into the Write Data register provided BWS[1:0] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. When deselected, the Write port will ignore all inputs after the pending Write operations have been completed. Byte Write Operations Byte Write operations are supported by the CY7C1302CV25. A Write operation is initiated as described in the Write Operation section above. The bytes that are written are determined by BWS0 and BWS1 which are sampled with each set of 18-bit data word. Asserting the appropriate Byte Write Select input during the data portion of a write will allow the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation. Single Clock Mode The CY7C1302CV25 can be used with a single clock mode. In this mode the device will recognize only the pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at CY7C1302CV25 power-up.This function is a strap option and not alterable during device operation. Concurrent Transactions The Read and Write ports on the CY7C1302CV25 operate completely independently of one another. Since each port latches the address inputs on different clock edges, the user can Read or Write to any location, regardless of the transaction on the other port. Also, reads and writes can be started in the same clock cycle. If the ports access the same location at the same time, the SRAM will deliver the most recent information associated with the specified address location. This includes forwarding data from a Write cycle that was initiated on the previous K clock rise. Depth Expansion The CY7C1302CV25 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). Each port select input can deselect the specified port. Deselecting a port will not affect the other port. All pending transactions (Read and Write) will be completed prior to the device being deselected. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM, The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ =1.5V. The output impedance is adjusted every 1024 cycles to account for drifts in supply voltage and temperature. Application Example[1] Note: 1. The above application shows 4 QDR-I being used. Document #: 38-05491 Rev. *A Page 4 of 18 CY7C1302CV25 PREMILINARY Truth Table[2, 3, 4, 5, 6, 7] Operation K RPS WPS Write Cycle: Load address on the rising edge of K clock; input write data on K and K rising edges. L-H X L D(A+0)at K(t) ↑ D(A+1) at K(t) ↑ Read Cycle: Load address on the rising edge of K clock; wait one cycle; read data on 2 consecutive C and C rising edges. L-H L X Q(A+0) at C(t+1)↑ Q(A+1) at C(t+1) ↑ NOP: No Operation L-H H H D=X Q = High-Z D=X Q = High-Z Stopped X X Previous State Previous State Standby: Clock Stopped DQ DQ Write Cycle Descriptions[2,8] BWS0 BWS1 K K Comments L L L-H – During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device. L L – L-H During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device. L H L-H – During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[17:9] remains unaltered. L H – L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[17:9] remains unaltered. H L L-H – During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] remains unaltered. H L – L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] remains unaltered. H H L-H – No data is written into the device during this portion of a Write operation. H H – L-H No data is written into the device during this portion of a Write operation. Notes: 2. X = Don't Care, H = Logic HIGH, L = Logic LOW, ↑ represents rising edge. 3. Device will power-up deselected and the outputs in a three-state condition. 4. “A” represents address location latched by the devices when transaction was initiated. A+0, A+1 represent the addresses sequence in the burst. 5. “t” represents the cycle at which a Read/Write operation is started. t+1 is the first clock cycle succeeding the “t” clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode. 7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0, BWS1 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved. Document #: 38-05491 Rev. *A Page 5 of 18 CY7C1302CV25 PREMILINARY Maximum Ratings Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired.) Storage Temperature .................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V DC Applied to Outputs in High-Z......... –0.5V to VDDQ + 0.5V Latch-up Current..................................................... >200 mA Operating Range Range Ambient Temperature (TA) VDD[10] VDDQ[10] 0°C to +70°C 2.5 ± 0.1V 1.4V to 1.9V Com’l DC Input Voltage[9 .............................. –0.5V to VDDQ + 0.5V Current into Outputs (LOW) .........................................20 mA Electrical Characteristics Over the Operating Range[11] DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Typ. Max. Unit VDD Power Supply Voltage 2.4 2.5 2.6 V VDDQ I/O Supply Voltage 1.4 1.5 1.9 V VOH Output HIGH Voltage Note 12 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V VOL Output LOW Voltage Note 13 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V VDDQ – 0.2 VDDQ V VSS 0.2 V VREF + 0.1 VDDQ + 0.3 V –0.3 VREF –0.1 V –0.3 VDDQ+0.3 V –5 5 µA VOH(LOW) Output HIGH Voltage IOH = –0.1 mA, Nominal Impedance VOL(LOW) Output LOW Voltage IOL = 0.1 mA, Nominal Impedance VIH Input HIGH Voltage[9] VIL Input LOW Voltage[9, 14] VIN Clock Input Voltage IX Input Load Current GND ≤ VI ≤ VDDQ IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled VREF Input Reference Voltage[15] Typical value = 0.75V IDD VDD Operating Supply VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC ISB1 Automatic Power-Down Current 5 µA 0.95 V 167 MHz 750 mA 133 MHz 650 mA 100 MHz 550 mA 167 MHz Max. VDD, Both Ports Deselected, VIN ≥ VIH or 133 MHz VIN ≤ VIL, f = 100 MHz fMAX = 1/tCYC, Inputs Static 470 mA 450 mA 430 mA Max. Unit –5 0.68 0.75 AC Input Requirements Over the Operating Range Parameter Description Test Conditions Min. Typ. VIH Input High (Logic 1) Voltage VREF + 0.2 – V VIL Input Low (Logic 0) Voltage – VREF – 0.2 V Notes: 9. Overshoot: VIH(AC) < VDDQ +0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > –1.5V (Pulse width less than tCYC/2). 10. Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 11. All voltage referenced to Ground. 12. Output are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω. 13. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω. 14. This spec is for all inputs except C and C Clock. For C and C Clock, VIL(Max.) = VREF – 0.2V. 15. VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54VDDQ, whichever is smaller. Document #: 38-05491 Rev. *A Page 6 of 18 CY7C1302CV25 PREMILINARY Thermal Resistance[16] Parameter Description Test Conditions ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) 165 FBGA Package Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 16.7 °C/W 2.5 °C/W Capacitance[16] Parameter Description CIN Input Capacitance CCLK Clock Input Capacitance CO Output Capacitance Test Conditions Max. TA = 25°C, f = 1 MHz, VDD = 2.5V. VDDQ = 1.5V Unit 5 pF 6 pF 7 pF AC Test Loads and Waveforms VDDQ/2 VDDQ/2 VREF VREF OUTPUT Z0 = 50Ω Device Under Test ZQ RQ = 250Ω (a) RL = 50Ω VREF = 0.75V VDDQ/2 R = 50Ω ALL INPUT PULSES 1.25V 0.75V OUTPUT Device Under Test ZQ INCLUDING JIG AND SCOPE 5 pF [17] 0.25V RQ = 250Ω (b) Switching Characteristics Over the Operating Range [17] Cypress Parameter -167 Consortium Parameter tPower[18] -133 Max. Min. Max. -100 Description Min. Min. Max. Unit VCC (typical) to the First Access Read or Write 10 10 10 µs Cycle Time tCYC tKHKH K Clock and C Clock Cycle Time 6.0 7.5 10.0 ns tKH tKHKL Input Clock (K/K and C/C) HIGH 2.4 3.2 3.5 ns tKL tKLKH Input Clock (K/K and C/C) LOW 2.4 tKHKH tKHKH K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise (rising edge to rising edge) 2.7 3.3 3.4 4.1 4.4 5.4 ns tKHCH tKHCH K/K Clock Rise to C/C Clock Rise (rising edge to rising edge) 0.0 2.0 0.0 2.5 0.0 3.0 ns 3.2 3.5 ns Set-up Times tSA tSA Address Set-up to Clock (K and K) Rise 0.7 0.8 1.0 ns tSC tSC Control Set-up to Clock (K and K) Rise (RPS, WPS, BWS0, BWS1) 0.7 0.8 1.0 ns tSD tSD D[17:0] Set-up to Clock (K and K) Rise 0.7 0.8 1.0 ns Notes: 16. Tested initially and after any design or process change that may affect these parameters. 17. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,Vref = 0.75V, RQ = 250W, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC test loads. 18. This part has a voltage regulator that steps down the voltage internally; tPower is the time power needs to be supplied above VDD minimum initially before a read or write operation can be initiated. Document #: 38-05491 Rev. *A Page 7 of 18 CY7C1302CV25 PREMILINARY Switching Characteristics Over the Operating Range (continued)[17] Cypress Parameter -167 Consortium Parameter Description Min. -133 Max. Min. Max. -100 Min. Max. Unit Hold Times tHA tHA Address Hold after Clock (K and K) Rise 0.7 0.8 1.0 ns tHC tHC Control Signals Hold after Clock (K and K) Rise (RPS, WPS, BWS0, BWS1) 0.7 0.8 1.0 ns tHD tHD D[17:0] Hold after Clock (K and K) Rise 0.7 0.8 1.0 ns Output Times tCO tCHQV C/C Clock Rise (or K/K in single clock mode) to Data Valid tDOH tCHQX Data Output Hold after Output C/C Clock Rise (Active to Active) tCHZ tCHZ Clock (C and C) Rise to High-Z (Active to High-Z)[19, 20] tCLZ tCLZ Clock (C and C) Rise to Low-Z[19, 20] 2.5 1.2 3.0 1.2 2.5 1.2 3.0 1.2 ns 3.0 1.2 ns 3.0 1.2 ns ns Notes: 19. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage. 20. At any given voltage and temperature tCHZ is less than tCLZ and, tCHZ less than tCO. Document #: 38-05491 Rev. *A Page 8 of 18 CY7C1302CV25 PREMILINARY Switching Waveforms[21, 22, 23] READ WRITE READ WRITE READ WRITE NOP WRITE NOP 1 2 3 4 5 6 7 8 9 10 K tKH tKL tKHKH tCYC K RPS tSC tHC WPS A A0 D D10 A1 A2 tSA tHA tSA tHA D11 D30 A3 A4 A5 D31 D50 D51 Q Q00 tKHCH tKHCH tCO Q01 tDOH tCLZ D60 tSD tHD tSD A6 Q20 D61 tHD Q21 Q40 Q41 tCHZ tDOH tCO C tKH tKL tKHKH tCYC C DON’T CARE UNDEFINED Notes: 21. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0 i.e., A0+1. 22. Outputs are disabled (High-Z) one clock cycle after a NOP. 23. In this example, if address A2=A1 then data Q20=D10 and Q21=D11. Write data is forwarded immediately as read results.This note applies to the whole diagram. Document #: 38-05491 Rev. *A Page 9 of 18 PREMILINARY IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-1900. The TAP operates using JEDEC standard 2.5V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port—Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data-Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Instruction codes). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the Document #: 38-05491 Rev. *A CY7C1302CV25 TDI and TDO pins as shown in TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction Page 10 of 18 PREMILINARY is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the “Update IR” state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. CY7C1302CV25 The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. EXTEST Output Bus Three-state IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a three-state mode. The boundary scan register has a special bit located at bit #47. When this scan cell, called the “extest output bus three-state”, is latched into the preload register during the “Update-DR” state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR”, the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Document #: 38-05491 Rev. *A Page 11 of 18 CY7C1302CV25 PREMILINARY TAP Controller State Diagram[24] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 1 SELECT DR-SCAN 0 1 0 1 CAPTURE-DR CAPTURE-DR 0 0 0 SHIFT-DR 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 0 PAUSE-IR 1 1 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 SHIFT-IR 1 0 1 SELECT IR-SCAN 0 UPDATE-IR 1 0 Note: 24. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05491 Rev. *A Page 12 of 18 CY7C1302CV25 PREMILINARY TAP Controller Block Diagram 0 Bypass Register Selection Circuitry TDI 2 1 0 1 0 Selection Circuitry Instruction Register 31 30 29 . . 2 TDO Identification Register 106 . . . . 2 1 0 Boundary Scan Register TCK TMS TAP Controller TAP Electrical Characteristics Over the Operating Range [11, 9, 25] Parameter Description Test Conditions Min. IOH = −2.0 mA 1.7 Output HIGH Voltage IOH = −100 µA 2.1 Output LOW Voltage IOL = 2.0 mA VOL2 Output LOW Voltage IOL = 100 µA VIH Input HIGH Voltage VIL Input LOW Voltage IX Input and Output Load Current VOH1 Output HIGH Voltage VOH2 VOL1 GND ≤ VI ≤ VDDQ TAP AC Switching Characteristics Over the Operating Range Parameter Description Max. Unit V V 0.7 V 0.2 V 1.7 VDD + 0.3 V –0.3 0.7 V –5 5 µA [26, 27] Min. Max. Unit 10 MHz tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH 40 ns tTL TCK Clock LOW 40 ns tTMSS TMS Set-up to TCK Clock Rise 10 ns tTDIS TDI Set-up to TCK Clock Rise 10 ns tCS Capture Set-up to TCK Rise 10 ns tTMSH TMS Hold after TCK Clock Rise 10 ns tTDIH TDI Hold after Clock Rise 10 ns tCH Capture Hold after Clock Rise 10 ns 100 ns Set-up Times Hold Times Notes: 25. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table. 26. TCS and TCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 27. Test conditions are specified using the load in TAP AC test conditions. Tr/Tf = 1 ns. Document #: 38-05491 Rev. *A Page 13 of 18 CY7C1302CV25 PREMILINARY TAP AC Switching Characteristics Over the Operating Range (continued) [26, 27] Parameter Description Min. Max. Unit Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 20 ns 0 ns TAP Timing and Test Conditions[27] 1.25V 50Ω ALL INPUT PULSES TDO 2.5V Z0 = 50Ω (a) 1.25V CL = 20 pF 0V GND tTH tTL Test Clock TCK tTCYC tTMSS tTMSH Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO tTDOX tTDOV Identification Register Definitions Value Instruction Field Revision Number (31:29) CY7C1302CV25 001 Cypress Device ID (28:12) 01011010010010110 Cypress JEDEC ID (11:1) 00000110100 ID Register Presence (0) 1 Document #: 38-05491 Rev. *A Description Version number. Defines the type of SRAM. Allows unique identification of SRAM vendor. Indicate the presence of an ID register. Page 14 of 18 CY7C1302CV25 PREMILINARY Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 107 Instruction Codes Instruction Code Description EXTEST 000 Captures the Input/Output ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Boundary Scan Order (continued) Boundary Scan Order Bump ID Bit # Bump ID 0 6R 23 9J 1 6P 24 9K 2 6N 25 10J 3 7P 26 11J 4 7N 27 11H 5 7R 28 10G 6 8R 29 9G 7 8P 30 11F 8 9R 31 11G 9 11P 32 9F 10 10P 33 10F 11 10N 34 11E 12 9P 35 10E 13 10M 36 10D 14 11N 37 9E 15 9M 38 10C 16 9N 39 11D 17 11L 40 9C 18 11M 41 9D 19 9L 42 11B 20 10L 43 11C 21 11K 44 9B 10K 45 10B 46 11A Bit # 22 Document #: 38-05491 Rev. *A Page 15 of 18 CY7C1302CV25 PREMILINARY Boundary Scan Order (continued) Boundary Scan Order (continued) Bit # Bump ID Bit # Bump ID 47 Internal 91 1M 48 9A 92 1L 49 8B 93 3N 50 7C 94 3M 51 6C 95 1N 52 8A 96 2M 53 7A 97 3P 54 7B 98 2N 55 6B 99 2P 56 6A 100 1P 57 5B 101 3R 58 5A 102 4R 59 4A 103 4P 60 5C 104 5P 61 4B 105 5N 62 3A 106 5R 63 1H 64 1A 65 2B 66 3B 67 1C 68 1B 69 3D 70 3C 71 1D 72 2C 73 3E 74 2D 75 2E 76 1E 77 2F 78 3F 79 1G 80 1F 81 3G 82 2G 83 1J 84 2J 85 3K 86 3J 87 2K 88 1K 89 2L 90 3L Document #: 38-05491 Rev. *A Page 16 of 18 PREMILINARY CY7C1302CV25 Ordering Information Speed (MHz) 167 Ordering Code CY7C1302CV25-167BZC Package Name Operating Range Package Type BB165D 13 x 15 x 1.4 mm FBGA 133 CY7C1302CV25-133BZC BB165D 13 x 15 x 1.4 mm FBGA 100 CY7C1302CV25-100BZC BB165D 13 x 15 x 1.4 mm FBGA Commercial Package Diagram 165 FBGA 13 x 15 x 1.40 mm BB165D 51-85180-** 51-85180-** Quad Data Rate SRAM and QDR SRAM comprise a new family of products developed by Cypress, IDT, NEC and Samsung. All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-05491 Rev. *A Page 17 of 18 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1302CV25 PREMILINARY Document History Page Document Title:CY7C1302CV25 9-Mb Burst of 2 Pipelined SRAM with QDR™ Architecture Document Number: 38-05491 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 208401 see ECN DIM New Data Sheet *A 230396 see ECN VBL Upload datasheet to the internet Document #: 38-05491 Rev. *A Page 18 of 18