CYPRESS CY8CMBR2044


CY8CMBR2044
Capacitive Button Controllers
Capacitive Button Controllers
Features
Overview
■
Easiest to use capacitive button controller
❐ Hardware configurable 4-button solution
❐ No software tools or programming required
❐ General purpose outputs (GPO) support direct LED drive
■
Robust noise performance
❐ High sensitivity, low noise capacitive sensing algorithm
❐ Strong immunity to radio frequency (RF) and alternating 
current (AC) noise
❐ Low radiated noise emission
■
SmartSense™ auto tuning
❐ No manual tuning required (reduces time to market)
®
❐ All CapSense parameters are automatically set in runtime
❐ Ensures signal to noise ratio (SNR) of 5:1 or greater
❐ Supports wide range of input capacitance (5 pF to 40 pF)
■
Advanced features
❐ Toggle feature on GPO
❐ Flanking sensor suppression (FSS) provides robust sensing
even with closely spaced sensors
❐ Delay Off feature (configurable LED run time)
❐ Easier production line testing
• Serial data out for debug
• Failure mode analysis of CapSense buttons
■
Wide operating range
❐ 1.71 V to 5.5 V ideal for unregulated battery applications
■
Low power consumption
[1]
❐ Supply current in run mode as low as 15 µA for every button
❐ Deep sleep current: 100 nA
■
Industrial temperature range: –40 °C to + 85 °C
■
16-pad quad flat no leads (QFN) package (3 mm x 3 mm x
0.6 mm)
The CY8CMBR2044 incorporates several innovative features to
save time, money, and can quickly enable a capacitive touch
sensing UI in your next design. It does not require any software
tools or coding because system configuration is done using
hardware. These features enable a broader audience of
designers to implement capacitive buttons without learning new
tool sets and developing code. In addition, this device is enabled
with Cypress’s revolutionary SmartSense auto tuning algorithm.
SmartSense ends the need to manually tune the UI during development as well as the required retuning during production ramp.
This saves valuable engineering time, test time, production yield
loss, and speeds the time to volume.
The CY8CMBR2044 CapSense controller supports up to four
capacitive sensing buttons and four GPOs. The GPO is an active
low output controlled directly by the CapSense input making it
ideal for a wide variety of consumer, industrial, and medical applications. The wide operating range of 1.71 V to 5.5 V enables
unregulated battery operation, further saving component cost.
This device supports ultra low power consumption in run mode
as well as deep sleep modes to enhance battery life. In addition
to this, the device also supports many advanced features which
enhance the robustness and user interface of the end solution.
Some of the key advanced features include FSS, which provides
robust sensing even with closely spaced sensors. This is a
critical requirement in small form factor applications. Another key
feature is failure mode analysis that helps ease production line
testing and reduces manufacturing costs.
Note
1. Power consumption calculated with 1.7% touch time, 500 ms scan rate, and CP of each sensor < 19 pF.
Cypress Semiconductor Corporation
Document Number: 001-57451 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 29, 2010
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CY8CMBR2044
Contents
Capacitive Button Controllers ...........................................1
Features ...............................................................................1
Overview ..............................................................................1
Pinout ..................................................................................3
Typical Circuits ...................................................................4
Schematic 1: 4-Buttons, 4-LEDs 
with Auto Reset Enabled ......................................................4
Schematic 2: 3-Buttons, 3-LEDs, 2-Outputs to Master, 
and Advanced Features Enabled .........................................5
Device Features ..................................................................6
CapSense Buttons ........................................................6
SmartSense Auto Tuning ..............................................6
General Purpose Outputs ..............................................6
Hardware Configuration ................................................6
Sensor Auto Reset ........................................................6
Toggle ...........................................................................7
Delay Off .......................................................................7
Flanking Sensor Suppression .......................................9
Failure Mode Analysis ...................................................9
Debug Data .................................................................10
Device Operating Modes ..................................................12
Low Power Sleep Mode ..............................................12
Deep Sleep Mode ........................................................15
Additional Components to Enable Advanced Features 15
Response Time .................................................................15
Document Number: 001-57451 Rev. *C
Layout Guidelines and Best Practices ...........................16
CapSense Button Shapes ...........................................17
Button Layout Design ..................................................17
Recommended Via Hole Placement ...........................17
Example PCB Layout Design with 
Four CapSense Buttons and Four LEDs ............................18
Electrical Specifications ..................................................19
Absolute Maximum Ratings .........................................19
Operating Temperature ...............................................19
DC Electrical Characteristics .......................................19
AC Electrical Specifications .........................................21
CapSense Specifications ............................................21
Ordering Information ........................................................22
Ordering Code Definitions ...........................................22
Package Information ........................................................23
Thermal Impedances by Package ...............................23
Solder Reflow Peak Temperature ...............................23
Package Diagram ........................................................23
Document Conventions ...................................................24
Acronyms Used ...........................................................24
Units of Measure .........................................................24
Document History Page ...................................................25
Sales, Solutions, and Legal Information ........................26
Worldwide Sales and Design Support .........................26
Products ......................................................................26
PSoC Solutions ...........................................................26
Page 2 of 26
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CY8CMBR2044
Pinout
Table 1. Pin Diagram and Definitions – CY8CMBR2044
If Unused
GPO1
DO
GPO activated by CS1
Leave open
2
GPO0
DO
GPO activated by CS0
Leave open
3
Toggle/
FSS
AI
Controls FSS and toggle. For
Ground
details refer to Table 5 on page 7
4
Delay
AI
Controls delay off time. For
Ground
details refer to Table 6 on page 8
5
CS0
AIO
CapSense input, controls GPO0 Ground
or serial debug data out
6
CS1
AIO
CapSense input, controls GPO1 Ground
or serial debug data out
7
VSS
P
Ground
8
CS2
AIO
CapSense input, controls GPO2 Ground
or serial debug data out
9
ARST
AIDO Controls auto reset delay. For
Leave open
details on auto reset delay, refer
to Table 4 on page 6
10
CS3
AIO
CapSense input, controls GPO3 Ground
or serial debug data out
11
XRES
DI
Device reset, active high, with
internal pull down
12
ScanRate/ AI
Sleep
Controls scan rate and deep
Ground
sleep. For details refer to Table 9
on page 13
13
VDD
P
Power
14
GPO3
DO
GPO activated by CS3
15
CMOD
AI
External integrating capacitor,
connect a 2.2 nF (±5%) to
ground
16
GPO2
DO
GPO activated by CS2
Document Number: 001-57451 Rev. *C
GPO1
GPO0
Toggle/FSS
Delay
14
13
1
GPO2
CMOD
GPO3
VDD
Description
16
15
Type
1
12
QFN
2
11
(Top View)
3
10
4
9
5
6
7
8
Label
ScanRate/Sleep
XRES
CS3
ARST
CS0
CS1
Vss
CS2
Pin
Leave open
Leave open
Leave open
Page 3 of 26
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CY8CMBR2044
Typical Circuits
Schematic 1: 4-Buttons, 4-LEDs with Auto Reset Enabled
In the above schematic, the device is configured to support:
■
Four CapSense buttons driving four LEDs
■
Sensor auto reset (ARST) pin pulled down with a 5 Kresistor to set sensor auto reset time to 20 seconds
■
Connect a 5.6 Kresistor on R9 or R12 to enable the serial debug data out feature
Document Number: 001-57451 Rev. *C
Page 4 of 26
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CY8CMBR2044
Schematic 2: 3-Buttons, 3-LEDs, 2-Outputs to Master, and Advanced Features Enabled
In the above schematic the device is configured to support:
■
Three CapSense buttons driving three outputs
■
Three LEDs driven by GPO0, GPO1, and GPO2
■
CS3 is disabled (grounded); therefore, GPO3 is left floating
■
FSS enabled, toggle disabled
■
Delay off – 1 second
■
Scan rate – 30 ms
■
Sensor auto reset – 20 seconds
■
Connect a 5.6 Kon resistor R11 to enable serial debug data out feature
Document Number: 001-57451 Rev. *C
Page 5 of 26
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CY8CMBR2044
Device Features
General Purpose Outputs
Table 2. Device Feature List
■
The GPOx is driven by CSx
■
Active low output – supports sinking configuration
■
If CSx is disabled (grounded), then GPOx must be left floating
■
A 5 ms pulse is triggered on the GPOx if the CSx fails the power
on self test (POST)
Benefits/ End Application
Problem Solved
Feature
Four GPOs
Driving LED, mechanical button
replacement
Flanking sensor
suppression
Provides more discrimination
between closely spaced sensors
Hardware Configuration
Toggle
Mechanical button replacement
■
Sensor auto reset (ARST)
Prevents stuck sensor, i.e. metal
object placed close to sensor
Advanced features are configured in hardware using external
resistors
Delay Off
Provides better feedback based on
button press
■
The resistances on hardware configurable pins are determined
once at power on
Failure mode analysis
Support for production testing and
debugging
Serial debug data
Support for production testing and
validating design
Sleep and deep sleep
Low power consumption
CapSense Buttons
■
Device supports up to four CapSense buttons
■
Ground the CSx pin to disable CapSense input
■
2.2 nF capacitor must be connected on the CMOD pin for
proper CapSense operation
SmartSense Auto Tuning
Sensor Auto Reset
■
The sensor auto reset time is controlled by the hardware
configuration on the ARST pin. Refer to Table 4 for details
■
This feature decides the maximum time the GPOx is driven
when CSx is continuously pressed
■
After the sensor auto reset has been triggered, the CSx hold
time of that sensor after the button has been released is given
in Table 3. Scan rate is determined by the hardware
configuration as shown in Table 9 on page 13
Table 3. Sensor Hold Time After Auto Reset
Sensor Press Time after
Sensor Auto Reset
Sensor Hold Time (ms)
< 2 sec
220
> 2 sec
ScanRate + 200
■
Device supports auto tuning of CapSense parameters
■
No manual tuning required; all parameters are set by the device
■
Compensates printed circuit board (PCB), device process
variations, and PCB vendor changes
Table 4. ARST Pin Hardware Configuration
■
The parasitic capacitance (CP) of each button must be less than
40 pF for proper CapSense operation
Pin connected to ground
5
Resistor of 5 K (10%) ohms
connected to ground
20
Pin connected to VDD or left
floating
No limit
Hardware Configuration
Sensor Max ON Time (sec)
Figure 1. Example of Sensor Auto Reset on GP0
Document Number: 001-57451 Rev. *C
Page 6 of 26
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CY8CMBR2044
Toggle
■
The Toggle feature is controlled by the hardware configuration on Toggle/FSS pin. For details, refer to Table 5
■
The state of GPx changes on every rising edge of CSx CapSense status
■
When Toggle is enabled, Delay Off is disabled
Figure 2. Example of Toggle Feature on GP0
Table 5. Toggle/FSS Hardware Pin Configuration
Sl. No.
Toggle/FSS Pin
Hardware Configuration
Toggle Enabled
FSS Enabled
1
Pin connected to ground or left floating
No
No
2
1.5 k (5%) resistor to ground
Yes
No
3
5.1 k (5%) resistor to ground
No
Yes
4
Pin connected to VDD
Yes
Yes
Delay Off
■
Delay off time is controlled by the hardware configuration on the delay pin. For details, see Table 6 on page 8
■
To enable delay off with Delay ‘D’ (multiple of 20 ms), a resistor ‘R’ should be connected between the delay pin and ground where
R = (Dx4) + 40 s
■
Delay off value specifies the duration for which the GPOx is driven low after the corresponding CapSense input CSx is released.
See Figure 3 on page 8
■
When a button gets reset, delay off is not applied on the corresponding GPO
■
Delay off feature is applicable to only one GPO at any point of time. In Figure 3 on page 8, GPO0 goes high prematurely (prior to
delay off time) because CS1 button is released. Therefore, the delay counter is reset. Now, GPO1 remains low for delay off time
after releasing CS1
■
Delay off feature is applicable to the GPO of the last button released
■
Delay off range: 0 ms to 2000 ms
Document Number: 001-57451 Rev. *C
Page 7 of 26
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CY8CMBR2044
Figure 3. Example Delay Off Timing Diagram on GP0 and GP1
Table 6. Delay Off Pin Hardware Configuration
Pin Configuration
Approximate Delay Off Time (in ms)
Grounded (default)
0
120 s (1%) to ground
20
200 s (1%) to ground
40
280 s (1%) to ground
60
.
.
.
.
7960 s (1%) to ground
1980
8040 s (1%) to ground
2000
> 8040 s (1%) to ground
2000
Pulled to VDD
2000
Floating
2000
Document Number: 001-57451 Rev. *C
Page 8 of 26
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CY8CMBR2044
Flanking Sensor Suppression
■
Provides discrimination between closely spaced sensors
■
At any point of time, only one sensor is reported as ON
■
The first sensor touched is reported as ON until it is released, even if other sensors are pressed
Figure 4. Sensor Status with Respect to Finger Touch when FSS is Enabled
Failure Mode Analysis
Sensor to Sensor Short
A built-in Power On Self Test (POST) mechanism detects the
following at power on reset (POR), which can be useful in
production testing.
Any Sensors that are shorted together is disabled and 5ms pulse
Sensor Shorted to Ground
If a sensor is disabled a 5 ms pulse is sent out on the corresponding GPO within 175 ms of power on.
is sent out on the GPOs of the shorted sensors within 175ms of
power on.
Figure 7. Sensor to Sensor Short
Figure 5. Sensor Shorted to Ground
Proper Value of CMOD
■
Recommended value of CMOD is 2 nF to 2.4 nF.
Sensor Shorted to VDD
■
If any sensor is shorted to VDD that sensor is disabled and a
5 ms pulse is sent out on the corresponding GPO within 175 ms
of power on.
If CMOD of < 1 nF or > 4 nF is connected, all sensors are
disabled and a 5 ms pulse is sent out on all the GPOs within
175 ms of power on.
Sensor CP > 40 pF
Figure 6. Sensor Shorted to VDD
Document Number: 001-57451 Rev. *C
If the parasitic capacitance (CP) of any sensor exceeds 40 pF
that sensor is disabled and a 5 ms pulse is sent out on the
corresponding GPO within 175 ms of power on.
Page 9 of 26
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CY8CMBR2044
Figure 8. Example Showing CS0 and CS1 Passing the POST and CS2 and CS3 are Failing
5 ms pulse
Max time to get 5 ms pulse is 175 ms after power up
In Figure 8 CS0 and CS1 are enabled; CS2 and CS3 are
disabled because the POST failed for these sensors. Therefore,
a 5 ms pulse is observed on GPO2 and GPO3.
■
Serial data is sent out with ~115,200 baud rate
■
Firmware revision, CapSense status, GPO status, raw count,
baseline, difference count, and parasitic capacitance of all
sensors are sent out
Debug Data
■
To enable this feature pull down any one of the CapSense pins
with a 5.6 k resistor to ground. Data is sent out on the same
CapSense pin
■
For designs having a maximum of three CapSense buttons,
Cypress recommends to take the debug data on a CapSense
button that is not used in design
■
If more than one CapSense pin is pulled down, debug data is
sent out only on one CapSense pin and the priority is CS0 >
CS1 > CS2 > CS3
■
■
The Cypress multi chart tool (see application note AN2397) can
be used to view the data
For designs with four CapSense buttons, Cypress
recommends taking debug data on two CapSense buttons. For
example, pull down CS0 with a 5.6 kresistor and read data
of CS1, CS2, and CS3. Next, pull down CS1 with a 5.6 k
resistor and read data of CS0, CS2, and CS3
Table 7. Data Format in Multi-chart: Serial TX8
Sl No
Raw Count Array
Baseline Array
Signal Array
MSB
LSB
MSB
LSB
MSB
LSB
0
0x00
FW_Revision
CS _Status
GPO_Status
0x00
CS2_CP
1
0x00
CS0_ CP
0x00
CS1_CP
0x00
CS3_ CP
2
CS0_RawCount
CS0_Baseline
CS0_DiffCount
3
CS1_RawCount
CS1_Baseline
CS1_DiffCount
4
CS2_RawCount
CS2_Baseline
CS2_DiffCount
5
CS3_RawCount
CS3_Baseline
CS3_DiffCount
Document Number: 001-57451 Rev. *C
Page 10 of 26
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CY8CMBR2044
Table 8. Serial Data Output
Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Data
0x0D
0x0A
0x00
FW_Revision
0x00
CS0_CP
CS0_RawCount_LSB
CS0_RawCount_MSB
CS1_RawCount_LSB
CS1_RawCount_MSB
CS2_RawCount_LSB
CS2_RawCount_MSB
CS3_RawCount_LSB
CS3_RawCount_MSB
CS _Status
GPO_Status
0x00
CS1_CP
CS0_ Baseline _LSB
CS0_ Baseline _MSB
CS1_ Baseline _LSB
CS1_ Baseline _MSB
CS2_ Baseline _LSB
CS2_ Baseline _MSB
CS3_ Baseline _LSB
CS3_ Baseline _MSB
0x00
CS2_CP
0x00
CS3_CP
CS0_ DiffCount _LSB
CS0_ DiffCount _MSB
CS1_ DiffCount _LSB
CS1_ DiffCount _MSB
CS2_ DiffCount _LSB
CS2_ DiffCount _MSB
CS3_ DiffCount _LSB
CS3_ DiffCount _MSB
0x00
0xFF
0xFF
Document Number: 001-57451 Rev. *C
Notes
Dummy data for multi chart
–
–
–
CS0 parasitic capacitance in Hex
Unsigned 16-bit integer
–
Unsigned 16-bit integer
–
Unsigned 16-bit integer
–
Unsigned 16-bit integer
–
Gives CapSense button status, least significant bit (LSB) contains CS0 status
Gives GPO status, LSB contains GP0 status
–
CS1 parasitic capacitance in Hex
Unsigned 16-bit integer
–
Unsigned 16-bit integer
–
Unsigned 16-bit integer
–
Unsigned 16-bit integer
–
–
CS2 parasitic capacitance in Hex
–
CS3 parasitic capacitance in Hex
Unsigned 16-bit integer
–
Unsigned 16-bit integer
–
Unsigned 16-bit integer
–
Unsigned 16-bit integer
–
Dummy data for multi chart
Page 11 of 26
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CY8CMBR2044
Device Operating Modes
There are two device operating modes:
■
Low power sleep mode
■
Deep sleep mode
Low Power Sleep Mode
The following flow chart describes the low power sleep mode operation.
Figure 9. Low Power Sleep Mode Operation
Scan all Sensors with 20 ms Scan rate (Scan
time + sleep time)
NO
NO button pressed
for 2 secs?
YES
YES
Scan all sensors with user defined scan rate.
NO
Is Any Sensor
active ?
Figure 10. Low Power Sleep Mode Implementation
■
To enable low power sleep mode, the hardware configurable pin ScanRate/Sleep should be pulled down to ground with resistor ‘R’
(1%). The scan rate values for different resistor values are given in Table 9 on page 13.
■
The range of scan rate is 20 to 530 ms.
.
Document Number: 001-57451 Rev. *C
Page 12 of 26
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CY8CMBR2044
Table 9. ScanRate/Sleep Pin Hardware Configuration
Resistor R (1%) in ohms
Approximate ScanRate (in ms)
Resistor R (1%) in ohms
Approximate ScanRate (in ms)
60
185
310
435
560
685
810
935
1060
1185
1310
1435
1560
1685
1810
1935
2060
2185
2310
2435
2560
2685
2810
2935
3060
3185
3310
3435
3560
3685
3810
3935
20
22
24
27
30
34
38
42
46
51
55
61
66
71
77
83
89
96
102
107
115
122
129
137
144
152
159
167
175
183
192
200
4060
4185
4310
4435
4560
4685
4810
4935
5060
5185
5310
5435
5560
5685
5810
5935
6060
6185
6310
6435
6560
6685
6810
6935
7060
7185
7310
7435
7560
7685
7810
7935
209
217
226
235
244
253
263
272
282
291
301
311
321
331
341
352
362
373
383
394
405
416
427
438
449
461
472
484
495
507
519
531
Document Number: 001-57451 Rev. *C
Page 13 of 26
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CY8CMBR2044
Figure 11. Average Current vs Scan Rate[2]
Note
2. Number of sensors = 3, Cp<19 pF, 0% touch time, VDD = 3 V
Document Number: 001-57451 Rev. *C
Page 14 of 26
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CY8CMBR2044
Deep Sleep Mode
Figure 12. ScanRate/Sleep Pin Connection to Enable Deep Sleep Mode
External Res R
Host Pin controlling
ScanRate/Sleep Pin
ScanRate/Sleep
CY8CMBR2044
HOST
■
To enable the deep sleep mode, the hardware configuration
pin ScanRate/Sleep should be connected to the master device
as shown in Figure 9 on page 12.
■
When device comes out of deep sleep mode, the CapSense
system is reinitialized. Typical time for reinitialization is 8 ms.
Any button press within this time is not reported.
■
ScanRate/Sleep pin should be connected to VDD for the device
to go into deep sleep.
■
After the device comes out of deep sleep, the device operates
in low power sleep mode.
■
In deep sleep mode, all blocks are turned off and the device
power consumption is 0.1 µA.
■
■
There is no CapSense scanning in deep sleep mode.
If the ScanRate/Sleep pin is pulled high at power on, then the
device does not go to deep sleep immediately. The device goes
to deep sleep after initializing all internal blocks and scanning
all sensors once.
■
ScanRate/Sleep pin should be pulled low for the device to wake
up from deep sleep.
■
If the ScanRate/Sleep pin is pulled high at power on, then the
scan rate is calculated when the device is taken out of Deep
Sleep by the master.
Additional Components to Enable Advanced Features
Resistors
required
1
Sl. No
Feature
1
Low power sleep and
deep sleep
2
Toggle/FSS
1
3
4
Delay Off
Sensor auto reset
1
1
Notes
Deep sleep is controlled by a master device. When the device comes out of deep sleep,
it enters into low power sleep mode based on settings. Resistor is not required if both
features are not used.
To enable both the features only one resistor is required. Resistor is not required if both
features are not used.
Resistor is not required if the feature is not used.
Resistor is not required if the feature is not used.
Response Time
Response time is the minimum amount of time the button should be touched for the device to detect as valid button press.
Condition
First button press
Consecutive button press after first button press
Document Number: 001-57451 Rev. *C
Response time (in ms)
Scan rate value + 20. For scan rate value, see Table 9 on page 13.
80
Page 15 of 26
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CY8CMBR2044
Layout Guidelines and Best Practices
Sl. No.
1
Category
Button shape
Min
–
Max
–
2
3
Button size
Button-button spacing
15 mm
–
4
Button ground clearance
5 mm
= Button
Ground
Clearance
0.5 mm
5
Ground flood – top layer
–
–
6
Ground flood – bottom layer
–
–
7
–
200 mm
8
9
Trace length from sensor to
CapSense IC pins
Trace width
Trace routing
0.17 mm
–
0.20 mm
–
10
Via position for the sensors
–
–
11
12
13
Via hole size for sensor traces
No. of via on sensor trace
Distance of CapSense series
resistor from sensor pin
–
1
–
–
2
10 mm
14
Distance between any
CapSense trace to ground flood
Device placement
10 mil
20 mil
–
–
Placement of components in two
layer PCB
Placement of components in four
layer PCB
–
–
–
–
15
16
17
2 mm
18
19
Overlay Thickness
Overlay material
0 mm
–
5 mm
–
20
Overlay Adhesives
–
–
21
LED Back Lighting
–
–
22
Board Thickness
–
–
Document Number: 001-57451 Rev. *C
Recommendations/Remarks
Solid round pattern, round with LED hole, rectangle
with round corners
10 mm
8 mm (Y dimension in Button Layout Design on page
17)
Button ground clearance = Overlay thickness
(X dimension in Button Layout Design on page 17)
Hatched ground 7 mil trace and 45 mil grid (15%
filling)
Hatched ground 7 mil trace and 70 mil grid (10%
filling)
< 100 mm
0.17 mm (7 mil)
Traces should be routed on the non sensor side. If
any non CapSense trace crosses CapSense trace,
ensure that intersection is orthogonal
Via should be placed near the edge of the
button/slider to reduce trace length thereby
increasing sensitivity
10 mil
1
Place CapSense series resistors close to the device
for noise suppression. CapSense resistors have
highest priority; place them first
20 mil
Mount the device on the layer opposite to sensor.
The CapSense trace length between the device and
sensors should be minimum (see trace length
above)
Top layer – sensors and bottom layer – device, other
components and traces
Top layer – sensors, second layer – CapSense
traces and VDD (avoid VDD traces below the
sensors), third layer – hatched ground, 
bottom layer – CapSense IC or device, other components, and non CapSense traces
1 mm
Should be non-conductive material. Glass, ABS
plastic, formica, wood, and so on. There should be
no air gap between PCB and overlay. Use adhesive
to stick the PCB and overlay
Adhesive should be non conductive and
dielectrically homogenous. 467MP and 468MP
adhesives made by 3M are recommended
Cut a hole in the sensor pad and use rear mountable
LEDs. Refer to “Example PCB Layout Design with
Four CapSense Buttons and Four LEDs” on page 18
Standard board thickness for CapSense FR4 based
designs is 1.6 mm
Page 16 of 26
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CY8CMBR2044
CapSense Button Shapes
Button Layout Design
X: Button to ground clearance (Refer to Layout Guidelines and Best Practices on page 16)
Y: Button to button clearance (Refer to Layout Guidelines and Best Practices on page 16)
Recommended Via Hole Placement
Document Number: 001-57451 Rev. *C
Page 17 of 26
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CY8CMBR2044
Example PCB Layout Design with Four CapSense Buttons and Four LEDs
Figure 13. Top Layer
Figure 14. Bottom Layer
Document Number: 001-57451 Rev. *C
Page 18 of 26
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CY8CMBR2044
Electrical Specifications
Absolute Maximum Ratings
Parameter
Description
Min
Typ
Max
Unit
Notes
+125
°C
Higher storage temperatures reduce data
retention time. Recommended storage
temperature is +25 °C ± 25 °C. Extended
duration storage temperatures above 85 °C
degrades reliability.
TSTG
Storage temperature
–55
25
VDD
Supply voltage relative to VSS
–0.5
–
+6.0
V
VIO
DC voltage on CapSense inputs and VSS – 0.5
digital output pins
–
VDD + 0.5
V
IMIG
Maximum current into any GPO
output pin
–25
–
+50
mA
ESD
Electro static discharge voltage
2000
–
–
V
LU
Latch up current
–
–
200
mA
Min
Typ
Max
Unit
Human body model ESD
In accordance with JESD78 standard
Operating Temperature
Parameter
Description
Notes
TA
Ambient temperature
–40
–
+85
°C
TJ
Operational die temperature
–40
–
+100
°C
Min
Typ
Max
Unit
Supply voltage
1.71
–
5.5
V
IDD
Supply current
–
2.88
4.0
mA
Conditions are VDD = 3.0 V, TA = 25 °C
IDA
Active current
–
2.88
4.0
mA
Conditions are VDD = 3.0 V, TA = 25 °C,
continuous sensor scan
IDS
Deep sleep current
–
0.1
0.5
µA
Conditions are VDD = 3.0 V, TA = 25 °C
IAV1
Average current
–
40
–
µA
Conditions are VDD = 3.0 V, TA = 25 °C, 
4 – buttons used, 0% touch time, CP of all
sensors<19 pF and scan rate = 530 ms
IAV2
Average current
–
63
–
µA
Conditions are VDD = 3.0 V, TA = 25 °C,
4 – buttons used, 0% touch time, CP of all
sensors>19 pF and scan rate = 530 ms
IAV3
Average current
–
1
–
mA
Conditions are VDD = 3.0 V, TA = 25 °C,
4 – buttons used, 100% touch time, CP of all
sensors<19 pF and scan rate = 20 ms
IAV4
Average current
–
1.6
–
mA
Conditions are VDD = 3.0 V, TA = 25 °C,
4 – buttons used, 100% touch time, CP of all
sensors>19 pF and <40 pF, 
scan rate = 20 ms
DC Electrical Characteristics
DC Chip Level Specifications
Parameter
VDD
[1, 2, 3]
Description
Notes
1. When VDD remains in the range from 1.75 V to 1.9 V for more than 50 µs, the slew rate when moving from the 1.75 V to 1.9 V range to greater than 2 V must be slower
than 1 V/500 µs. This helps to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SRPOWER_UP parameter.
2. If you power down the device, make sure that VDD falls below 100 mV before powering back up.
3. For proper CapSense block functionality, if the drop in VDD exceeds 5% of the base VDD, the rate at which VDD drops should not exceed 200 mV/s. Base VDD can be
between 1.8 V and 5.5 V.
Document Number: 001-57451 Rev. *C
Page 19 of 26
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CY8CMBR2044
DC General Purpose I/O Specifications
These tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and 
–40 °C = TA = 85°C, 2.4 V to 3.0 V and –40 °C = TA = 85 °C, or 1.71 V to 2.4 V and –40 °C = TA = 85 °C, respectively. Typical
parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only.
Table 10. 3.0 V to 5 V DC General Purpose I/O Specifications
Parameter
Description
Min
Typ
Max
Unit
Notes
VOH1
High output voltage on GP0, GP1,
GP2, GP3
VDD – 0.2
–
–
V
IOH < 10 µA, maximum of 40 µA source
current in all I/Os
VOH2
High output voltage on GP0, GP1
VDD – 0.9
–
–
V
IOH = 1 mA, maximum of 2 mA source
current in all I/Os
VOH3
High output voltage on GP2, GP3
VDD – 0.9
–
–
V
IOH = 5 mA, maximum of 10 mA source
current in all I/Os
VOL
Low output voltage
–
–
0.75
V
IOL = 25 mA/pin, VDD > 3.30, maximum of
60 mA sink current on GPO0, GPO1,
GPO2, GPO3
Notes
Table 11. 2.4 V to 3.0 V DC General Purpose I/O Specifications
Parameter
Description
Min
Typ
Max
Unit
VOH1
High output voltage on GP0, GP1,
GP2, GP3
VDD – 0.2
–
–
V
IOH < 10 µA, maximum of 40 µA source
current in all I/Os
VOH2
High output voltage on GP0, GP1
VDD – 0.4
–
–
V
IOH = 0.2 mA, maximum of 0.4 mA source
current in all I/Os
VOH3
High output voltage on GP2, GP3
VDD – 0.5
–
–
V
IOH = 2 mA, maximum of 4 mA source
current in all I/Os
VOL
Low output voltage
–
–
0.72
V
IOL = 10 mA/pin, maximum of 30 mA sink
current on GPO0, GPO1, GPO2, GPO3
Table 12. 1.71V to 2.4V DC General Purpose I/O Specifications
Min
Typ
Max
Unit
VOH1
Parameter
High output voltage on GP0,GP1
Description
VDD – 0.2
–
–
V
IOH =10 µA, maximum of 20 µA source
current in all I/Os
VOH2
High output voltage on GP0,GP1
VDD – 0.5
–
–
V
IOH = 0.5 mA, maximum of 1 mA source
current in all I/Os
VOH3
High output voltage on GP2,GP3
VDD – 0.2
–
–
V
IOH = 100 µA, maximum of 200 µA source
current in all I/Os
VOH4
High output voltage on GP2,GP3
VDD – 0.5
–
–
V
IOH = 2 mA, maximum of 4 mA source
current in all I/Os
VOL
Low output voltage
–
–
0.4
V
IOL = 5 mA/pin, maximum of 20 mA sink
current on GPO0, GPO1, GPO2, GPO3
Document Number: 001-57451 Rev. *C
Notes
Page 20 of 26
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CY8CMBR2044
AC Electrical Specifications
AC Chip Level Specifications
Parameter
SRPOWER_UP
Description
Power supply slew rate
Min
Max
Unit
Notes
–
250
V/ms
VDD slew rate during power up
TXRST
External reset pulse width at power up
1
–
ms
After supply voltage is valid
TXRST2
External reset pulse width after power up
10
–
µs
Applies after part has booted
AC General Purpose I/O Specifications
Min
Typ
Max
Unit
Notes
TRise1
Parameter
Rise time on GPO0 and GPO1, 
Cload = 50 pF
Description
15
–
80
ns
VDD = 3.0 to 3.6 V, 10% – 90%
TRise2
Rise time on GPO2 and GPO3, 
Cload = 50 pF
10
–
50
ns
VDD = 3.0 to 3.6 V, 10% – 90%
TRise3
Rise time on GPO0 and GPO1, 
Cload = 50 pF
15
–
80
ns
VDD = 1.71 to 3.0V, 10% – 90%
TRise2
Rise time on GPO2 and GPO3, 
Cload = 50 pF
10
–
80
ns
VDD = 1.71 to 3.0 V, 10% – 90%
TRise4
Fall time, Cload=50 pF all GPO outputs
10
–
50
ns
VDD = 3.0 to 3.6 V, 90% – 10%
TFall2
Fall time, Cload=50 pF all GPO outputs
10
–
70
ns
VDD = 1.71 to 3.0 V, 90% – 10%
Min
Typ
Max
Unit
Notes
CP is the total capacitance
seen by the pin when no
finger is present. CP is sum of
C_sensor, C_trace, and
Capacitance of the vias and
CPIN
CapSense Specifications
Parameter
Description
CP
Parasitic capacitance
5.0
–
(CP+CF)<40
pF
CPMAX
Maximum parasitic capacitance till which
sensor works
37
40
43
pF
CF
Finger capacitance
0.25
–
(CP+CF)<40
pF
CPIN
Capacitive load on pins as input
0.5
1.7
7
pF
CMOD
External integrating capacitor
2
2.2
2.4
nF
Mandatory for CapSense to
work
Rs
Series resistor between pin and the
sensor
–
560
–

Reduces the RF noise
Document Number: 001-57451 Rev. *C
CF is the capacitance added
by the finger touch
Page 21 of 26
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CY8CMBR2044
Ordering Information
Package Type
Operating
Temperature
CapSense
Block
CapSense
Inputs
GPOs
XRES Pin
CY8CMBR2044-24LKXI
16 Pad (3 x 3 x 0.6 mm) QFN
Industrial
Yes
4
4
Yes
CY8CMBR2044-24LKXIT
16 Pad (3 x 3 x 0.6 mm) QFN
(Tape and Reel)
Industrial
Yes
4
4
Yes
Ordering Code
Ordering Code Definitions
Document Number: 001-57451 Rev. *C
Page 22 of 26
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CY8CMBR2044
Package Information
Thermal Impedances by Package
Package
Typical JA[3]
16 QFN
32.7 °C/W
Solder Reflow Peak Temperature
Package
Minimum Peak Temperature[4]
Maximum Peak Temperature
16 QFN
240 °C
260 °C
Package Diagram
Figure 15. 16-Pad Quad Flat No Leads (QFN) No E-pad 3x3 mm Package Outline (Sawn)
2.9
3.1
0.20 min
1
1
2
2.9
3.1
0.20 DIA TYP.
2
1.5 (NOM)
0.45
0.55
PIN #1 ID
0.152 REF.
0.30
0.18
0.05 MAX
0.50
0.60 MAX
1.5
SEATING PLANE
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTES:
PART NO.
DESCRIPTION
LG16A
LEAD-FREE
LD16A
STANDARD
1. JEDEC # MO-220
2. Package Weight: 0.014g
3. DIMENSIONS IN MM, MIN
MAX
001-09116 *E
Notes
3. TJ = TA + Power x JA
4. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 °C with Sn-Pb or 245 ± 5 °C with Sn-Ag-Cu
paste. Refer to the solder manufacturer specifications.
Document Number: 001-57451 Rev. *C
Page 23 of 26
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CY8CMBR2044
Document Conventions
Units of Measure
Acronyms Used
The following table lists all the abbreviations used to measure
the PSoC devices.
The following table lists the acronyms that are used in this
document.
Numeric Naming
Table 13. Acronyms
Acronym
Description
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase 'h' (for example, '14h' or
'3Ah'). Hexadecimal numbers may also be represented by a '0x'
prefix, the C coding convention. Binary numbers have an
appended lowercase 'b' (for example, 01010100b' or
'01000011b'). Numbers not indicated by an 'h', 'b', or 0x are
decimal.
AC
alternating current
AI
analog input
AIO
analog input/output
AIDO
analog input/digital output
DO
digital output
P
power pins
CF
finger capacitance
°C
degree Celsius
CP
parasitic capacitance
CS
CapSense
k
Kilohm
FSS
flanking sensor suppression
µA
microampere
GPO
general purpose output
µs
microsecond
LSB
least significant bit
mA
milliampere
MSB
most significant bit
ms
millisecond
PCB
printed circuit board
mV
millivolts
POR
power on reset
nA
nanoampere
POST
power on self test

ohm
RF
radio frequency
pF
picofarad
V
volts
Document Number: 001-57451 Rev. *C
Table 14. Units of Measure
Acronym
Description
Page 24 of 26
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CY8CMBR2044
Document History Page
Document Title: CY8CMBR2044 Capacitive Button Controllers
Document Number: 001-57451
Orig. of
Submission
Rev.
ECN No.
Description of Change
Change
Date
**
2807997
SLAN
12/03/2009 New Data sheet
*A
2949368
SLAN
06/10/2010 Updated Features and Overview
Added Units of Measure and numeric naming sections
Updated Pinout
Updated Schematic1 and Schematic2
Added Device Feature List
Changed H/W configuration on the delay pin
Added Figure 4, Figure 5, and Figure 7
Added Debug Data
Updated Deep Sleep Mode
Updated CapSense Button Shapes
Updated Table 7 and Table 8
Changed Example PCB Layout Design with Four CapSense Buttons and
Four LEDs
Updated Electrical Specifications
Added Ordering Code Definitions
*B
2975370
SLAN
07/09/2010 Updated Features
Updated Pinout
Updated Typical Circuits
Added Device Feature List
Added Figure 3, Figure 5, and Figure 7
Added Debug Data
Updated Deep Sleep Mode
Added Ordering Information
*C
2996393
SLAN
07/29/2010 Updated Features
Document Number: 001-57451 Rev. *C
Page 25 of 26
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CY8CMBR2044
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2009-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-57451 Rev. *C
Revised July 29, 2010
®
Page 26 of 26
®
CapSense Express™ and PSoC Designer™ are trademarks and PSoC and CapSense are registered trademarks of Cypress Semiconductor Corp.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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