CY8CMBR2016 CapSense® Express™ 16 Button Matrix Controller Capacitive Button Controllers Features ■ Hardware Configurable Matrix CapSense® Controller ❐ Does not require software tools or programming ❐ 16 buttons can be configured individually or as a matrix ❐ Supports 3x4 and 4x4 matrix configurations ■ Matrix Host Interface Communication ❐ Industry standard host interface protocols reuse existing host processor firmware • Key Scan Interface • Truth Table Interface ❐ Encoded GPO Interface - minimizes number of pins required ■ SmartSense™ Auto-Tuning ❐ Maintains optimal button performance even in noisy environments ❐ CapSense parameters dynamically set in runtime ❐ Wide parasitic capacitance (CP) range (5–40 pF) ❐ Saves time and effort in device tuning ■ Noise Immunity ❐ High sensitivity, low noise capacitive sensing algorithm ❐ Strong immunity to RF and AC noise ❐ Low radiated noise emission ■ System Diagnostics of CapSense Buttons ❐ Reports any faults at device power up ❐ Button shorts ❐ Improper value of modulating capacitor (CMOD) ❐ Parasitic capacitance (CP) out of range ■ Advanced Features ❐ Flanking Sensor Suppression (FSS) provides robust sensing even with closely spaced buttons ❐ Buzzer Signal Output ❐ Configurable sensitivity for all buttons ❐ Interrupt line to host to indicate any CapSense button status change ❐ Serial Debug Data out • Simplifies production line testing and system debug ■ Wide operating range ❐ 1.71–5.5 V ❐ Ideal for both regulated and unregulated battery applications [1] ■ Low power consumption [2] ❐ Supply current in run mode as low as 20 µA per button ❐ Deep sleep current: 100 nA ■ Industrial temperature range: –40 °C to + 85 °C ■ 48-pin QFN package (6 × 6 × 0.6 mm) Overview The CY8CMBR2016 CapSense Express capacitive touch sensing controller incorporates several innovative features to save time and money to quickly enable a capacitive touch sensing user interface in your design. It is a hardware configurable device and does not require any software tools, firmware coding or device programming. This device is enabled with Cypress's revolutionary SmartSense™ auto-tuning algorithm. SmartSense™ auto-tuning ends the need to manually tune the user interface during development and production ramp. This speeds the time to volume and saves valuable engineering time, test time and production yield loss. The device supports up to 16 capacitive touch buttons that can be organized in any format, such as a matrix array. With its backward compatible key scan interface, it can enable users to achieve quick-to-market (retrofit) designs in large keypad applications such as fire alarm control panels, security systems, and door locks. Any application that requires up to 16 CapSense buttons can utilize CY8CMBR2016. The wide operating range of 1.71 V to 5.5 V enables unregulated battery operation, further saving component cost. This device supports ultra low-power consumption in both run mode and deep sleep mode to stretch battery life. In addition, this device also supports many advanced features, which enhance the robustness and user interface of the end solution. Some of the key advanced features include Noise Immunity and FSS. Noise Immunity improves the immunity of the device against radiated and conducted noise, such as audio and radio frequency (RF) noise. FSS provides robust sensing even with closely spaced buttons. FSS is a critical requirement in small form factor applications. The CY8CMBR2016 provides three different host interface communication modes. These include the industry standard host interface protocols such as Key Scan Interface and Truth Table Interface. These two protocols reuse existing host processor firmware leading to easy conversion of existing mechanical buttons to CapSense. The third host interface communication is the Encoded GPO Interface with a 4-bit output, which minimizes the number of pins required for a button output. These three outputs are configurable which helps provide a wide variety of device usage in multiple applications. Serial Debug Data output gives the critical information about the design, such as button Cp and raw counts. This further helps in production line testing. Notes 1. Supply variation should not be more than 5% for proper CapSense operation 2. Power consumption calculated with 250 ms scan time, 2% touch time and CP of each button < 19 pF. Cypress Semiconductor Corporation Document Number: 001-67921 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 31, 2012 CY8CMBR2016 Contents Pinout ................................................................................ 3 Typical Circuits ................................................................. 4 Configuring the CY8CMBR2016 ...................................... 8 Device Features ................................................................ 8 CapSense Buttons ...................................................... 8 SmartSense Auto-Tuning ............................................ 8 Flanking Sensor Suppression (FSS) ........................... 8 Key Scan Interface ...................................................... 8 Truth Table Output .................................................... 10 Encoded 4-bit Output ................................................ 10 Buzzer Signal Output ................................................ 10 Interrupt Line ............................................................. 10 Button Auto Reset ..................................................... 10 Output Select ............................................................. 11 Scan Rate .................................................................. 11 Sensitivity .................................................................. 11 System Diagnostics ................................................... 11 Serial Debug Data Out .............................................. 12 Power Consumption and Device Operating Modes .. 15 Response Time ......................................................... 15 Document Number: 001-67921 Rev. *C Deep Sleep Mode ...................................................... 16 Layout Guidelines and Best Practices ......................... 16 Sample Layout ................................................................ 19 Electrical Specifications ................................................ 21 DC Electrical Characteristics ..................................... 21 AC Electrical Specifications ....................................... 23 CapSense Specification ............................................ 23 Package Information ...................................................... 24 Ordering Information ...................................................... 25 Ordering Code Definitions ......................................... 25 Appendix ......................................................................... 26 Acronyms ........................................................................ 27 Document Conventions ................................................. 27 Units of Measure ....................................................... 27 Document History Page ................................................. 28 Sales, Solutions, and Legal Information ...................... 28 Worldwide Sales and Design Support ....................... 28 Products .................................................................... 28 PSoC Solutions ................................................................ 28 Page 2 of 28 CY8CMBR2016 Pinout Table 1. Pinout for the Device Description Figure 1. Device Pinout No connection 2 OUT_7 DO READ_3/TT_ROW_3/EO_3/ FMEA_CLK line - Output port interface pin 7 NC 3 OUT_5 DO READ_1/TT_ROW_1/EO_1 Output port interface pin 5 OUT_7 OUT_5 4 OUT_3 DIO SCAN_3/TT_COL_3 - Output port interface pin 3 OUT_3 OUT_1 5 OUT_1 DIO SCAN_1/TT_COL_1 - Output port interface pin 1 6 OUT_SEL AI Selects the output interface 7 ARST AI Controls button auto reset period 8 CS9 AI CapSense button 9 9 CS8 AI CapSense button 8 CS13 AI CapSense button 13 11 CS12 AI CapSense button 12 12 NC – Reserved pin 13 FSS DI Controls FSS feature 14 NC – No connection 15 NC – No connection 3 4 5 6 7 8 9 10 11 12 CY8CMBR2016 (Top View) FSS NC NC SLEEP DEBUG Vss 10 OUT_SEL ARST CS9 CS8 CS13 CS12 NC 1 2 36 35 34 33 32 31 30 29 28 27 26 25 OUT_6 OUT_4 OUT_2 OUT_0 CS6 CS7 CS10 CS11 CS14 CS15 XRES SCAN NC NC Vdd SENSITIVITY NC Buzzer Type – 48 CMOD 47 Vss 46 INT 45 CS4 44 CS5 43 NC 42 NC 41 Vdd 40 CS0 39 CS1 38 CS2 37 CS3 Pin Name NC 13 14 15 16 17 18 19 20 21 22 23 24 Pin 1 16 SLEEP DI Controls entry/exit to Deep Sleep 17 DEBUG DO Serial Debug Data out from the device (UART TX8 line) 18 VSS – GND 19 NC – No connection 34 OUT_2 DIO SCAN_2/TT_COL_2 - Output port interface pin 2 20 NC – No connection 35 OUT_4 DO READ_0/TT_ROW_0/EO_0 - Output port interface pin 4 21 VDD – Power supply 36 OUT_6 DO READ_0/TT_ROW_0/EO_2/FMEA_D ATA - Output port interface pin 6 22 SENSITIVITY AI Selects the sensitivity of the CS system 37 CS3 AI CapSense button 3 23 NC – Reserved for shield out 38 CS2 AI CapSense button 2 24 BUZZER DO Connects to DC Buzzer for audio feedback 39 CS1 AI CapSense button 1 25 SCAN AI Controls the sleep rate of the system 40 CS0 AI CapSense button 0 26 XRES DI System reset pin 41 Vdd – Power supply 27 CS15 AI CapSense button 15 42 NC – No connection 28 CS14 AI CapSense button 14 43 NC – No connection 29 CS11 AI CapSense button 11 44 CS5 AI CapSense button 5 30 CS10 AI CapSense button 10 45 CS4 AI CapSense button 4 31 CS7 AI CapSense button 7 46 INT DO Interrupt line to Host 32 CS6 AI CapSense button 6 47 Vss – GND 33 OUT_0 DIO SCAN_0/TT_COL_0 - Output port interface pin 0 48 CMOD AI Modulator capacitor, 2.2 nF Document Number: 001-67921 Rev. *C Page 3 of 28 CY8CMBR2016 Typical Circuits Scan Lines (ODL Mode) Figure 2. Schematic 1: 16 Buttons with Key Scan Output Mode Scan Lines SCAN_0 SCAN_1 SCAN_2 INT Read Lines (Strong Drive) READ_0 Read Lines Host Host HDR SCAN_3 READ_1 READ_2 READ_3 X INT Line Mechanical Keypad Document Number: 001-67921 Rev. *C Page 4 of 28 CY8CMBR2016 In Schematic 1, CY8CMBR2016 is configured as follows: ■ 16 CapSense buttons ■ Key Scan Interface ■ Continuous scan mode ■ High sensitivity for all buttons ■ FSS enabled ■ Button Auto Reset disabled ■ Serial Debug Data Out disabled ■ DC buzzer output ■ Reset button ■ Interrupt line output Document Number: 001-67921 Rev. *C Page 5 of 28 CY8CMBR2016 Figure 3. Schematic 2: 16 Buttons with Truth Table Output Mode Document Number: 001-67921 Rev. *C Page 6 of 28 CY8CMBR2016 In Schematic 2, CY8CMBR2016 is configured as follows: ■ 16 CapSense buttons ■ Truth Table Output configured to drive LEDs ■ Continuous Scan mode ■ High sensitivity for all buttons ■ FSS disabled ■ Button Auto Reset enable, with a period of 5 seconds ■ Serial Debug Data Out enabled ■ DC buzzer output ■ Reset button ■ Interrupt line output Document Number: 001-67921 Rev. *C Page 7 of 28 CY8CMBR2016 Configuring the CY8CMBR2016 SmartSense Auto-Tuning The CY8CMBR2016 device features are configured using external resistors. The resistors on the hardware configurable pins are determined by the device upon power-on. The Appendix on page 26 gives the matrix of features enabled using different external resistor configurations. ■ Device supports auto-tuning of CapSense button parameters. ■ No manual tuning required; all parameters are automatically tuned by the device. ■ Compensates printed circuit board (PCB) variations, device process variations, and PCB vendor changes. ■ Ensures portability of the user interface design. Device Features Table 2. Device Feature List Feature Flanking Sensor Suppression (FSS) Description/Use 16 CapSense Buttons Mechanical button/keypad replacement Flanking Sensor Suppression (FSS) Helps in distinguishing closely spaced buttons Key Scan Interface Mechanical matrix replacement Truth Table Output Easy to decode truth table based output mode 4-bit Encoded Output Fewer pins needed to output button status Button Auto Reset Prevents buttons from getting stuck during run time Scan/Sleep Rate Configures the device based on power needs Configurable Sensitivity Selects the sensitivity for the system – minimum change in capacitance to be detected Deep Sleep Reduce power consumption by hibernating the device System Diagnostics Supports for production testing and debugging ■ Helps to distinguish closely spaced buttons. ■ Also used in situations when a button can produce opposite effects. For example, an interface with two buttons for brightness control (UP or DOWN). ■ FSS action can be explained for the following different scenarios: ❐ When only one button is touched, it is reported as ON. ❐ When more than one button is detected as ON and previously one of those buttons was touched, then the previously touched button is reported as ON. (Refer to Figure 4.) Key Scan Interface ■ Mimics legacy mechanical keypads - Four SCAN lines (I/P) and four READ lines (O/P) ■ Reads the SCAN lines and updates the READ lines based on the button status (Refer to Figure 5). ■ ‘Plug' n 'Play' replacement for mechanical keypads. ■ When buttons are disabled or found to be invalid, Table 3 helps identifying the scan and read lines. ■ When the SCAN lines are not used, they should be connected to VDD ■ OUT0 to OUT3 in the pin out form the SCAN lines and OUT4 to OUT7 form the READ lines ■ Refer Figure 6 for SCAN line waveform details. CapSense Buttons ■ Device supports up to 16 CapSense Buttons. ■ Ground the CSx Pin to disable CapSense input. ■ 2.2 nF (± 10%) capacitor should be connected on CMOD pin for proper CapSense operation. ■ The parasitic capacitance (CP) of each button must be less than 40 pF for proper CapSense operation. Document Number: 001-67921 Rev. *C Table 3. Key Scan interface Selection based on # of Buttons No. of Buttons (>12) SCAN × READ Lines 4×4 Scan Lines OUT0 to OUT3 (<=12) && (>8) 3×4 OUT0 to OUT2 (<=8) && (>4) 2×4 OUT0 to OUT1 (<=4) 1×4 OUT0 Page 8 of 28 CY8CMBR2016 Figure 4. Button Status with Respect to Finger Touch when FSS is Enabled [3] Scan Lines Scan Lines (ODL Mode) Figure 5. Key Scan interface Retrofit CY8CMBR2016 Read Lines Read Lines (Strong Drive) Host X Mechanical Keypad Figure 6. SCAN Line Waveform Details Note 3. When finger moves from one button to other (FSS enabled). Document Number: 001-67921 Rev. *C Page 9 of 28 CY8CMBR2016 Truth Table Output ■ Another output interface providing matrix outputs. ■ All pins are output pins - divided into ROW/COLUMN. ■ Only one button can be reported at a time - cannot be used in conjunction with FSS disabled. ■ Button status is reported in an encoded ROW/COLUMN fashion as shown in Figure 7. ■ Each button has its own ROW-COLUMN code. ■ Easy to integrate into a system requiring a simple interface with single key press requirement. ■ OUT4 to OUT7 in the pin out form the ROW lines and OUT0 to OUT3 form the COLUMN lines. Figure 7. Truth Table Output Table 4. Encoded Output Keypress Detected By CapSense EO[3:0] Interrupt Time Key #1 0000 1 Key #2 0001 1 Key #3 0010 1 Key #4 0011 1 … … 1 1111 1 XXXX 0 Key #16 No keys pressed Buzzer Signal Output ■ A dedicated pin for buzzer output is provided in the device. ■ Buzzer output can be used to drive an p-type transistor driving a buzzer or directly a DC buzzer up to 10 mA sink current. Interrupt Line Encoded 4-bit Output ■ Only 4 pins to report a button press out of 16 buttons. ■ Each button has its own code. ■ ■ ■ An interrupt line to the host controller. ■ On a button touch, the device pulls the INT line HIGH to indicate an interrupt to the host. The INT line remains HIGH as long as a button is touched. ■ Can be used as a latch input at the host side to read the OUT lines. ■ Can also be used as an interrupt line for the host controller to read the OUT lines. Button Auto Reset ■ Prevents button stuck, due to any conducting object placed close to a button. Only one button can be reported at a time using this interface. ■ Useful when output to be kept ON only for a specific time. Table 4 defines the decode table. ■ The Button Auto Reset period is controlled by the hardware configuration on the ARST pin. Refer Table 18 in Appendix on page 26 for pin configuration details. ■ When touched, a button is treated active for a maximum of Button Auto Reset period (refer to Figure 8). ■ After the button is released the CSx will be hold for 440 ms. Document Number: 001-67921 Rev. *C Page 10 of 28 CY8CMBR2016 Figure 8. Button Auto Reset Button is touched for more than the Auto Reset period Auto Reset period Button Output Output is not driven after Auto Reset period Output Select ■ ■ ■ One among the three output interfaces defined earlier in the section can be selected by the hardware configuration on the OUT_SEL pin. Refer Table 18 in Appendix on page 26 for pin configuration details. Only one of the three output interfaces can be used at a given time. Scan Rate ■ This defines the rate at which the device scans all the buttons and then sleeps, in the Low Power Sleep mode. For more details about Low Power Sleep mode, refer to Power Consumption and Device Operating Modes on page 15. ■ The device scan rate is defined by the hardware configuration on the SCAN pin. Refer Table 18 in Appendix on page 26 for details. ■ Device power consumption is dependent on Scan Rate. For a higher scan rate, the power consumption is less, and vice versa. Refer to the CY8CMBR2016 Design Guide, section 5 for power calculations. Sensitivity can be controlled by the hardware configuration on the SENSITIVITY pin. For details, refer to Table 18 in Appendix on page 26. System Diagnostics A built-in power on self test (POST) mechanism detects the following at power on reset (POR), which can be useful in production testing. Any failure is reported on the OUT_6 and OUT_7 pins, as detailed below. Button Shorted to Ground If a button is disabled/found shorted to Ground (as shown in Figure 11), then the corresponding bit in the button mask is set, and the same is sent out serially through the OUT_6 pin, synchronised with a 2 kHz clock on OUT_7 pin. If no clock is sensed on OUT_7 till 300 ms after power-on, then all the buttons have passed the System Diagnostics. If a clock is sensed, then starting from the first falling edge of the clock, each button takes up one clock slot. A high output on OUT_6 during a falling edge on OUT_7 indicates a failure of the button in that clock slot. ■ Sensitivity is defined as the minimum change in capacitance which can be detected as a finger touch. ■ Use higher sensitivity setting when the overlay thickness is higher, or the button diameter is small. The clock output stops after indicating the last failed button. For instance, if Button 1, 3 and 5 are disabled, then the System Diagnostics data is transmitted as shown in Figure 9. CS1 failure is marked by a HIGH on OUT_6 in the 0.5 ms to 1 ms slot. CS3 failure is marked by a HIGH on OUT_6 in the 1.5 ms to 2 ms slot. CS5 failure is marked by a HIGH on OUT_6 in the 2.5 ms to 3 ms slot. After indicating the failure of CS5, clock output is ceased. ■ Use a lower sensitivity setting when power consumption needs to be low. As an example, Figure 10 shows the System Diagnostics output when CS1, CS3 and CS15 fail the POST. ■ Possible sensitivity settings are “High”, “Medium”, and “Low”. Sensitivity Figure 9. System Diagnostics of Disabled Button - Scenario 1 Document Number: 001-67921 Rev. *C Page 11 of 28 CY8CMBR2016 Figure 10. System Diagnostics of Disabled Button - Scenario 2 Figure 11. Button Shorted to GND Button to Button Short Any button that are shorted together are disabled and the corresponding bit field is set and System Diagnostics data is sent as defined in button to GND short section. Button Figure 13. Button to Button Short Button CY8CMBR2016 shorting shorting Button Shorted to VDD CY8CMBR2016 Button If any button is shorted to VDD that button is disabled and the corresponding bit field is set and System Diagnostics data is sent as defined in button to GND short section. Improper Value of CMOD Figure 12. Button Shorted to VDD VDD ■ Recommended value of CMOD is 2 nF to 2.4 nF. ■ If CMOD of < 1 nF or > 4 nF is connected, all buttons are disabled and the status output will be logic high on all slots. Button CP > 40 pF shorting Button CY8CMBR2016 If the parasitic capacitance (CP) of any button exceeds 40 pF that button is disabled and the corresponding bit field is set and System Diagnostics data is sent as defined in button to GND short section. Serial Debug Data Out ■ Used to see CapSense data through the Debug pin. ■ To enable this feature, the DEBUG pin is pulled down with a 5.6 K resistor. ■ The Cypress MultiChart tool can be used to view the debug data for each button ■ Serial data is sent out at ~115,200 baud rate ■ Firmware revision, CapSense status, baseline, raw counts, difference counts and parasitic capacitances of all sensors are sent out For more information on Raw Count, Baseline, Difference Count, and Parasitic Capacitance, refer Getting Started with CapSense, section 2. Document Number: 001-67921 Rev. *C Page 12 of 28 CY8CMBR2016 For more information on MultiChart tool, refer AN2397 CapSense Data Viewing Tools, method 2. ■ ■ The Serial Debug Data is sent by the device in the order shown in Table 6 on page 13. The MultiChart tool arranges the data in the format as shown in Table 5 on page 13. Table 5. Serial Debug Data Arranged in MultiChart Raw Count Array Sl. No. MSB Baseline Array LSB MSB Difference Count array LSB MSB 0 CS0_RC CS0_BL CS0_DIFF 1 CS1_RC CS1_BL CS1_DIFF 2 CS2_RC CS2_BL CS2_DIFF 3 CS3_RC CS3_BL CS3_DIFF 4 CS4_RC CS4_BL CS4_DIFF 5 CS5_RC CS5_BL CS5_DIFF 6 CS6_RC CS6_BL CS6_DIFF 7 CS7_RC CS7_BL CS7_DIFF 8 CS8_RC CS8_BL CS8_DIFF 9 CS9_RC CS9_BL CS9_DIFF LSB 10 CS10_RC CS10_BL CS10_DIFF 11 CS11_RC CS11_BL CS11_DIFF 12 CS12_RC CS12_BL CS12_DIFF 13 CS13_RC CS13_BL CS13_DIFF 14 CS14_RC CS14_BL CS14_DIFF 15 CS15_RC CS15_BL CS15_DIFF 16 0x00 F/W Rev CS_Status 0x00 CS10_CP 17 0x00 CS0_CP 0x00 CS5_CP 0x00 CS11_CP 18 0x00 CS1_CP 0x00 CS6_CP 0x00 CS12_CP 19 0x00 CS2_CP 0x00 CS7_CP 0x00 CS13_CP 20 0x00 CS3_CP 0x00 CS8_CP 0x00 CS14_CP 21 0x00 CS4_CP 0x00 CS9_CP 0x00 CS15_CP Table 6. Serial Data Output sent by CY8CMBR2016 BYTE DATA Notes 0 0x0D Dummy variables for multi chart tool 1 0x0A 2 CS0_RC CS0 Raw counts, unsigned 16-bit integer CS1_RC CS1 Raw counts, unsigned 16-bit integer CS2_RC CS2 Raw counts, unsigned 16-bit integer ------------ ------------------------------------------------------ 3 4 5 6 7 ----- Document Number: 001-67921 Rev. *C Page 13 of 28 CY8CMBR2016 Table 6. Serial Data Output sent by CY8CMBR2016 (continued) BYTE 32 DATA Notes CS15_RC CS15 Raw counts, unsigned 16-bit integer 0x00 – 33 34 35 FW_REV Firmware revision 36 0x00 – 37 CS0_CP Parasitic capacitance of CS0 38 0x00 – 39 CS1_CP Parasitic capacitance of CS1 40 0x00 – 41 CS2_CP Parasitic capacitance of CS2 42 0x00 – 43 CS3_CP Parasitic capacitance of CS3 44 0x00 – 45 CS4_CP Parasitic capacitance of CS4 46 CS0_BL CS0 Baseline, unsigned 16-bit integer CS1_BL CS1 Baseline, unsigned 16-bit integer CS2_BL CS2 Baseline, unsigned 16-bit integer ------------ ------------------------------------------------------ CS15_BL CS15 Baseline, unsigned 16-bit integer 78 79 CS_Status CapSense Status, unsigned 16 bit integer – 80 0x00 – 81 CS5_CP Parasitic capacitance of CS5 82 0x00 – 83 CS6_CP Parasitic capacitance of CS6 84 0x00 – 85 CS7_CP Parasitic capacitance of CS7 86 0x00 – 87 CS8_CP Parasitic capacitance of CS8 88 0x00 – 89 CS9_CP Parasitic capacitance of CS9 90 CS0_DIFF CS0 difference counts, unsigned 16-bit integer 91 92 CS1_ DIFF CS1 difference counts, unsigned 16-bit integer 93 94 CS2_ DIFF CS2 difference counts, unsigned 16-bit integer ------------ ------------------------------------------------------ 47 48 49 50 51 76 77 Document Number: 001-67921 Rev. *C Page 14 of 28 CY8CMBR2016 Table 6. Serial Data Output sent by CY8CMBR2016 (continued) BYTE 121 DATA Notes CS15_ DIFF CS15 difference counts, unsigned 16-bit integer 0x00 – 124 CS10_CP Parasitic capacitance of CS10 125 0x00 – 126 CS11_CP Parasitic capacitance of CS11 127 0x00 – 128 CS12_CP Parasitic capacitance of CS12 129 0x00 – 130 CS13_CP Parasitic capacitance of CS13 131 0x00 – 132 CS14_CP Parasitic capacitance of CS14 133 0x00 – 134 CS15_CP Parasitic capacitance of CS15 135 0x00 Dummy variable for multi chart tool 136 0xFF 137 0xFF 122 123 Power Consumption and Device Operating Modes The CY8CMBR2016 is designed to meet the low power requirements of battery powered applications. To design for the lowest operating current ■ Ground all unused CapSense inputs ■ Minimize Cp using the design guidelines in Getting Started with CapSense, section 3.7.1. ■ Lower the supply voltage. ■ Use a higher Button Scan Rate or Deep Sleep operating mode. To know more about the steps to reduce power consumption, refer to CY8CMBR2016 Design Guide, section 5. There are two device operating modes: ■ Low power sleep mode ■ Deep sleep mode Low Power Sleep Mode The following flow chart describes the low power sleep mode operation. Figure 14. Low Power Sleep Mode Operation For details on Low power sleep look at the Scan Rate on page 11 section. Response Time Response Time is the minimum amount of time the button should be touched for the device to detect as valid button touch. Document Number: 001-67921 Rev. *C It is given by the following equations RTFBT =User defined Button Scan Rate + 40 ms RTCBT = 40 ms Where, RTFBT is Response time for first button touch RTCBT is Response time for consecutive button touch after first button touch Page 15 of 28 CY8CMBR2016 Refer to Scan Rate on page 11 section for more details on the User defined Button Scan Rate. For example, consider a nine button design with the User defined Button Scan Rate set to Low (250 ms). The response time for such a design is given as: RTFBT =250+40=290 ms RTCBT = 40 ms ■ To enable the deep sleep mode, the hardware configuration pin Sleep should be connected to the master device. ■ Master should pull the pin to VDD for the device to go into deep sleep. ■ The master output pin should be in strong drive mode, so that the Sleep pin is not left floating. ■ In deep sleep mode, all blocks are turned off and the device power consumption is 0.1 µA. ■ There is no CapSense scanning in deep sleep mode. ■ Sleep pin should be pulled low for the device to wake up from deep sleep. ■ When device comes out of deep sleep mode, the CapSense system is reinitialized. Typical time for re-initialization is 8 ms.Any button press within this time is not reported. ■ After the device comes out of deep sleep, the device operates in low power sleep mode. ■ If the Sleep pin is pulled high at power on, then the device does not go to deep sleep immediately. The device goes to deep sleep after initializing all internal blocks and scanning all sensors once. ■ If the Sleep pin is pulled high at power on, then the scan rate is calculated when the device is taken out of Deep Sleep by the master. Deep Sleep Mode Figure 15. SLEEP Pin Configuration to Enable Deep Sleep SLEEP Digital Output pin (Controls Deep Sleep) CY8CMBR2016 Host Controller Layout Guidelines and Best Practices Table 7. Layout Guidelines Sl. No. Category Min Max Recommendations/Remarks – – Solid round pattern, Round with LED hole, rectangle with round corners 5 mm 15 mm 1. Button shape 2. Button size 3. Button-Button spacing equal to button ground clearance 4. Button ground clearance 0.5 mm 2 mm 5. Ground flood - Top layer – – Hatched ground 7 mil trace and 45 mil grid (15% filling) 6. Ground flood bottom layer – – Hatched ground 7 mil trace and 70 mil grid (10% filling) 7. Trace length from sensor to device pin – 450 8. Trace width 9. Trace routing – – Traces should be routed on the non sensor side. If any non CapSense trace crosses CapSense trace, ensure that intersection is orthogonal. 10. Via position for the sensors – – Via should be placed near the edge of the button to reduce trace length thereby increasing sensitivity. 11. Via hole size for sensor traces – – 10 mil 12. No. of via on sensor trace 1 2 1 0.17 mm Document Number: 001-67921 Rev. *C Given in layout estimator sheet 8 mm Given in layout estimator sheet Given in layout estimator sheet 0.20 mm 0.17 mm (7 mil) Page 16 of 28 CY8CMBR2016 Table 7. Layout Guidelines (continued) Sl. No. Category Min Max – 10 mm Recommendations/Remarks 13. CapSense series resistor placement Place CapSense series resistors close to the device for noise suppression.CapSense resistors have highest priority compared to other resistors, so place them first. 14. Distance between 10 mil any CapSense trace to ground flood 20 mil 20 mil 15. Device placement – – Mount the device on the layer opposite to sensor. The CapSense trace length between the device and sensors should be minimum (see trace length above) 16. Placement of components in two layer PCB – – Top layer-Sensors and bottom layer-device, other components and traces. 17. Placement of components in four layer PCB – – Top layer-Sensors, second layer – CapSense traces & Vdd and avoid the Vdd traces below the sensors, third layer-hatched ground, Bottom layer- device other components and non CapSense traces 18. Overlay thickness 0 mm 5 mm Use layout estimator sheet to decide on overlay, given maximum limit is for plastic overlay. 19. Overlay material – – Should to be non-conductive material. Glass, ABS Plastic, Formica, wood etc. No air gap should be there between PCB and overlay. Use adhesive to stick the PCB and overlay. 20. Overlay adhesives – – Adhesive should be non conductive and dielectrically homogenous. 467 MP and 468 MP adhesives made by 3 M are recommended. 21. Board thickness – – Standard board thickness for CapSense FR4 based designs is 1.6 mm. Figure 16. CapSense Button Shapes Figure 17. Button Layout Design X: Button to ground clearance (Refer to Layout Guidelines and Best Practices on page 16) Document Number: 001-67921 Rev. *C Page 17 of 28 CY8CMBR2016 Y: Button to button clearance (Refer to Layout Guidelines and Best Practices on page 16) Figure 18. Recommended via Hole Placement Document Number: 001-67921 Rev. *C Page 18 of 28 CY8CMBR2016 Sample Layout Figure 19. Top Layer Document Number: 001-67921 Rev. *C Page 19 of 28 CY8CMBR2016 Figure 20. Bottom Layer Document Number: 001-67921 Rev. *C Page 20 of 28 CY8CMBR2016 Electrical Specifications This section presents the DC and AC electrical specifications of the CY8CMBR2044 device. Table 8. Absolute Maximum Ratings Parameter Description TSTG Storage temperature Min Typ Max Unit Notes –55 25 +125 °C Higher storage temperatures reduce data retention time. Recommended storage temperature is +25 °C ± 25 °C. Extended duration storage temperatures above 85 °C degrade reliability. VDD Supply voltage relative to VSS –0.5 – +6.0 V – VIO DC voltage on CapSense inputs and digital output pins VSS – 0.5 – VDD + 0.5 V – IMIG Maximum current into any GPO output pin –25 – +50 mA – ESD Electrostatic discharge voltage 2000 – – V LU Latch up current – – 200 mA Min Typ Max Unit Human body model ESD In accordance with JESD78 standard Table 9. Operating Temperature Parameter Description TA Ambient temperature TC Commercial temperature TJ Operational die temperature Notes –40 – +85 °C – 0 – +70 °C – –40 – +100 °C – DC Electrical Characteristics The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 10. DC Chip Level Specifications Parameter Description Min Typ Max Unit 1.71 – 5.5 V Notes VDD[4, 5, 6] Supply voltage IDD Supply current – 3.3 4.0 mA Conditions are VDD = 3.0 V, TA = 25 °C IDA Active current – 3.3 4.0 mA Conditions are VDD = 3.0 V, TA = 25 °C, continuous sensor scan IDS Deep sleep current – 0.1 0.5 A Conditions are VDD = 3.0 V, TA = 25 °C IAV1 Average current – 0.25 – mA Conditions are VDD = 3.0 V, TA = 25 °C and 16 buttons used, with 0% touch time, CP of all sensors < 19 pFand scan rate = 250 ms IAV2 Average current – 2.13 – mA Conditions are VDD = 3.0 V, TA = 25 °C and 16 buttons used, with 50% touch time, CP of all sensors < 19 pFand scan rate = 250 ms, Key Scan mode enabled IAV3 Average current – 0.42 – mA Conditions are VDD = 3.0 V, TA = 25 °C and 16 buttons used, with 0% touch time, CP of all sensors >19 pF and < 40 pF and scan rate = 250 ms IAV4 Average current – 2.2 – mA Conditions are VDD = 3.0 V, TA = 25 °C and 16 buttons used, with 50% touch time, CP of all sensors >19 pF and < 40 pF and scan rate = 250 ms, Key Scan mode enabled – Notes 4. When VDD remains in the range from 1.75 V to 1.9 V for more than 50 µs, the slew rate when moving from the 1.75 V to 1.9 V range to greater than 2 V must be slower than 1 V/500 µs. This helps to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SRPOWER_UP parameter. 5. After power down, ensure that VDD falls below 100 mV before powering backup. 6. For proper CapSense block functionality, if the drop in VDD exceeds 5% of the base VDD, the rate at which VDD drops should not exceed 200 mV/s. Base VDD can be between 1.8 V and 5.5 V Document Number: 001-67921 Rev. *C Page 21 of 28 CY8CMBR2016 DC General Purpose I/O Specifications These tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and –40 °C TA 85 °C, 2.4 V to 3.0 V and –40 °C TA 85 °C, or 1.71 V to 2.4 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 11. 3.0 V to 5.5 V DC General Purpose I/O Specification Parameter Description Min Typ Max Unit Notes VOH1 High output voltage on all output pins VDD – 0.2 – – V IOH < 10 µA, Maximum of 40 µA source in all I/Os VOH2 High output voltage on OUT pins VDD – 0.9 – – V IOH = 1 mA, Maximum of 2 mA source in all I/Os VOH3 High output voltage on INT and BUZZ pins VDD – 0.9 – – V IOH = 5 mA, Maximum of 10 mA source in all I/Os VOL Low output voltage – – 0.75 V IOL = 25 mA/pin, VDD > 3.3 V, Maximum of 60 mA source in all I/Os VIL Input low voltage – – 0.80 V – VIH Input high voltage 2.00 – – V – Table 12. 2.4 V to 3.0 V DC General Purpose I/O Specifications Min Typ Max Unit Notes VOH1 Parameter High output voltage on all outputs Description VDD – 0.2 – – V IOH < 10 µA, Maximum of 40 µA Source in all I/Os VOH2 High output voltage on OUT pins VDD – 0.4 – – V IOH = 0.2 mA, Maximum of 0.4 mA source in all I/Os VOH3 High output voltage on INT and BUZZ VDD – 0.5 – – V IOH = 2 mA, Maximum of 4 mA source in all I/Os VOL Low output voltage – – 0.75 V IOL = 10 mA/pin, VDD > 3.3 V, Maximum of 30 mA source in all I/Os VIL Input low voltage – – 0.72 V – VIH Input high voltage 1.40 – – V – Table 13. 1.71 V to 2.4 V DC General Purpose I/O Specifications Parameter Description Min Typ Max Unit Notes VOH1 High output voltage on OUT pins VDD – 0.2 – – V IOH =10 µA, maximum of 20 µA source in all I/Os VOH2 High output voltage on OUT pins VDD – 0.5 – – V IOH = 0.5 mA, maximum of 1 mA source in all I/Os VOH3 High output voltage on INT and BUZZ VDD – 0.2 – – V IOH =100 µA, maximum of 200 µA source in all I/Os VOH4 High output voltage on INT and BUZZ VDD – 0.5 – – V IOH = 2 mA, maximum of 4 mA source in all I/Os VOL Low output voltage – – 0.4 V IOL = 5 mA/pin, VDD > 3.3 V, maximum of 20 mA source in all I/Os VIL Input low voltage – – 0.30 × VDD V – VIH Input high voltage 0.65 × VDD – – V – Document Number: 001-67921 Rev. *C Page 22 of 28 CY8CMBR2016 AC Electrical Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 14. AC Chip-Level Specifications Parameter Description SRPOWER_UP Power supply slew rate Min Max Unit Notes – 250 V/ms VDDslew rate during power-up TXRST External reset pulse width at power-up 1 – ms Applicable after device power supply is active TXRST2 External reset pulse width after power-up 10 – ms Applicable after device VDD has reached maximum value Table 15. AC General Purpose I/O Specifications Min Typ Max Unit TRise1 Parameter Rise time on OUT pins, Cload = 50 pF Description 15 – 80 ns VDD = 3.0 to 3.6 V, 10%–90% Notes TRise2 Rise time on INT and BUZZ pins, Cload = 50 pF 10 – 50 ns VDD = 3.0 to 3.6 V, 10%–90% TRise3 Rise time on OUT pins, Cload = 50 pF 15 – 80 ns VDD = 1.71 to 3.0 V, 10%–90% TRise4 Rise time on INT and BUZZ pins, Cload = 50 pF 10 – 80 ns VDD = 1.71 to 3.0 V, 10%–90% TFall1 Fall time, Cload = 50 pF all outputs 10 – 50 ns VDD = 3.0 to 3.6 V, 90%–10% TFall2 Fall time, Cload = 50 pF all outputs 10 – 70 ns VDD = 1.71 to 3.0 V, 90%–10% CapSense Specification Min Typ Max Unit Notes CP Parameter Parasitic capacitance Description 5.0 – (CP+CF)<40 pF CP is the total capacitance seen by the pin when no finger is present. CP is sum of C_sensor, C_trace, and Capacitance of the vias and CPIN CF Finger capacitance 0.25 – (CP+CF)<40 pF CF is the capacitance added by the finger touch CPIN Capacitive load on pins as input 0.5 1.7 7 pF Mandatory for CapSense to work CMOD External modulator capacitor 2 2.2 2.4 nF Mandatory for CapSense to work RS Series resistor between pin and the button – 560 616 Reduces the RF noise Document Number: 001-67921 Rev. *C Page 23 of 28 CY8CMBR2016 Package Information Table 16. Thermal Impedances by Package Typical θJA[7] Package 48-pin QFN [8] 19 °C/W Table 17. Solder Reflow Peak Temperature Package 48-pin QFN Minimum Peak Temperature [9] Maximum Peak Temperature Time at Max Temperature 240 °C 260 °C 30 s Figure 21. 48-pin (6 × 6 × 0.6 mm) QFN 001-57280 *D Notes 7. TJ = TA + Power x θJA 8. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane 9. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 °C with Sn-Pb or 245 ± 5 °C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications Document Number: 001-67921 Rev. *C Page 24 of 28 CY8CMBR2016 Ordering Information Ordering Code CY8CMBR2016-24LQXI CY8CMBR2016-24LQXIT Package Type Operating CapSense Temperature Inputs 48-pin (6 × 6 × 0.6 mm) QFN 48-pin (6 × 6 × 0.6 mm) QFN (Tape and Reel) Other I/Os XRES pin Industrial 17 [10] 17 [11] Yes Industrial [10] [11] Yes 17 17 Ordering Code Definitions CY 8 C MBR 2016 - 24 LQX I (T) T = Tape and Reel, Blank = Standard Temperature Range: I = Industrial Package Code: LQX = QFN Pb-free Speed: 24 MHz Part Number: 2016 MBR = Mechanical Button Replacement Technology Code: C = CMOS Marketing Code: 8 = PSoC Company ID: CY = Cypress Notes 10. 16 CapSense input + 1 CMOD pin 11. 8 Configurable GPIOs + 1 buzzer output + 1 Sleep line + 1 Interrupt line + 1 Debug line + 5 configuration pins Document Number: 001-67921 Rev. *C Page 25 of 28 CY8CMBR2016 Appendix Table 18. Device Features versus Resistor Configuration Matrix Features Comments Flanking Sensor Suppression (FSS) Disabled Button Auto Reset Output Select Scan Rate Sensitivity Deep Sleep Mode Pin configuration Ground Enabled VDD / Floating Enabled, Auto Reset period = 5 ms Ground Enabled, Auto Reset period = 20 ms 1.5 kΩ (±5%) to ground Enabled, Auto Reset period = 40 ms 5 kΩ (±5%) to ground Disabled VDD / Floating Truth Table I/F Ground Encoded 4 bit output 1.5 kΩ (±5%) to ground Keypad scanning interface output VDD / Floating Low, 250 ms Ground Medium, 150 ms 1.5 kΩ (±5%) to ground High, 40 ms 5 kΩ (±5%) to ground Continuous scan VDD / Floating Low Ground Medium 1.5 kΩ (±5%) to ground High VDD / Floating Device out of Deep Sleep Ground Device in Deep Sleep VDD Document Number: 001-67921 Rev. *C Device Pin Name FSS ARST OUT_SEL SCAN SENSITIVITY SLEEP Page 26 of 28 CY8CMBR2016 Acronyms Acronym Document Conventions Description Units of Measure AC alternating current CF finger capacitance °C degree Celsius CMOD modulator capacitor kHz kilohertz CP parasitic capacitance k kilohm EO_x Encoded Output - Bit ‘x’ MHz megahertz FMEA failure mode effect analysis M megaohm FSS flanking sensor suppression A microampere ODL Open Drain Low F microfarad POR power-on reset s microsecond POST power on self test mA milliampere QFN quad flat no leads ms millisecond RF radio frequency mV millivolt READ_x KeyScan Interface - ‘x’th Read line nA nanoampere SCAN_x KeyScan Interface - ‘x’th Scan line nF nanofarad SNR signal-to-noise ratio ns nanosecond TT_COL_x Truth Table Column output - ‘x’th Column ohm pF picofarad ppm parts per million s second V volt W watt TT_ROW_x Truth Table Row output - ‘x’th Row Document Number: 001-67921 Rev. *C Symbol Unit of Measure Page 27 of 28 CY8CMBR2016 Document History Page Document Title: CY8CMBR2016, CapSense® Express™ 16 Button Matrix Controller Document Number: 001-67921 Revision ECN Orig. of Change Submission Date Description of Change ** 3202566 MSUR 03/22/2011 New datasheet *A 3387102 MSUR 10/10/2011 Changed status from Preliminary to Final. Added Char data into the table and some minor edits to the document. *B 3473096 MSUR 12/22/2011 No technical updates. *C 3633927 UDYG 10/31/2012 Updated title. Updated Features, Scan Rate, Sensitivity, and Button Shorted to Ground section. Added parameters VIL and VIH in Table 11, Table 12, and Table 13, and parameter TC in Table 9. Added Figure 15 and section Response Time. Updated Package Information. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2011-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-67921 Rev. *C Revised October 31, 2012 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 28 of 28