64 CYM1464 512Kx8 Static RAM Module Features constructed using four 256K x 4 static RAMs in SOJ packages mounted on an epoxy laminate substrate with pins. • High-density 4-megabit SRAM module • High-speed CMOS SRAMs — Access time of 20 ns • Low active power — 1.93W (max.) • JEDEC-compatible pinout • 32-pin, 0.6-inch-wide DIP package • TTL-compatible inputs and outputs • Low profile — Max. height of 0.34 inches Writing to the module is accomplished when the chip select (CS) and write enable (WE) inputs are both LOW. Data on the eight input/output pins (I/O0 through I/O7) of the device is written into the memory location specified on the address pins (A0 through A18). Reading the device is accomplished by taking chip select and output enable (OE) LOW, while write enable (WE) remains inactive or HIGH. Under these conditions, the contents of the memory location specified on the address pins (A0 through A18) will appear on the eight appropriate data input/output pins (I/O0 through I/O7). The input/output pins remain in a high-impedance state unless the module is selected, outputs are enabled, and write enable (WE) is HIGH. Functional Description The CYM1464 is a high-performance 4-megabit static RAM module organized as 512K words by 8 bits. This module is Logic Block Diagram Pin Configuration DIP Top View A0 − A17 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND WE OE 256K x 4 SRAM A18 1 OF 2 DECODER 256K x 4 SRAM 256K x 4 SRAM 256K x 4 SRAM CS 1S 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 I/O0 − I/O 7 Selection Guide 1464-20 1464-22 1464-25 1464-30 1464-35 1464-45 1464-55 Maximum Access Time (ns) 20 22 25 30 35 45 55 Maximum Operating Current (mA) 350 350 300 300 Maximum Standby Current (mA) 240 240 240 240 Cypress Semiconductor Corporation Document #: 38-05272 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised March 15, 2002 CYM1464 Maximum Ratings Operating Range (Above which the useful life may be impaired.) Range Ambient Temperature VCC Commercial 0°C to +70°C 5V ± 10% Storage Temperature ..................................... −55°C to +125°C Ambient Temperature with Power Applied.................................................... −10°C to +85°C Supply Voltage to Ground Potential .................−0.5V to +7.0V DC Voltage Applied to Outputs in High Z State .....................................................−0.5V to +7.0V DC Input Voltage .................................................−0.5V to +7.0V Electrical Characteristics Over the Operating Range 1464-20, 22, 25 Test Conditions Min. VOH Parameter Output HIGH Voltage Description VCC = Min., IOH = −4.0 mA 2.4 VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 1464-30, 35, 45, 55 Max. Min. 0.4 2.2 [1] Max. Unit 2.4 V 0.4 V VCC +0.3 V VCC +0.3 2.2 −0.5 0.8 −0.5 0.8 V −10 +10 −10 +10 µA −10 +10 −10 +10 µA VIL Input LOW Voltage IIX Input Load Current IOZ Output Leakage Current GND < V0 < VCC, Output Disabled ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, CS < VIL 350 300 mA ISB1 Automatic CS Power-Down Current VCC = Max., CS > VIH, Min. Duty Cycle = 100% 240 240 mA ISB2 Automatic CS Power-Down Current VCC = Max., CS > VCC − 0.2V, VIN > VCC − 0.2V or VIN < 0.2V 60 60 mA GND < VI < VCC Capacitance[2] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 40 pF 30 pF TA = 25°C, f = 1 MHz, VCC = 5.0V AC Test Loads and Waveforms R1481 Ω R1481 Ω 5V ALL INPUT PULSES 5V OUTPUT R2 255Ω 30 pF INCLUDING JIG AND SCOPE 3.0V 90% OUTPUT R2 255Ω 5 pF < 5 ns INCLUDING JIG AND SCOPE (a) Equivalent to: OUTPUT GND 10% 90% 10% < 5 ns (b) THÉVENIN EQUIVALENT 167Ω 1.73V Notes: 1. VIL (min.) = −3.0V for pulse widths less than 20 ns. 2. Tested on a sample basis. Document #: 38-05272 Rev. ** Page 2 of 8 CYM1464 Switching Characteristics Over the Operating Range[3] 1464-20 Parameter Description Min. 1464-22 Max. Min. 1464-25 Max. Min. Max. 1464-30 Min. Max. Unit READ CYCLE tRC Read Cycle Time 20 22 tAA Address to Data Valid tOHA Data Hold from Address Change tACS CS LOW to Data Valid 20 22 tDOE OE LOW to Data Valid 13 13 tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z 0 tLZCS CS LOW to Low Z 5 tHZCS CS HIGH to High Z[4] 0 20 5 25 22 0 0 ns 25 30 ns 15 15 ns 5 0 10 10 ns 0 5 15 ns 0 0 5 15 30 5 0 10 ns 25 5 0 30 10 10 0 15 ns ns 0 20 ns [5] WRITE CYCLE tWC Write Cycle Time 20 22 25 30 ns tSCS CS LOW to Write End 15 17 20 25 ns tAW Address Set-Up to Write End 15 15 20 25 ns tHA Address Hold from Write End 3 3 3 3 ns tSA Address Set-Up to Write Start 5 5 5 5 ns tPWE WE Pulse Width 15 15 15 20 ns tSD Data Set-Up to Write End 12 12 15 15 ns tHD Data Hold from Write End 2 2 2 2 ns tLZWE WE HIGH to Low Z 0 tHZWE WE LOW to High Z[4] 0 15 Switching Characteristics Over the Operating Range 0 Description ns 15 15 ns [3] 1464-35 Parameter 0 15 Min. Max. 1464-45 Min. Max. 1464-55 Min. Max. Unit 55 ns READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACS CS LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z 0 tHZOE OE HIGH to High Z 0 tLZCS CS LOW to Low Z 10 tHZCS 35 [4] CS HIGH to High Z 45 35 5 5 35 25 0 15 0 0 ns 55 ns 30 ns 0 15 10 20 ns 5 45 20 0 55 45 0 ns 15 10 20 0 ns ns 20 ns Notes: 3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 4. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage. 5. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05272 Rev. ** Page 3 of 8 CYM1464 Switching Characteristics Over the Operating Range (continued)[3] 1464-35 Parameter Description Min. Max. 1464-45 Min. 1464-55 Max. Min. Max. Unit [5] WRITE CYCLE tWC Write Cycle Time 35 45 55 ns tSCS CS LOW to Write End 30 40 50 ns tAW Address Set-Up to Write End 30 40 50 ns tHA Address Hold from Write End 3 3 3 ns tPWE WE Pulse Width 25 35 40 ns tSD Data Set-Up to Write End 20 25 35 ns tHD Data Hold from Write End 2 3 3 ns tLZWE WE HIGH to Low Z 0 0 0 ns [4] WE LOW to High Z tHZWE 15 15 20 ns Switching Waveforms Read Cycle No. 1 [6,7] tRC ADDRESS tAA tOHA DATAOUT Read Cycle No. 2 PREVIOUS DATA VALID DATA VALID [6,8] tRC CS tACS OE tHZOE tDOE tHZCS tLZOE HIGH IMPEDANCE DATA OUT HIGH IMPEDANCE DATA VALID tLZCS tPD tPU V CC SUPPLY CURRENT ICC 50% 50% ISB Notes: 6. WE is HIGH for read cycle. 7. Device is continuously selected, CS = VIL. 8. Address valid prior to or coincident with CS transition LOW. Document #: 38-05272 Rev. ** Page 4 of 8 CYM1464 Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled) [5] tWC ADDRESS tSCS CS tAW tSA tHA tPWE WE tSD tHD DATA VALID DATAIN tLZWE tHZWE DATAI/O HIGH IMPEDANCE DATA UNDEFINED Write Cycle No. 2 (CS Controlled)[5,9] tWC ADDRESS tSCS tSA CS tAW tHA tPWE WE tSD DATAIN tHD DATA VALID tHZWE DATAI/O HIGH IMPEDANCE DATA UNDEFINED Note: 9. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05272 Rev. ** Page 5 of 8 CYM1464 Truth Table CS WE OE H X X High Z Input/Output Deselect/Power-Down Mode L H L Data Out Read Word L L X Data In Write Word L H H High Z Deselect Ordering Information Speed (ns) Ordering Code Package Type Package Type Operating Range 20 CYM1464PD−20C PD02 32-Pin DIP Module Commercial 22 CYM1464PD−22C PD02 32-Pin DIP Module Commercial 25 CYM1464PD−25C PD02 32-Pin DIP Module Commercial 30 CYM1464PD−30C PD02 32-Pin DIP Module Commercial 35 CYM1464PD−35C PD02 32-Pin DIP Module Commercial 45 CYM1464PD−45C PD02 32-Pin DIP Module Commercial 55 CYM1464PD−55C PD02 32-Pin DIP Module Commercial Document #: 38-05272 Rev. ** Page 6 of 8 CYM1464 Package Diagrams 32-Pin DIP Module PD02 1.590 1.610 0.600 0.620 0.590 0.610 0.007 0.013 0.315 0.335 0.100 TYP Document #: 38-05272 Rev. ** 0.015 0.025 0.125 0.175 0.050 TYP DIMENSIONSININCHES MIN. MAX. Page 7 of 8 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CYM1464 Document Title: CYM1464 512K x 8 Static RAM Module Document Number: 38-05272 REV. ECN NO. Issue Date Orig. of Change ** 114173 3/19/02 DSG Document #: 38-05272 Rev. ** Description of Change Change from Spec number: 38-M-00030 to 38-05272 Page 8 of 8