PRELIMINARY CY7C1071AV33 32-Mbit (2M x 16) Static RAM Features Low Enable (BLE) is LOW, then data from the I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A20). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A20). • High density 32-Mbit SRAM • High speed — tAA = 10 ns • Low active power Reading from the device is accomplished by enabling the chip by taking CE HIGH while forcing the Output Enable (OE) LOW and the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of Read and Write modes. — ICC = 450 mA • Operating voltages of 3.3 ± 0.3V • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE LOW), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE HIGH, and WE LOW). • Available in standard 119-ball FBGA Functional Description The CY7C1071AV33 is a 3.3V high-performance 32-Megabit static RAM organized as a 2,097,152 words by 16 bits. The CY7C1071AV33 is available in a 119-ball grid array (FBGA) package. Writing to the device is accomplished by enabling the chip (CE HIGH) while forcing the Write Enable (WE) input LOW. If Byte Logic Block Diagram 2048K × 16 RAM Array SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA-IN DRIVERS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 BHE WE CE OE BLE Power-down Circuit Cypress Semiconductor Corporation Document #: 38-05634 Rev. *A • CE 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 1, 2005 PRELIMINARY CY7C1071AV33 Selection Guide CY7C1071AV33-10 CY7C1071AV33-12 Unit 10 12 ns Maximum Access Time Maximum Operating Current Com’l / Ind’l 450 400 mA Maximum CMOS Standby Current Com’l / Ind’l 100 100 mA Pin Configurations 119 BGA (Top View) 1 2 3 4 5 6 7 A NC A A A A A NC B C D E F G H J K L M N P NC NC NC A BHE VDD A CE VSS NC A VSS A NC VSS A BLE VDD NC NC NC I/O8 VSS VDD VSS VDD VSS I/O0 I/O9 VDD VSS VSS VSS VDD I/O1 I/O10 VSS VDD VSS VDD VSS I/O2 I/O11 NC VDD VSS VSS VDD VSS VSS VSS VDD VDD VSS I/O3 DNU I/O12 I/O13 VDD VSS VSS VDD VSS VSS VSS VDD VDD VSS I/O4 I/O5 R T U I/O14 VDD VSS VSS VSS VDD I/O6 I/O15 VSS VDD VSS VDD VSS I/O7 NC VDD VSS VSS VSS VDD NC NC A NC A NC A NC WE A A NC OE A A NC NC A A NC A A Document #: 38-05634 Rev. *A Page 2 of 10 PRELIMINARY CY7C1071AV33 Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-Up Current ..................................................... >200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range [1] Supply Voltage on VCC to Relative GND .... –0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[1] ....................................–0.3V to VCC + 0.3V Range Ambient Temperature VCC Commercial 0°C to +70°C 3.3V ± 0.3V DC Input Voltage[1] .................................–0.3V to VCC + 0.3V Industrial –40°C to +85°C DC Electrical Characteristics Over the Operating Range -10 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA Min. -12 Max. Min. 2.4 Max. Unit 2.4 V VOL Output LOW Voltage 0.4 V VIH Input HIGH Voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 V VIL Input LOW Voltage[1] –0.3 0.8 –0.3 0.8 V 0.4 IIX Input Load Current GND < VI < VCC –2 +2 –2 +2 μA IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –2 +2 –2 +2 μA ICC VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC Com’l / Ind’l 450 400 mA ISB1 Automatic CE Power-down Current —TTL Inputs CE <= VIL, Max. VCC,VIN > VIH or VIN < VIL, f = fMAX 140 140 mA ISB2 Automatic CE Power-down Current —CMOS Inputs CE <= 0.3V, Max. VCC, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 100 100 mA Com’l / Ind’l Capacitance[2] Parameter Description CIN Input Capacitance COUT I/O Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. Unit 12 pF 15 pF Thermal Resistance[2] Parameter Description Test Conditions All-Packages Unit ΘJA Thermal Resistance (Junction to Ambient)[2] Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board TBD °C/W ΘJC Thermal Resistance (Junction to Case)[2] TBD °C/W Notes: 1. VIL (min.) = –2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns. 2. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05634 Rev. *A Page 3 of 10 PRELIMINARY CY7C1071AV33 AC Test Loads and Waveforms[3] 50Ω OUTPUT VTH = 1.5V Z0 = 50Ω OUTPUT 30 pF* (a) R1 317Ω 3.3V R2 351Ω 5 pF* INCLUDING JIG AND SCOPE (b) * Capacitive Load consists of all components of the test environment. ALL INPUT PULSES 3.3V 90% GND 90% 10% 10% Fall time: > 1 V/ns Rise time > 1 V/ns (c) AC Switching Characteristics Over the Operating Range [4] -10 Parameter Description Min. -12 Max. Min. Max. Unit Read Cycle tpower VCC(typical) to the first access[5] 1 10 1 ms tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE HIGH to Data Valid 10 12 ns tDOE OE LOW to Data Valid 5 6 ns tLZOE OE LOW to Low-Z tHZOE OE HIGH to CE HIGH to Low-Z[6] tHZCE CE LOW to High-Z[6] tPU CE HIGH to Power-Up[7] tPD CE LOW to Power-Down[7] tDBE Byte Enable to Data Valid tLZBE Byte Enable to Low-Z tHZBE Write 3 5 ns 6 3 5 0 6 12 1 5 ns ns 12 10 1 ns ns 0 10 ns ns 1 3 Byte Disable to High-Z ns 12 3 1 High-Z[6] tLZCE 12 10 ns ns ns 6 ns Cycle[8, 9] tWC Write Cycle Time 10 12 ns tSCE CE HIGH to Write End 7 8 ns Notes: 3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1 ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and specified transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise. 5. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 6. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. 7. These parameters are guaranteed by design and are not tested. 8. The internal Write time of the memory is defined by the overlap of CE HIGH and WE LOW. Chip enables must be active and WE and byte enables must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05634 Rev. *A Page 4 of 10 PRELIMINARY CY7C1071AV33 AC Switching Characteristics Over the Operating Range (continued)[4] -10 Parameter Description Min. -12 Max. Min. Max. Unit tAW Address Set-up to Write End 7 8 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-up to Write Start 0 0 ns tPWE WE Pulse Width 7 8 ns tSD Data Set-up to Write End 5.5 6 ns tHD Data Hold from Write End 0 0 ns tLZWE WE HIGH to Low-Z[6] 3 3 ns tHZWE [6] WE LOW to High-Z tBW Byte Enable to End of Write 5 6 7 ns 8 ns Data Retention Characteristics Over the Operating Range Parameter Conditions[11] Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[2] Chip Deselect to Data Retention Time tR [10] Min. Max Unit 100 mA 2.0 Com’l / Ind’l Operation Recovery Time VCC = VDR = 2.0V, CE < 0.3V VIN > VCC – 0.3V or VIN < 0.3V 0 V ns μs Data Retention Waveform DATA RETENTION MODE 3.0V VCC VDR > 2V 3.0V tR tCDR CE Switching Waveforms Read Cycle No. 1[11, 13] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 10. Test conditions assume tf < 3 ns. 11. No input may exceed VCC + 0.3V. 12. Device is continuously selected. OE, BHE and/or BHE = VIL. CE = VIH. 13. WE is HIGH for Read cycle. Document #: 38-05634 Rev. *A Page 5 of 10 PRELIMINARY CY7C1071AV33 Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[13, 14] ADDRESS tRC CE tACE OE tHZOE tDOE BHE,BLE tLZOE tHZCE tDBE tLZBE DATA OUT tHZBE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU IICC CC 50% 50% ISB Write Cycle No. 1 (CE Controlled)[15, 16] tWC ADDRESS tSCE tSA CE tAW tHA tPWE WE tBW BHE,BLE tSD tHD DATA I/O Notes: 14. Address valid prior to or coincident with CE transition HIGH. 15. Data I/O is high-impedance if OE or BHE and/or BLE = VIH. 16. If CE goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05634 Rev. *A Page 6 of 10 PRELIMINARY CY7C1071AV33 Switching Waveforms (continued) Write Cycle No. 2 (BLE or BHE Controlled)[15, 16] tWC ADDRESS tSA BHE,BLE tBW tAW tHA tPWE WE tSCE CE tSD tHD DATA I/O Write Cycle No. 3 (WE Controlled, OE LOW)[15, 16] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE,BLE tHZWE tSD tHD DATA I/O tLZWE Document #: 38-05634 Rev. *A Page 7 of 10 PRELIMINARY CY7C1071AV33 Truth Table CE OE WE BLE BHE I/O0–I/O7 I/O8–I/O15 Mode Power L X X X X High-Z High-Z Power-down Standby (ISB) H L H L L Data Out Data Out Read All Bits Active (ICC) H L H L H Data Out High-Z Read Lower Bits Only Active (ICC) H L H H L High-Z Data Out Read Upper Bits Only Active (ICC) H X L L L Data In Data In Write All Bits Active (ICC) H X L L H Data In High-Z Write Lower Bits Only Active (ICC) H X L H L High-Z Data In Write Upper Bits Only Active (ICC) H H H X X High-Z High-Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 Ordering Code CY7C1071AV33-10 BBC Package Name BB119 Package Type 119-Ball (14 x 22 x 2.02 mm) FBGA CY7C1071AV33-10 BBI 12 CY7C1071AV33-12 BBC CY7C1071AV33-12 BBI Document #: 38-05634 Rev. *A Operating Range Commercial Industrial BB119 119-Ball (14 x 22 x 2.02 mm) FBGA Commercial Industrial Page 8 of 10 PRELIMINARY CY7C1071AV33 Package Diagram 119 FBGA (14 x 22 x 2.02 mm) BB119B -# -#!" !#/2.%2 ¼8 ! ! " " # $ # $ % % & & ( * + , ' ( ¼ ' * + , - . 0 . 0 2 2 4 4 5 5 ¼ # " ¼ 8 2%&%2%.#%*%$%#.! 0+'7)%'(4GMS 3%!4).'0,!.% # ¼ -!8 # ! 51-85210-** All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05634 Rev. *A Page 9 of 10 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY CY7C1071AV33 Document History Page Document Title: CY7C1071AV33 32-Mbit (2M x 16) Static RAM Document Number: 38-05634 REV. Orig. of ECN NO. Issue Date Change Description of Change ** 278072 See ECN RKF New Datasheet *A 397695 See ECN SYT Converted from “Advance Information” to “Preliminary” Changed the MPN from CYM1071AV33 to CY7C1071AV33 Changed Title from “CY7C1071AV33 32-Mbit (2M x 16) Static RAM Module” to “CY7C1071AV33 32-Mbit (2M x 16) Static RAM “ Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Removed redundant information from the “Features” and “Functional Description” sections Edited typo ‘A19’ to ‘A20’ in the Functional Description on Page # 1 Changed Package offering from 119 PBGA (BG119) to 119 FBGA (BB119) Removed the Package Column from the Capacitance table on Page # 3 Changed the DC Voltage Applied to Outputs in High-Z State and DC Input Voltage from “-0.5V to VCC + 0.5V” to “-0.3V to VCC + 0.3V” in the Maximum Ratings on Page # 3 Changed tDBE from 5 ns to 10 ns and 6 ns to 12 ns for -10 and -12 speed bins respectively on Page # 4 Included spec for ICCDR = 100 mA in the Data Retention Characteristics table on Page# 5 Edited footnote # 11 from “VCC + 0.5V” to “VCC + 0.3V” Referenced footnotes # 15 and 16 on to Write Cycle No.2 Page # 7 Updated the Ordering Information to include the BB119 Package Document #: 38-05634 Rev. *A Page 10 of 10