CYPRESS CY62128V

1*CY62128V Family
CY62128V Family
128K x 8 Static RAM
Features
LOW Output Enable (OE) and three-state drivers. These devices have an automatic power-down feature, reducing the
power consumption by over 99% when deselected. The
CY62128V family is available in the standard 450-mil-wide
SOIC, 32-lead TSOP-I, and STSOP packages.
• Low voltage range:
— 2.7V–3.6V (CY62128V)
— 2.3V–2.7V (CY62128V25)
•
•
•
•
•
Writing to the device is accomplished by taking Chip Enable
one (CE1) and Write Enable (WE) inputs LOW and the Chip
Enable two (CE2) input HIGH. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A16).
— 1.6V–2.0V (CY62128V18)
Low active power and standby power
Easy memory expansion with CE and OE features
TTL-compatible inputs and outputs
Automatic power-down when deselected
CMOS for optimum speed/power
Reading from the device is accomplished by taking Chip Enable one (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable two (CE2) HIGH. Under
these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
Functional Description
The CY62128V family is composed of three high-performance
CMOS static RAMs organized as 131,072 words by 8 bits.
Easy memory expansion is provided by an active LOW Chip
Enable (CE1), an active HIGH Chip Enable (CE2), an active
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
Logic Block Diagram
Pin Configurations
Top View
SOIC
NC
A16
A14
A12
I/O0
INPUT BUFFER
I/O1
512x 256x 8
ARRAY
I/O2
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
I/O3
I/O4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
62128V-2
I/O5
COLUMN
DECODER
CE1
CE2
WE
I/O6
POWER
DOWN
A9
A 10
A 11
A12
A13
A14
A15
A16
I/O7
OE
A4
A5
A6
A7
A12
A14
A16
NC
VCC
A15
CE2
WE
A13
A8
A9
A11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Reverse TSOP I
Top View
(not to scale)
62128V-1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
I/O7
CE1
A10
OE
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
25
26
27
26
28
29
30
31
32
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
STSOP
Top View
(not to scale)
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP I
Top View
(not to scale)
•
3901 North First Street
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
62128V-4
62128V-3
Cypress Semiconductor Corporation
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
•
San Jose
•
CA 95134
•
408-943-2600
March 27, 2001
CY62128V Family
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Range
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ........................................... –0.5V to +4.6V
Ambient Temperature
VCC
0°C to +70°C
1.6V to 3.6V
–40°C to +85°C
1.6V to 3.6V
Commercial
DC Voltage Applied to Outputs
in High Z State[1] ....................................–0.5V to VCC + 0.5V
Industrial
DC Input Voltage[1] .................................–0.5V to VCC + 0.5V
Product Portfolio
Power Dissipation (Commercial)
VCC Range
Product
Min.
Typ.
[2]
Operating (ICC)
Typ.
[2]
Standby (ISB2)
Maximum
Typ.
[2]
Max.
Speed
CY62128V
2.7V
3.0V
3.6V
55, 70 ns
20 mA
40 mA
0.4 µA
100 µA (XL = 10 µA)
Maximum
CY62128V25
2.3V
2.5V
2.7V
100 ns
15 mA
20 mA
0.3 µA
50 µA (LL = 12 µA)
CY62128V18
1.6V
1.8V
2.0V
200 ns
10 mA
15 mA
0.3 µA
30 µA (LL = 10 µA)
Electrical Characteristics Over the Operating Range
CY62128V-55/70
Parameter
Description
Test Conditions
Min.
Typ.[2]
Max.
VOH
Output HIGH Voltage
VCC = Min., IOH = –1.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 2.1 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
IIX
Input Load Current
GND < VI < VCC
–1
±1
+1
µA
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
–1
±1
+1
µA
ICC
VCC Operating Supply
Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
mA
ISB1
Automatic CE
Power-Down Current—
TTL Inputs
2.4
Unit
V
2
–0.5
Max. VCC, CE > VIH,
VIN > VIH or
VIN < VIL, f = fMAX
0.4
V
VCC
+0.5V
V
Com’l,
70 ns
L
20
40
LL, XL
20
40
Ind’l,
55 ns
LL
23
50
Ind’l,
70 ns
L
20
40
LL
20
40
Com’l,
70 ns
L
15
300
LL, XL
15
300
Coml,
55 ns
LL
17
350
Ind’l
L
15
300
LL
15
300
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ., TA = 25°C.
2
µA
CY62128V Family
Electrical Characteristics Over the Operating Range (continued)
CY62128V-55/70
Parameter
ISB2
Description
Typ.[2]
Max.
Unit
0.4
100
µA
LL
15
µA
XL
10
µA
L
100
µA
LL
30
µA
Test Conditions
Automatic CE
Power-Down Current—
CMOS Inputs
Max. VCC,
CE > VCC – 0.3V
VIN > VCC – 0.3V
or VIN < 0.3V, f = 0
Min.
Com’l
L
Ind’l
Electrical Characteristics Over the Operating Range
CY62128V25-100
Parameter
Description
Test Conditions
Min.
2.4
Typ.
[2]
Max.
CY62128V18-200
Min.
Typ.[2]
Max.
Output HIGH Voltage
VCC = Min., IOH = –0.1 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 0.1 mA
0.2
V
VIH
Input HIGH Voltage
2
VCC
+0.5
0.7*
VCC
VCC
+0.3
V
VIL
Input LOW Voltage
–0.5
0.8
–0.5
0.3*
VCC
V
IIX
Input Load Current
GND < VI < VCC
–1
±1
+1
–1
±0.1
+1
µA
IOZ
Output Leakage Current
GND < VO < VCC, Output
Disabled
–1
±1
+1
–1
±0.1
+1
µA
ICC
VCC Operating Supply
Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
L
15
20
10
15
mA
Automatic CE
Power-Down Current—
TTL Inputs
Max. VCC, CE > VIH,
VIN > VIH or
VIN < VIL, f = fMAX
L
15
300
5
100
µA
Automatic CE
Power-Down Current—
CMOS Inputs
Max. VCC,
CE > VCC – 0.3V
VIN > VCC – 0.3V
or VIN < 0.3V, f = 0
L
0.4
50
0.4
30
µA
LL
12
10
µA
Indust’l Temp Range
LL
24
20
µA
ISB1
ISB2
0.8*
VCC
Unit
VOH
V
0.4
LL
LL
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.0V
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
3
Max.
Unit
6
pF
8
pF
CY62128V Family
AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
OUTPUT
1.8V
R2
50 pF
GND
90%
10%
< 5 ns
< 5 ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
90%
10%
62128V–5
62128V–6
THÉVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
3.3V
2.5V
1.8V
Unit
R1
1213
15909
10800
Ohms
R2
1378
4487
4154
Ohms
RTH
645
3500
3000
Ohms
VTH
1.75V
0.55V
0.50V
Volts
Data Retention Characteristics (Over the Operating Range)
Parameter
Conditions[4]
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
Min.
Typ.[2]
Max.
1.6
Com’l
L
LL,
XL
Ind’l
L
LL
tCDR[3]
Chip Deselect to Data Retention Time
tR
Operation Recovery Time
VCC = 2V
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
No input may exceed
VCC+0.3V
Unit
V
0.4
10
µA
10
µA
20
µA
20
µA
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
1.8V
VDR > 1.6 V
1.8V
tR
tCDR
CE
C62128V–7
Note:
4. No input may exceed VCC+0.3V.
4
CY62128V Family
Data Retention Current Graph (for “L” version only)
DATA RETENTIO N
CURRENT
vs. SUPPLY VOLTAGE
70
60
50
40
30
TA =25°C
20
10
3.6
2.6
0
1.6
SUPPLY CURRENT (µA)
80
SUPPLY VOLTAGE (V)
Switching Characteristics Over the Operating Range[5]
Parameter
Description
62128V-55
62128V-70
62128V25-100
62128V18-200
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
55
70
100
200
ns
tDOE
OE LOW to Data Valid
20
35
75
125
ns
tLZOE
OE LOW to Low
tHZOE
55
Z[6]
OE HIGH to High
55
5
Z[6]
CE LOW to Low
tHZCE
CE HIGH to High Z[6, 7]
tPU
CE LOW to Power-Up
100
70
10
10
20
10
CE HIGH to Power-Down
55
10
0
70
ns
75
50
ns
ns
75
0
100
ns
ns
10
10
0
200
50
25
ns
10
10
10
0
100
25
20
200
10
10
Z[6, 7]
tLZCE
tPD
70
ns
ns
200
ns
[8, 9]
WRITE CYCLE
tWC
Write Cycle Time
55
70
100
200
ns
tSCE
CE LOW to Write End
45
60
100
190
ns
tAW
Address Set-Up to Write End
45
60
100
190
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tPWE
WE Pulse Width
45
55
90
125
ns
tSD
Data Set-Up to Write End
25
30
60
100
ns
tHD
Data Hold from Write End
0
tHZWE
WE LOW to High Z[6, 7]
tLZWE
5.
6.
7.
8.
9.
WE HIGH to Low
Z[6]
0
20
5
0
25
5
0
50
10
ns
100
15
ns
ns
Test conditions assume signal transition time of 5 ns or less timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100-pF load capacitance.
At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE signals must be LOW and CE2 HIGH to initiate a
write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
5
CY62128V Family
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC
ADDRESS
tOHA
DATA OUT
tAA
DATA VALID
PREVIOUS DATA VALID
62128V–8
Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS
tRC
CE1
CE2
tACE
OE
tHZOE
tDOE
DATA OUT
tHZCE
tLZOE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
ICC
50%
50%
ISB
62128V-9
Write Cycle No. 1 (CE1 or CE2 Controlled)[13,14]
tWC
ADDRESS
tSCE
CE1
tSA
CE2
tSCE
tHA
tAW
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
62128V-10
Notes:
10. Device is continuously selected. OE, CE = VIL, CE2=VIH.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
13. Data I/O is high impedance if OE = VIH.
14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
6
CY62128V Family
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]
tWC
ADDRESS
tSCE
CE1
CE2
tSCE
tAW
tHA
tSA
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 15
tHZOE
62128V-11
Truth Table
CE1
CE2
OE
WE
H
X
X
X
High Z
I/O0–I/O7
Power-Down
Mode
Standby (ISB)
X
L
X
X
High Z
Power-Down
Standby (ISB)
L
H
L
H
Data Out
Read
Active (ICC)
L
H
X
L
Data In
Write
Active (ICC)
L
H
H
H
High Z
Selected, Outputs Disabled
Active (ICC)
Note:
15. During this period, the I/Os are in output state and input signals should not be applied.
7
Power
CY62128V Family
Ordering Information
Speed
(ns)
Ordering Code
55
CY62128VLL-55ZAI
70
CY62128VL-70SC
Package
Name
Package Type
Operating
Range
ZA32
32-Lead STSOP Type 1
Industrial
S34
32-Lead 450-Mil SOIC
Commercial
Z32
32-Lead TSOP Type 1
CY62128VLL-70SC
CY62128VL-70ZC
CY62128VLL-70ZC
CY62128VL-70ZAC
ZA32
32-Lead STSOP Type 1
ZR32
32-Lead Reverse TSOP Type 1
CY62128VLL-70ZAC
CY62128VLL-70ZRC
CY62128VLL-70SI
S34
32-Lead 450-Mil SOIC
CY62128VL-70ZI
Z32
32-Lead TSOP Type 1
Industrial
CY62128VLL-70ZI
CY62128VL-70ZAI
ZA32
32-Lead STSOP Type 1
ZR32
32-Lead Reverse TSOP Type 1
CY62128VLL-70ZAI
CY62128VLL-70ZRI
200
CY62128V18L-200ZC
Z32
CY62128V18L-200ZAI
ZA32
32-Lead TSOP Type 1
Commercial
32-Lead STSOP Type 1
Industrial
CY62128V18LL-200ZAI
Document #: 38-00547-*C
8
CY62128V Family
Package Diagrams
32-Lead (450 MIL) Molded SOIC S34
51-85081-A
9
CY62128V Family
Package Diagrams
32-Lead Thin Small Outline Package Z32
51-85056-C
10
CY62128V Family
Package Diagrams
32-Lead Shrunk Thin Small Outline Package ZA32
51-85094-C
11
CY62128V Family
Package Diagrams
32-Lead Reverse Thin Small Outline Package ZR32
51-85089-B
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.