ETC CY62148L-70SC

fax id: 1079
PRELIMINARY
CY62148
512K x 8 Static RAM
Features
an automatic power-down feature that reduces power consumption by more than 99% when deselected.
• 4.5V−5.5V operation
• CMOS for optimum speed/power
• Low active power
— 660 mW (max.)
• Low standby power (Commercial L version)
— 2.75 mW (max.)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE options
Writing to the device is accomplished by taking chip enable
(CE) and write enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18).
Reading from the device is accomplished by taking chip enable (CE) and output enable (OE) LOW while forcing write enable (WE) HIGH for read. Under these conditions, the contents
of the memory location specified by the address pins will appear on the I/O pins.
Functional Description
The CY62148 is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE), an active LOW
output enable (OE), and three-state drivers. This device has
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY62148 is available in a standard 32 pin 450-mil-wide
body width SOIC and 32 pin TSOP II packages.
Logic Block Diagram
Pin Configuration
Top View
SOIC
TSOPII
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
I/O0
INPUT BUFFER
CE
I/O1
I/O2
SENSE AMPS
ROW DECODER
A0
A1
A4
A5
A6
A7
A12
A14
A16
A17
512K x 8
ARRAY
I/O3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
I/O4
VCC
A15
A18
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
62148-2
I/O5
COLUMN
DECODER
I/O6
POWER
DOWN
I/O7
A2
A3
A 15
A 18
A 13
A8
A9
A 11
A 10
WE
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Cypress Semiconductor Corporation
62148-1
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
June 30, 1998
PRELIMINARY
CY62148
Selection Guide
CY62148–55
CY62148–70
CY62148–100
Maximum Access Time (ns)
55
70
100
Maximum Operating Current (mA)
120
120
120
L
90
90
90
LL
90
90
90
2 mA
2 mA
2 mA
L
100 µA
100 µA
100 µA
Com’l
LL
20 µA
20 µA
20 µA
Ind’l
LL
40 µA
40 µA
40 µA
Maximum CMOS Standby Current
Shaded areas contain advance information.
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Supply Voltage on VCC to Relative GND........ –0.5V to +7.0V
Range
DC Voltage Applied to Outputs
in High Z State[1] ....................................–0.5V to VCC + 0.5V
Commercial
Industrial
DC Input Voltage[1].................................–0.5V to VCC + 0.5V
Ambient
Temperature[2]
VCC
0°C to +70°C
4.5V - 5.5V
–40°C to +85°C
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –1 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 2.1 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage[1]
IIX
Input Load Current
IOZ
Output Leakage Current
ICC
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
ISB1
Automatic CE
Power-Down Current
— TTL Inputs
Max. VCC, CE ≥ V IH
VIN ≥ VIH or
VIN ≤ VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current
— CMOS Inputs
Max. VCC,
CE ≥ VCC – 0.3V,
VIN ≥ VCC – 0.3V,
or VIN ≤ 0.3V, f=0
Min.
Typ[3]
Max.
2.4
Unit
V
0.4
V
2.2
VCC +
0.3
V
–0.3
0.8
V
GND ≤ VI ≤ VCC
–1
+1
µA
GND ≤ VI ≤ VCC, Output Disabled
–1
+1
µA
120
mA
L
90
mA
LL
90
mA
15
mA
1.6 µA
2
mA
L
1.6
100
µA
Com’l
LL
1.6
20
µA
Ind’l
LL
1.6
40
µA
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “instant on” case temperature.
3. Typical values are measured at VCC = 5V, TA =25oC, and are included for reference only and are not tested or guaranteed.
4. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
2
PRELIMINARY
CY62148
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
6
pF
8
pF
TA = 25°C, f = 1 MHz,
VCC = 5.0V
AC Test Loads and Waveforms
R1 1838 Ω
5V
ALL INPUT PULSES
R1 1838 Ω
5.0V
5V
OUTPUT
90%
OUTPUT
R2
994 Ω
100 pF
R2
994 Ω
5 pF
INCLUDING
JIG AND
SCOPE
(a)
INCLUDING
JIG AND
SCOPE
90%
10%
10%
GND
≤ 3ns
≤ 3 ns
62148–3
(b)
62148-2
Equivalent to:
THÉVENIN EQUIVALENT
645 Ω
1.75V
OUTPUT
Switching Characteristics[6] Over the Operating Range
62148–55
Parameter
Description
Min.
Max.
62148–70
Min.
Max.
62148–100
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z [8]
tHZOE
tLZCE
55
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
tPU
CE LOW to Power-Up
WRITE CYCLE
100
70
10
55
10
35
5
20
10
25
20
CE HIGH to Power-Down
ns
50
ns
ns
30
25
55
100
10
0
ns
ns
30
0
70
ns
ns
5
10
0
ns
100
70
20
5
[7, 8]
tHZCE
tPD
10
[7, 8]
[8]
70
55
ns
ns
100
ns
[9]
tWC
Write Cycle Time
55
70
100
ns
tSCE
CE LOW to Write End
45
60
80
ns
tAW
Address Set-Up to Write End
45
60
80
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
45
55
60
ns
tSD
Data Set-Up to Write End
25
25
25
ns
Notes
5. Tested initially and after any design or process changes that may affect these parameters.
6. Test conditions assume signal transition time of 5ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I OL/IOH and 100pF load capacitance.
7. t HZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
3
PRELIMINARY
CY62148
Switching Characteristics[6] Over the Operating Range (continued)
62148–55
Parameter
tHD
Description
Min.
Data Hold from Write End
WE HIGH to Low Z
tHZWE
WE LOW to High Z[7,8]
Max.
0
[8]
tLZWE
62148–70
Min.
62148–100
Max.
Min.
0
5
Unit
0
5
20
Max.
ns
5
ns
25
30
ns
Data Retention Characteristics Over the Operating Range
Parameter
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
Conditions
Min.
Typ[3]
Max
Unit
2.0
Com’l
L
LL
Ind’l
tCDR[5]
Chip Deselect to Data Retention Time
tR
Operation Recovery Time
No input may exceed VCC + 0.3V
VCC = VDR = 3.0V,
CE > VCC – 0.3V
VIN > VCC – 0.3V or VIN < 0.3V
V
1.6 µA
LL
1.7
mA
80
µA
20
µA
40
µA
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
3.0V
VCC
VDR > 2V
3.0V
tR
tCDR
CE
62148–5
Switching Waveforms
Read Cycle No.1[10,11]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
62148-4
Notes:
10. Device is continuously selected. OE, CE = VIL.
11. WE is HIGH for read cycle.
4
PRELIMINARY
CY62148
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)[11,12]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
DATA OUT
tHZCE
tLZOE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
ICC
50%
50%
ISB
62148-5
Write Cycle No. 1 (CE Controlled)[13,14]
tWC
ADDRESS
tSCE
CE
tSA
tHA
tAW
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
62148-6
Notes:
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O is high impedance if OE = VIH.
14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
5
PRELIMINARY
CY62148
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13,14]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 15
tHZOE
Write Cycle No.3 (WE Controlled, OE LOW)
62148-7
[13,14]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
DATAI/O
NOTE 15
tHD
DATA VALID
tLZWE
tHZWE
62148-8
Notes:
15. During this period the I/Os are in the output state and input signals should not be applied
6
PRELIMINARY
CY62148
Truth Table
CE
OE
WE
I/O0 – I/O7
Mode
Power
H
X
X
High Z
Power-Down
Standby (ISB)
L
L
H
Data Out
Read
Active (ICC)
L
X
L
Data In
Write
Active (ICC)
L
H
H
High Z
Selected, Outputs Disabled
Active (ICC)
Document #: 38-00564
Ordering Information
Speed
(ns)
70
Ordering Code
CY62148-70SC
CY62148-70ZSC
CY62148L-70SC
CY62148L-70ZSC
CY62128LL-70SC
CY62148LL-70ZSC
CY62148-70SI
CY62148-70ZSI
CY62148L-70SI
CY62148L-70ZSI
CY62128LL-70SI
CY62148LL-70ZSI
100
CY62148-100SC
CY62148-100ZSC
CY62148L-100SC
CY62148L-100ZSC
CY62128LL-100SC
CY62148LL-100ZSC
CY62148-100SI
CY62148-100ZSI
CY62148L-100SI
CY62148L-100ZSI
CY62128LL-100SI
CY62148LL-100ZSI
Package
Name
S34
ZS32
S34
ZS32
S34
ZS32
S34
ZS32
S34
ZS32
S34
ZS32
S34
ZS32
S34
ZS32
S34
ZS32
S34
ZS32
S34
ZS32
S34
ZS32
Package Type
32-Lead (450-Mil) Molded SOIC
Operating
Range
Commercial
32-Lead TSOP II
32-Lead (450-Mil) Molded SOIC
32-Lead TSOP II
32-Lead (450-Mil) Molded SOIC
32-Lead TSOP II
32-Lead (450-Mil) Molded SOIC
Industrial
32-Lead TSOP II
32-Lead (450-Mil) Molded SOIC
32-Lead TSOP II
32-Lead (450-Mil) Molded SOIC
32-Lead TSOP II
32-Lead (450-Mil) Molded SOIC
Commercial
32-Lead TSOP II
32-Lead (450-Mil) Molded SOIC
32-Lead TSOP II
32-Lead (450-Mil) Molded SOIC
32-Lead TSOP II
32-Lead (450-Mil) Molded SOIC
32-Lead TSOP II
32-Lead (450-Mil) Molded SOIC
32-Lead TSOP II
32-Lead (450-Mil) Molded SOIC
32-Lead TSOP II
7
Industrial
PRELIMINARY
CY62148
Package Diagrams
32-Lead (450-Mil) Molded SOIC S34
51-85081-A
8
PRELIMINARY
CY62148
Package Diagrams (continued)
32-Lead TSOP II ZS32
51-85095
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.