CYPRESS CY7C1512-15ZC

1CY 7C15 12
PRELIMINARY
CY7C1512
64K x 8 Static RAM
Features
• High speed
— tAA = 15 ns
• CMOS for optimum speed/power
• Low active power
— 770 mW
• Low standby power
— 28 mW
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options
Functional Description
The CY7C1512 is a high-performance CMOS static RAM organized as 65,536 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE1), an active
HIGH chip enable (CE2), an active LOW output enable (OE),
and three-state drivers. This device has an automatic power-down feature that reduces power consumption by more
than 75% when deselected.
Writing to the device is accomplished by taking chip enable
one (CE1) and write enable (WE) inputs LOW and chip enable
two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through
I/O7) is then written into the location specified on the address
pins (A0 through A15).
Reading from the device is accomplished by taking chip enable one (CE1) and output enable (OE) LOW while forcing
write enable (WE) and chip enable two (CE2) HIGH. Under
these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
The CY7C1512 is available in standard TSOP type I and
450-mil-wide plastic SOIC packages.
Logic Block Diagram
Pin Configurations
SOIC
Top View
NC
NC
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
I/O0
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
A7
I/O1
I/O2
I/O3
64K x 8
ARRAY
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
NC
A14
A12
A7
A6
A5
A4
I/O4
I/O5
CE 1
CE2
WE
COLUMN
DECODER
I/O6
POWER
DOWN
I/O7
OE
1512-1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
TSOP I
Top View
(not to scale)
1512-2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
Selection Guide
Maximum Access Time (ns)
Maximum Operating
Commercial
Current (mA)
Maximum CMOS
Commercial
Standby Current (mA)
Cypress Semiconductor Corporation
•
7C1512-15
15
140
7C1512-20
20
130
7C1512-25
25
120
7C1512-35
35
110
7C1512-70
70
110
5
5
5
5
5
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
June 1996 – Revised October 1996
PRELIMINARY
Maximum Ratings
CY7C1512
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL–STD–883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Latch-Up Current ..................................................... >200 mA
Operating Range
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V
Range
DC Voltage Applied to Outputs
in High Z State[1] .....................................–0.5V to VCC +0.5V
Commercial
Industrial
Ambient
Temperature[2]
VCC
0°C to +70°C
5V ± 10%
–40°C to +85°C
5V ± 10%
DC Input Voltage[1]..................................–0.5V to VCC +0.5V
Electrical Characteristics Over the Operating Range[3]
Parameter
Description
Test Conditions
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
7C1512-15
7C1512-20
7C1512-25
Min.
Min.
Min.
Max.
Unit
VOL
Output LOW Voltage
0.4
V
VIH
Input HIGH Voltage
2.2
VCC +
0.3
2.2
VCC +
0.3
2.2
VCC +
0.3
V
VIL
Input LOW Voltage[1]
–0.3
0.8
–0.3
0.8
–0.3
0.8
V
IIX
Input Load Current
–1
+1
–1
+1
–1
+1
µA
IOZ
Output Leakage Current
–5
+5
–5
+5
–5
+5
µA
Current[4]
IOS
Output Short Circuit
ICC
VCC Operating
Supply Current
VCC = Max., VOUT = GND
VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC
ISB1
Automatic CE
Power–Down Current
— TTL Inputs
ISB2
Automatic CE
Power–Down Current
— CMOS Inputs
2.4
Max.
Output HIGH Voltage
GND < VI < VCC
GND < VI < VCC,Output Disabled
2.4
Max.
VOH
0.4
Description
V
0.4
–300
–300
–300
mA
140
130
120
mA
Max. VCC, CE1 > VIH or
CE2 < VIL, VIN > VIH or VIN < VIL,
f = fMAX
40
30
30
mA
Max. VCC, CE1 > VCC – 0.3V,
or CE2 < 0.3V, VIN > VCC – 0.3V,
or VIN < 0.3V, f=0
5
5
5
mA
7C1512-35
Parameter
2.4
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
Min.
Max.
2.4
7C1512-70
Min.
0.4
Voltage[1]
Max.
2.4
Unit
V
0.4
V
2.2
VCC+ 0.3
2.2
VCC+ 0.3
V
–0.3
0.8
–0.3
0.8
V
–1
+1
–1
+1
µA
+5
–5
VIL
Input LOW
IIX
Input Load Current
IOZ
Output Leakage Current
+5
µA
IOS
Output Short
Circuit Current[4]
VCC = Max., VOUT = GND
–300
–300
mA
ICC
VCC Operating
Supply Current
VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC
110
110
mA
ISB1
Automatic CE
Power-Down Current
— TTL Inputs
Max. VCC, CE1 > VIH or CE2 < VIL,
VIN > VIH or VIN < VIL, f = fMAX
25
25
mA
ISB2
Automatic CE
Power-Down Current
— CMOS Inputs
Max. VCC, CE1 > VCC – 0.3V, or CE2 <
0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f=0
5
5
mA
GND < VI < VCC
GND < VI < VCC, Output Disabled
–5
Notes:
1. VIL (min.) = -2.0V for pulse durations of less than 20 ns.
2. TA is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
2
PRELIMINARY
CY7C1512
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
9
pF
9
pF
AC Test Loads and Waveforms
ALL INPUT PULSES
R1 480Ω
R1 480Ω
5V
5V
OUTPUT
3.0V
90%
OUTPUT
R2
255Ω
30 pF
R2
255Ω
5 pF
INCLUDING
JIG AND
SCOPE
(a)
INCLUDING
JIG AND
SCOPE
(b)
90%
10%
GND
10%
<3ns
< 3 ns
1512-3
1512-4
Equivalent to:
OUTPUT
THVENIN EQUIVALENT
167Ω
1.73V
Switching Characteristics [3, 6] Over the Operating Range
Parameter
Description
7C1512-15
7C1512-20
7C1512-25
Min.
Min.
Min.
Max.
Max.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
20
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW to Data Valid, CE2 HIGH to Data Valid
15
20
25
ns
tDOE
OE LOW to Data Valid
7
8
10
ns
tLZOE
OE LOW to Low Z
15
3
tHZOE
OE HIGH to High
tLZCE
CE1 LOW to Low Z, CE2 HIGH to Low Z[8]
20
3
0
Z[7, 8]
7
tHZCE
CE1 HIGH to High Z, CE2 LOW to High
tPU
CE1 LOW to Power-Up, CE2 HIGH to Power-Up
tPD
CE1 HIGH to Power-Down, CE2 LOW to Power-Down
25
8
7
10
8
15
ns
5
0
ns
ns
10
0
20
ns
ns
0
3
0
ns
5
0
3
Z[7, 8]
25
ns
ns
25
ns
WRITE CYCLE[9]
tWC
Write Cycle Time
15
20
25
ns
tSCE
CE1 LOW to Write End, CE2 HIGH to Write End
12
15
20
ns
tAW
Address Set-Up to Write End
12
15
20
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
12
15
20
ns
tSD
Data Set-Up to Write End
8
10
15
ns
tHD
Data Hold from Write End
0
0
0
ns
Z[8]
tLZWE
WE HIGH to Low
tHZWE
WE LOW to High Z[7, 8]
5.
6.
7.
8.
9.
3
3
7
5
8
ns
10
ns
Tested initially and after any design or process changes that may affect these parameters.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write,
and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the write.
3
PRELIMINARY
CY7C1512
Switching Characteristics[3, 6] Over the Operating Range (continued)
7C1512-35
Parameter
Description
Min.
Min.
7C1512-70
Min.
Min.
Unit
READ CYCLE
tRC
Read Cycle Time
35
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW to Data Valid, CE2 HIGH to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z
35
5
15
OE HIGH to High
tLZCE
CE1 LOW to Low Z, CE2 HIGH to Low Z[8]
15
Z[7, 8]
tPU
tPD
CE1 HIGH to Power-Down, CE2 LOW to Power-Down
70
ns
15
ns
ns
15
5
15
0
ns
ns
15
0
35
ns
ns
0
5
CE1 HIGH to High Z, CE2 LOW to High
CE1 LOW to Power-Up, CE2 HIGH to Power-Up
WRITE
70
35
Z[7, 8]
ns
5
0
tHZOE
tHZCE
70
ns
ns
70
ns
CYCLE[9]
tWC
Write Cycle Time
35
70
ns
tSCE
25
60
ns
tAW
CE1 LOW to Write End, CE2 HIGH to Write End
Address Set-Up to Write End
25
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
25
60
ns
tSD
Data Set-Up to Write End
20
55
ns
tHD
Data Hold from Write End
0
0
ns
Z[8]
tLZWE
WE HIGH to Low
tHZWE
WE LOW to High Z[7, 8]
5
5
15
ns
15
ns
Switching Waveforms
Read Cycle No. 1 [10, 11]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
1512-5
Notes:
10. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
11. WE is HIGH for read cycle.
4
PRELIMINARY
CY7C1512
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled) [11, 12]
ADDRESS
tRC
CE1
CE2
tACE
OE
tHZOE
tDOE
DATA OUT
tHZCE
tLZOE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
ICC
50%
50%
ISB
1512-6
Write Cycle No. 1 (CE1 or CE2 Controlled) [13, 14]
tWC
ADDRESS
tSCE
CE1
tSA
CE2
tSCE
tAW
tHA
WE
tSD
DATA I/O
tHD
DATA VALID
1512-7
Notes:
12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
13. Data I/O is high impedance if OE = VIH.
14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
5
PRELIMINARY
CY7C1512
Switching Waveforms (continued)
Read Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]
tWC
ADDRESS
tSCE
CE1
CE2
tSCE
tAW
t HA
tSA
tPWE
WE
OE
tSD
DATA I/O
t HD
DATA INVALID
NOTE 15
tHZOE
Write Cycle No. 3 (WE Controlled, OE LOW)
1512-8
[14]
tWC
ADDRESS
tSCE
CE1
CE2
tSCE
tAW
tSA
tHA
tPWE
WE
tSD
DATA I/O
NOTE 15
tHD
DATA VALID
tLZWE
tHZWE
1512-9
Note:
15. During this period the I/Os are in the output state and input signals should not be applied.
6
PRELIMINARY
CY7C1512
Truth Table
I/O0 − I/O7
CE1
CE2
OE
WE
Mode
Power
H
X
X
X
High Z
Power-Down
Standby (I SB)
X
L
X
X
High Z
Power-Down
L
H
L
H
Data Out
Read
Standby (I SB)
Active (ICC)
L
H
X
L
Data In
Write
Active (ICC)
L
H
H
H
High Z
Selected, Outputs Disabled
Active (ICC)
Ordering Information
Speed
(ns)
15
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C1512-15SC
S34
32-Lead (450-Mil) Molded SOIC
CY7C1512-15ZC
Z32
32-Lead TSOP Type I
CY7C1512-20ZI
Z32
32-Lead TSOP Type I
Industrial
CY7C1512-20SC
S34
32-Lead (450-Mil) Molded SOIC
Commercial
CY7C1512-20ZC
Z32
32-Lead TSOP Type I
CY7C1512-20ZI
Z32
32-Lead TSOP Type I
Industrial
CY7C1512-25SC
S34
32-Lead (450-Mil) Molded SOIC
Commercial
CY7C1512-25ZC
Z32
32-Lead TSOP Type I
CY7C1512-25ZI
Z32
32-Lead TSOP Type I
Industrial
35
CY7C1512-35SC
S34
32-Lead (450-Mil) Molded SOIC
Commercial
70
CY7C1512-70SC
S34
32-Lead (450-Mil) Molded SOIC
Commercial
20
25
CY7C1512-70ZC
Z32
32-Lead TSOP Type I
CY7C1512-70ZI
Z32
32-Lead TSOP Type I
Shaded areas contain advanced information.
Document #: 38-00522-A
7
Commercial
Industrial
PRELIMINARY
CY7C1512
Package Diagrams
32-Lead (450 -Mil) Molded SOIC S34
32-Lead Thin Small Outline Package Z32
© Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.