ONSEMI MC10E452FN

MC10E452, MC100E452
5VECL 5-Bit Differential
Register
Description
The MC10E/100E452 is a 5-bit differential register with differential
data (inputs and outputs) and clock. The registers are triggered by a
positive transition of the positive clock (CLK) input. A high on the
Master Reset (MR) asynchronously resets all registers so that the Q
outputs go LOW.
The differential input structures are clamped so that the inputs of
unused registers can be left open without upsetting the bias network of
the device. The clamping action will assert the D and the CLK sides of
the inputs. Because of the edge triggered flip-flop nature of the device
simultaneously opening both the clock and data inputs will result in an
output which reaches an unidentified but valid state. Note that the
input clamps only operate when both inputs fall to 2.5 V below VCC.
The fully differential design of the device makes it ideal for very
high frequency applications where a registered data path is necessary.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Differential D, CLK and Q; VBB Reference Available
1100 MHz Min. Toggle Frequency
Asynchronous Master Reset
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
Internal Input 50 kW Pulldown Resistors, Output Q3 will Default to
Low State When Inputs Are Left Open
ESD Protection: Human Body Model; > 2 kV
Machine Model; > 200 V
Charged Device Model; > 2 kV
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level:
Pb = 1
Pb−Free = 3
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 315 devices
Pb−Free Packages are Available*
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PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1 28
MCxxxE452FNG
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 11
1
Publication Order Number:
MC10E452/D
MC10E452, MC100E452
D3
D3
D4
D4 VCCO Q4
Q4
25
24
23
22
19
21
20
Table 1. PIN DESCRIPTION
MR
26
18
Q3
CLK
27
17
CLK
28
VEE
PIN
FUNCTION
D[0:4], D[0:4]
ECL Differential Data Inputs
Q3
MR
ECL Master Reset Input
16
VCC
CLK, CLK
ECL Differential Clock Input
1
15
Q2
Q[0:4], Q[0:4]
ECL Differential Data Outputs
VBB
2
14
Q2
VBB
Reference Voltage Output
VCC, VCCO
Positive Supply
D2
3
13
Q1
VEE
Negative Supply
D2
4
12
Q1
5
6
7
D1
D1
D0
8
9
10
11
D0 VCCO Q0
Q0
* All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
Figure 1. Pinout: PLCC−28 (Top View)
D0
D0
D
Q
Q0
Q0
R
D1
D1
D
Q
Q1
Q1
R
D2
D2
D
Q
Q2
Q2
Q
Q3
Q3
Q
Q4
R
D3
D3
D
R
D4
D4
D
Q4
CLK
CLK
R
MR
VBB
Figure 2. Logic Diagram
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2
MC10E452, MC100E452
Table 2. MAXIMUM RATINGS
Rating
Unit
VCC
Symbol
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
Condition 2
8
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
−6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
0 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
PLCC−28
22 to 26
°C/W
Tsol
Wave Solder
265
265
°C
VI v VCC
VI w VEE
Pb
Pb−Free
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. 10E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 1)
−40°C
Symbol
Characteristic
Min
0°C
Typ
Max
74
89
Min
25°C
Typ
Max
74
89
Min
85°C
Typ
Max
74
89
Min
Typ
Max
Unit
74
89
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage
(Note 2)
3980
4070
4160
4020
4105
4190
4090
4185
4280
mV
VOL
Output LOW Voltage
(Note 2)
3050
3210
3370
3050
3210
3370
3050
3227
3405
mV
VIH
Input HIGH Voltage
(Single−Ended)
3830
3995
4160
3870
4030
4190
3940
4110
4280
mV
VIL
Input LOW Voltage (Single−
Ended)
3050
3285
3520
3050
3285
3520
3050
3302
3555
mV
VBB
Output Voltage Reference
3.62
3.74
3.65
3.75
3.69
3.81
V
VIHCMR
Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 3)
2.2
4.6
2.2
4.6
2.2
4.6
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
3.57
3.7
150
150
0.5
0.3
150
0.5
0.25
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
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3
MC10E452, MC100E452
Table 4. 10E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 4)
−40°C
Symbol
Characteristic
Min
0°C
Typ
Max
74
89
Min
25°C
Typ
Max
74
89
Min
85°C
Typ
Max
74
89
Min
Typ
Max
Unit
74
89
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage
(Note 5)
−1020
−930
−840
−980
−895
−810
−910
−815
−720
mV
VOL
Output LOW Voltage
(Note 5)
−1950
−1790
−1630
−1950
−1790
−1630
−1950
−1773
−1595
mV
VIH
Input HIGH Voltage
(Single−Ended)
−1170
−1005
−840
−1130
−970
−810
−1060
−890
−720
mV
VIL
Input LOW Voltage
(Single−Ended)
−1950
−1715
−1480
−1950
−1715
−1480
−1950
−1698
−1445
mV
VBB
Output Voltage Reference
−1.38
−1.27
−1.35
−1.25
−1.31
−1.19
V
VIHCMR
Input HIGH Voltage
Common Mode Range
(Differential Configuration)
(Note 6)
−2.8
−0.4
−2.8
−0.4
−2.8
−0.4
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
−1.43
−1.3
150
150
0.5
0.3
150
0.5
0.065
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
5. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
6. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
Table 5. 100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 7)
−40°C
Symbol
Characteristic
Max
74
89
3975
4050
4120
Output LOW Voltage
(Note 8)
3190
3295
VIH
Input HIGH Voltage
(Single−Ended)
3835
VIL
Input LOW Voltage
(Single−Ended)
3190
VBB
Output Voltage Reference
VIHCMR
Input HIGH Voltage Common Mode Range (Differential Configuration)
(Note 9)
IIH
Input HIGH Current
IIL
Input LOW Current
Power Supply Current
VOH
Output HIGH Voltage
(Note 8)
VOL
3.62
Typ
Max
74
89
3.74
Min
25°C
Typ
IEE
Min
0°C
Typ
Max
74
89
3975
4050
4120
3380
3190
3255
3975
4120
3835
3355
3525
3190
3.62
3.74
2.2
4.6
150
Min
85°C
Typ
Max
Unit
85
102
mA
3975
4050
4120
mV
3380
3190
3260
3380
mV
3975
4120
3835
3975
4120
mV
3355
3525
3190
3355
3525
mV
3.62
3.74
3.62
3.74
V
2.2
4.6
2.2
4.6
V
150
mA
150
0.5
0.3
Min
150
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
8. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
9. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
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MC10E452, MC100E452
Table 6. 100E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 10)
−40°C
Symbol
Characteristic
Min
0°C
Typ
Max
74
89
Min
25°C
Typ
Max
74
89
Min
85°C
Typ
Max
74
89
Min
Typ
Max
Unit
85
102
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage
(Note 11)
−1025
−950
−880
−1025
−950
−880
−1025
−950
−880
mV
VOL
Output LOW Voltage
(Note 11)
−1810
−1705
−1620
−1810
−1745
−1620
−1810
−1740
−1620
mV
VIH
Input HIGH Voltage
(Single−Ended)
−1165
−1025
−880
−1165
−1025
−880
−1165
−1025
−880
mV
VIL
Input LOW Voltage
(Single−Ended)
−1810
−1645
−1475
−1810
−1645
−1475
−1810
−1645
−1475
mV
VBB
Output Voltage Reference
−1.38
−1.26
−1.38
−1.26
−1.38
−1.26
V
VIHCMR
Input HIGH Voltage Common
Mode Range
(Differential Configuration)
(Note 12)
−2.8
−0.4
−2.8
−0.4
−2.8
−0.4
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
−1.38
−1.26
150
150
0.5
150
0.3
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
10. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
11. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
12. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
Table 7. AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 13)
−40°C
Symbol
Characteristic
Min
Typ
fMAX
Maximum Toggle Frequency
1.1
tPLH
tPHL
Propagation Delay to Output CLK (Diff)
CLK (SE)
MR
425
375
375
600
600
625
tS
Setup Time
D
175
tH
Hold Time
D
tRR
Reset Recovery Time
tPW
Minimum Pulse Width
tskew
Within-Device Skew (Note 14)
tJITTER
Random Clock Jitter (RMS)
VPP
Input Voltage Swing
(Differential Configuration)
150
tr/tf
Rise/Fall Times 20−80%
250
CLK
MR
25°C
Max
Min
Typ
85°C
Max
1.1
850
900
900
600
600
625
−50
150
225
50
750
450
800
850
900
GHz
−50
150
−50
ps
200
50
200
50
ps
700
450
700
450
< 1.0
150
800
850
900
400
400
< 1.0
725
Unit
600
600
625
50
475
Max
475
425
425
400
400
1000
Typ
1.1
475
425
425
400
400
Min
1000
ps
50
ps
< 1.0
ps
150
275
ps
475
1000
mV
675
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
13. 10 Series: VEE can vary −0.46 V / +0.06 V.
100 Series: VEE can vary −0.46 V / +0.8 V.
14. Within-device skew is defined as identical transitions on similar paths through a device.
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MC10E452, MC100E452
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping †
MC10E452FN
PLCC−28
37 Units / Rail
MC10E452FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC10E452FNR2
PLCC−28
500 / Tape & Reel
MC10E452FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
MC100E452FN
PLCC−28
37 Units / Rail
MC100E452FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC100E452FNR2
PLCC−28
500 / Tape & Reel
MC100E452FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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MC10E452, MC100E452
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
−N−
0.007 (0.180)
B
Y BRK
T L−M
M
0.007 (0.180)
U
M
N
S
T L−M
S
S
N
S
D
Z
−M−
−L−
W
28
D
X
V
1
A
0.007 (0.180)
R
0.007 (0.180)
C
M
M
T L−M
T L−M
S
S
N
S
N
S
0.007 (0.180)
H
N
S
S
G
J
0.004 (0.100)
−T− SEATING
T L−M
S
N
T L−M
S
N
S
K
PLANE
F
VIEW S
G1
M
K1
E
S
T L−M
S
VIEW D−D
Z
0.010 (0.250)
0.010 (0.250)
G1
VIEW S
S
NOTES:
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
−−−
0.025
−−−
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
−−− 0.020
2_
10_
0.410
0.430
0.040
−−−
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7
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
−−−
0.64
−−−
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
−−−
0.50
2_
10_
10.42
10.92
1.02
−−−
0.007 (0.180)
M
T L−M
S
N
S
MC10E452, MC100E452
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
MC10E452/D