MC100EL14 5V ECL 1:5 Clock Distribution Chip The MC100EL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The EL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. • MARKING DIAGRAM 50 ps Output-to-Output Skew 100EL14 AWLYYWWG Synchronous Enable/Disable Multiplexed Clock Input The 100 Series Contains Temperature Compensation 1 PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Q Output will Default LOW with Inputs Open or at VEE • • Internal Input Pull−down Resistors on All Inputs, Pull−up Resistors • SOIC−20L DW SUFFIX CASE 751D 20 Features • • • • • http://onsemi.com on Inverted Inputs Pb−Free Packages are Available* A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 October, 2006 − Rev. 7 1 Publication Order Number: MC100EL14/D MC100EL14 VCC 20 EN VCC NC SCLK CLK CLK VBB 19 17 18 16 15 14 13 SEL VEE 12 11 Table 1. PIN DESCRIPTION PIN 10 D Q 1 Q0 2 Q0 3 Q1 4 Q1 5 Q2 6 Q2 7 Q3 8 Q3 9 Q4 FUNCTION CLK, CLK ECL Diff Clock Inputs SCLK ECL Scan Clock Input EN ECL Sync Enable SEL ECL Clock Select Input Q0−4, Q0−4 ECL Diff Clock Outputs 10 VBB Reference Voltage Output Q4 VCC Positive Supply VEE Negative Supply NC No Connect * All VCC pins are tied together on the die. Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Table 2. FUNCTION TABLE Figure 1. Logic Diagram and Pinout Assignment CLK* L H X X X SCLK* SEL* EN* Q X X L H X L L H H X L L L L H L H L H L (Note ) 1. On next negative transition of CLK or SCLK **Pins will default low when left open. Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor 75 kW ESD Protection Human Body Model Machine Model Charge Device Model Moisture Sensitivity (Note 2) Flammability Rating > 2 kV > 200 V > 4 kV Level 1 Oxygen Index: 28 to 34 Transistor Count UL 94 V−0 @ 0.125 in 303 Devices Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. http://onsemi.com 2 MC100EL14 Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 8 V VEE NECL Mode Power Supply VCC = 0 V −8 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−20L SOIC−20L 90 60 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−20L 30 to 35 °C/W Tsol Wave Solder <2 to 3 sec @ 248°C <2 to 3 sec @ 260°C 265 265 °C Pb Pb−Free VI ≤ VCC VI ≥ VEE Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 3 MC100EL14 Table 5. 100EL SERIES PECL DC CHARACTERISTICS VCC = 5.0 V; VEE = 0.0 V (Note 3) −40°C Symbol Characteristic Min 25°C Typ Max 32 40 Min 85°C Typ Max 32 40 Min Typ Max Unit 34 42 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 4) 3915 3995 4120 3975 4045 4120 3975 4050 4120 mV VOL Output LOW Voltage (Note 4) 3170 3305 3445 3190 3295 3380 3190 3295 3380 mV VIH Input HIGH Voltage (Single−Ended) 3835 4120 3835 4120 3835 4120 mV VIL Input LOW Voltage (Single−Ended) 3190 3525 3190 3525 3190 3525 mV VBB Output Voltage Reference 3.62 3.74 3.62 3.74 3.62 3.74 V VIHCMR Common Mode Range (Differential Configuration) (Note 5) VPP < 500 mV VPP ≥ 500 mV IIH Input HIGH Current IIL Input LOW Current V 1.3 1.5 4.6 4.6 1.2 1.4 4.6 4.6 150 0.5 1.2 1.4 4.6 4.6 150 0.5 150 0.5 mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Input and output parameters vary 1:1 with VCC.VEE can vary +0.8 V / −0.5 V. 4. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC.The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak−to−peak voltage lies between VPP(min) and 1 V. Table 6. 100EL SERIES NECL DC CHARACTERISTICSVCC = 0.0 V; VEE = −5.0 V (Note 6) −40°C Typ Max 32 40 Max 32 40 −1085 −1005 −880 −1025 −955 −880 Output LOW Voltage (Note 7) −1830 −1695 −1555 −1810 −1705 VIH Input HIGH Voltage (Single−Ended) −1165 −880 VIL Input LOW Voltage (Single−Ended) −1810 VBB Output Voltage Reference −1.38 VIHCMR Common Mode Range (Differential Configuration) (Note 8) VPP < 500 mV VPP ≥ 500 mV Characteristic Power Supply Current VOH Output HIGH Voltage (Note 7) VOL IIH Input HIGH Current IIL Input LOW Current Min 85°C Typ Symbol IEE Min 25°C Min Typ Max Unit 34 42 mA −1025 −955 −880 mV −1620 −1810 −1705 −1620 mV −1165 −880 −1165 −880 mV −1475 −1810 −1475 −1810 −1475 mV −1.26 −1.38 −1.26 −1.38 −1.26 V V −3.7 −3.5 −0.4 −0.4 −3.8 −3.6 150 0.5 −0.4 −0.4 −3.8 −3.6 150 0.5 −0.4 −0.4 150 0.5 mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. Input and output parameters vary 1:1 with VCC.VEE can vary +0.8 V / −0.5 V. 7. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC.The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak−to−peak voltage lies between VPP(min)and 1 V. http://onsemi.com 4 MC100EL14 Table 7. AC CHARACTERISTICS VCC = 5.0 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −5.0 V (Note 9) −40°C Min Characteristic Symbol Typ 25°C Max Min 1 Typ 85°C Max Min Typ Maximum Toggle Frequency (See Figure 2, fMAX/Jitter) tPLH tPHL Prop Delay tSKEW Part-to-Part Skew Within-Device Skew (Note 10) tJITTER Random Clock Jitter (RMS) @ 1 GHz (See Figure 2, fMAX/Jitter) tS Setup Time EN 0 0 −133 0 ps tH Hold Time EN 250 250 140 250 ps VPP Input Swing (Note 11) 150 1000 150 1000 150 1000 mV tr tf Output Rise/Fall Times Q (20% − 80%) 230 500 230 500 230 500 ps 520 470 470 720 770 770 580 530 530 680 680 680 200 50 1 Unit fmax CLK to Q (Diff) CLK to Q (SE) SCLK to Q 1 Max 780 830 830 630 580 580 200 50 1 1 GHz 830 880 880 ps 200 50 ps 1 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. VEE can vary +0.8 V / −0.5 V. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 10. Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW transitions. 11. VPP(min) is the minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40. 800 2.0 700 VOUTPP (mV) Jitter 600 500 1.0 400 0.5 300 200 200 400 600 800 1000 1200 FIN (MHz) Figure 2. Output Voltage Amplitude / RMS Jitter vs. Input Frequency at Ambient Temperature (Typical) http://onsemi.com 5 0 1400 JITTEROUT ps (RMS) 1.5 VOUTPP MC100EL14 Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION4 Package Shipping† MC100EL14DW SOIC−20L 38 Units / Rail MC100EL14DWG SOIC−20L (Pb−Free) 38 Units / Rail MC100EL14DWR2 SOIC−20L 1000 / Tape & Reel MC100EL14DWR2G SOIC−20L (Pb−Free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 MC100EL14 Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 7 MC100EL14 PACKAGE DIMENSIONS SO−20 WB CASE 751D−05 ISSUE G A 20 q X 45 _ E h H M 10X 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 1 10 20X B B 0.25 M T A S B S L A 18X e A1 SEATING PLANE C T DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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