ETC EUA4992/4992A

芯美电子
EUA4992/4992A
2.25W Stereo Audio Power Amplifier
DESCRIPTION
FEATURES
The EUA4992/4992A are dual bridge-connected audio
power amplifiers, capable of delivering 1.25W of
continuous average power to an 8Ω BTL with less than 1%
distortion (THD+N) from a 5.0V power supply, and
540mW to an 8Ω BTL load from a 3.3V power supply.
The EUA4992/4992A provide high quality audio while
requiring few external components and minimal power
consumption. They feature a low-power shutdown mode,
which is achieved by driving the SHUTDOWN pin with
logic low.
The EUA4992/4992A contain circuitry to prevent
from ”pop and click” noise that would otherwise occur
during turn-on and turn-off transitions.
For maximum flexibility, the EUA4992/4992A provide an
externally controlled gain (with resistors), as well as an
externally controlled turn-on and turn-off times (with the
bypass capacitor).
The EUA4992/4992A are available in a 16-pin TQFN
package.
Output Power at 10% THD+N, VDD=5V
-- 2.25W/CH (typ) into a 4Ω Load
-- 1.54W/CH (typ) into a 8Ω Load
Output Power at 1% THD+N, VDD=5V
-- 1.9W/CH (typ) into a 4Ω Load
-- 1.25W/CH (typ) into a 8Ω Load
Output Power at 1% THD+N, VDD=3.3V
-- 0.75W/CH (typ) into a 4Ω Load
-- 0.54W/CH (typ) into a 8Ω Load
Shutdown Current 0.06µA (typ)
Supply Voltage Range 2.5V to 5.5V
“Click and Pop” Suppression
Thermal Shutdown Protection Circuitry
Available in 3mm×3mm TQFN-16 (EUA4992)
and 4mm×4mm TQFN-16 (EUA4992A) Packages
RoHS compliant and 100% lead(Pb)-free
APPLICATIONS
Cell Phones
Portable and Desktop Computers
Portable Audio System
Multimedia Monitors
Typical Application Circuit
Figure 1.
DS4992/4992A Ver 0.1 Mar. 2008
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EUA4992/4992A
Pin Configurations
Package Type
Pin Configurations
TQFN-16
Pin Description
NAME
PIN
I/O
INA
4
I
Left Channel Input
INB
8
I
Right Channel Input
-OUTA
3
O
Left Channel –Output
+OUTA
1
O
Left Channel +Output
-OUTB
10
O
Right Channel –Output
+OUTB
12
O
Right Channel +Output
VDD
2,11
SHUTDOWN
15
BYPASS
9
GND
5,6,7,13,14,16
DS4992/4992A Ver 0.1 Mar. 2008
DESCRIPTION
Supply Voltage
I
Shutdown control, hold low for shutdown mode
Bypass capacitor which provides the common mode voltage
GND
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EUA4992/4992A
Ordering Information
Order Number
Package Type
EUA4992JIR1
TQFN-16
EUA4992AJIR1
TQFN-16
EUA4992/A
Marking
xxxxx
4992
xxxxx
4992A
Operating Temperature Range
-40 °C to 85°C
-40 °C to 85°C
□ □ □ □
Lead Free Code
1: Lead Free 0: Lead
Packing
R: Tape & Reel
Operating temperature range
I: Industry Standard
Package Type
J: TQFN
DS4992/4992A Ver 0.1 Mar. 2008
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EUA4992/4992A
Absolute Maximum Ratings
▓
Supply voltage ----------------------------------------------------------------------------------------------
6V
▓
Input voltage --------------------------------------------------------------------------------- -0.3 V to VDD +0.3V
▓
Storage temperature rang, Tstg
▓
Junction Temperature --------------------------------------------------------------------------------------
------------------------------------------------------------------- -65°C to 150°C
150°C
Recommended Operating Conditions
Min
Max
Unit
Supply voltage (from AC input),VCC
2.5
5.5
V
Operating junction temperature range, TJ
-40
150
°C
Electrical Characteristics (5V)
The following specifications apply for VDD=5V unless otherwise noted. Limits apply for TA=25°C.
Symbol
VDD
Parameter
Conditions
IDD
Supply Voltage
Quiescent Power Supply
Current
VIN=0V,IO=0A
ISD
Shutdown Current
GND applied to the shutdown pin
2.5
TWU
Shutdown Input Voltage
High
Shutdown Input Voltage
Low
Turn on time
1µF bypass cap (C4)
VOS
Output Offset Voltage
VIN=0V
VIH
VIL
PO
THD+N
PSRR
EUA4992/4992A
Unit
Min Typ Max.
5.5
V
5
8
mA
0.06
1
µA
1.1
V
0.9
107
5
V
ms
25
mV
THD+N=1%, f=1KHz RL=4Ω (Note 1)
1.90
W
THD+N=1%, f=1KHz RL=8Ω
1.25
W
THD+N=10%, f=1KHz RL=4Ω (Note 1)
2.25
W
THD+N=10%, f=1KHz RL=8Ω
1.54
W
Total Harmonic Distortion +
Noise
1KHz, Avd=2 RL=8Ω,Po=1W
0.06
%
Power Supply Rejection
Ratio
Input grounded f=217Hz Vripple=200m
Vp-p C4=1µF, RL=8Ω
Input grounded f=1KHz Vripple=200m
Vp-p C4=1µF, RL=8Ω
Input unterminated f=217Hz
Vripple=200m Vp-p C4=1µF, RL=8Ω
Input unterminated f=1KHz
Vripple=200m Vp-p C4=1µF, RL=8Ω
Output Power
51
63
dB
69
66
Xtalk
Channel separation
f=1KHz, C4=1µF
95
dB
VNO
Output noise voltage
1KHz
11
uVrms
Note 1. The thermal performance of the QFN package when used with the exposed-DAP connected to a thermal plane is
sufficient for driving 4Ω loads.
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EUA4992/4992A
Electrical Characteristics (3.3V)
The following specifications apply for VDD=3.3V unless otherwise noted. Limits apply for TA=25°C.
Symbol
Parameter
Conditions
EUA4992/4992A
Unit
Min Typ Max.
IDD
Quiescent Power Supply
Current
VIN=0V,IO=0A
3.8
mA
ISD
Shutdown Current
GND applied to the shutdown pin
0.02
µA
TWU
Shutdown Input Voltage
High
Shutdown Input Voltage
Low
Turn on time
1µF bypass cap (C4)
VOS
Output Offset Voltage
VIN=0V
VIH
VIL
PO
THD+N
PSRR
0.9
V
0.8
V
105
ms
5
mV
THD+N=1%, f=1KHz RL=4Ω (Note 1)
0.75
W
THD+N=1%, f=1KHz RL=8Ω
0.54
W
THD+N=10%, f=1KHz RL=4Ω (Note 1)
0.93
W
THD+N=10%, f=1KHz RL=8Ω
0.64
W
Total Harmonic Distortion +
Noise
1KHz, Avd=2 RL=8Ω,Po=0.25W
0.076
%
Power Supply Rejection
Ratio
Input grounded f=217Hz Vripple=200m
Vp-p C4=1µF, RL=8Ω
Input grounded f=1KHz Vripple=200m
Vp-p C4=1µF, RL=8Ω
Input unterminated f=217Hz
Vripple=200m Vp-p C4=1µF, RL=8Ω
Input unterminated f=1KHz
Vripple=200m Vp-p C4=1µF, RL=8Ω
Output Power
51
64
dB
76
70
Xtalk
Channel separation
f=1KHz, C4=1µF
95
dB
VNO
Output noise voltage
1KHz
11
uVrms
Note 1. The thermal performance of the QFN package when used with the exposed-DAP connected to a thermal plane is
sufficient for driving 4Ω loads.
DS4992/4992A Ver 0.1 Mar. 2008
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EUA4992/4992A
Typical Operating Characteristics
Figure2.
Figure3.
Figure4.
Figure5.
Figure6.
DS4992/4992A Ver 0.1 Mar. 2008
Figure7.
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EUA4992/4992A
Figure8.
Figure9.
Figure10.
Figure11.
Figure12.
Figure13.
DS4992/4992A Ver 0.1 Mar. 2008
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EUA4992/4992A
Figure14.
Figure15.
Figure16.
Figue17.
Power Dissipation vs Output Power, VDD=5V
1.4
4 ohm
POWER DISSIPATION(W)
1.2
1.0
0.8
8 ohm
0.6
0.4
0.2
0.0
0.0
0.5
1.0
1.5
OUTPUT POWER(W)
Figure19.
Figure18.
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2.0
2.5
芯美电子
EUA4992/4992A
Power Dissipation vs Output Power, VDD=2.6V
Power Dissipation vs Output Power, VDD=3.3V
0.40
0.6
4 ohm
POWER DISSIPATION(W)
POWER DISSIPATION(W)
0.35
4 ohm
0.5
0.4
8 ohm
0.3
0.2
0.1
0.30
0.25
8 ohm
0.20
0.15
0.10
0.05
0.00
0.0
0.0
0.2
0.4
0.6
0.8
0.0
1.0
0.1
0.2
0.3
0.4
0.5
0.6
OUTPUT POWER(W)
OUTPUT POWER(W)
Figure20.
Figure21.
Output Power vs Supply Voltage, RL=4 ohm
Output Power vs Supply Voltage, RL=8 ohm
3.0
F=1KHz
2.0
F=1KHz
1.8
2.5
OUTPUT POWER(W)
OUTPUT POWER(W)
1.6
2.0
10% THD+N
1.5
1% THD+N
1.0
0.5
1.4
10% THD+N
1.2
1.0
1% THD+N
0.8
0.6
0.4
0.2
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
SUPPLY VOLTAGE(V)
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE(V)
Figure22.
Figure23.
Output Power vs Supply Voltage, RL=16 ohm
1.2
F=1KHz
1.1
1.0
OUTPUT POWER(W)
0.9
0.8
10% THD+N
0.7
0.6
0.5
1% THD+N
0.4
0.3
0.2
0.1
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE(V)
Figure24.
DS4992/4992A Ver 0.1 Mar. 2008
Figure25.
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5.0
5.5
芯美电子
EUA4992/4992A
Figure26.
DS4992/4992A Ver 0.1 Mar. 2008
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EUA4992/4992A
Application Information
Bridged Configuration Explanation
As shown in Figure 1, the EUA4992/4992A consists of two
pairs of operational amplifiers, forming a two-channel
(channel A and channel B) stereo amplifier. (Though the
following discusses channel A, it applies equally to channel
B.) External resistors Rf and Ri set the closed-loop gain of
Amp1A, whereas two internal 20kΩ resistors set Amp2A’s
gain at -1. The EUA4992/4992A drives a load, such as a
speaker, connected between the two amplifier outputs,
-OUTA and +OUTA.
Figure 1 shows that Amp1A’s output serves as Amp2A’s
input. This results in both amplifiers producing signals
identical in magnitude, but 180° out of phase. Taking
advantage of this phase difference, a load is placed
between –OUTA and +OUTA and driven differentially
(commonly referred to as "bridge mode"). This results in a
differential gain of
(
A VD = 2 × R f / R i
)
(1)
Bridge mode amplifiers are different from single-ended
amplifiers that drive loads connected between a single
amplifier’s output and ground. For a given supply voltage,
bridge mode has a distinct advantage over the single-ended
configuration: its differential output doubles the voltage
swing across the load. This produces four times the output
power when compared to a single-ended amplifier under the
same conditions. This increase in attainable output power
assumes that the amplifier is not current limited or that the
output signal is not clipped. To ensure minimum output
signal clipping when choosing an amplifier’s closed-loop
gain, refer to the Audio Power Amplifier Design section.
Another advantage of the differential bridge output is no net
DC voltage across the load. This is accomplished by biasing
channel A’s and channel B’s outputs at half-supply. This
eliminates the coupling capacitor that single supply, single
ended amplifiers require. Eliminating an output coupling
capacitor in a single-ended configuration forces a
single-supply amplifier’s half-supply bias voltage across the
load. This increases internal IC power dissipation and may
permanently damage loads such as speakers.
Power Supply Bypassing
As with any power amplifier, proper supply bypassing is
critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator
typically use a 10µF in parallel with a 0.1µF filter
capacitors to stabilize the regulator’s output, reduce noise
on the supply line, and improve the supply’s transient
response. However, their presence does not eliminate the
need for a local 1.0µF tantalum bypass capacitance
connected between the EUA4992/4992A’s supply pins
and ground. Do not substitute a ceramic capacitor for the
tantalum. Doing so may cause oscillation in the output
signal. Keep the length of leads and traces that connect
DS4992/4992A Ver 0.1 Mar. 2008
capacitors between the EUA4992/4992A’s power supply
pin and ground as short as possible. Connecting a 1µF
capacitor, CB, between the BYPASS pin and ground
improves the internal bias voltage’s stability and improves
the amplifier’s PSRR. The PSRR improvements increase
as the bypass pin capacitor value increases. Too large,
however, increases turn-on time and can compromise
amplifier’s click and pop performance. The selection of
bypass capacitor values, especially CB, depends on
desired PSRR requirements, click and pop performance
(as explained in the section, Proper Selection of
External Components), system cost, and size constraints.
Micro-Power Shutdown
The voltage applied to the SHUTDOWN pin controls the
EUA4992/4992A’s
shutdown
function.
Activate
micro-power shutdown by applying VDD to the
SHUTDOWN pin. When active, the EUA4992/4992A’s
micro-power shutdown feature turns off the amplifier’s
bias circuitry, reducing the supply current.
There are a few ways to control the micro-power
shutdown. These include using a single-pole, single-throw
switch, a microprocessor, or a microcontroller. When
using a switch, connect an external 10kΩ pull-up resistor
between the SHUTDOWN pin and VDD. Connect the
switch between the SHUTDOWN pin and ground. Select
normal amplifier operation by closing the switch.
Opening the switch connects the SHUTDOWN pin to
VDD through the pull-up resistor, disable micro-power
shutdown. The switch and resistor guarantee that the
SHUTDOWN pin will not float. This prevents unwanted
state changes. In a system with a microprocessor or a
microcontroller, use a digital output to apply the control
voltage to the SHUTDOWN pin. Driving the
SHUTDOWN pin with active circuitry eliminates the pull
up resistor.
Table 1. Logic Level Truth Table for
Shutdown Operation
SHUTDOWN
OPERATIONAL MODE
High
Full power, stereo BTL amplifiers
Low
Micro-power Shutdown
Selecting Proper External Components
Optimizing the EUA4992/4992A’s performance requires
properly selecting external components. Though the
EUA4992/4992A operates well when using external
components with wide tolerances, best performance is
achieved by optimizing component values.
The EUA4992/4992A is unity-gain stable, giving a
designer maximum design flexibility. The gain should be
set to no more than a given application requires. This
allows the amplifier to achieve minimum THD+N and
maximum signal-to-noise ratio. These parameters are
compromised as the closed-loop gain increases. However,
low gain demands input signals with greater voltage
swings to achieve maximum output power. Fortunately,
many signal sources such as audio CODECs have outputs
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of 1VRMS (2.83VP-P). Please refer to the Audio Power
Amplifier Design section for more information on
selecting the proper gain.
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires high
value input coupling capacitor (Ci in Figure 1). A high
value capacitor can be expensive and may compromise
space efficiency in portable designs. In many cases,
however, the speakers used in portable systems, whether
internal or external, have little ability to reproduce signals
below 150Hz. Applications using speakers with this
limited frequency response reap little improvement by
using large input capacitor.
Besides effecting system cost and size, Ci has an affect on
the EUA4992/4992A’s click and pop performance. When
the supply voltage is first applied, a transient (pop) is
created as the charge on the input capacitor changes from
zero to a quiescent state. The magnitude of the pop is
directly proportional to the input capacitor’s size. Higher
value capacitors need more time to reach a quiescent DC
voltage (usually VDD/2) when charged with a fixed current.
The amplifier’s output charges the input capacitor through
the feedback resistor, Rf. Thus, pops can be minimized by
selecting an input capacitor value that is no higher than
necessary to meet the desired -3dB frequency.
A shown in Figure 1, the input resistor (RI) and the input
capacitor, CI produce a -3dB high pass filter cutoff
frequency that is found using Equation (2).
1
(2)
2 πR IN C I
As an example when using a speaker with a low
frequency limit of 150Hz, CI. The 1.0µF CI shown in
Figure 1 allows the EUA4992/4992A to drive high
efficiency, full range speaker whose response extends
below 30Hz.
Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful
consideration should be paid to value of CB, the capacitor
connected to the BYPASS pin. Since CB determines how
fast the EUA4992/4992A settles to quiescent operation,
its value is critical when minimizing turn-on pops. The
slower the EUA4992/4992A’s outputs ramp to their
quiescent DC voltage (nominally 1/2 VDD), the smaller the
turn-on pop. Choosing CB equal to 1.0µF along with a
small value of Ci (in the range of 0.1µF to 0.39µF),
produces a click-less and pop-less shutdown function. As
discussed above, choosing Ci no larger than necessary for
the desired bandwidth helps minimize clicks and pops.
Optimizing Click and Pop Reduction Performance
The EUA4992/4992A contains circuitry to minimize
turn-on and shutdown transients or "clicks and pop". For
this discussion, turn-on refers to either applying the power
supply voltage or when the shutdown mode is deactivated.
While the power supply is ramping to its final value, the
f _3dB =
DS4992/4992A Ver 0.1 Mar. 2008
EUA4992/4992A’s internal amplifiers are configured as
unity gain buffers. An internal current source changes the
voltage of the BYPASS pin in a controlled, linear manner.
Ideally, the input and outputs track the voltage applied to
the BYPASS pin. The gain of the internal amplifiers
remains unity until the voltage on the bypass pin reaches
1/2 VDD. As soon as the voltage on the BYPASS pin is
stable, the device becomes fully operational. Although the
bypass pin current cannot be modified, changing the size
of CB alters the device’s turn-on time and the magnitude
of "clicks and pops". Increasing the value of CB reduces
the magnitude of turn-on pops. However, this presents a
tradeoff: as the size of CB increases, the turn-on time
increases. There is a linear relationship between the size
of CB and the turn-on time.
In order eliminate "clicks and pops", all capacitors must
be discharged before turn-on. Rapidly switching VDD may
not allow the capacitors to fully discharge, which may
cause "clicks and pops".
Audio Power Amplifier Design
Audio Amplifier Design: Driving 1W into an 8Ω Load
The following are the desired operational parameters:
Power Output:
1WRMS
Load Impedance:
8Ω
Input Level:
1VRMS
Input Impedance:
20kΩ
Bandwidth:
100Hz-20 kHz ± 0.25 dB
The design begins by specifying the minimum supply
voltage necessary to obtain the specified output power.
One way to find the minimum supply voltage is to use the
Output Power vs Supply Voltage curve in the Typical
Performance Characteristics section. Another way,
using Equation (4), is to calculate the peak output voltage
necessary to achieve the desired output power for a given
load impedance. To account for the amplifier’s dropout
voltage, two additional voltages, based on the Dropout
Voltage vs Supply Voltage in the Typical Performance
Characteristics curves, must be added to the result
obtained by Equation (3). The result in Equation (4).
Vopeak =
(2R L PO )
VDD ≥ (VOUTPEAK + (VOD TOP + VOD BOT ))
(3)
(4)
The Output Power vs Supply Voltage graph for an 8Ω
load indicates a minimum supply voltage of 4.6V. This is
easily met by the commonly used 5V supply voltage. The
additional voltage creates the benefit of headroom,
allowing the EUA4992/4992A to produce peak output
power in excess of 1W without clipping or other audible
distortion. The choice of supply voltage must also not
create a situation that violates maximum power
dissipation as explained above in the Power Dissipation
section.
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After satisfying the EUA4992/4992A’s power dissipation
requirements, the minimum differential gain is found
using Equation (5).
A VD ≥
(PO R L ) / (VIN ) = Vorms / Vinrms
(5)
Thus, a minimum gain of 2.83 allows the
EUA4992/4992A’s to reach full output swing and
maintain low noise and THD+N performance. For this
example, let AVD = 3.
The amplifier’s overall gain is set using the input (Ri) and
feedback (Rf) resistors. With the desired input impedance
set at 20kΩ, the feedback resistor is found using Equation
(6).
(6)
R f / R i = A VD / 2
The value of Rf is 30 kΩ.
The last step in this design example is setting the
amplifier’s -3dB frequency bandwidth. To achieve the
desired ±0.25dB pass band magnitude variation limit, the
low frequency response must extend to at least one-fifth
the lower bandwidth limit and the high frequency
response must extend to at least five times the upper
bandwidth limit. The gain variation for both response
limits is 0.17dB, well within the ±0.25dB desired limit.
The results are an
and an
f L = 100 Hz / 5 = 20 Hz
FH = 20 kHz × 5 = 100 kHz
Thermal Pad Considerations
The thermal pad must be connected to ground. The
package with thermal pad of the EUA4992/4992A
requires special attention on thermal design. If the
thermal design issues are not properly addressed, the
EUA4992/4992A will go into thermal shutdown when
driving a heavy load.
The thermal pad on the bottom of the EUA4992/4992A
should be soldered down to a copper pad on the circuit
board. Heat can be conducted away from the thermal pad
through the copper plane to ambient. If the copper plane
is not on the top surface of the circuit board, 8 to 10 vias
of 13 mil or smaller in diameter should be used to
thermally couple the thermal pad to the bottom plane.
For good thermal conduction, the vias must be plated
through and solder filled. The copper plane used to
conduct heat away from the thermal pad should be as
large as practical.
If the ambient temperature is higher than 25℃,a larger
copper plane or forced-air cooling will be required to
keep the EUA4992/4992A junction temperature below
the thermal shutdown temperature (150℃). In higher
ambient temperature, higher airflow rate and/or larger
copper area will be required to keep the IC out of thermal
shutdown.
(7)
(8)
As mentioned in the External Components section, Ri
and Ci create a highpass filter that sets the amplifier’s
lower bandpass frequency limit. Find the coupling
capacitor’s value using Equation (9).
1
2 πR i f C
(9)
1 / (2 π ∗ 20 kΩ ∗ 20 Hz ) = 0.398 µF
(10)
Ci ≥
the result is
Use a 0.39µF capacitor, the closest standard value. The
product of the desired high frequency cutoff (100kHz in
this example) and the differential gain, AVD, determines
the upper pass band response limit. With AVD = 3 and fH =
100kHz, the closed-loop gain bandwidth product (GBWP)
is 300kHz. This is less than the EUA4992/4992A’s
3.5MHz GBWP. With this margin, the amplifier can be
used in designs that require more differential gain while
avoiding performance-lrestricting bandwidth limitations.
DS4992/4992A Ver 0.1 Mar. 2008
13
联系电话：１５９９９６４４５７９　８３１５１７１５
芯美电子
EUA4992/4992A
Packaging Information
TQFN-16 (3mm × 3mm)
SYMBOLS
A
A1
b
E
D
D1
E1
e
L
DS4992/4992A Ver 0.1 Mar. 2008
MILLIMETERS
MIN.
MAX.
0.70
0.80
0.00
0.05
0.18
0.30
2.90
3.10
2.90
3.10
1.70
1.70
0.50
0.30
0.50
INCHES
MIN.
0.028
0.000
0.007
0.114
0.114
MAX.
0.031
0.002
0.012
0.122
0.122
0.067
0.067
0.020
0.012
0.020
14
联系电话：１５９９９６４４５７９　８３１５１７１５
芯美电子
EUA4992/4992A
TQFN-16 (4mm × 4mm)
DETAILA
SYMBOLS
A
A1
b
E
D
D1
E1
e
L
DS4992/4992A Ver 0.1 Mar. 2008
MILLIMETERS
MIN.
MAX.
0.70
0.80
0.00
0.05
0.25
0.35
3.90
4.10
3.90
4.10
2.50
2.50
0.65
0.30
0.50
INCHES
MIN.
0.028
0.000
0.009
0.153
0.153
MAX.
0.031
0.002
0.014
0.161
0.161
0.098
0.098
0.026
0.012
0.020
15
联系电话：１５９９９６４４５７９　８３１５１７１５