June 2007 HYB18T512161B2F–20/25 512-Mbit x16 DDR2 SDRAM DDR2 SDRAM RoHS compliant Internet Data Sheet Rev. 1.1 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM HYB18T512161B2F–20/25 Revision History: 2007-06, Rev. 1.1 Page Subjects (major changes since last revision) All Typo Changes We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] qag_techdoc_rev400 / 3.2 QAG / 2006-08-01 05152007-ZYAH-ACMZ 2 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 1 Overview This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family for graphics application and describes its main characteristics. 1.1 Features The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features: • Data masks (DM) for write data • 1.8 V ± 0.1V VDD for [–20/–25] • 1.8 V ± 0.1V VDDQ for [–20/–25] • Posted CAS by programmable additive latency for better • DRAM organizations with 16 data in/outputs command and data bus efficiency • Double Data Rate architecture: • Off-Chip-Driver impedance adjustment (OCD) and On– two data transfers per clock cycle Die-Termination (ODT) for better signal quality. – four internal banks for concurrent operation • Auto-Precharge operation for read and write bursts • Programmable CAS Latency: 3, 4, 5, 6, 7 • Auto-Refresh, Self-Refresh and power saving PowerDown modes • Programmable Burst Length: 4 and 8 • Average Refresh Period 7.8 μs at a TCASE lower than 85 • Differential clock inputs (CK and CK) • Bi-directional, differential data strobes (DQS and DQS) are °C, 3.9 μs between 85 °C and 95 °C transmitted / received with data. Edge aligned with read • Full Strength and reduced Strength (60%) Data-Output Drivers data and center-aligned with write data. • DLL aligns DQ and DQS transitions with clock • 2kB page size • Packages: P-TFBGA-84 • DQS can be disabled for single-ended data strobe operation • RoHS Compliant Products1) • Commands entered on each positive clock edge, data and data mask are referenced to both edges of DQS TABLE 1 Ordering Information for RoHS compliant products Product Number Org. Clock (MHz) Package HYB18T512161B2F–20/25 ×16 500/400 P-TFBGA-84 1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 3 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 1.2 Description All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion. A 15-bit address bus is used to convey row, column and bank address information in a RAS-CAS multiplexing style. An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. The DDR2 SDRAM is available in P-TFBGA package. The 512-Mb DDR2 DRAM is a high-speed Double-DataRate-Two CMOS DRAM device containing 536,870,912 bits and internally configured as a quad-bank DRAM. The 512-Mb device is organized as 8 Mbit × 16 I/O × 4 banks chip. These devices achieve high speed transfer rates starting at 800 Mb/sec/pin for general applications. The device is designed to comply with all DDR2 DRAM key features: 1. posted CAS with additive latency, 2. write latency = read latency - 1, 3. normal and weak strength data-output driver, 4. Off-Chip Driver (OCD) impedance adjustment 5. On-Die Termination (ODT) function. Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 4 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 2 Configuration 2.1 Chip Configuration The chip configuration of a DDR2 SDRAM is listed by function in Table 2. The abbreviations used in the Ball# and Buffer Type columns are explained in Table 3 and Table 4 respectively. The ball numbering for the FBGA package is depicted in Figure 1. TABLE 2 Chip Configuration of DDR2 SDRAM Ball# Name Ball Type Buffer Type Function J8 CK I SSTL K8 CK I SSTL Clock Signal CK, Complementary Clock Signal CK Note: CK and CK are differential system clock inputs. All address and control inputs are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossing of CK and CK (both direction of crossing) K2 CKE I SSTL Clock Enable Note: CKE HIGH activates and CKE LOW deactivates internal clock signals and device input buffers and output drivers. Taking CKE LOW provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active PowerDown (row Active in any bank). CKE is synchronous for power down entry and exit and for self-refresh entry. Input buffers excluding CKE are disabled during self-refresh. CKE is used asynchronously to detect self-refresh exit condition. Self-refresh termination itself is synchronous. After VREF has become stable during power-on and initialisation sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained HIGH throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down K7 RAS I SSTL L7 CAS I SSTL Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) K3 WE I SSTL L8 CS I SSTL Clock Signals Control Signals Chip Select Address Signals Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 5 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM Ball# Name Ball Type Buffer Type Function L2 BA0 I SSTL Bank Address Bus 1:0 L3 BA1 I SSTL L1 NC I SSTL M8 A0 I SSTL M3 A1 I SSTL M7 A2 I SSTL N2 A3 I SSTL N8 A4 I SSTL N3 A5 I SSTL N7 A6 I SSTL P2 A7 I SSTL P8 A8 I SSTL P3 A9 I SSTL M2 A10 I SSTL AP I SSTL P7 A11 I SSTL R2 A12 I SSTL G8 DQ0 I/O SSTL G2 DQ1 I/O SSTL H7 DQ2 I/O SSTL H3 DQ3 I/O SSTL H1 DQ4 I/O SSTL H9 DQ5 I/O SSTL F1 DQ6 I/O SSTL Address Signal 12:0, Address Signal 10/Autoprecharge Data Signals F9 DQ7 I/O SSTL C8 DQ8 I/O SSTL C2 DQ9 I/O SSTL D7 DQ10 I/O SSTL D3 DQ11 I/O SSTL D1 DQ12 I/O SSTL D9 DQ13 I/O SSTL B1 DQ14 I/O SSTL B9 DQ15 I/O SSTL UDQS I/O SSTL Data Signal 15:0 Note: Bi-directional data bus. DQ[15:0] Data Strobe B7 A8 UDQS I/O SSTL F7 LDQS I/O SSTL E8 LDQS I/O SSTL Data Strobe Upper Byte Note: UDQS corresponds to the data on DQ[15:8] Data Strobe Lower Byte Note: LDQS corresponds to the data on DQ[7:0] Data Mask Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 6 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM Ball# Name Ball Type Buffer Type Function B3 UDM I SSTL F3 LDM I SSTL Data Mask Upper/Lower Byte Note: LDM and UDM are the input mask signals and control the lower or upper bytes. VDDQ VDD VSSQ VSS PWR – I/O Driver Power Supply PWR – Power Supply PWR – I/O Driver Power Supply PWR – Power Supply VREF VDDQ VDDL VDD VSSQ VSSDL VSS AI – I/O Reference Voltage PWR – I/O Driver Power Supply PWR – Power Supply PWR – Power Supply PWR – I/O Driver Power Supply PWR – Power Supply PWR – Power Supply NC – Not Connected I SSTL On-Die Termination Control Note: ODT is applied to each DQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM signal. An EMRS(1) control bit enables or disables the ODT functionality. Power Supplies A9,C1,C3,C7,C9 A1 A7,B2,B8,D2,D8 A3,E3 Power Supplies J2 E9, G1, G3, G7, G9 J1 E1, J9, M9, R1 E7, F2, F8, H2, H8 J7 A3, E3,J3,N1,P9 Not Connected A2, E2, R3, R7, R8, L1 NC Other Balls K9 ODT TABLE 3 Abbreviations for Ball Type Abbreviation Description I Standard input-only ball. Digital levels. O Output. Digital levels. I/O I/O is a bidirectional input/output signal. AI Input. Analog levels. PWR Power GND Ground NC Not Connected Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 7 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM TABLE 4 Abbreviations for Buffer Type Abbreviation Description SSTL Serial Stub Terminated Logic (SSTL_18) LV-CMOS Low Voltage CMOS CMOS CMOS Levels OD Open Drain. The corresponding ball has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR. FIGURE 1 Chip Configuration, PG-TFBGA-84 (top view) $ 6664 8'46 6''4 8'0 % 8'46 6664 '4 '4 6''4 & 6''4 '4 6''4 '4 6664 '4 ' '4 6664 '4 6'' 1& 666 ( 6664 /'46 6''4 '4 6664 /'0 ) /'46 6664 '4 6''4 '4 6''4 * 6''4 '4 6''4 '4 6664 '4 + '4 6664 '4 6''/ 65() 666 - 966 '/ &. 6'' &.( :( . 5$6 &. 2'7 %$ %$ / &$6 &6 $ $3 $ 0 $ $ $ $ 1 $ $ $ $ 3 $ $ $ 1& 5 1& 1& 6'' .# 666 '4 6664 6''4 1& 666 6'' 6'' 666 0337 Notes 2. LDM is the data mask signal for DQ[7:0], UDM is the data mask signal for DQ[15:8] 3. VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VDD, VDDQ, VSSDL, VSS, and VSSQ are isolated on the device. 1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is data strobe for DQ[7:0] Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 8 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 2.2 512 Mbit DDR2 Addressing TABLE 5 512-Mbit DDR2 Addressing Configuration 32-Mbit x 16 Bank Address BA[1:0] Number of Banks 4 Auto-Precharge A10 / AP Note Row Address A[12:0] Column Address A[9:0] Number of Column Address Bits 10 1) Number of I/Os 16 2) Page Size [Bytes] 2048 (2K) 3) 1) Referred to as ’colbits’ 2) Referred to as ’org’ 3) PageSize = 2colbits× org/8 [Bytes Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 9 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 3 Functional Description % $ % $ $ $ $ $ $ $ $ $ $ $ $ $ $ 3 ' : 5 ' / / 7 0 & / % 7 % / Z Z ZZ Z Z Z U H J D G G U TABLE 6 Mode Register Definition (BA[1:0] = 00B) Field Bits Type1) Description BA1 14 reg. addr. Bank Address [1] BA1 Bank Address 0B BA0 13 PD 12 w Active Power-Down Mode Select PD Fast exit 0B 1B PD Slow exit WR [11:9] w Write Recovery2) Note: All other bit combinations are illegal. Bank Address [0] 0B BA0 Bank Address 001B 010B 011B 100B 101B 110B WR 2 WR 3 WR 4 WR 5 WR 6 WR 7 DLL 8 w DLL Reset DLL No 0B 1B DLL Yes TM 7 w Test Mode 0B TM Normal Mode 1B TM Vendor specific test mode CL [6:4] w CAS Latency Note: All other bit combinations are illegal. 010B 011B 100B 101B 110B 111B Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ CL reserved CL 3 CL 4 CL 5 CL 6 CL 7 10 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM Field Bits Type1) Description BT 3 w Burst Type 0B BT Sequential BT Interleaved 1B BL [2:0] w Burst Length Note: All other bit combinations are illegal. 010B BL 4 011B BL 8 1) w = write only register bits 2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer: WR [cycles] ≥ tWR (ns) / tCK (ns). The mode register must be programmed to fulfill the minimum requirement for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by tCK.MIN. % $ $ $ $ $ $ $ $ $ $ $ $ % $ $ $ 4 R I I 2 & ' 3 U R J U D P ' 4 6 5 W W U H J D G G U $ / 5 ' , & ' / / W W Z Z Z Z Z Z Z TABLE 7 Extended Mode Register Definition (BA[1:0] = 01B) Field Bits Type1) Description BA1 14 reg. addr. Bank Address [1] 0B BA1 Bank Address BA0 13 Qoff 12 DQS 10 Bank Address [0] BA0 Bank Address 1B w OCD [9:7] Program Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ Output Disable 0B QOff Output buffers enabled QOff Output buffers disabled 1B Complement Data Strobe (DQS Output) 0B DQS Enable 1B DQS Disable Off-Chip Driver Calibration Program 000B OCD OCD calibration mode exit, maintain setting 001B OCD Drive (1) 010B OCD Drive (0) 100B OCD Adjust mode 111B OCD OCD calibration default 11 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM Type1) Field Bits AL [5:3] Description Additive Latency Note: All other bit combinations are illegal. 000B 001B 010B 011B 100B 101B 110B AL 0 AL 1 AL 2 AL 3 AL 4 AL 5 AL 6 RTT 6,2 Nominal Termination Resistance of ODT 00B RTT ∞ (ODT disabled) 01B RTT 75 Ohm 10B RTT 150 Ohm 11B RTT 50 Ohm DIC 1 Off-chip Driver Impedance Control DIC Full (Driver Size = 100%) 0B 1B DIC Reduced DLL 0 DLL Enable 0B DLL Enable 1B DLL Disable 1) w = write only register bits %$ %$ $ $ $ $ $ $ 65) $ $ $ $ $ $ $ 3$65 UHJDGGU TABLE 8 EMRS(2) Programming Extended Mode Register Definition (BA[1:0]=10B) Field Bits Type1) BA1 14 reg. addr., Bank Address [1] 1B BA1 Bank Address BA0 13 Bank Address [0] BA0 Bank Address 0B A [12:8] w Address Bus 00000B A Address bits SRF 7 w Address Bus, High Temperature Self Refresh Rate for TCASE > 85°C 0B A7 disable 1B A7 enable 2) A [6:3] w Address Bus 0000B A Address bits Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ Description 12 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM Field Type1) Bits Description Partial Self Refresh for 4 banks PASR [2:0] Address Bus, Partial Array Self Refresh for 4 Banks3) 000B PASR0 Full Array 001B PASR1 Half Array (BA[1:0]=00, 01) 010B PASR2 Quarter Array (BA[1:0]=00) 011B PASR3 Not defined 100B PASR4 3/4 array (BA[1:0]=01, 10, 11) 101B PASR5 Half array (BA[1:0]=10, 11) 110B PASR6 Quarter array (BA[1:0]=11) 111B PASR7 Not defined w 1) w = write only 2) When DRAM is operated at 85°C ≤ TCase ≤ 95°C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self refresh mode can be entered. 3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued % $ % $ $ $ $ $ $ $ $ $ $ $ $ $ $ U H J D G G U 0 3 % 7 TABLE 9 EMR(3) Programming Extended Mode Register Definition (BA[1:0]=10B) Type 1) Field Bits BA1 14 Bank Adress[1] BA1 Bank Address 1B BA0 13 Bank Adress[0] 1B BA0 Bank Address A [12:0] w Description Address Bus[12:0] 0B A[12:0] Address bits 1) w = write only TABLE 10 ODT Truth Table Input Pin EMRS(1) Address Bit A10 DQ[7:0] X DQ[15:8] X LDQS X LDQS 0 UDQS X UDQS 0 Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ EMRS(1) Address Bit A11 X X 13 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM Input Pin EMRS(1) Address Bit A10 LDM X UDM X EMRS(1) Address Bit A11 Note: X = don’t care; 0 = bit set to low; 1 = bit set to high TABLE 11 Burst Length and Sequence Burst Length Starting Address (A2 A1 A0) Sequential Addressing (decimal) Interleave Addressing (decimal) 4 x00 0, 1, 2, 3 0, 1, 2, 3 8 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 Notes 2. Order of burst access for sequential addressing is “nibblebased” and therefore different from SDR or DDR components 1. PageSize and Length is a function of I/O organization:32Mb (CA[9:0]); Page Size = 2 kByte; Page Length = 1024 Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 14 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 4 Truth Tables TABLE 12 Command Truth Table Function CKE CS RAS CAS WE BA0 BA1 A[12:11] A10 A[9:0] Note1)2)3) Previous Cycle Current Cycle (Extended) Mode Register Set H H L L L L BA OP Code Auto-Refresh H H L L L H X X X X 4) Self-Refresh Entry H L L L L H X X X X 4)6) Self-Refresh Exit L H H X X X X X X X 4)6)7) L H H H 4)5) Single Bank Precharge H H L L H L BA X L X 4)5) Precharge all Banks H H L L H L X X H X 4) Bank Activate H H L L H H BA Row Address Write H H L H L L BA Column L Column 4)5)8) Write with AutoPrecharge H H L H L L BA Column H Column 4)5)8) Read H H L H L H BA Column L Column 4)5)8) Read with AutoPrecharge H H L H L H BA Column H Column 4)5)8) No Operation H X L H H H X X X X 4) Device Deselect H X H X X X X X X X 4) Power Down Entry H L H X X X X X X X 4)9) L H H H H X X X X X X X 4)9) L H H H Power Down Exit L H 4)5) 1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 2) “X” means “H or L (but a defined logic level)”. 3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock. 5) Bank addresses BA[1:0] determine which bank is to be operated upon. For (E)MRS BA[1:0] selects an (Extended) Mode Register. 6) VREF must be maintained during Self Refresh operation. 7) Self Refresh Exit is asynchronous. 8) Burst reads or writes at BL = 4 cannot be terminated. 9) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 15 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM TABLE 13 Clock Enable (CKE) Truth Table for Synchronous Transitions Current State1) CKE Command Action (N)2) (N)2)3)RAS, CAS, WE, CS Note4)5) Previous Cycle6) (N-1) Current Cycle6) (N) L L X Maintain Power-Down 7)8)11) L H DESELECT or NOP Power-Down Exit 7)9)10)11) L L X Maintain Self Refresh 8)11)12) L H DESELECT or NOP Self Refresh Exit 9)12)13)14) Bank(s)Active H L DESELECT or NOP Active Power-Down Entry 7)9)10)11)15) All Banks Idle H L DESELECT or NOP Precharge Power-Down Entry 9)10)11)15) H L AUTOREFRESH Self Refresh Entry 7)11)14)16) Any State other H than listed above H Refer to the Command Truth Table Power-Down Self Refresh 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) 14) 15) 16) 17) 17) Current state is the state of the DDR2 SDRAM immediately prior to clock edge N. Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. CKE must be maintained HIGH while the device is in OCD calibration mode. Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge. The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh requirements “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1)). All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only. tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2×tCKE + tIH. VREF must be maintained during Self Refresh operation. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. Valid commands for Self Refresh Exit are NOP and DESELCT only. Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or Refresh operations are in progress. Self Refresh mode can only be entered from the All Banks Idle state. Must be a legal command as defined in the Command Truth Table. TABLE 14 Data Mask (DM) Truth Table Name (Function) DM DQs Note Write Enable L Valid 1) Write Inhibit H X 1) 1) Used to mask write data; provided coincident with the corresponding data. Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 16 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 5 Electrical Characteristics TABLE 15 DRAM Component Operating Temperature Range Symbol Parameter Rating Unit Notes TCASE Operating Temperature 0 to 95 °C 1)2)3)4) 1) Operating Temperature is the case surface temperature on the center / top side of the DRAM. 2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case temperature must be maintained between 0 - 95 °C under all other specification parameters. 3) Above 85 °C case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 μs. 4) When operating this product in the 85°C to 95°C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to “1“. Note, when the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50% 5.1 Absolute Maximum Ratings TABLE 16 Absolute Maximum Ratings Symbol VDD VDDQ VDDL VIN, VOUT TJ TSTG Parameter Rating Unit Notes min max Voltage on VDD pin relative to VSS –1.0 2.3 V 1) Voltage on VDDQ pin relative to VSS –0.5 2.3 V 1) Voltage on VDDL pin relative to VSS –0.5 2.3 V 1) Voltage on any pin relative to VSS –0.5 2.3 V 1) 125 °C 1) 150 °C 1)2) Junction Temperature Storage Temperature –55 1) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2) Storage Temperature is the case surface temperature on the center/top side of the DRAM. Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 17 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 5.2 DC Characteristics TABLE 17 Recommended DC Operating Conditions (SSTL_18) Symbol VDD VDDDL VDDQ VREF VTT Parameter Rating Unit Notes Min. Typ. Max. Supply Voltage 1.7 1.8 1.9 V 1)2) Supply Voltage for DLL 1.7 1.8 1.9 V 1)2) Supply Voltage for Output 1.7 1.8 1.9 V 1)2) Input Reference Voltage 0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ V 3)4) Termination Voltage VREF – 0.04 VREF VREF + 0.04 V 5) 1) HYB18T512161B2F–20/25 2) VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together. 3) The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 × VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 4) Peak to peak ac noise on VREF may not exceed ± 2% VREF (dc) 5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in die dc level of VREF. TABLE 18 ODT DC Electrical Characteristics Parameter / Condition Symbol Min. Nom. Max. Unit Note Termination resistor impedance value for EMRS(1)[A6,A2] = [0,1]; 75 Ohm Rtt1(eff) 60 75 90 Ω 1) Termination resistor impedance value for EMRS(1)[A6,A2] =[1,0]; 150 Ohm Rtt2(eff) 120 150 180 Ω 1) Termination resistor impedance value for EMRS(1)(A6,A2)=[1,1]; 50 Ohm Rtt3(eff) 40 50 60 Ω 1) Deviation of VM with respect to VDDQ / 2 delta VM –6.00 — + 6.00 % 2) 1) Measurement Definition for Rtt(eff): Apply VIH(ac) and VIL(ac) to test pin separately, then measure current I(VIHac) and I(VILac) respectively. Rtt(eff) = (VIH(ac) – VIL(ac)) /(I(VIHac) – I(VILac)). 2) Measurement Definition for VM: Turn ODT on and measure voltage (VM) at test pin (midpoint) with no load: delta VM = ((2 x VM / VDDQ) – 1) x 100% TABLE 19 Input and Output Leakage Currents Symbol Parameter / Condition Min. Max. Unit Notes IIL Input Leakage Current; any input 0 V < VIN < VDD –2 +2 μA 1) IOL Output Leakage Current; 0 V < VOUT < VDDQ –5 +5 μA 2) 1) all other pins not under test = 0 V 2) DQ’s, LDQS, LDQS, UDQS, UDQS, DQS, DQS are disabled and ODT is turned off Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 18 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 5.3 DC & AC Characteristics DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1) “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timing are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is verified by design and characterization but not subject to production test. In single ended mode, the DQS signals are internally disabled and don’t care. TABLE 20 DC & AC Logic Input Levels Symbol Parameter Min. Max. Units VIH(dc) VIL(dc) VIH(ac) VIL(ac) DC input logic high VREF + 0.125 V DC input low –0.3 VDDQ + 0.3 VREF – 0.125 AC input logic high VREF + 0.250 — V AC input low — VREF – 0.250 V V TABLE 21 Single-ended AC Input Test Conditions Symbol Condition Value Unit Notes VREF VSWING.MAX Input reference voltage 0.5 x VDDQ V 1) Input signal maximum peak to peak swing 1.0 V 1) SLEW Input signal minimum Slew Rate 1.0 V / ns 2)3) 1) Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2) The input signal minimum Slew Rate is to be maintained over the range from VIH(ac).MIN to VREF for rising edges and the range from VREF to VIL(ac).MAX for falling edges as shown in Figure 2 3) AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 19 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM FIGURE 2 Single-ended AC Input Test Conditions Diagram 9''4 9,+DFPLQ 9,+GFPLQ 96:,1*0$ ; 95() 9,/GFPD[ 9,/DFPD[ 966 GHOWD7) GHOWD75 PLQ 95( 9 ) 5LV LQ J6OH Z ,+ D F GHOWD75 95( ) 9,/D FPD[ )DOOLQ J6OHZ GHOWD7) TABLE 22 Differential DC and AC Input and Output Logic Levels Symbol VIN(dc) VID(dc) VID(ac) VIX(ac) VOX(ac) 1) 2) 3) 4) Parameter Min. Max. DC input signal voltage –0.3 DC differential input voltage 0.25 AC differential input voltage 0.5 AC differential cross point input voltage 0.5 × VDDQ – 0.175 AC differential cross point output voltage 0.5 × VDDQ – 0.125 VDDQ + 0.3 VDDQ + 0.6 VDDQ + 0.6 0.5 × VDDQ + 0.175 0.5 × VDDQ + 0.125 Unit Notes — 1) — 2) V 3) V 4) V 5) VIN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc. VID(dc) specifies the input differential voltage VTR– VCP required for switching. The minimum value is equal to VIH(dc) – VIL(dc). VID(ac) specifies the input differential voltage VTR – VCP required for switching. The minimum value is equal to VIH(ac) – VIL(ac). The value of VIX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac) indicates the voltage at which differential input signals must cross. 5) The value of VOX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac) indicates the voltage at which differential input signals must cross. FIGURE 3 Differential DC and AC Input and Output Logic Levels Diagram 9'' 4 975 &URVVLQJ3RLQW 9,' 9,;RU9 2; 9&3 9664 Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 20 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 5.4 Output Buffer Characteristics TABLE 23 Full Strength Calibrated Pull-up Driver Characteristics Voltage (V) Calibrated Pull-up Driver Current [mA] Nominal(18 Nominal Minimum1) Nominal Low2)(18.75 Ohms) ohms)3) (21 Ohms) Nominal High2)(17.25 Ohms) Nominal Maximum4) (15 Ohms) 0.2 –9.5 –10.7 –11.4 –11.8 –13.3 0.3 –14.3 –16.0 –16.5 –17.4 –20.0 0.4 –18.3 –21.0 –21.2 –23.0 –27.0 1) 2) 3) 4) The driver characteristics evaluation conditions are Nominal Minimum 95 °C (TCASE). VDDQ = 1.7 V, any process The driver characteristics evaluation conditions are Nominal Low and Nominal High 25 °C (TCASE), VDDQ = 1.8 V, any process The driver characteristics evaluation conditions are Nominal 25 °C (TCASE), VDDQ = 1.8 V, typical process The driver characteristics evaluation conditions are Nominal Maximum 0 °C (TCASE), VDDQ = 1.9 V, any process TABLE 24 Full Strength Calibrated Pull-down Driver Characteristics Voltage (V) Calibrated Pull-down Driver Current [mA] Nominal Minimum1) (21 Ohms) Nominal Low2)(18.75 Ohms) 0.2 9.5 10.7 11.5 11.8 13.3 0.3 14.3 16.0 16.6 17.4 20.0 0.4 18.7 21.0 21.6 23.0 27.0 1) 2) 3) 4) Nominal3)(18 ohms) Nominal High2)(17.25 Ohms) Nominal Maximum4) (15 Ohms) The driver characteristics evaluation conditions are Nominal Minimum 95 °C (TCASE). VDDQ = 1.7 V, any process The driver characteristics evaluation conditions are Nominal Low and Nominal High 25 °C (TCASE), VDDQ = 1.8V, any process The driver characteristics evaluation conditions are Nominal 25 °C (TCASE), VDDQ = 1.8 V, typical process The driver characteristics evaluation conditions are Nominal Maximum 0 °C (TCASE), VDDQ = 1.9 V, any process Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 21 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 5.5 Input / Output Capacitance TABLE 25 Input / Output Capacitance Symbol Parameter Min. Max. Unit CCK Input capacitance, CK and CK 1.0 2.0 pF CDCK Input capacitance delta, CK and CK — 0.25 pF CI Input capacitance, all other input-only pins 1.0 1.75 pF CDI Input capacitance delta, all other input-only pins — 0.25 pF CIO Input/output capacitance, DQ, DM, DQS, DQS 2.5 3.5 pF CDIO Input/output capacitance delta, DQ, DM, DQS, DQS — 0.5 pF Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 22 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 5.6 Overshoot and Undershoot Specification TABLE 26 AC Overshoot / Undershoot Specification for Address and Control Pins Parameter –20 –25 Unit Maximum peak amplitude allowed for overshoot area 0.5 0.5 V Maximum peak amplitude allowed for undershoot area 0.5 0.5 V Maximum overshoot area above VDD 0.80 0.80 V.ns Maximum undershoot area below VSS 0.80 0.80 V.ns FIGURE 4 AC Overshoot / Undershoot Diagram for Address and Control Pins 9ROWV9 0D[LP XP$PSOLWXGH 2YH UVK RRW$UH D 9'' 966 0D[LP XP$PSOLWXGH 7LP H QV Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 23 8QGHUV KRRW$ UH D Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM TABLE 27 AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins Parameter –20 –25 Unit Maximum peak amplitude allowed for overshoot area 0.9 0.9 V Maximum peak amplitude allowed for undershoot area 0.9 0.9 V Maximum overshoot area above VDDQ 0.23 0.23 V.ns Maximum undershoot area below VSSQ 0.23 0.23 V.ns FIGURE 5 AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins 9ROWV 9 0D[LP XP$PSOLWXGH 2YH UVK RRW$UH D 9'' 4 966 4 0D[LP XP$PSOLWXGH 7LP H QV Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 24 8QGHUV KRRW$ UH D Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 5.7 AC Characteristics 5.7.1 Speed Grade Definitions TABLE 28 Speed Grade Definition Speed Grade –20 Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 @ CL = 6 @ CL = 7 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time –25 Unit Note Symbol Min. Max. Min. Max. tCK tCK tCK tCK tCK tRAS tRC tRCD tRP 5 8 5 8 ns 1)2)3)4) 3.75 8 3.75 8 ns 1)2)3)4) 3 8 3 8 ns 1)2)3)4) 2.5 8 2.5 8 ns 1)2)3)4) 2.0 8 — — ns 1)2)3)4) 45 70k 45 70k ns 1)2)3)4)5) 60 — 60 — ns 1)2)3)4) 15 — 15 — ns 1)2)3)4) 15 — 15 — ns 1)2)3)4) 1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 8Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements” according to Chapter 7.1 only. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS is defined in Chapter 7.3. 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. See Chapter 7.1 for the reference load for timing measurements. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI. Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 25 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 5.7.2 AC Timing Parameters List of Timing Parameters TABLE 29 Timing Parameter by Speed Grade Parameter Symbol –20 Unit Notes1) –25 2)3)4)5)6) Min. Max. Min. Max. tAC tCCD tCH tCKE tCL tDAL –450 +450 –500 +500 ps 2 — 2 — 0.45 0.55 0.45 0.55 Minimum time clocks remain ON after CKE asynchronously drops LOW DQ output access time from CK / CK 3 — 3 — 0.45 0.55 0.45 0.55 WR + tRP — WR + tRP — tCK tCK tCK tCK tCK tDELAY tIS + tCK + tIH –– tIS + tCK + tIH –– ns 8) DQ and DM input hold time (differential data strobe) tDH 145 –– 250 –– ps 9) DQ and DM input hold time (single ended data strobe) tDH1 -105 –– 0 –– ps 9) DQ and DM input pulse width (each input) tDIPW tDQSCK tDQSL,H tDQSQ 0.35 — 0.35 — tCK –450 +450 –500 +500 ps 0.35 — 0.35 — tCK — 280 — 280 ps Write command to 1st DQS latching transition tDQSS WL – 0.25 WL + 0.25 WL – 0.25 WL + 0.25 tCK DQ and DM input setup time (differential data strobe) tDS 20 125 –– ps 9) DQ and DM input setup time (single ended data tDS1 strobe) -105 0 –– ps 9) DQS falling edge hold time from CK (write cycle) tDSH 0.2 — 0.2 — DQS falling edge to CK setup time (write cycle) tDSS 0.2 — 0.2 — tCK tCK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time DQS output access time from CK / CK DQS input low (high) pulse width (write cycle) DQS-DQ skew (for DQS & associated DQ signals) Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ tHP tHZ tIH tIPW MIN. (tCL, tCH) — tIS tLZ(DQ) 400 tLZ(DQS) tMRD — tAC.MAX 525 0.6 2× tAC.MIN tAC.MIN 2 26 — tAC.MAX 7)18) 9) 10) 11) MIN. (tCL, tCH) — 12) — tAC.MAX ps 575 — ps 0.6 — tCK 450 — ps 2× tAC.MAX ps 12) tAC.MAX ps 12) — tCK tAC.MAX tAC.MIN tAC.MIN — 2 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM Parameter Symbol –20 Unit Notes1) –25 2)3)4)5)6) OCD drive mode output delay tOIT tQH tQHS tREFI Min. Max. Min. Max. 0 12 0 12 ns tHP–tQHS — tHP–tQHS — — 380 — 380 ps — 7.8 — 7.8 μs 13)14) — 3.9 — 3.9 μs 13)15) Auto-Refresh to Active/Auto-Refresh command tRFC period 105 — 105 — ns 16) tRPRE Read postamble tRPST Active bank A to Active bank B command period tRRD Internal Read to Precharge command delay tRTP tWPRE Write preamble Write postamble tWPST Write recovery time for write without AutotWR 0.9 1.1 0.9 1.1 12) 0.40 0.60 0.40 0.60 tCK tCK 10 — 10 — ns 14)17) 7.5 — 7.5 — ns 0.35 x tCK — 0.35 x tCK — 0.40 0.60 0.40 0.60 tCK tCK 14 — 15 — ns Write recovery time for write with AutoPrecharge WR tWR/tCK Internal Write to Read command delay tWTR tXARD 7.5 2 — 2 Exit active power-down mode to Read command (slow exit, lower power) tXARDS 10 – AL — Exit precharge power-down to any valid command (other than NOP or Deselect) tXP 2 Exit Self-Refresh to non-Read command tXSNR tXSRD Data output hold time from DQS Data hold skew factor Average periodic refresh Interval Read preamble 12) 17) Precharge Exit power down to any valid command (other than NOP or Deselect) Exit Self-Refresh to Read command tWR/tCK tCK 18) ns 19) — tCK 20) 8 – AL — tCK 20) — 2 — tCK tRFC +10 — tRFC +10 — ns 200 — 200 — tCK — 7.5 — 1) VDDQ, VDD refer to Chapter 1. 2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 5 of this data sheet. 4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.The DQS / DQS, input reference level is the crosspoint when in differential strobe mode;The input reference level for signals other than CK/CK, DQS / DQS is defined in Chapter 5.3 of this data sheet. 5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 6) The output timing reference voltage level is VTT. See Chapter 5 for the reference load for timing measurements. 7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MR. 8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change during power-down, a specific procedure is required. 9) timing is referenced to Industrial standard definition 10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle. 11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 27 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 13) The Auto-Refresh command interval has be reduced to 3.9 μs when operating the DDR2 DRAM in a temperature range between 85 °C and 95 °C. 14) 0 °C ≤ TCASE ≤ 85 °C 15) 85 °C < TCASE ≤ 95 °C 16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 17) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 18) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS. 19) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz. 20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active powerdown mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow power-down exit timing tXARDS has to be satisfied. 5.7.3 ODT AC Electrical Characteristics TABLE 30 ODT AC Electrical Characteristics and Operating Conditions for all bins Symbol Parameter / Condition Values Min. tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD Unit Note Max. ODT turn-on delay 2 2 tCK ODT turn-on tAC.MAX + 0.7 ns 2 tCK + tAC.MAX + 1 ns ns ODT turn-on (Power-Down Modes) tAC.MIN tAC.MIN + 2 ns ODT turn-off delay 2.5 2.5 tCK ODT turn-off tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns ns ODT turn-off (Power-Down Modes) tAC.MIN tAC.MIN + 2 ns ODT to Power Down Mode Entry Latency 3 — ODT Power Down Exit Latency 8 — 1) ns 2) ns tCK tCK 1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 28 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 6 Specifications and Conditions TABLE 31 IDD Measurement Conditions Parameter Symbol Note Operating Current - One bank Active - Precharge tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching; Databus inputs are switching. IDD0 1)2)3)4)5)6) Operating Current - One bank Active - Read - Precharge IOUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), tRCD = tRCD(IDD), AL = 0, CL = CL(IDD); CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching; Databus inputs are switching. IDD1 1)2)3)4)5)6) Precharge Power-Down Current IDD2P All banks idle; CKE is LOW; tCK = tCK(IDD);Other control and address inputs are stable; Data bus inputs are floating. 1)2)3)4)5)6) Precharge Standby Current IDD2N All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are switching, Data bus inputs are switching. 1)2)3)4)5)6) Precharge Quiet Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are stable, Data bus inputs are floating. IDD2Q 1)2)3)4)5)6) Active Power-Down Current All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable; Data bus inputs are floating. MRS A12 bit is set to “0” (Fast Power-down Exit). IDD3P(0) 1)2)3)4)5)6) Active Power-Down Current All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable, Data bus inputs are floating. MRS A12 bit is set to 1 (Slow Power-down Exit); IDD3P(1) 1)2)3)4)5)6) Active Standby Current IDD3N All banks open; tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data Bus inputs are switching; 1)2)3)4)5)6) Operating Current IDD4R Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS = tRAS.MAX.(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data Bus inputs are switching; IOUT = 0 mA. 1)2)3)4)5)6) Operating Current IDD4W Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data Bus inputs are switching; 1)2)3)4)5)6) Burst Refresh Current IDD5B tCK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are switching, Data bus inputs are switching. 1)2)3)4)5)6) IDD5D 1)2)3)4)5)6) Distributed Refresh Current tCK = tCK(IDD), Refresh command every tREFI = 7.8 μs interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are switching, Data bus inputs are switching. Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 29 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM Parameter Symbol Self-Refresh Current IDD6 CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data bus inputs are floating. Operating Bank Interleave Read Current IDD7 1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 × tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD); CKE is HIGH, CS is HIGH between valid commands. Address bus inputs are stable during deselects; Data bus is switching. 1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V 2) IDD specifications are tested after the device is properly initialized. 3) IDD parameter are specified with ODT disabled. 4) 5) 6) 7) Note 1)2)3)4)5)6) 1)2)3)4)5)6)7) Data Bus consists of DQ, DM, DQS, DQS, LDQS, LDQS, UDQS and UDQS. Definitions for IDD: see Table 32 Timing parameter minimum and maximum values for IDD current measurements are defined in chapter 7.. A = Activate, RA = Read with Auto-Precharge, D=DESELECT TABLE 32 Definition for IDD Parameter Description LOW defined as VIN ≤ VIL(ac).MAX HIGH defined as VIN ≥ VIH(ac).MIN STABLE defined as inputs are stable at a HIGH or LOW level FLOATING defined as inputs are VREF = VDDQ / 2 SWITCHING defined as: Inputs are changing between high and low every other clock (once per two clocks) for address and control signals, and inputs changing between high and low every other clock (once per clock) for DQ signals not including mask or strobes Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 30 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM TABLE 33 IDD Specification Speed Grade –20 –25 Symbol typ. typ. IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P(0) IDD3P(1) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7 84 80 Note mA 93 90 mA 4 4 mA 42 37 mA 38 34 mA 26 22 mA 1) 7 7 mA 2) 47 41 mA 203 173 mA 192 162 mA 121 117 mA 5 5 mA 3) 4 4 mA 3) 206 203 mA 1) MRS(12)=0 2) MRS(12)=1 3) 0 ≤ TCASE ≤ 85°C Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ Unit 31 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 7 Package 7.1 Package Dimension FIGURE 6 Package Outline P-TFBGA-84 (top view) Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 32 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 7.2 Package Thermal Characteristics TABLE 34 Package thermal characteristics 1) JESD51 Theta_jC2) Theta_jA Industrial standard Board 1s0p 2s0p Air Flow 0 m/s 1 m/s 3 m/s 0 m/s 1 m/s 3 m/s Rth[K/W] 69 53 47 41 35 33 5 1) Junction to Ambient thermal resistance. The value has been obtained by simulation using the conditions stated in the Industrial standard JESD-51 standard. 2) Junction to Case thermal resistance. The value has been obtained by simulation. Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 33 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM Contents 1 1.1 1.2 Overview 3 Features 3 Description 4 2 2.1 2.2 Configuration 5 Chip Configuration 5 512 Mbit DDR2 Addressing 9 3 Functional Description 10 4 Truth Tables 15 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.7.1 5.7.2 5.7.3 Electrical Characteristics 17 Absolute Maximum Ratings 17 DC Characteristics 18 DC & AC Characteristics 19 Output Buffer Characteristics 21 Input / Output Capacitance 22 Overshoot and Undershoot Specification 23 AC Characteristics 25 Speed Grade Definitions 25 AC Timing Parameters 26 ODT AC Electrical Characteristics 28 6 Specifications and Conditions 29 7 7.1 7.2 Package 32 Package Dimension 32 Package Thermal Characteristics 33 Contents 34 List of Tables 35 List of Figures 36 Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 34 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Ordering Information for RoHS compliant products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Chip Configuration of DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Abbreviations for Ball Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 512-Mbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Mode Register Definition (BA[1:0] = 00B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Extended Mode Register Definition (BA[1:0] = 01B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 EMRS(2) Programming Extended Mode Register Definition (BA[1:0]=10B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 EMR(3) Programming Extended Mode Register Definition (BA[1:0]=10B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ODT Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Command Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Clock Enable (CKE) Truth Table for Synchronous Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Data Mask (DM) Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DRAM Component Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Recommended DC Operating Conditions (SSTL_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Input and Output Leakage Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DC & AC Logic Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Single-ended AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Differential DC and AC Input and Output Logic Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Full Strength Calibrated Pull-up Driver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Full Strength Calibrated Pull-down Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AC Overshoot / Undershoot Specification for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . 24 Speed Grade Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Timing Parameter by Speed Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 ODT AC Electrical Characteristics and Operating Conditions for all bins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 IDD Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Definition for IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 IDD Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 35 Internet Data Sheet HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Chip Configuration, PG-TFBGA-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Single-ended AC Input Test Conditions Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . 24 Package Outline P-TFBGA-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 36 Internet Data Sheet Edition 2007-06 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Under no circumstances may the Qimonda product as referred to in this Internet Data Sheet be used in 1. Any applications that are intended for military usage (including but not limited to weaponry), or 2. Any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining, sustaining or protecting human life (such applications, devices and systems collectively referred to as "Critical Systems"), if a) A failure of the Qimonda product can reasonable be expected to - directly or indirectly (i) Have a detrimental effect on such Critical Systems in terms of reliability, effectiveness or safety; or (ii) Cause the failure of such Critical Systems; or b) A failure or malfunction of such Critical Systems can reasonably be expected to - directly or indirectly (i) Endanger the health or the life of the user of such Critical Systems or any other person; or (ii) Otherwise cause material damages (including but not limited to death, bodily injury or significant damages to property, whether tangible or intangible). www.qimonda.com