QIMONDA HYB25D512160BT-6

September 2006
HYB25D512[40/80/16]0B[C/T](L)
HYB25D512[40/80/16]0B[E/F](L)
512-Mbit Double-Data-Rate SDRAM
DDR SDRAM
Internet Data Sheet
Rev. 1.63
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
HYB25D512[40/80/16]0B[C/T](L), HYB25D512[40/80/16]0B[E/F](L)
Revision History: 2006-09, Rev. 1.63
Page
Subjects (major changes since last revision)
All
Qimonda update
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Adapted internet edition
Previous Revision: 2005-10, Rev. 1.62
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-01
03062006-PFFJ-YJY2
2
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
1
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main
characteristics
1.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Features
Double data rate architecture: two data transfers per clock cycle
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
DQS is edge-aligned with data for reads and is center-aligned with data for writes
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation
Data mask (DM) for write data
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Burst Lengths: 2, 4, or 8
CAS Latency: (1.5), 2, 2.5, 3
Auto Pre charge option for each burst access
Auto Refresh and Self Refresh Modes
RAS-lockout supported tRAP=tRCD
7.8 µs Maximum Average Periodic Refresh Interval
2.5 V (SSTL_2 compatible) I/O
VDDQ = 2.5 V ± 0.2 V and 2.6 V ± 0.1 V for DDR400
VDD = 2.5 V ± 0.2 V and 2.6 V ± 0.1 V for DDR400
P-TFBGA-60 and P-TSOPII-66 package
TABLE 1
Performance
Part Number Speed Code
–5
–6
–7
Unit
Speed Grade
Component
DDR400B
DDR333B
DDR266A
—
Module
PC3200–3033
PC2700–2533
PC2100–2033
—
max. Clock
Frequency
@CL3
@CL2.5
@CL2
Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
fCK3
fCK2.5
fCK2
200
166
–
MHz
166
166
143
MHz
133
133
133
MHz
3
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
1.2
Description
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write
command. The address bits registered coincident with the
Active command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4 or 8 locations. An Auto Precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
As with standard SDRAMs, the pipelined, multibank
architecture of DDR SDRAMs allows for concurrent
operation, thereby providing high effective bandwidth by
hiding row precharge and activation time.
An auto refresh mode is provided along with a power-saving
power-down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II
compatible.
Note: The functionality described and the timing
specifications included in this data sheet are for the
DLL Enabled mode of operation.
The 512-Mbit Double-Data-Rate SDRAM is a high-speed
CMOS, dynamic random-access memory containing
536,870,912 bits. It is internally configured as a quad-bank
DRAM.
The 512-Mbit Double-Data-Rate SDRAM uses a doubledata-rate architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n pre fetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access
for
the
512-Mbit Double-Data-Rate SDRAM
effectively consists of a single 2n-bit wide, one clock cycle
data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads and
by the memory controller during Writes. DQS is edge-aligned
with data for Reads and center-aligned with data for Writes.
The 512-Mbit Double-Data-Rate SDRAM operates from a
differential clock (CK and CK; the crossing of CK going HIGH
and CK going LOW is referred to as the positive edge of CK).
Commands (address and control signals) are registered at
every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
4
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 2
Ordering Information
Part Number1)
Org. CAS-RCD-RP
Latencies
Clock
(MHz)
CAS-RCD-RP
Latencies
Clock
(MHz)
Speed
Package
HYB25D512800BT–5
×8
3.0-3-3
200
2.5-3-3
166
DDR400B
P-TSOPII-66
HYB25D512160BT–5
×16
2.5-3-3
166
2-3-3
133
DDR333
HYB25D512400BT–6
×4
HYB25D512800BT–6
×8
HYB25D512160BT–6
×16
HYB25D512160BTL–6
×16
HYB25D512400BT–7
×4
HYB25D512400BC–5
×4
HYB25D512800BC–5
×8
HYB25D512160BC–5
×16
HYB25D512400BC–6
×4
HYB25D512800BC–6
×8
HYB25D512160BC–6
×16
143
DDR266
3.0-3-3
200
2.5-3-3
166
DDR400B
2.5-3-3
166
2-3-3
133
DDR333
1) HYB: designator for memory components
25D: DDR SDRAMs at VDDQ = 2.5 V
512: 512-Mbit density
400/800/160: Product variations x4, ×8 and ×16
B: Die revision B
C/F/E/T: Package type FBGA and TSOP
L: Low power (on request)
Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
5
P-TFBGA-60
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 3
Ordering Information for RoHS compliant products
Part Number
Org.
CAS-RCD-RP
Latencies
Clock
(MHz)
CAS-RCD-RP
Latencies
Clock
(MHz)
Speed
Package
HYB25D512400BF–5
×4
3.0-3-3
200
2.5-3-3
166
DDR400B
P-TFBGA-60
HYB25D512800BF–5
×8
HYB25D512160BF–5
×16
HYB25D512400BF–6
×4
2.5-3-3
166
2-3-3
133
DDR333
HYB25D512800BF–6
×8
HYB25D512160BF–6
×16
HYB25D512400BE–5
×4
3.0-3-3
200
2.5-3-3
166
DDR400B
HYB25D512800BE–5
×8
HYB25D512160BE–5
×16
HYB25D512400BE–6
×4
2.5-3-3
166
2-3-3
133
DDR333
HYB25D512800BE–6
×8
HYB25D512800BEL–6
×8
HYB25D512160BE–6
×16
HYB25D512160BEL–6
×16
HYB25D512400BE–7
×4
Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
143
DDR266A
6
P-TSOPII-66
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
2
Pin Configuration
The pin configuration of a DDR SDRAM is listed by function in Table 4 (60 pins). The abbreviations used in the Pin#/Buffer#
column are explained in Table 5 and Table 6 respectively. The pin numbering for FBGA is depicted in Figure 1 and that of the
TSOP package in Figure 2
TABLE 4
Pin Configuration of DDR SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
G2, 45
CK
I
SSTL
Clock Signal
G3, 46
CK
I
SSTL
Complementary Clock Signal
H3, 44
CKE
I
SSTL
Clock Enable
RAS
I
SSTL
Row Address Strobe
G8, 22
CAS
I
SSTL
Column Address Strobe
G7, 21
WE
I
SSTL
Write Enable
H8, 24
CS
I
SSTL
Chip Select
BA0
I
SSTL
Bank Address Bus 2:0
J7, 27
BA1
I
SSTL
K7, 29
A0
I
SSTL
L8, 30
A1
I
SSTL
L7, 31
A2
I
SSTL
M8, 32
A3
I
SSTL
Clock Signals
Control Signals
H7, 23
Address Signals
J8, 26
Address Bus 11:0
M2, 35
A4
I
SSTL
L3, 36
A5
I
SSTL
L2, 37
A6
I
SSTL
K3, 38
A7
I
SSTL
K2, 39
A8
I
SSTL
J3, 40
A9
I
SSTL
K8, 28
A10
I
SSTL
AP
I
SSTL
J2, 41
A11
I
SSTL
H2, 42
A12
I
SSTL
Address Signal 12
Note: 256 Mbit or larger dies
NC
NC
—
Note: 128 Mbit or smaller dies
A13
I
SSTL
Address Signal 13
Note: 1 Gbit based dies
NC
NC
—
Note: 512 Mbit or smaller dies
F9, 17
Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
7
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
Data Signal 3:0
Data Signals ×4 organization
B7, 5
DQ0
I/O
SSTL
D7, 11
DQ1
I/O
SSTL
D3, 56
DQ2
I/O
SSTL
B3, 62
DQ3
I/O
SSTL
Data Strobe ×4 organisation
E3, 51
DQS
I/O
SSTL
Data Strobe
I
SSTL
Data Mask
Data Signal 7:0
Data Mask ×4 organization
F3, 47
DM
Data Signals ×8 organization
A8, 2
DQ0
I/O
SSTL
B7, 5
DQ1
I/O
SSTL
C7, 8
DQ2
I/O
SSTL
D7, 11
DQ3
I/O
SSTL
D3, 56
DQ4
I/O
SSTL
C3, 59
DQ5
I/O
SSTL
B3, 62
DQ6
I/O
SSTL
A2, 65
DQ7
I/O
SSTL
Data Signal
Data Strobe ×8 organisation
E3, 51
DQS
I/O
SSTL
Data Strobe
I
SSTL
Data Mask
Data Signal 15:0
Data Mask ×8 organization
F3, 47
DM
Data Signals ×16 organization
A8, 2
DQ0
I/O
SSTL
B9, 4
DQ1
I/O
SSTL
B7, 5
DQ2
I/O
SSTL
C9, 7
DQ3
I/O
SSTL
C7, 8
DQ4
I/O
SSTL
D9, 10
DQ5
I/O
SSTL
D7, 11
DQ6
I/O
SSTL
E9, 13
DQ7
I/O
SSTL
E1, 54
DQ8
I/O
SSTL
D3, 56
DQ9
I/O
SSTL
D1, 57
DQ10
I/O
SSTL
C3, 59
DQ11
I/O
SSTL
C1, 60
DQ12
I/O
SSTL
B3, 62
DQ13
I/O
SSTL
B1, 63
DQ14
I/O
SSTL
A2, 65
DQ15
I/O
SSTL
Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
8
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
Data Strobe ×16 organization
E3, 51
UDQS
I/O
SSTL
Data Strobe Upper Byte
E7, 16
LDQS
I/O
SSTL
Data Strobe Lower Byte
Data Mask ×16 organization
F3, 47
UDM
I
SSTL
Data Mask Upper Byte
F7, 20
LDM
I
SSTL
Data Mask Lower Byte
AI
—
I/O Reference Voltage
PWR
—
I/O Driver Power Supply
PWR
—
Power Supply
PWR
—
Power Supply
VSS
PWR
—
Power Supply
A2, 65
NC
NC
—
Not Connected
Note: ×4 organization
A8, 2
NC
NC
—
Not Connected
Note: ×4 organization
B1, 63
NC
NC
—
Not Connected
Note: ×8 and ×4 organisation
B9, 4
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
C1, 60
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
C3, 59
NC
NC
—
Not Connected
Note: ×4 organization
C7, 8
NC
NC
—
Not Connected
Note: ×4 organization
C9, 7
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
D1, 57
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
D9, 10
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
E1, 54
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
Power Supplies
VREF
A9, B2, C8, D2, VDDQ
F1, 49
E8, 3, 9, 15, 55,
61
A7, F8, M7, 1,
18, 33
VDD
A1, B8, C2, D8, VSSQ
E2, 6, 12, 52,
58, 64
A3,F2, M3, 34,
48, 66,
Not Connected
Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
9
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
E7, 16
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
E9, 13
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
F7, 20
NC
NC
—
Not Connected
Note: ×8 and ×4 organization
F9, 14, 17, 19,
25,43, 50, 53
NC
NC
—
Not Connected
Note: ×16, ×8 and ×4 organization
TABLE 5
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NC
Not Connected
TABLE 6
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL2)
LV-CMOS
Low Voltage CMOS
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
10
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
FIGURE 1
Pin Configuration P-TFBGA-60 Top View, see the balls throught the package
9664
1&
966
1&
9''4
1&
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9''
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Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
11
033'
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
FIGURE 2
Pin Configuration P-TSOPII-66-1
[
[
[
9''
9''
9''
966
966
966
1&
'4
'4
'4
'4
1&
9''4
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9664
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Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
12
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
3
Functional Description
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write
command. The address bits registered coincident with the
Active command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-A12 select the row).
The address bits registered coincident with the Read or Write
command are used to select the starting column location for
the burst access.
Prior to normal operation, the DDR SDRAM must be
initialized. The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
The 512-Mbit Double-Data-Rate SDRAM is a high-speed
CMOS, dynamic random-access memory containing
536,870,912 bits. The 512-Mbit Double-Data-Rate SDRAM
is internally configured as a quad-bank DRAM.
The 512-Mbit Double-Data-Rate SDRAM uses a doubledata-rate architecture to achieve high-speed operation. The
double-data-rate architecture is essentially a 2n pre fetch
architecture, with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 512-Mbit Double-Data-Rate SDRAM consists
of a single 2n-bit wide, one clock cycle data transfer at the
internal DRAM core and two corresponding n-bit wide, onehalf clock cycle data transfers at the I/O pins.
Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
13
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
%$
%$
$
$
$
$
$
$
$
$
$
$
$
$
2SHUD
WLQ
J0
2'
(
&/
%7
%/
Z
Z
Z
Z
UHJD
GGU
$
TABLE 7
Mode Register Definition
Field
Bits
Type
Description
BL
[2:0]
w
Burst Length
Number of sequential bits per DQ related to one read/write command.
Note: All other bit combinations are RESERVED.
001B 2
010B 4
011B 8
BT
3
w
Burst Type
See Table 8 for internal address sequence of low order address bits.
0B
Sequential
1B
Interleaved
CL
[6:4]
w
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
010B
011B
101B
110B
MODE [12:7]
w
2
3
(1.5 Optional, not covered by this data sheet)
2.5
Operating Mode
Note: All other bit combinations are RESERVED.
000000B
000010B
Rev. 1.63, 2006-09
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Normal Operation without DLL Reset
DLL Reset
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 8
Burst Definition
Burst Length
Starting Column Address
A2
A1
A0
Type = Sequential
Type = Interleaved
0
0-1
0-1
1
1-0
1-0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
2
4
8
Order of Accesses Within a Burst
1
1
3-0-1-2
3-2-1-0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Notes
1.
2.
3.
4.
For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block.
For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within the block.
Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
%$
%$
$
$
$
$
$
$
$
$
$
02'(
$
$
$
$
'6
'//
TABLE 9
Extended Mode Register Definition
Field
Bits
Type
Description
DLL
0
w
DLL Status
0B
Enabled
1B
Disabled
DS
1
w
Drive Strength
Normal
0B
1B
Weak
MODE
[12:2]
w
Operating Mode
Note: All other bit combinations are RESERVED.
0B
Rev. 1.63, 2006-09
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Normal Operation
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Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 10
Truth Table 1a: Commands
Name (Function)
CS
RAS
CAS
WE
Address
MNE
Note
Deselect (NOP)
H
X
X
X
X
NOP
1)2)
No Operation (NOP)
L
H
H
H
X
NOP
1)2)
Active (Select Bank And Activate Row)
L
L
H
H
Bank/Row
ACT
1)3)
Read (Select Bank And Column, And Start Read Burst)
L
H
L
H
Bank/Col
Read
1)4)
Write (Select Bank And Column, And Start Write Burst)
L
H
L
L
Bank/Col
Write
1)4)
Burst Terminate
L
H
H
L
X
BST
1)5)
Precharge (Deactivate Row In Bank Or Banks)
L
L
H
L
Code
PRE
1)6)
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)
L
L
L
H
X
AR/SR
1)7)8)
Mode Register Set
L
L
L
L
Op-Code
MRS
1)9)
1) CKE is HIGH for all commands shown except Self Refresh.
VREF must be maintained during Self Refresh operation
2) Deselect and NOP are functionally interchangeable.
3) BA0-BA1 provide bank address and A0-A12 provide row address.
4) BA0, BA1 provide bank address; A0-Ai provide column address (where i = 8 for ×16, i = 9 for ×8 and 9, 11 for ×4);
A10 HIGH enables the Auto Precharge feature (non persistent), A10 LOW disables the Auto Precharge feature.
5) Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto
Precharge enabled or for write bursts.
6) A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
7) This command is AUTO REFRESH if CKE is HIGH; Self Refresh if CKE is LOW.
8) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
9) BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects
Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode
Register).
TABLE 11
Truth Table 1b: DM Operation
Name (Function)
DM
DQs
Note
Write Enable
L
Valid
1)
Write Inhibit
H
X
1)
1) Used to mask write data; provided coincident with the corresponding data.
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 12
Truth Table 2: Clock Enable (CKE)
Current State
CKE n-1
CKEn
Command n
Action n
Note
Previous
Cycle
Current
Cycle
Self Refresh
L
L
X
Maintain Self-Refresh
1)
Self Refresh
L
H
Deselect or NOP
Exit Self-Refresh
2)
Power Down
L
L
X
Maintain Power-Down
–
Power Down
L
H
Deselect or NOP
Exit Power-Down
–
All Banks Idle
H
L
Deselect or NOP
Precharge Power-Down Entry
–
All Banks Idle
H
L
AUTO REFRESH
Self Refresh Entry
–
Bank(s) Active
H
L
Deselect or NOP
Active Power-Down Entry
–
H
H
See Table 13
–
–
1) VREF must be maintained during Self Refresh operation
2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of 200
clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
Notes
1.
2.
3.
4.
CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
Current state is the state of the DDR SDRAM immediately prior to clock edge n.
COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
All states and sequences not shown are illegal or reserved.
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 13
Truth Table 3: Current State Bank n - Command to Bank n (same bank)
Current State
CS
RAS
CAS
WE
Command
Action
Note
Any
H
X
X
X
Deselect
NOP. Continue previous operation.
1)2)3)4)5)6)
L
H
H
H
No Operation
NOP. Continue previous operation.
1) to 6)
L
L
H
H
Active
Select and activate row
1) to 6)
L
L
L
H
AUTO REFRESH
–
1) to 7)
L
L
L
L
MODE REGISTER
SET
–
1) to 7)
L
H
L
H
Read
Select column and start Read burst
1) to 6), 8)
L
H
L
L
Write
Select column and start Write burst
1) to 6), 8)
L
L
H
L
Precharge
Deactivate row in bank(s)
1) to 6), 9)
Read (Auto
Precharge
Disabled)
L
H
L
H
Read
Select column and start new Read burst
1) to 6), 8)
L
L
H
L
Precharge
Truncate Read burst, start Precharge
1) to 6), 9)
L
H
H
L
BURST
TERMINATE
BURST TERMINATE
1) to 6), 10)
Write (Auto
Precharge
Disabled)
L
H
L
H
Read
Select column and start Read burst
1) to 6), 8), 11)
L
H
L
L
Write
Select column and start Write burst
1) to 6), 8)
Idle
Row Active
1) to 6), 9), 11)
Truncate Write burst, start Precharge
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 12 and after tXSNR/tXSRD has been met (if the previous state
L
L
H
L
Precharge
was self refresh).
2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed
to be issued to that bank when in that state. Exceptions are covered in the notes below.
3) Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in
progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
4) The following states must not be interrupted by a command issued to the same bank.
Pre charging: Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the idle state.
Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in the “row active”
state.
Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states.
Allowable commands to the other bank are determined by its current state and according to Table 14.
5) The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive
clock edge during these states.
Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is met, the DDR SDRAM is in the
“all banks idle” state.
Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once tMRD is met,
the DDR SDRAM is in the “all banks idle” state.
Pre charging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle state.
6) All states and sequences not shown are illegal or reserved.
7) Not bank-specific; requires that all banks are idle.
8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
9) May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for pre charging.
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
10) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.
11) Requires appropriate DM masking.
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 14
Truth Table 4: Current State Bank n - Command to Bank m (different bank)
Current State
CS
RAS CAS WE
Command
Action
Note
Any
H
X
X
X
Deselect
NOP. Continue previous operation.
1)2)3)4)5)6)
L
H
H
H
No Operation
NOP. Continue previous operation.
1) to 6)
Idle
X
X
X
X
Any Command
Otherwise Allowed to
Bank m
–
1) to 6)
Row Activating,
Active, or Pre
charging
L
L
H
H
Active
Select and activate row
1) to 6)
L
H
L
H
Read
Select column and start Read burst
1) to 7)
L
H
L
L
Write
Select column and start Write burst
1) to 7)
L
L
H
L
Precharge
–
1) to 6)
Read (Auto
Precharge
Disabled)
L
L
H
H
Active
Select and activate row
1) to 6)
L
H
L
H
Read
Select column and start new Read burst
1) to 7)
L
L
H
L
Precharge
–
1) to 6)
Write (Auto
Precharge
Disabled)
L
L
H
H
Active
Select and activate row
1) to 6)
L
H
L
H
Read
Select column and start Read burst
1) to 8)
L
H
L
L
Write
Select column and start new Write burst
1) to 7)
L
L
H
L
Precharge
–
1) to 6)
L
L
H
H
Active
Select and activate row
1) to 6)
L
H
L
H
Read
Select column and start new Read burst
1) to 7), 9)
L
H
L
L
Write
Select column and start Write burst
1) to 7), 9), 10)
L
L
H
L
Precharge
–
1) to 6)
L
L
H
H
Active
Select and activate row
1) to 6)
L
H
L
H
Read
Select column and start Read burst
1) to 7), 9)
L
H
L
L
Write
Select column and start new Write burst
1) to 7), 9)
L
L
H
L
Precharge
–
1) to 6)
Read (With Auto
Precharge)
Write (With Auto
Precharge)
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 12: Clock Enable (CKE) and after tXSNR/tXSRD has been met (if
the previous state was self refresh).
2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those
allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in
the notes below.
3) Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in
progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge Enabled: See 10).
Write with Auto Precharge Enabled: See 10).
4) AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle.
5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
6) All states and sequences not shown are illegal or reserved.
7) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
8) Requires appropriate DM masking.
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
9) Concurrent Auto Precharge:
This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto precharge is enabled any
command may follow to the other banks as long as that command does not interrupt the read or write data transfer and all other limitations
apply (e.g. contention between READ data and WRITE data must be avoided). The minimum delay from a read or write command with
auto precharge enable, to a command to a different banks is summarized in Table 15.
10) A Write command may be applied after the completion of data output.
TABLE 15
Truth Table 5: Concurrent Auto Precharge
From Command
To Command (different bank)
Minimum Delay with Concurrent Auto Unit
Precharge Support
WRITE w/AP
Read or Read w/AP
1 + (BL/2) + RU(tWTR/tCK)1)
Read w/AP
Write to Write w/AP
BL/2
Precharge or Activate
1
Read or Read w/AP
BL/2
Write or Write w/AP
RU(CL)1) + BL/2
Precharge or Activate
1
1) RU means rounded to the next integer
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tCK
tCK
tCK
tCK
tCK
tCK
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
4
Electrical Characteristics
4.1
Operating Conditions
TABLE 16
Absolute Maximum Ratings
Parameter
Symbol
Values
min.
typ.
–
Unit
Note/ Test
Condition
VDDQ +
V
–
max.
Voltage on I/O pins relative to VSS
VIN, VOUT
–0.5
Voltage on inputs relative to VSS
VIN
VDD
VDDQ
TA
TSTG
PD
IOUT
–1
–
+3.6
V
–
–1
–
+3.6
V
–
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
Power dissipation (per SDRAM component)
Short circuit output current
0.5
–1
–
+3.6
V
–
0
–
+70
°C
–
-55
–
+150
°C
–
–
1
–
W
–
–
50
–
mA
–
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This is a stress
rating only, and functional operation should be restricted to recommended operation conditions. Exposure
to absolute maximum rating conditions for extended periods of time may affect device reliability and
exceeding only one of the values may cause irreversible damage to the integrated circuit.
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 17
Input and Output Capacitances
Parameter
Input Capacitance: CK, CK
Delta Input Capacitance
Input Capacitance:
All other input-only pins
Symbol
CI1
CdI1
CI2
Values
Unit
Note/
Test Condition
Min.
Typ.
Max.
1.5
—
2.5
pF
TSOPII 1)
2.0
—
3.0
pF
TFBGA 1)
—
—
0.25
pF
1)
1.5
—
2.5
pF
TFBGA 1)
2.0
—
3.0
pF
TSOPII 1)
Delta Input Capacitance:
All other input-only pins
CdIO
—
—
0.5
pF
1)
Input/Output Capacitance: DQ, DQS, DM
CIO
3.5
—
4.5
pF
TFBGA 1)2)
4.0
—
5.0
pF
TSOPII 1)2)
—
—
0.5
pF
1)
Delta Input/Output Capacitance:
DQ, DQS, DM
CdIO
1) These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5 V ± 0.2 V, f= 100 MHz, TA = 25 °C, VOUT(DC)
= VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.
2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the
board level.
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 18
Electrical Characteristics and DC Operating Conditions
Parameter
Symbol
Unit Note1)/Test Condition
Values
Min.
Typ.
Max.
VDD
VDD
VDDQ
VDDQ
VDDSPD
VSS,
VSSQ
VREF
VTT
2.3
2.5
2.7
V
2.5
2.6
2.7
V
2.3
2.5
2.7
V
2.5
2.6
2.7
V
fCK ≤ 166 MHz
fCK > 166 MHz 2)
fCK ≤ 166 MHz 3)
fCK > 166 MHz 2)3)
2.3
2.5
3.6
V
—
0
—
0
V
—
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V
4)
VREF – 0.04
—
VREF + 0.04
V
5)
VIH(DC)
VIL(DC)
VIN(DC)
VREF + 0.15
—
V
6)
–0.3
—
V
6)
–0.3
—
VDDQ + 0.3
VREF – 0.15
VDDQ + 0.3
V
6)
Input Differential Voltage,
CK and CK Inputs
VID(DC)
0.36
—
VDDQ + 0.6
V
6)7)
VI-Matching Pull-up Current
to Pull-down Current
VIRatio
0.71
—
1.4
—
8)
Input Leakage Current
II
–2
—
2
µA
Any input 0 V ≤ VIN ≤ VDD;
All other pins not under test
= 0 V 9)
Output Leakage Current
IOZ
–5
—
5
µA
DQs are disabled;
0 V ≤ VOUT ≤ VDDQ 9)
Output High Current, Normal IOH
Strength Driver
—
—
–16.2
mA
VOUT = 1.95 V
Device Supply Voltage
Device Supply Voltage
Output Supply Voltage
Output Supply Voltage
EEPROM supply voltage
Supply Voltage, I/O Supply
Voltage
Input Reference Voltage
I/O Termination Voltage
(System)
Input High (Logic1) Voltage
Input Low (Logic0) Voltage
Input Voltage Level,
CK and CK Inputs
16.2
—
—
mA VOUT = 0.35 V
Output Low Current, Normal IOL
Strength Driver
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V; VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400);
2)
3)
4)
5)
6)
7)
8)
9)
DDR400 conditions apply for all clock frequencies above 166 MHz
Under all conditions, VDDQ must be less than or equal to VDD.
Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ.
VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF.
Inputs are not recognized as valid until VREF stabilizes.
VID is the magnitude of the difference between the input level on CK and the input level on CK.
The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and
voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between
pull-up and pull-down drivers due to process variation.
Values are shown per pin.
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
4.2
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD
Specifications and Conditions, and Electrical Characteristics and AC Timing.)Note
Note
1. All voltages referenced to VSS
2. Tests for AC timing, IDD, and electrical, AC and DC
characteristics, may be conducted at nominal
reference/supply voltage levels, but the related
specifications and device operation are guaranteed for
the full voltage range specified.
3. Figure 3 represents the timing reference load used in
defining the relevant timing parameters of the part. It is not
intended to be either a precise representation of the
typical system environment nor a depiction of the actual
load presented by a production tester. System designers
will use IBIS or other simulation tools to correlate the
timing reference load to a system environment.
Manufacturers will correlate to their production test
conditions (generally a coaxial transmission line
terminated at the tester electronics).
4. AC timing and IDD tests may use a VIL to VIH swing of up
to 1.5 V in the test environment, but input timing is still
referenced to VREF (or to the crossing point for CK, CK),
and parameter specifications are guaranteed for the
specified AC input levels under normal use conditions.
The minimum slew rate for the input signals is 1 V/ns in
the range between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined
in the SSTL_2 Standard (i.e. the receiver effectively
switches as a result of the signal crossing the AC input
level, and remains in that state as long as the signal does
not ring back above (below) the DC input LOW (HIGH)
level).
6. For System Characteristics like Setup & Holdtime
Derating for Slew Rate, I/O Delta Rise/Fall Derating, DDR
SDRAM Slew Rate Standards, Overshoot & Undershoot
specification and Clamp V-I characteristics see the latest
JEDEC specification for DDR components.
FIGURE 3
AC Output Load Circuit Diagram / Timing Reference Load
VTT
50 Ω
Output
(VOUT)
Timing Reference Point
30 pF
Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
26
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 19
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
Symbol
–5
–6
DDR400B
DDR333
Unit Note1)/Test
Condition
Min.
Max.
Min.
Max.
DQ output access time from
CK/CK
tAC
–0.5
+0.5
–0.7
+0.7
ns
2)3)4)5)
CK high-level width
tCH
tCK
0.45
0.55
0.45
0.55
tCK
2)3)4)5)
5
8
6
12
ns
CL = 3.0 2)3)4)5)
6
12
6
12
ns
CL = 2.5 2)3)4)5)
7.5
12
7.5
12
ns
CL = 2.0 2)3)4)5)
tCL
tDAL
0.45
0.55
0.45
0.55
tCK
2)3)4)5)
tCK
2)3)4)5)6)
tDH
tDIPW
0.4
—
0.45
—
ns
2)3)4)5)
1.75
—
1.75
—
ns
2)3)4)5)6)
tDQSCK
–0.6
+0.6
–0.6
+0.6
ns
2)3)4)5)
DQS input low (high) pulse width tDQSL,H
(write cycle)
0.35
—
0.35
—
tCK
2)3)4)5)
—
+0.40
—
+0.40
ns
Clock cycle time
CK low-level width
Auto precharge write recovery +
precharge time
DQ and DM input hold time
DQ and DM input pulse width
(each input)
DQS output access time from
CK/CK
DQS-DQ skew (DQS and
associated DQ signals)
tDQSQ
(tWR/tCK)+(tRP/tCK)
TFBGA
2)3)4)5)
—
+0.40
—
+0.45
ns
TSOPII
2)3)4)5)
Write command to 1st DQS
latching transition
tDQSS
0.72
1.25
0.75
1.25
tCK
2)3)4)5)
DQ and DM input setup time
tDS
tDSH
0.4
—
0.45
—
ns
2)3)4)5)
0.2
—
0.2
—
tCK
2)3)4)5)
DQS falling edge to CK setup time tDSS
(write cycle)
0.2
—
0.2
—
tCK
2)3)4)5)
tHP
tHZ
min. (tCL, tCH)
—
min. (tCL, tCH)
—
ns
2)3)4)5)
—
+0.7
–0.7
+0.7
ns
2)3)4)5)7)
tIH
0.6
—
0.75
—
ns
fast slew rate
DQS falling edge hold time from
CK (write cycle)
Clock Half Period
Data-out high-impedance time
from CK/CK
Address and control input hold
time
Control and Addr. input pulse
width (each input)
Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
tIPW
3)4)5)6)8)
0.7
—
0.8
—
ns
slow slew
rate3)4)5)6)8)
2.2
—
2.2
—
ns
2)3)4)5)9)
27
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
Parameter
Address and control input setup
time
Data-out low-impedance time
from CK/CK
Symbol
tIS
tLZ
Mode register set command cycle tMRD
time
DQ/DQS output hold time
Data hold skew factor
tQH
tQHS
–5
–6
DDR400B
DDR333
Unit Note1)/Test
Condition
Min.
Max.
Min.
Max.
0.6
—
0.75
—
ns
fast slew rate
3)4)5)6)8)
0.7
—
0.8
—
ns
slow slew
rate3)4)5)6)8)
–0.7
+0.70
–0.70
+0.70
ns
2)3)4)5)7)
2
—
2
—
tCK
2)3)4)5)
tHP –tQHS
—
tHP –tQHS
—
ns
2)3)4)5)
—
+0.50
—
+0.50
ns
TFBGA
2)3)4)5)
—
+0.50
—
+0.55
ns
TSOPII
2)3)4)5)
Active to Autoprecharge delay
Active to Precharge command
Active to Active/Auto-refresh
command period
tRCD
—
tRCD
—
ns
2)3)4)5)
40
70E+3
42
70E+3
ns
2)3)4)5)
55
—
60
—
ns
2)3)4)5)
15
—
18
—
ns
2)3)4)5)
—
7.8
—
7.8
µs
2)3)4)5)8)
65
—
72
—
ns
2)3)4)5)
tRP
tRPRE
tRPST
tRRD
15
—
18
—
ns
2)3)4)5)
0.9
1.1
0.9
1.1
tCK
2)3)4)5)
0.40
0.60
0.40
0.60
tCK
2)3)4)5)
10
—
12
—
ns
2)3)4)5)
tWPRE
tWPRES
tWPST
tWR
tWTR
0.25
—
0.25
—
tCK
2)3)4)5)
0
—
0
—
ns
2)3)4)5)10)
0.40
0.60
0.40
0.60
tCK
2)3)4)5)11)
tXSNR
tRAP
tRAS
tRC
tRCD
Average Periodic Refresh Interval tREFI
Auto-refresh to Active/AutotRFC
Active to Read or Write delay
refresh command period
Precharge command period
Read preamble
Read postamble
Active bank A to Active bank B
command
Write preamble
Write preamble setup time
Write postamble
Write recovery time
Internal write to read command
delay
Exit self-refresh to non-read
command
15
—
15
—
ns
2)3)4)5)
2
—
1
—
tCK
2)3)4)5)
75
—
75
—
ns
2)3)4)5)
2)3)4)5)
Exit self-refresh to read command tXSRD
200
—
200
—
tCK
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
28
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH(ac) and VIL(ac).
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW at this time, depending
on tDQSS.
11) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
TABLE 20
AC Timing - Absolute Specifications for PC2100
Parameter
Symbol
–7
Unit
Note1)/Test
Condition
DDR266A
DQ output access time from CK/CK
CK high-level width
Clock cycle time
tAC
tCH
tCK
tCL
Auto precharge write recovery + precharge time
tDAL
DQ and DM input hold time
tDH
DQ and DM input pulse width (each input)
tDIPW
DQS output access time from CK/CK
tDQSCK
DQS input low (high) pulse width (write cycle)
tDQSL,H
DQS-DQ skew (DQS and associated DQ signals) tDQSQ
Write command to 1st DQS latching transition
tDQSS
DQ and DM input setup time
tDS
DQS falling edge hold time from CK (write cycle) tDSH
DQS falling edge to CK setup time (write cycle)
tDSS
Clock Half Period
tHP
Data-out high-impedance time from CK/CK
tHZ
Address and control input hold time
tIH
CK low-level width
Min.
Max.
–0.75
+0.75
ns
2)3)4)5)
0.45
0.55
tCK
2)3)4)5)
7.5
12
ns
CL = 3.02)3)4)5)
7.5
12
ns
CL = 2.52)3)4)5)
7.5
12
ns
CL = 2.02)3)4)5)
0.45
0.55
2)3)4)5)
(tWR/tCK)+(tRP/tCK)
—
tCK
tCK
0.5
—
ns
2)3)4)5)
1.75
—
ns
2)3)4)5)6)
–0.75
+0.75
ns
2)3)4)5)
0.35
—
tCK
2)3)4)5)
—
+0.5
ns
TSOPII 2)3)4)5)
0.75
1.25
tCK
2)3)4)5)
0.5
—
ns
2)3)4)5)
0.2
—
2)3)4)5)
0.2
—
tCK
tCK
ns
2)3)4)5)
min. (tCL, tCH)
2)3)4)5)6)
2)3)4)5)
–0.75
+0.75
ns
2)3)4)5)7)
0.9
—
ns
fast slew rate
3)4)5)6)8)
1.0
—
ns
slow slew rate
3)4)5)6)8)
Control and Addr. input pulse width (each input)
Address and control input setup time
tIPW
tIS
2.2
—
ns
2)3)4)5)9)
0.9
—
ns
fast slew rate
3)4)5)6)8)
1.0
—
ns
slow slew rate
3)4)5)6)8)
Data-out low-impedance time from CK/CK
Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
tLZ
–0.75
29
+0.75
ns
2)3)4)5)7)
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
Parameter
Symbol
–7
Unit
Note1)/Test
Condition
tCK
2)3)4)5)
ns
2)3)4)5)
DDR266A
Mode register set command cycle time
DQ/DQS output hold time
Data hold skew factor
Active to Read w/AP delay
Active to Precharge command
Active to Active/Auto-refresh command period
Active to Read or Write delay
Average Periodic Refresh Interval
Auto-refresh to Active/Auto-refresh command
period
Precharge command period
Read preamble
Read postamble
Active bank A to Active bank B command
Write preamble
Write preamble setup time
Write postamble
Write recovery time
Internal write to read command delay
Exit self-refresh to non-read command
Min.
Max.
tMRD
tQH
tQHS
tRAP
tRAS
tRC
tRCD
tREFI
tRFC
2
—
tRP
tRPRE
tRPST
tRRD
tWPRE
tWPRES
tWPST
tWR
tWTR
tXSNR
tXSRD
tHP –tQHS
—
0.75
ns
TSOPII 2)3)4)5)
tRCD
—
ns
2)3)4)5)
45
120E+3
ns
2)3)4)5)
65
—
ns
2)3)4)5)
20
—
ns
2)3)4)5)
7.8
—
µs
2)3)4)5)10)
75
—
ns
2)3)4)5)
20
—
ns
2)3)4)5)
2)3)4)5)
0.9
1.1
0.4
0.6
tCK
tCK
15
—
ns
2)3)4)5)
2)3)4)5)
0.25
—
tCK
0
—
ns
2)3)4)5)11)
0.4
—
tCK
2)3)4)5)12)
15
—
ns
2)3)4)5)
1
—
tCK
2)3)4)5)
ns
2)3)4)5)13)
tCK
2)3)4)5)
75
Exit self-refresh to read command
1) VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V ; 0 °C ≤ TA ≤ 70 °C
2)3)4)5)
200
—
2) Input slew rate ≥ 1 V/ns
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH(ac) and VIL(ac).
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
13) In all circumstances, tXSNR can be satisfied using tXSNR = tRFC,min + 1 × tCK
Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
30
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 21
IDD Conditions
Parameter
Symbol
Operating Current: one bank; active/ precharge; tRC = tRCMIN; tCK = tCKMIN;
DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two
clock cycles.
IDD0
Operating Current: one bank; active/read/precharge; Burst = 4;
Refer to the following page for detailed test conditions.
IDD1
Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤ VILMAX; tCK = tCKMIN
IDD2P
IDD2F
Precharge Floating Standby Current: CS ≥ VIHMIN, all banks idle;
CKE ≥ VIHMIN; tCK = tCKMIN, address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS
and DM.
Precharge Quiet Standby Current:
CS ≥ VIHMIN, all banks idle; CKE ≥ VIHMIN; tCK = tCKMIN, address and other control inputs stable
at ≥ VIHMIN or ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
IDD2Q
Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤ VILMAX; tCK = tCKMIN; VIN = VREF for DQ, DQS and DM.
IDD3P
Active Standby Current: one bank active; CS ≥ VIHMIN; CKE ≥ VIHMIN; tRC = tRASMAX; tCK = tCKMIN; DQ, DM and DQS IDD3N
inputs changing twice per clock cycle; address and control inputs changing once per clock cycle.
Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs changing
once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A,
CL = 3 for DDR333; tCK = tCKMIN; IOUT = 0 mA
IDD4R
Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing
once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A,
CL = 3 for DDR333; tCK = tCKMIN
IDD4W
Auto-Refresh Current: tRC = tRFCMIN, burst refresh
IDD5
IDD6
IDD7
Self-Refresh Current: CKE ≤ 0.2 V; external clock on; tCK = tCKMIN
Operating Current: four bank; four bank interleaving with BL = 4; Refer to the following page for detailed test
conditions.
Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
31
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 22
IDD Specification
Unit
Note1)/Test Condition
100
mA
×4/×8 2)3)
100
120
mA
×16 3)
100
90
110
mA
×4/×8 3)
105
125
115
140
mA
×16 3)
4
1.6
4
1.7
4
mA
3)
20
24
25
30
30
36
mA
3)
15
21
17
24
19
26
mA
3)
9
13
11
15
12
16
mA
3)
29
35
35
41
39
47
mA
×4/×8 3)
31
37
37
44
42
50
mA
×16 3)
67
78
77
90
85
100
mA
×4/×8 3)
85
100
105
125
120
145
mA
×16 3)
71
83
81
95
90
105
mA
×4/×8 3)
90
105
110
130
125
150
mA
×16 3)
IDD5
IDD6
170
205
185
220
205
245
mA
3)4)
2.6
5.0
2.7
5.0
2.8
5.0
mA
3)
2.5
2.5
2.5
2.5
2.5
2.5
mA
low power
IDD7
204
243
234
279
260
310
mA
×4/×8 3)
215
255
255
310
285
340
mA
×16 3)
–7
–6
–5
DDR266A
DDR333
DDR400B
Symbol
Typ.
Max.
Typ.
Max.
Typ.
Max.
IDD0
65
78
75
90
80
80
95
90
110
75
90
85
90
110
1.5
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
1) Test conditions for typical values: VDD = 2.5 V (DDR266, DDR333), VDD = 2.6 V (DDR400), TA = 25 °C, test conditions for maximum values:
VDD = 2.7 V, TA = 10 °C
2) IDD specifications are tested after the device is properly initialized and measured at 133 MHz for DDR266, 166 MHz for DDR333, and 200
MHz for DDR400.
3) Input slew rate = 1 V/ns.
4) Enables on-chip refresh and address counters.
Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
32
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
5
Package Outlines
There are two package types used for this product family each in lead-free and lead-containing assembly:
• P-TFBGA: Plastic Thin Fine-Pitch Ball Grid Array Package
TABLE 23
TFBGA Common Package Properties (non-green/green)
Description
Size
Units
Ball Size
0.460
mm
Recommended Landing Pad
0.350
mm
Recommended Solder Mask
0.450
mm
• P-TSOPII: Plastic Thin Small Outline Package Type II
FIGURE 4
Package Outline of P-TFBGA-60-[9/22] (green/non-green)
12
11 x 1 = 11
0.18 MAX.
1
2)
B
1)
5)
A
2)
4)
10
8 x 0.8 = 6.4
2.2 MAX.
0.8
0.2
3)
0.1 C
0.31 MIN.
1.2 MAX.
0.1 C
ø0.46 ±0.05
60x
ø0.15 M
A B
C
ø0.08 M
1) Dummy Pads without Ball
2) Middle of Packages Edges
3) Package Orientation Mark A1
4) Bad Unit Marking (BUM)
5) Die Sort Fiducial
Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
C SEATING PLANE
GPA09554
33
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
FIGURE 5
Gage Plane
0.65 Basic
0.35 +0.1
-0.05
0.805 REF
0.1
Seating Plane
10.16 ±0.13
0.25 Basic
1.20 MAX.
0.05 MIN.
Package Outline of P-TSOPII-66-1 (Lead-Free/Lead-Containing)
0.5 ±0.1
11.76 ±0.2
22.22 ±0.13
Lead 1
GPX09261
Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
34
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Pin Configuration P-TFBGA-60 Top View, see the balls throught the package . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration P-TSOPII-66-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Output Load Circuit Diagram / Timing Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline of P-TFBGA-60-[9/22] (green/non-green) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline of P-TSOPII-66-1 (Lead-Free/Lead-Containing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
35
11
12
26
33
34
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering Information for RoHS compliant products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration of DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Mode Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Extended Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Truth Table 1a: Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Truth Table 1b: DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Truth Table 2: Clock Enable (CKE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Truth Table 3: Current State Bank n - Command to Bank n (same bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Truth Table 4: Current State Bank n - Command to Bank m (different bank). . . . . . . . . . . . . . . . . . . . . . . . . . 21
Truth Table 5: Concurrent Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Electrical Characteristics and DC Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AC Timing - Absolute Specifications for PC3200 and PC2700. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AC Timing - Absolute Specifications for PC2100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
IDD Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TFBGA Common Package Properties (non-green/green) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
36
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
4.1
4.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Rev. 1.63, 2006-09
03062006-PFFJ-YJY2
37
Internet Data Sheet
Edition 2006-09
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2006.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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