LTC1740 14-Bit, 6Msps, Sampling ADC U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC®1740 is a 6Msps, 14-bit sampling A/D converter that draws only 245mW from either a single 5V or dual ±5V supplies. This easy-to-use device includes a high dynamic range sample-and-hold and a programmable precision reference. 6Msps Sample Rate 79dB S/(N + D) and 91dB SFDR at 2.5MHz fIN Single 5V Supply or ±5V Supplies Integral Nonlinearity Error: < 1LSB Differential Nonlinearity: < 0.5LSB 80MHz Full-Power Bandwidth Sampling ±2.5V and ±1.25V Bipolar Input Ranges 2.5V Signal Ground Available Out-of-Range Indicator True Differential Inputs with 75dB CMRR Power Dissipation: 245mW 36-Pin SSOP Package (0.209 Inch Width) The LTC1740 has a flexible input circuit that allows differential full-scale input ranges of ±2.5V and ±1.25V with the internal reference, or any full-scale input range up to ±2.5V with an external reference. The input common mode voltage is arbitrary, though a 2.5V reference is provided for single supply applications. DC specifications include 1LSB typical INL, 0.5LSB typical DNL and no missing codes over temperature. Outstanding AC performance includes 79dB S/(N␣ +␣ D) and 91dB SFDR at an input frequency of 2.5MHz. U APPLICATIO S ■ ■ ■ ■ ■ Telecommunications Multiplexed Data Acquisition Systems High Speed Data Acquisition Spectral Analysis Imaging Systems The unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 80MHz bandwidth. The 75dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. A separate output logic supply allows direct connection to 3V components. , LTC and LT are registered trademarks of Linear Technology Corporation. W BLOCK DIAGRA 5V 5V 1µF 8 + 1 VIN 1000pF – 2 3 VDD + AIN 9 32 VDD VDD 33 19 VDD 4096-Point FFT OVDD OF S/H –AIN 12 D7 OUTPUT BUFFERS DIGITAL CORRECTION LOGIC D6 2.5V REFERENCE 20 DIGITAL OUTPUT 26 VREF BUSY 30 VSS 29 VSS 6 GND CLK 7 GND 10 –40 –60 –80 D0 (LSB) 2.250V 1µF 18 SENSE 1µF fSMPL = 6MHz fIN = 2.5MHz, 5VP-P 5V SUPPLY –20 VCM MODE SELECT 5 0 36 D13 (MSB) PIPELINED 14-BIT ADC 1µF 4 1µF AMPLITUDE (dB) 1µF 3V TO 5V GND 34 GND 31 GND 11 OGND 28 OGND –100 27 35 1740 TA01 6MHz CLK –120 0 0.5 1.0 1.5 2.0 FREQUENCY (MHz) 2.5 3.0 1740 TA02 0V OR –5V 1740f 1 LTC1740 W U U U W W W ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION 0VDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................. 6V Negative Supply Voltage (VSS) ................................ – 6V Total Supply Voltage (VDD to VSS) ........................... 12V Analog Input Voltage (Note 3) ......................... (VSS – 0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 3) ......................... (VSS – 0.3V) to (VDD + 0.3V) Digital Output Voltage ........ (VSS – 0.3V) to (VDD + 0.3V) Power Dissipation .............................................. 500mW Operating Temperature Range LTC1740C ............................................... 0°C to 70°C LTC1740I ............................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW +AIN 1 36 OF –AIN 2 35 CLK VCM 3 34 GND SENSE 4 33 VDD VREF 5 32 VDD GND 6 31 GND GND 7 30 VSS VDD 8 29 VSS VDD 9 28 OGND GND 10 27 BUSY OGND 11 26 D0 D13 (MSB) 12 25 D1 D12 13 24 D2 D11 14 23 D3 D10 15 22 D4 D9 16 21 D5 D8 17 20 D6 D7 18 19 OVDD LTC1740CG LTC1740IG G PACKAGE 36-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 95°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. U CO VERTER CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With internal 4.500V reference. Specifications are guaranteed for both dual supply and single supply operation. (Notes 4, 5) PARAMETER CONDITIONS Resolution (No Missing Codes) Integral Linearity Error ● ● (Note 7) TYP MAX UNITS 1 ±2.5 LSB 0.5 1.25 LSB ±15 ± 60 ± 80 LSB LSB ±30 ± 75 LSB 14 (Note 6) Differential Linearity Error Offset Error MIN –1 Bits ● Full-Scale Error Full-Scale Tempco IOUT(REF) = 0 ±15 ppm/°C 1740f 2 LTC1740 U U A ALOG I PUT The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 4) SYMBOL PARAMETER CONDITIONS VIN Analog Input Range VREF = 4.5V (SENSE = 0V) VREF = 2.25V (SENSE Tied to VREF) External VREF (SENSE = 5V) IIN Analog Input Leakage Current CIN Analog Input Capacitance tACQ Sample-and-Hold Acquisition Time tAP Sample-and-Hold Aperture Delay Time tjitter Sample-and-Hold Aperture Delay Time Jitter CMRR Analog Input Common Mode Rejection Ratio W U DY A IC ACCURACY MIN TYP MAX UNITS ±2.50 ±1.25 ±VREF/1.8 ● ● ● V V V ±10 ● Between Conversions During Conversions µA 12 4 pF pF 67 ns – 900 VSS < (–AIN = +AIN) < VDD ps 0.6 psRMS 75 dB VDD = OVDD = 5V, VSS = 0V, VREF = 4.5V, AIN = – 0.1dBFS, AC coupled differential input. SYMBOL PARAMETER CONDITIONS S/(N + D) Signal-to-Noise Plus Distortion Ratio 1MHz Input Signal 2.5MHz Input Signal MIN 79.1 79.0 TYP dB dB THD Total Harmonic Distortion 1MHz Input Signal, First 5 Harmonics 2.5MHz Input Signal, First 5 Harmonics – 90 – 89 dB dB SFDR Spurious Free Dynamic Range 1MHz Input Signal 2.5MHz Input Signal 92 91 dB dB Full-Power Bandwidth 80 Input Referred Noise 0.45 MAX UNITS MHz LSBRMS U U U I TER AL REFERE CE CHARACTERISTICS TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS VCM Output Voltage IOUT = 0 2.475 2.500 2.525 V VCM Output Tempco IOUT = 0 ±15 ppm/°C VCM Line Regulation 4.75V ≤ VDD ≤ 5.25V – 5.25V ≤ VSS ≤ – 4.75V 0.6 0.03 mV/V mV/V VCM Output Resistance 0.1mA ≤ IOUT ≤ 0.1mA 8 Ω VREF Output Voltage SENSE = GND, IOUT = 0 SENSE = VREF, IOUT = 0 SENSE = VDD 4.500 2.250 Drive VREF with External Reference V V V VREF Output Tempco ±15 ppm/°C 1740f 3 LTC1740 U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 4) SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage VDD = 5.25V, VSS = 0V VDD = 5.25V, VSS = – 5V ● ● VIL Low Level Input Voltage VDD = 4.75V, VSS = 0V VDD = 4.75V, VSS = – 5V ● ● 0.8 0.8 V V IIN Digital Input Current VIN = 0V to VDD ● ±10 µA CIN Digital Input Capacitance VOH High Level Output Voltage VOL Low Level Output Voltage 0VDD = 4.75V, IO = –10µA 0VDD = 4.75V, IO = –200µA 0VDD = 2.7V, IO = –10µA 0VDD = 2.7V, IO = –200µA 0VDD = 4.75V, IO = 160µA 0VDD = 4.75V, IO = 1.6mA 0VDD = 2.7V, IO = 160µA 0VDD = 2.7V, IO = 1.6mA MIN TYP MAX UNITS 2.4 2.4 ● 4.0 ● 2.3 V V 1.8 pF 4.74 4.71 2.6 V V V V 0.05 0.10 0.05 0.10 ● ● V V V V 0.4 0.4 ISOURCE Output Source Current VOUT = 0V, 0VDD = 5V 50 mA ISINK Output Sink Current VOUT = VDD, 0VDD = 5V 35 mA U W POWER REQUIRE E TS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 4) SYMBOL PARAMETER CONDITIONS MIN VDD Positive Supply Voltage (Note 9) 4.75 OVDD Output Supply Voltage (Note 9) VSS Negative Supply Voltage Dual Supply Mode Single Supply Mode TYP MAX UNITS 5.25 V 2.7 VDD V – 5.25 – 4.75 V V 0 IDD Positive Supply Current ● 47 60 mA ISS Negative Supply Current ● 2.3 2.6 mA PD Power Dissipation ● 245 300 mW WU TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 4) SYMBOL PARAMETER CONDITIONS MIN fSAMPLE Sampling Frequency ● tCONV Conversion Time ● tACQ Acquisition Time tH tL tAP Aperature Delay of Sample-and-Hold t1 t2 TYP MAX 100 135 0.05 6 UNITS MHz ns (Note 9) ● 31 67 ns CLK High Time (Note 9) ● 20 83.3 ns CLK Low Time (Note 9) ● 20 83.3 ns – 900 ps CLK↑ to BUSY↓ 3.5 ns BUSY↑ to Outputs Valid 1.5 ns Data Latency 3 Cycles 1740f 4 LTC1740 WU TI I G CHARACTERISTICS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or above VDD without latchup. Note 4: VDD = 5V, VSS = –5V or 0V, fSAMPLE = 6MHz, tr = tf = 5ns unless otherwise specified. Note 5: Linearity, offset and full-scale specifications apply for a single-ended +AIN input with – AIN tied to VCM for single supply and 0V for dual supply. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Bipolar offset is the offset voltage measured from –0.5LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111. Note 8: Guaranteed by design, not subject to test. Note 9: Recommended operating conditions. U W TYPICAL PERFOR A CE CHARACTERISTICS Typical INL at 6Msps S/(N + D) vs Input Frequency and Amplitude Typical DNL at 6Msps 80 1.0 2.0 VIN = 0dBFS 0.8 1.5 75 0.6 VIN = –6dBFS 0.5 0 –0.5 S/(N + D) (dBc) 0.4 DNL (LSB) INL (LSB) 1.0 0.2 0 –0.2 –0.4 –1.0 –0.6 –1.5 –0.8 –2.0 –1.0 0 4096 8192 12288 8192 CODE 12288 S/(N + D) vs Input Frequency and Amplitude 0.1 1 10 INPUT FREQUENCY (MHz) SFDR and THD vs Input Frequency 95 VIN = 0dBFS 95 90 75 90 SFDR VIN = –20dBFS 60 SINGLE SUPPLY 5V INPUT RANGE DIFFERENTIAL INPUT 6Msps 75 70 65 60 55 100 1740 G04 –THD 80 AMPLITUDE (dB) AMPLITUDE (dB) 65 1 10 INPUT FREQUENCY (MHz) 85 –THD 70 0.1 SFDR 85 VIN = –6dBFS 100 1740 G03 SFDR and THD vs Input Frequency 80 S/(N + D) (dBc) 16384 DUAL SUPPLIES 5V INPUT RANGE DIFFERENTIAL INPUT 6Msps 1740 G02 1740 G01 50 VIN = –20dBFS 60 50 4096 CODE 55 65 55 0 16384 70 DUAL SUPPLIES 5V INPUT RANGE AIN = 0dBFS DIFFERENTIAL INPUT 6Msps 80 75 70 65 60 55 50 SINGLE SUPPLY 5V INPUT RANGE AIN = 0dBFS DIFFERENTIAL INPUT 6Msps 50 0.1 1 10 INPUT FREQUENCY (MHz) 100 1740 G05 0.1 1 10 INPUT FREQUENCY (MHz) 100 1740 G06 1740f 5 LTC1740 U W TYPICAL PERFOR A CE CHARACTERISTICS Spurious-Free Dynamic Range vs Input Amplitude Spurious-Free Dynamic Range vs Input Amplitude 100 100 95 dBFS dBFS 70 dBc 60 DUAL SUPPLIES 5V INPUT RANGE DIFFERENTIAL INPUT 6Msps 50 0 –50 80 70 dBc 60 SINGLE SUPPLY 5V INPUT RANGE DIFFERENTIAL INPUT 6Msps 50 0 –50 0 –40 –30 –20 –10 INPUT AMPLITUDE (dBFS) 85 AMPLITUDE (dBc) 80 75 70 65 5 6 SAMPLE FREQUENCY (MHz) Nonaveraged 4096 Point FFT Nonaveraged 4096 Point FFT 0 DUAL SUPPLIES 6Msps –20 fIN = 2.5MHz, 5VP-P DIFFERENTIAL INPUT –40 85 AMPLITIDE (dB) S/(N + D) 75 70 65 –40 –60 –80 7 –60 –80 –100 –100 –120 –120 –140 5 6 SAMPLE FREQUENCY (MHz) 8 SINGLE SUPPLY 6Msps fIN = 2.5MHz, 5VP-P DIFFERENTIAL INPUT –20 AMPLITIDE (dB) SFDR 90 8 1740 G09 0 60 SINGLE SUPPLY 5V INPUT RANGE 55 DIFFERENTIAL INPUT 6Msps 50 3 0 1 2 4 7 1740 G08 S/(N + D) and SFDR vs Sample Frequency 80 S/(N + D) 80 60 DUAL SUPPLIES 5V INPUT RANGE 55 DIFFERENTIAL INPUT 6Msps 50 3 0 1 2 4 0 –40 –30 –20 –10 INPUT AMPLITUDE (dBFS) 1740 G07 95 SFDR 90 90 SFDR (dBc AND dBFS) SFDR (dBc AND dBFS) 90 AMPLITUDE (dBc) S/(N + D) and SFDR vs Sample Frequency –140 0 0.5 2 1.5 1 FREQUENCY (MHz) 3 2.5 0 0.5 2 1.5 1 FREQUENCY (MHz) 1740 G11 1740 G10 IDD vs Clock Frequency 2.5 3 1740 G12 ISS vs Clock Frequency 2.5 49 47 2.0 VREF = 4.5V ISS (mA) IDD (mA) 45 43 41 VREF = 2.25V 1.5 1.0 39 0.5 37 0 35 0 1 4 3 5 2 CLOCK FREQUENCY (MHz) 6 1740 G13 0 1 5 2 3 4 CLOCK FREQUENCY (MHz) 6 1740 G14 1740f 6 LTC1740 U U U PIN FUNCTIONS + AIN (Pin 1): Positive Analog Input. – AIN (Pin 2): Negative Analog Input. VCM (Pin 3): 2.5V Reference Output. Optional input common mode for single supply operation. Bypass to GND with a 1µF to 10µF ceramic capacitor. SENSE (Pin 4): Reference Programming Pin. Ground selects VREF = 4.5V. Short to VREF for VREF = 2.25V. Connect SENSE to VDD to drive VREF with an external reference. Connect SENSE directly to VDD, VREF or GND. Do not drive SENSE with a logic signal. VREF (Pin 5): DAC Reference. Bypass to GND with a 1µF to 10µF ceramic capacitor. GND (Pins 6, 7, 10, 31, 34): Analog Power Ground. VDD (Pins 8, 9): Analog 5V Supply. Bypass to GND with a 1µF to 10µF ceramic capacitor. (Do not share a capacitor with Pins 32 and 33.) OGND (Pins 11, 28): Output Logic Ground. Connect to GND. OVDD (Pin 19): Positive Supply for the Output Logic. Can be 2.7V to 5.25V. Bypass to GND with a 1µF to 10µF ceramic capacitor. BUSY (Pin 27): BUSY is low when a conversion is in progress. When a conversion is finished and the ADC is acquiring the input signal, BUSY is high. Either the falling edge of BUSY or the rising edge of CLK can be used to latch the output data. VSS (Pins 29, 30): Negative Supply. Can be – 5V or 0V. If VSS is not shorted to GND, bypass to GND with a 1µF ceramic capacitor. VDD (Pins 32, 33): Analog 5V Supply. Bypass to GND with a 1µF to 10µF ceramic capacitor (do not share a capacitor with Pins 8, 9). CLK (Pin 35): Conversion Start Signal. This active high signal starts a conversion on its rising edge. OF (Pin 36): Overflow Output. This signal is high when the digital output is 01 1111 1111 1111 or 10 0000 0000 0000. D13 to D0 (Pins 12 to 18, 20 to 26): Data Outputs. The output format is two’s complement. 1740f 7 LTC1740 W FUNCTIONAL BLOCK DIAGRA U 3V TO 5V U 5V OVDD VDD + AIN S/H PIPELINED 14-BIT ADC OF –AIN D13 (MSB) VCM DIGITAL CORRECTION LOGIC MODE SELECT OUTPUT BUFFERS D0 (LSB) SENSE 2.5V REFERENCE BUSY VREF CLK 1740 FBD VSS GND GND OGND 0V OR –5V WU W TI I G DIAGRA N+1 ANALOG INPUT N N+2 tCLOCK tH N+3 tL CLK tCONV tACQ DATA OUTPUT N-3 N-2 N-1 N t2 BUSY 1740 TD t1 1740f 8 LTC1740 U W U U APPLICATIO S I FOR ATIO Conversion Details The LTC1740 is a high performance 14-bit A/D converter that operates up to 6Msps. It is a complete solution with an on-chip sample-and-hold, a 14-bit pipelined CMOS ADC and a low drift programmable reference. The digital output is parallel, with a 14-bit two’s complement format and an out-of-range (overflow) bit. The rising edge of the CLK begins the conversion. The differential analog inputs are simultaneously sampled and passed on to the pipelined A/D. After two more conversion starts (plus a 100ns conversion time) the digital outputs are updated with the conversion result and will be ready for capture on the third rising clock edge. Thus even though a new conversion is begun every time CLK goes high, each result takes three clock cycles to reach the output. The analog signals that are passed from stage to stage in the pipelined A/D are stored on capacitors. The signals on these capacitors will be lost if the delay between conversions is too long. For accurate conversion results, the part should be clocked faster than 50kHz. In some pipelined A/D converters if there is no clock present, dynamic logic on the chip will droop and the power consumption sharply increases. The LTC1740 doesn’t have this problem. If the part is not clocked for 1ms, an internal timer will refresh the dynamic logic. Thus the clock can be turned off for long periods of time to save power. 5V digital systems. For single supply operation, VSS should be connected to analog ground. For dual supply operation, VSS should be connected to – 5V. All VDD pins should be connected to a clean 5V analog supply. (Don’t connect VDD to a noisy system digital supply.) Analog Input Range The LTC1740 has a flexible analog input with a wide selection of input ranges. The input range is always differential and is set by the voltage at the VREF pin (Figure␣ 1). The input range of the A/D core is fixed at ±VREF/1.8. The reference voltage, VREF, is either set by the on-chip voltage reference or directly driven by an external voltage. Internal Reference Figure 2 shows a simplified schematic of the LTC1740 reference circuitry. An on-chip temperature compensated bandgap reference (VCM) is factory trimmed to 2.500V. The voltage at the VREF pin sets the input span of the ADC to ±VREF/1.8. An internal voltage divider converts VCM to 2.250V, which is connected to a reference amplifier. The reference programming pin, SENSE, controls how the TO ADC VREF 1µF + 1k Power Supplies The LTC1740 will operate from either a single 5V or dual ±5V supply, making it easy to interface the analog input to single or dual supply systems. The digital output drivers have their own power supply pin (OVDD) which can be set from 3V to 5V, allowing direct connection to either 3V or + VIN – R1 5k SENSE R2 5k LOGIC 2.5V REFERENCE +AIN –AIN VREF – ±VREF 1.8 ADC CORE 2.250V VCM 1µF 1740 F01 1740 F02 Figure 1. Analog Input Circuit Figure 2. Reference Circuit 1740f 9 LTC1740 U W U U APPLICATIO S I FOR ATIO reference amplifier drives the VREF pin. If SENSE is tied to ground, the reference amplifier feedback is connected to the R1/R2 voltage divider, thus making VREF = 4.500V. If SENSE is tied to VREF, the reference amplifier feedback is connected to SENSE thus making VREF = 2.250V. If SENSE is tied to VDD, the reference amplifier is disconnected from VREF and VREF can be driven by an external voltage. With additional resistors between VREF and SENSE, and SENSE and GND, VREF can be set to any voltage between 2.250V and 4.5V. An external reference or a DAC can be used to drive VREF over a 0V to 5V range (Figures 3a and 3b). The input impedance of the VREF pin is 1kΩ, so a buffer may be required for high accuracy. Driving VREF with a DAC is useful in applications where the peak input signal amplitude may vary. The input span of the ADC can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. 5V VIN VOUT VREF 1µF LT1019A-2.5 5V LTC1740 SENSE 1740 F03a Figure 3a. Using the LT1019-2.5 as an External Reference; Input Range = ±1.39V + 2.250V VREF – SENSE 5k LTC1450 VCM 1µF Figure 3b. Driving VREF with a DAC Driving the Analog Inputs The differential inputs of the LTC1740 are easy to drive. The inputs may be driven differentially or single-ended (i.␣ e., the AIN – input is held at a fixed value). The AIN – and AIN + inputs are simultaneously sampled and any common mode signal is reduced by the high common mode rejection of the sample-and-hold circuit. Any common mode input value is acceptable as long as the input pins stay between VDD and VSS. During conversion the analog inputs are high impedance. At the end of conversion the inputs draw a small current spike while charging the sample-and-hold. DC Coupling the Input LTC1740 1µF The VCM pin is a low output impedance 2.5V reference that can be used by external circuitry. For single 5V supply applications it is convenient to connect AIN – directly to the VCM pin. For superior dynamic performance in dual supply mode, the LTC1740 should be operated with the analog inputs centered at ground, and in single supply mode the inputs should be centered at 2.5V. For the best dynamic performance, the analog inputs can be driven differentially via a transformer or differential amplifier. VCM 1µF 5k Both the VCM and VREF pins must be bypassed with capacitors to ground. For best performance, 1µF or larger ceramic capacitors are recommended. For the case of external circuitry driving VREF, a smaller capacitor can be used at VREF so the input range can be changed quickly. In this case, a 0.2µF or larger ceramic capacitor is acceptable. 1740 F03b In many applications the analog input signal can be directly coupled to the LTC1740 inputs. If the input signal is centered around ground, such as when dual supply op amps are used, simply connect AIN – to ground and connect VSS to – 5V (Figure 4). In a single power supply system with the input signal centered around 2.5V, connect AIN – to VCM and VSS to ground (Figure 5). If the input signal is not centered around ground or 2.5V, the voltage for AIN – must be generated externally by a resistor divider or a voltage reference (Figure 6). 1740f 10 LTC1740 U W U U APPLICATIO S I FOR ATIO 5V 5V C 0V +AIN VIN 0V +AIN VIN LTC1740 LTC1740 –AIN –AIN R VCM 1µF C R VCM VSS 1µF 1405 F04 VSS 1740 F07 –5V Figure 4. DC Coupling a Ground Centered Signal (Dual Supply System) Figure 7. AC Coupling to the LTC1740. Note That the Input Signal Can Almost Always Be Directly Coupled with Better Performance 5V 2.5V 5V MINI CIRCUITS T1-1T +AIN VIN VIN LTC1740 15Ω +AIN 1000pF –AIN 15Ω VCM 1µF LTC1740 –AIN VCM VSS 1µF 1740 F05 Figure 5. DC Coupling a Signal Centered Around 2.5V (Single Supply System) VSS 1740 F08a Figure 8a. Single Supply Transformer Coupled Input 5V MINI CIRCUITS T1-1T 5V 15Ω +AIN 2.500V +AIN VIN 0V 1.25V VIN LTC1740 15Ω –AIN 5V 1000pF VREF 1µF LTC1740 –AIN VCM SENSE VSS 1µF 1740 F06 VSS 1740 F08b –5V Figure 8b. Dual Supply Transformer Coupled Input Figure 6. DC Coupling a 0V to 2.5V Signal Differential Operation AC Coupling the Input The analog inputs to the LTC1740 can also be AC coupled through a capacitor, though in most cases it is simpler to directly couple the input to the ADC. Figure 7 shows an example where the input signal is centered around ground and the ADC operates from a single 5V supply. Note that the performance would improve if the ADC was operated from a dual supply and the input was directly coupled (as in Figure 4). With AC coupling the DC resistance to ground should be roughly matched for AIN + and AIN – to maintain offset accuracy. The THD and SFDR performance of the LTC1740 can be improved by using a center tap RF transformer to drive the inputs differentially. Though the signal can no longer be DC coupled, the improvement in dynamic performance makes this an attractive solution for some applications. Typical connections for single and dual supply systems are shown in Figures 8a and 8b. Good choices for transformers are the Mini Circuits T1-1T (1:1 turns ratio) and T4-6T (1:4 turns ratio). For best results the transformer should be located close to the LTC1740 on the printed circuit board. 1740f 11 LTC1740 U W U U APPLICATIO S I FOR ATIO Choosing an Input Amplifier The best choice for an op amp to drive the LTC1740 will depend on the application. Generally applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. Input Filtering The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1740 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 80MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 9 shows a 1000pF capacitor from + AIN to – AIN and a 30Ω source resistor to limit the input bandwidth to 5.3MHz. The 1000pF capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the amplifier driving VIN from the ADC’s small current glitch. In undersampling applications, an input capacitor this large may prohibitively limit the input bandwidth. If this is the case, use as large an input capacitance as possible. High quality capacitors and resistors should be +AIN 1000pF LTC1740 –AIN 1740 F09 Figure 9. RC Input Filter used since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self-heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. Digital Outputs and Overflow Bit (OF) Figure 10 shows the ideal input/output characteristics for the LTC1740. The output data is two’s complement binary for all input ranges and for both single and dual supply operation. One LSB = VREF/(0.9 • 16384). To create a straight binary output, invert the MSB (D13). The overflow bit (OF) indicates when the analog input is outside the input range of the converter. OF is high when the output code is 10 0000 0000 0000 or 01 1111 1111 1111. 1 OVERFLOW 0 BIT 011…111 011…110 011…101 OUTPUT CODE Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (<100Ω) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of␣ 1 and has a unity-gain bandwidth of 50MHz, then the output impedance at 50MHz must be less than 100Ω. The second requirement is that the closed-loop bandwidth must be greater than 50MHz to ensure adequate smallsignal settling for full throughput rate. If slower op amps are used, more settling time can be provided by increasing the time between conversions. 30Ω VIN 100…010 100…001 100…000 –(FS – 1LSB) FS – 1LSB INPUT VOLTAGE (V) 1740 F10 Figure 10. LTC1740 Transfer Characteristics 1740f 12 LTC1740 U W U U APPLICATIO S I FOR ATIO Full-Scale and Offset Adjustment Timing In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset error should be adjusted before full-scale error. Figure 11 shows a method for error adjustment for a dual supply, 5.00V input range application. For zero offset error apply – 0.15mV (i.␣ e., – 0.5LSB) at + AIN and adjust R1 until the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111. For full-scale adjustment, apply an input voltage of 2.49954V (FS – 1.5LSBs) at + AIN and adjust R2 until the output code flickers between 01 1111 1111 1110 and 01 1111 1111 1111. The conversion start is controlled by the rising edge of the CLK pin. Once a conversion is started it cannot be stopped or restarted until the conversion cycle is complete. Output data is updated at the end of conversion, or about 100ns after a conversion is begun. There is an additional two cycle pipeline delay, so the data for a given conversion is output two full clock cycles plus 100ns after the convert start. Thus output data can be latched on the third CLK rising edge after the rising edge that samples the input. Digital Output Drivers The LTC1740 output drivers can interface to logic operating from 3V to 5V by setting OVDD to the logic power supply. OVDD requires a 1µF decoupling capacitor. To prevent digital noise from affecting performance, the load capacitance on the digital outputs should be minimized. If large capacitive loads are required, (>30pF) external buffers or 100Ω resistors in series with the digital outputs are suggested. Clock Input The LTC1740 only uses the rising edge of the CLK pin for internal timing, and CLK doesn’t necessarily need to have a 50% duty cycle. For optimal AC performance the rise time of the CLK should be less than 5ns. If the available clock has a rise time slower than 5ns, it can be locally sped up with a logic gate. The clock can be driven with 5V CMOS, 3V CMOS or TTL logic levels. 5V VIN 5V R1 50k +AIN 24k –AIN 100Ω LTC1740 –5V VREF 1µF 10k R2 1k SENSE VSS 1740 F11 10k –5V Figure 11. Offset and Full-Scale Adjust Circuit 1740f 13 LTC1740 U W U U APPLICATIO S I FOR ATIO As with all fast ADCs, the noise performance of the LTC1740 is sensitive to clock jitter when high speed inputs are present. The SNR performance of an ADC when the performance is limited by jitter is given by: SNR = – 20log (2π fIN tJ)dB where fIN is the frequency of an input sine wave and tJ is the root-mean-square jitter due to the clock, the analog input and the A/D aperture jitter. To minimize clock jitter, use a clean clock source such as a crystal oscillator, treat the clock signals as sensitive analog traces and use dedicated packages with good supply bypassing for any clock drivers. Board Layout To obtain the best performance from the LTC1740, a printed circuit board with a ground plane is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track. An analog ground plane separate from the logic system ground should be placed under and around the ADC. Pins␣ 6, 7, 10, 31, 34 (GND), Pins 11, 28 (OGND) and all other analog grounds should be connected to this ground plane. In single supply mode, Pins 29, 30 (VSS) should also be connected to this ground plane. All bypass capacitors for the LTC1740 should also be connected to this ground plane (Figure 12). The digital system ground 1 should be connected to the analog ground plane at only one point, near the OGND pin (Pin 28). The analog ground plane should be as close to the ADC as possible. Care should be taken to avoid making holes in the analog ground plane under and around the part. To accomplish this, we recommend placing vias for power and signal traces outside the area containing the part and the decoupling capacitors (Figure 13). Supply Bypassing High quality, low series resistance ceramic 1µF capacitors should be used at the VDD pins, VCM and VREF. If VSS is connected to – 5V it should also be bypassed to ground with 1µF. In single supply operation VSS should be shorted to the ground plane as close to the part as possible. OVDD requires a 1µF decoupling capacitor to ground. Surface mount capacitors such as the AVX 0805ZC105KAT provide excellent bypassing in a small board space. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. BYPASS CAPACITOR LTC1740 PLACE NON-GROUND VIAS AWAY FROM GROUND PLANE AND BYPASS CAPACITORS AVOID BREAKING GROUND PLANE IN THIS AREA 1740 F13 Figure 13. Cross Section of the LTC1740 Printed Circuit Board DIGITAL SYSTEM LTC1740 +AIN ANALOG GROUND PLANE 1000pF ANALOG INPUT CIRCUITRY + – 2 –AIN VCM VREF 3 GND GND VDD VDD GND OGND OVDD 5 1µF 6 1µF 7 8 9 10 1µF 11 VSS VSS GND VDD VDD GND OGND 19 29 1µF 30 1µF 31 32 33 34 28 1µF ANALOG GROUND PLANE 1740 F12 Figure 12. Power Supply Grounding 1740f 14 LTC1740 U PACKAGE DESCRIPTION G Package 36-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 12.50 – 13.10* (.492 – .516) 1.25 ±0.12 7.8 – 8.2 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 5.3 – 5.7 7.40 – 8.20 (.291 – .323) 0.42 ±0.03 0.65 BSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 RECOMMENDED SOLDER PAD LAYOUT 5.00 – 5.60** (.197 – .221) 2.0 (.079) 0° – 8° 0.09 – 0.25 (.0035 – .010) 0.55 – 0.95 (.022 – .037) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 0.65 (.0256) BSC 0.22 – 0.38 (.009 – .015) 0.05 (.002) G36 SSOP 0802 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE 1740f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC1740 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1405 LTC1406 LTC1411 LTC1412 LTC1414 LTC1420 LT1461 LTC1666 LTC1667 LTC1668 LTC1741 LTC1742 LTC1743 LTC1744 LTC1745 LTC1746 LTC1747 LTC1748 LT1807 12-Bit, 5Msps Sampling ADC with Parallel Output 8-Bit, 20Msps ADC 14-Bit, 2.5Msps ADC 12-Bit, 3Msps, Sampling ADC 14-Bit, 2.2Msps ADC 12-Bit, 10Msps ADC Micropower Precision Series Reference 12-Bit, 50Msps DAC 14-Bit, 50Msps DAC 16-Bit, 50Msps DAC 12-Bit, 65Msps ADC 14-Bit, 65Msps ADC 12-Bit, 50Msps ADC 14-Bit, 50Msps ADC 12-Bit, 25Msps ADC 14-Bit, 25Msps ADC 12-Bit, 80Msps ADC 14-Bit, 80Msps ADC 325MHz, Low Distortion Dual Op Amp Pin Compatible with the LTC1420 Undersampling Capability up to 70MHz 5V, No Pipeline Delay, 80dB SINAD ±5V, No Pipeline Delay, 72dB SINAD ±5V, 81dB SINAD and 95dB SFDR 71dB SINAD and 83dB SFDR at Nyquist 0.04% Max Initial Accuracy, 3ppm/°C Drift Pin Compatible with the LTC1668, LTC1667 Pin Compatible with the LTC1668, LTC1666 16-Bit, No Missing Codes, 90dB SINAD, –100dB THD Pin Compatible with the LTC1748 Pin Compatible with the LTC1748 Pin Compatible with the LTC1748 Pin Compatible with the LTC1748 Pin Compatible with the LTC1748 Pin Compatible with the LTC1748 Pin Compatible with the LTC1748 76.3dB SNR and 90dB SFDR Rail-to-Rail Input and Output 1740f 16 Linear Technology Corporation LT/TP 0603 1K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2003