ADS5422 ADS 542 2 SBAS250 – MARCH 2002 14-Bit, 62MSPS Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● HIGH DYNAMIC RANGE: High SFDR: 85dB at 10MHz fIN High SNR: 72dB at 10MHz fIN ● PREMIUM TRACK-AND-HOLD: Differential or Single-Ended Inputs Selectable Full-Scale Input Range ● FLEXIBLE CLOCKING: Differential or Single-Ended Accepts Sine or Square Wave Clocking Down to 0.5Vp-p Variable Threshold Level The ADS5422 is a high-dynamic range 14-bit, 62MSPS, pipelined Analog-to-Digital (A/D) converter. It includes a high-bandwidth linear track-and-hold that gives good spurious performance up to the Nyquist rate. This high-bandwidth track-and-hold also has a low jitter of only 0.25ps rms, leading to excellent SNR performance. The clock input can accept a low level differential sine wave or square wave signal down to 0.5Vp-p, further improving the SNR performance. It also accepts a single-ended clock signal and has flexible threshold levels. The ADS5422 has a 4Vp-p differential input range (2Vp-p • 2 inputs) for optimum spurious-free dynamic range. The differential operation gives the lowest even-order harmonic components. A lower input voltage can also be selected using the internal references, further optimizing SFDR. Alternatively, a single-ended input range can be used by tying the IN input to the common-mode voltage if desired. APPLICATIONS ● COMMUNICATIONS RECEIVERS ● TEST INSTRUMENTATION ● CCD IMAGING The ADS5422 also provides an over-range flag that indicates when the input signal has exceeded the converter’s full-scale range. This flag can also be used to reduce the gain of the front-end signal conditioning circuitry. The ADS5422 is available in an LQFP-64 package. +VS DV CLK ADS5422 Timing Circuitry CLK 2Vp-p IN 14-Bit Pipelined A/D Core T/H 2Vp-p IN Error Correction Logic 3-State Outputs CM (+2.5V) OVR Reference Ladder and Driver Reference and Mode Select REFT VREF SEL1 SEL2 D0 • • • D13 REFB PD OE VDRV Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY LQFP-64 PM –40°C to +85°C ADS5422Y " " " " ADS5422Y/ 250 ADS5422Y/1k5 Tape and Reel, 250 Tape and Reel, 1500 ADS5422 " NOTES: (1) For the most current specifications and package information, refer to our web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY +VS ....................................................................................................... +6V Analog Input ........................................................... (–0.3V) to (+VS +0.3V) Logic Input ............................................................. (–0.3V) to (+VS +0.3V) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +150°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. TIMING DIAGRAM N+9 N+8 N+2 N+1 Analog In N+4 N+3 N tA N+5 tL tCONV N + 10 N+7 N+6 tH Clock 10 Clock Cycles t2 Data Out N – 10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N Data Invalid t1 Data Valid Output tDV SYMBOL t CONV tL tH tA t1 t2 tDV DESCRIPTION MIN Convert Clock Period Clock Pulse LOW Clock Pulse HIGH Aperture Delay Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max Data Valid Output, CL = 15pF 16.1 7.05 7.05 TYP t CONV /2 t CONV /2 3 3.9 7.7 3 MAX UNITS 1µs ns ns ns ns ns ns ns DESIRED FULL-SCALE RANGE SEL1 SEL2 INTERNAL VREF 4Vp-p 3Vp-p 2Vp-p GND GND VREF GND +VS GND 2V 1.5V 1V NOTE: For external reference operation, tie VREF to +VS. The full-scale range will be 2x the reference value. For example, selecting a 2V external reference will set the full-scale values of 1.5V to 3.5V for both IN and IN inputs. TABLE I: Reference and Full-Scale Range Select. 2 ADS5422 www.ti.com SBAS250 ELECTRICAL CHARACTERISTICS TA = specified temperature range, typical at 25°C, differential input range = 1.5V to 3.5V, sampling rate = 62MHz, internal reference, and VDRV = 3V, unless otherwise noted. ADS5422Y PARAMETER CONDITIONS MIN RESOLUTION SPECIFIED TEMPERATURE RANGE ANALOG INPUT Standard Differential Input Range Optional Single-Ended Input Range Common-Mode Voltage Optional Input Ranges Analog Input Bias Current Input Impedance DIGITAL INPUTS Logic Family (Other Clock Inputs) Convert Command (Start Conversion) Logic Family (Other Clock Inputs) HIGH Level Input Current(4) (VIN = 5V) LOW Level Input Current (VIN = 0V) HIGH Level Input Voltage LOW Level Input Voltage Input Capacitance DIGITAL OUTPUTS Logic Family Logic Coding Low Output Voltage (IOL = 50µA to 1.6mA) High Output Voltage, (IOH = 50µA to 0.5mA) Low Output Voltage, (IOL = 50µA to 1.6mA) High Output Voltage, (IOH = 50µA to 1.6mA) 3-State Enable Time 3-State Disable Time Output Capacitance ACCURACY Zero Error (Referred to –FS) Zero Error Drift (Referred to –FS) Gain Error(5) Gain Error Drift(5) Power-Supply Rejection of Gain Internal Reference Tolerance External Reference Voltage Range Reference Input Resistance POWER-SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Current: +IS Output Driver Supply Current (VDRV = 3V) Power Dissipation: VDRV = 3V Power Down Thermal Resistance, θJA LQFP-64 MAX UNITS Bits Ambient Air –40 +85 °C 2Vp-p • 2 4Vp-p 1.5 0.5 3.5 4.5 V V V V µA MΩ || pF 62M Samples/s Clk Cyc 2.5 2Vp-p or 3Vp-p 1 1.25 || 9 Selectable CONVERSION CHARACTERISTICS Sample Rate Data Latency DYNAMIC CHARACTERISTICS Differential Linearity Error (largest code error) f = 1MHz f = 10MHz No Missing Codes Integral Nonlinearity Error, f = 10MHz Spurious-Free Dynamic Range(1) f = 1MHz f = 10MHz f = 30MHz 2-Tone Intermodulation Distortion(3) f = 14.5MHz and 15.5MHz (–7dB each tone) Signal-to-Noise Ratio (SNR) f = 1MHz f = 10MHz f = 30MHz Signal-to-(Noise + Distortion) (SINAD) f = 1MHz f = 10MHz f = 30MHz Output Noise Aperture Delay Time Aperture Jitter Overvoltage Recovery Time Full-Scale Step Acquisition Time TYP 14 Tested 1M 10 ±0.65 ±0.65 Tested ±4.0 LSB LSB LSBs 85 85 81 dBFS(2) dBFS dBFS 90 dBc 73 72 72 dBFS dBFS dBFS 72 71 71 0.6 3 0.25 2 5 dBFS dBFS dBFS LSBs rms ns ps rms ns ns +3V/+5V Logic Compatible CMOS +0.5 +VS Vp-p 78 70 67 Input Grounded Rising Edge of Convert Clock ±1.0 100 10 +2.0 +1.0 5 µA µA V V pF +3V/+5V Logic Compatible CMOS Straight Offset Binary VDRV = 3V +0.2 +2.5 VDRV = 5V +0.2 +2.5 OE = H to L OE = L to H 20 2 5 40 10 at 25°C 0.05 15 0.5 20 68 ±10 2 1.0 ±1.0 at 25°C ∆VS = ±5% REFT, REFB Deviation from Ideal 0.9 Operating Operating Operating +4.75 +5.0 240 12 1.2 40 47 ±1.0 ±50 2.025 +5.25 1.4 V V V V ns ns pF %FS ppm/°C %FS ppm/°C dB mV V kΩ V mA mA W mW °C/W NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to full scale. (3) 2-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the 2-tone fundamental envelope. (4) A 50kΩ pull-down resistor is inserted internally. (5) Includes internal reference. ADS5422 SBAS250 www.ti.com 3 PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I/O I I O O O O O O O O O O O O O O DESIGNATOR +VS +VS +VS +VS +VS +VS GND GND CLK CLK GND GND GND GND OVR DV B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 NC NC DESCRIPTION PIN I/O 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Analog Supply Voltage Analog Supply Voltage Digital Supply Voltage Digital Supply Voltage Digital Supply Voltage Digital Supply Voltage Ground Ground Convert Clock Input Complementary Clock Input Ground Ground Ground Ground Over-Range Indicator Data Valid Pulse: HI = Data Valid Data Bit 1 (D13) (MSB) Data Bit 2 (D12) Data Bit 3 (D11) Data Bit 4 (D10) Data Bit 5 (D9) Data Bit 6 (D8) Data Bit 7 (D7) Data Bit 8 (D6) Data Bit 9 (D5) Data Bit 10 (D4) Data Bit 11 (D3) Data Bit 12 (D2) Data Bit 13 (D1) Data Bit 14 (D0) (LSB) No Internal Connection No Internal Connection DESIGNATOR VDRV VDRV VDRV GND GND GND OE PD BTC GND GND SEL2 SEL1 VREF GND GND GND REFB CM REFT GND GND GND GND IN GND IN GND BYP GND +VS +VS I I DESCRIPTION Output Driver Supply Voltage Output Driver Supply Voltage Output Driver Supply Voltage Ground Ground Ground Output Enable: HI = High Impedance Power Down: HI = Power Down; LO = Normal HI = Binary Two’s Complement Ground Ground Reference Select 2: See Table I Reference Select 1: See Table I Internal Reference Voltage Ground Ground Ground Bottom Reference Voltage Bypass Common-Mode Voltage (Midscale) Top Reference Voltage Bypass Ground Ground Ground Ground Complementary Analog Input Ground Analog Input Ground Reference Bypass Ground Analog Supply Voltage Analog Supply Voltage GND IN GND IN GND GND GND GND REFT CM REFB GND 63 BYP 64 GND +VS Top View +VS PIN CONFIGURATION 62 61 60 59 58 57 56 55 54 53 52 51 50 49 LQFP +VS 1 48 GND +VS 2 47 GND +VS 3 46 VREF +VS 4 45 SEL1 +VS 5 44 SEL2 +VS 6 43 GND GND 7 42 GND GND 8 CLK 41 BTC ADS5422Y 9 40 PD 20 21 22 23 24 25 26 27 28 29 30 31 32 NC 19 NC 18 B14 17 B13 33 VDRV B12 34 VDRV DV 16 B11 OVR 15 B10 35 VDRV B9 GNDRV 14 B8 36 GNDRV B7 GNDRV 13 B6 37 GNDRV B5 GND 12 B4 38 GNDRV B3 GND 11 B2 39 OE B1 CLK 10 NC = No Internal Connection 4 ADS5422 www.ti.com SBAS250 TYPICAL CHARACTERISTICS TA = 25°C, VS = +5V, differential input range = 1.5V to 3.5V each input (4Vp-p), sampling rate = 62MSPS, internal reference, and VDRV = 3V, unless otherwise noted. SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE 0 0 fIN = 1MHz, –1dBFS –20 fIN = 10MHz, –1dBFS –20 SFDR = 85.5dBFS SFDR = 85dBFS –40 SNR = 71.9dBFS Amplitude (dB) Amplitude (dB) SNR = 72.3dBFS –60 –80 –100 –40 –60 –80 –100 –120 –120 0 5 10 15 20 25 30 0 5 10 Frequency (MHz) 15 20 SPECTRAL PERFORMANCE 0 fIN = 15MHz, –1dBFS –20 fIN = 15MHz, –3dBFS –20 SFDR = 84.0dBFS SFDR = 85.2dBFS SNR = 71.2dBFS –40 SNR = 72.7dBFS Amplitude (dB) Amplitude (dB) 30 SPECTRAL PERFORMANCE 0 –60 –80 –100 –40 –60 –80 –100 –120 –120 0 5 10 15 20 25 30 0 5 10 Frequency (MHz) 15 20 25 30 Frequency (MHz) SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE (2Vp-p) 0 0 fIN = 15MHz, –6dBFS –20 fIN = 10MHz, –3dBFS –20 SFDR = 84.6dBFS SFDR = 85.2dBFS SNR = 73.5dBFS –40 SNR = 69.8dBFS Amplitude (dB) Amplitude (dB) 25 Frequency (MHz) –60 –80 –100 –40 –60 –80 –100 –120 –120 0 5 10 15 20 25 30 0 Frequency (MHz) 10 15 20 25 30 Frequency (MHz) ADS5422 SBAS250 5 www.ti.com 5 TYPICAL CHARACTERISTICS (Cont.) TA = 25°C, VS = +5V, differential input range = 1.5V to 3.5V each input (4Vp-p), sampling rate = 62MSPS, internal reference, and VDRV = 3V, unless otherwise noted. SPECTRAL PERFORMANCE (3Vp-p) TWO-TONE INTERMODULATION DISTORTION 0 0 fIN = 10MHz, –3dBFS –20 f1 = (–7dBc) = 14.5MHz –20 SFDR = 85.1dBFS f2 = (–7dBc) = 15.5MHz SFDR = 89.7dB SNR = 71.9dBFS –40 Amplitude (dB) Amplitude (dB) –40 –60 –80 –100 –60 –80 –100 –120 –120 0 5 10 15 20 25 30 31 0 5 10 Frequency (MHz) 5 fIN = 1MHz 0.8 25 30 3 0.4 2 0.2 1 ILE (LSB) 0.6 0 –0.2 fIN = 1MHz 4 0 –1 –0.4 –2 –0.6 –3 –0.8 –4 –5 –1 0 2000 4000 6000 0 8000 10000 12000 14000 16000 2000 4000 6000 8000 10000 12000 14000 16000 Code Code SFDR AND SNR vs INPUT FREQUENCY SWEPT POWER (SFDR) 100 100 SFDR fIN = 10MHz dBc 90 90 80 80 SFDR (dBFS, dBc) SFDR, SNR (dBFS) 20 INTEGRAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR 1 DLE (LSB) 15 Frequency (MHz) SNR 70 60 70 60 50 dBFS 40 30 20 50 10 0 40 1.0 10 100 –60 Frequency (MHz) 6 –50 –40 –30 –20 –10 0 Input Amplitude (dBFS) ADS5422 www.ti.com SBAS250 TYPICAL CHARACTERISTICS (Cont.) TA = 25°C, VS = +5V, differential input range = 1.5V to 3.5V each input (4Vp-p), sampling rate = 62MSPS, internal reference, and VDRV = 3V, unless otherwise noted. OUTPUT NOISE HISTOGRAM (DC Common-Mode Input) SWEPT POWER (SNR) 600000 90 fIN = 10MHz dBFS 80 500000 400000 60 50 Count SNR (dBFS, dBc) 70 dBc 40 300000 200000 30 20 100000 10 Code 0 0 –60 –50 –40 –30 –20 –10 N–3 0 N–2 N–1 N N+1 N+2 N+3 Input Amplitude (dBFS) APPLICATION INFORMATION THEORY OF OPERATION S5 The ADS5422 is a high-speed, high-performance, CMOS A/D converter built with a fully differential pipeline architecture. Each stage contains a low-resolution quantizer and digital error correction logic ensuring good differential linearity. The conversion process is initiated by a rising edge of the external convert clock. Once the signal is captured by the input track-and-hold amplifier, the bits are sequentially encoded starting with the MSB. This process results in a data latency of 10 clock cycles after which the output data is available as a 14-bit parallel word either coded in a Straight Offset Binary or Binary Two’s Complement format. The analog input of the ADS5422 consists of a differential track-and-hold circuit, as shown in Figure 1. The differential topology produces a high level of AC performance at high sampling rates. It also results in a very high usable input bandwidth—especially important for Intermediate Frequency (IF) or undersampling applications. Both inputs (IN, IN) require external biasing up to a common-mode voltage that is typically at the mid-supply level (+VS/2). This is because the on-resistance of the CMOS switches is lowest at this voltage, minimizing the effects of the signal-dependent, nonlinearity of RON. The track-and-hold circuit can also convert a single-ended input signal into a fully differential signal for the quantizer. For ease of use, the ADS5422 incorporates a selectable voltage reference, a versatile clock input and a logic output driver designed to interface to 3V or 5V logic. S3 S1 CIN S2 CIN IN T&H IN S4 S6 Tracking Phase: S1, S2, S3, S4 closed; S5, S6 open Hold Phase: S1, S2, S3, S4 open; S5, S6 closed FIGURE 1. Simplified Circuit of Input Track-and-Hold Amplifier. ANALOG INPUTS TYPES OF APPLICATIONS The analog input of the ADS5422 can be configured in various ways and driven with different circuits, depending on the application and the desired level of performance. Offering an extremely high dynamic range at high input frequencies, the ADS5422 is particularly well suited for communication systems that digitize wideband signals. Features on the ADS5422 SBAS250 ADS5422 www.ti.com 7 ADS5422, like the input range selector, or the option of an external reference, provide the needed flexibility to accommodate a wide range of applications. In any case, the analog interface/driver requirements should be carefully examined before selecting the appropriate circuit configuration. The circuit definition should include considerations on the input frequency spectrum and amplitude, and single-ended versus differential driver configuration, as well as the available power supplies. DIFFERENTIAL VERSUS SINGLE-ENDED The ADS5422 input structure allows it to be driven either single-ended or differentially. Differential operation of the ADS5422 requires an input signal that consists of an inphase and a 180° out-of-phase component simultaneously applied to the inputs (IN, IN). Differential signals offer a number of advantages, which in many applications will be instrumental in achieving the best harmonic performance of the ADS5422: • The signal amplitude is half of that required for the singleended operation and is, therefore, less demanding to achieve while maintaining good linearity performance from the signal source. • The reduced signal swing allows for more headroom of the interface circuitry and, therefore, a wider selection of the best suitable driver amplifier. • Even-order harmonics are minimized. • Improves the noise immunity based on the converter’s common-mode input rejection. For the single-ended mode, the signal is applied to one of the inputs while the other input is biased with a DC voltage to the required common-mode level. Both inputs are identical in terms of their impedance and performance with the exception that by applying the signal to the complementary input (IN) instead of the IN input will invert the orientation of the input signal relative to the output code. For example, if the input driver operates in inverting mode, using IN as the signal input will restore the phase of the signal to its original orientation. Time-domain applications may benefit from a single-ended interface configuration and a reduced circuit complexity. Driving the ADS5422 with a single-ended signal will result in a trade-off of the excellent distortion performance, while maintaining a good Signal-to-Noise Ratio (SNR). The trade-off of the differential input configuration over the single-ended is its increase in circuit complexity. In either case, the selection of the driver amplifier should be such that the amplifier’s performance will not degrade the A/D converter's performance. INPUT FULL-SCALE RANGE VERSUS PERFORMANCE Employing dual supply amplifiers and AC-coupling will usually yield the best results. DC-coupling and/or single-supply amplifiers impose additional design constraints due to their 8 headroom requirements, especially when selecting the 4Vp-p input range. The full-scale input range of the ADS5422 is defined either by the settings of the reference select pins (SEL1, SEL2) or by an external reference voltage (see Table I). By choosing between the different signal input ranges, trade-offs can be made between noise and distortion performance. For maximizing the SNR—important for timedomain applications—the 4Vp-p range may be selected. This range may also be used with low-level (–6dBFS to –40dBFS) but high frequency inputs (multi-tone). The 3Vp-p range may be considered for achieving a combination of both low-noise and distortion performance. Here, the SNR number is typically 3dB down compared to the 4Vp-p range, while an improvement in the distortion performance of the driver amplifier may be realized due to the reduced output power level required. The third option, 2Vp-p full-scale range, may be considered mainly for applications requiring DC-coupling and/or single-supply operation of the driver and the converter. INPUT BIASING (VCM) The ADS5422 operates from a single +5V supply, and requires each of the analog inputs to be externally biased to a common-mode voltage of typically +2.5V. This allows a symmetrical signal swing while maintaining sufficient headroom to either supply rail. Communication systems are usually AC-coupled in between signal processing stages, making it convenient to set individual common-mode voltages and allow optimizing the DC operating point for each stage. Other applications, such as imaging, process mainly unipolar or DC-restored signals. In this case, the common-mode voltage may be shifted such that the full input range of the converter is utilized. It should be noted that the CM pin is not internally buffered, but ties directly to the reference ladder; therefore, it is recommended to keep loading of this pin to a minimum (< 10µA) to avoid an increase in the converter’s nonlinearity. Additionally, the DC voltage at the CM pin is not precisely +2.5V, but is subject to the tolerance of the top and bottom references, as well as the resistor ladder. Furthermore, the common-mode voltage typically declines with an increase in sampling frequency. This, however, does not affect the performance. INPUT IMPEDANCE The input of the ADS5422 is capacitive, and the driving source needs to provide the slew current to charge or discharge the input sampling capacitor while the track-andhold amplifier is in track mode (see Figure 1). This effectively results in a dynamic input impedance that is a function of the sampling frequency. Figure 2 depicts the differential input impedance of the ADS5422 as a function of the input frequency. ADS5422 www.ti.com SBAS250 domain versus frequency domain). Generally, increasing the size of the series resistor and/or capacitor will improve the signal-to-noise ratio, however, depending on the signal source, large resistor values may be detrimental to the harmonic distortion performance. In any case, the use of the RC network is optional but optimizing the values to adapt to the specific application is encouraged. DIFFERENTIAL INPUT IMPEDANCE vs INPUT FREQUENCY 1000 ZIN (kΩ) 100 10 ANALOG INPUT DRIVER CONFIGURATIONS 1 0.1 0.01 0.1 1 10 100 1000 fIN (MHz) FIGURE 2. Differential Input Impedance versus Input Frequency. For applications that use op amps to drive the A/D converter, it is recommended that a series resistor be added between the amplifier output and the converter inputs. This will isolate the converter’s capacitive input from the driving source and avoid gain peaking, or instability; furthermore, it will create a 1st-order, low-pass filter in conjunction with the specified input capacitance of the ADS5422. Its cutoff frequency can be adjusted further by adding an external shunt capacitor from each signal input to ground. The optimum values of this RC network, however, depend on a variety of factors including the ADS5422’s sampling rate, the selected op amp, the interface configuration, and the particular application (time The following section provides some principal circuit suggestions on how to interface the analog input signal to the ADS5422. Figure 3 shows an example of a typical analog interface circuit. Here, it is assumed that the input signal is already available in differential form, i.e. coming from a preceding mixer stage. The differential driver performs an impedance transformation as well as amplifying the signal to match the selected full-scale input range of the ADS5422, for example, 4Vp-p. The common-mode voltage (VCM) for the converter input is established by connecting the inputs to the midpoints of resistor divider. The input signal is AC-coupled through capacitors (CC) to the inputs of the converter which are set to a VCM of approximately +2.5VDC. Some differential driver circuits may allow setting an appropriate common-mode voltage directly at the driver input. This will simplify the interface to the ADS5422 and eliminate the external biasing resistors and the coupling capacitors. Suitable integrated circuits include the THS4131 and THS4141. These parts permit a DC-coupled interface solution; however, their use is limited to about a 10MHz input frequency, for which they maintain acceptable distortion performance providing a 2Vp-p (max) output swing on ±5V supplies. Alternatively, combining a differential driver circuit with a step-up transformer can lead to significant improvement of the distortion performance. 1kΩ 1kΩ CC 0.1µF REFT VIN IN Differential Driver CC 0.1µF ADS5422 VCM ≈ +2.5V VIN IN REFB 1kΩ NOTE: Bypassing capacitors not shown. 1kΩ FIGURE 3. AC-Coupling Allows for Easy DC Biasing of the ADS5422 Inputs While the Input Signal is Applied by the Differential Input Driver. ADS5422 SBAS250 www.ti.com 9 TRANSFORMER-COUPLED INTERFACE CIRCUITS directly tied to the CM pin of the converter, as shown in Figure 4. The value of termination resistor RT should be chosen to satisfy the termination requirements of the source impedance (RS). It can be calculated using the equation RT = n2 • RS to ensure proper impedance matching. If the application allows for AC-coupling but requires a signal conversion from a single-ended source to drive the ADS5422 differentially, using a transformer offers a number of advantages. As a passive component, it does not add to the total noise, and by using a step-up transformer, further signal amplification can be realized. As a result, the signal swing of the amplifier driving the transformer can be reduced, leading to more headroom for the amplifier and improved distortion performance. TRANSFORMER COUPLED, SINGLE-ENDED-TODIFFERENTIAL CONFIGURATION For applications in which the input frequency is limited to approximately 10MHz (e.g., baseband), a high-speed operational amplifier may be used. The OPA687 is configured for the noninverting mode; this amplifies the single-ended input signal and drives the primary of a RF transformer, as shown in Figure 5. To maintain the very low distortion performance of the OPA687, it may be advantageous to set the full-scale input range of the ADS5422 to 3Vp-p or 2Vp-p (refer to Reference section for details on selecting the converter’s full-scale range). A transformer interface solution is given in Figure 4. The input signal is assumed to be an IF and bandpass filtered prior to the IF amplifier. Dedicated IF amplifiers are commonly fixed-gain blocks and feature a very high bandwidth, a low-noise figure and high-intercept point, but at the expense of high quiescent currents, which are often around 100mA. The IF amplifier may be AC-coupled, or directly connected to the primary side of the transformer. A variety of miniature RF transformers are readily available from different manufacturers, (e.g., Mini-Circuits, Coilcraft, or Trak). For selection, it is important to carefully examine the application requirements and determine the correct model, the desired impedance ratio, and frequency characteristics. Furthermore, the appropriate model must support the targeted distortion level and should not exhibit any core saturation at full-scale voltage levels. Since the transformer does not appreciably load the A/D converter’s reference, its center tap can be The circuit also shows the use of an additional RC low-pass filter placed in series with each converter input. This optional filter can be used to set a defined corner frequency and attenuate some of the wideband noise. The actual component values would need to be tuned for individual application requirements. As a guideline, resistor values are typically in the range of 10Ω to 100Ω, and capacitors in the range of 10pF to 200pF. In any case, the RIN and CIN values should have a low tolerance. This will ensure that the ADS5422 sees closely matched source impedances. +5V Optional Bandpass Filter VIN (IF) IF Amplifier XFR 1:n RS RIN IN RT CIN RIN ADS5422 IN CIN CM VCM ≈ +2.5V NOTE: Supply bypassing not shown. + 2.2µF 0.1µF FIGURE 4. Driving the ADS5422 with a Low Distortion RF Amplifier and a Transformer Suited for IF Sampling Applications. +5V –5V +5V RG RS VIN OPA687 0.1µF RIN 1:n IN RT R1 RIN CIN ADS5422 IN CIN VCM ≈ +2.5V CM R2 + 2.2µF 0.1µF FIGURE 5. Converting a Single-Ended Input Signal into a Differential Signal Using a RF Transformer. 10 ADS5422 www.ti.com SBAS250 AC-COUPLED, DIFFERENTIAL INTERFACE WITH GAIN two tones, each 2Vp-p across the OPA687 outputs. The lower curve is for a 2Vp-p envelope resulting in a 1Vp-p amplitude per tone. The basic measurement dynamic range for the two close-in spurious tones is approximately 85dBc. The 4Vp-p test does not show measurable 3rd-order spurious until 25MHz, while the 2Vp-p is unmeasurable up to 40MHz center frequency. 2-tone, 2nd-order intermodulation distortion was unmeasurable for this circuit. The interface circuit example presented in Figure 6 employs two OPA687s, (decompensated voltage feedback op amps), optimized for gains of 12V/V or higher. Implementing a new compensation technique allows to operate the OPA687s with a reduced signal gain of 8.5V/V, while maintaining the high loop gain and the associated excellent distortion performance offered by the decompensated architecture. For a detailed discussion on this circuit and the compensation scheme, refer to the OPA687 data sheet. Input transformer, T1, converts the single-ended input signal to a differential signal required at the amplifier’s inverting inputs, which are tuned to provide a 50Ω impedance match to an assumed 50Ω source. To achieve the 50Ω input match at the primary of the 1:2 transformer, the secondary must see a 200Ω load impedance. Both amplifiers are configured for the inverting mode resulting in close gain and phase matching of the differential signal. This technique, along with a highly symmetrical layout, is instrumental in achieving a substantial reduction of the second harmonic, while retaining excellent 3rd-order performance. A common-mode voltage, VCM, is applied to the noninverting inputs of the OPA687. Additional series 20Ω resistors isolate the output of the op amps from the capacitive load presented by the 80pF capacitors and the input capacitance of the ADS5422. This 20Ω/80pF combination sets a pole at approximately 88MHz and rolls off some of the wideband noise resulting in a reduction of the noise floor. If the application requires a DC-coupled interface and conversion from a single-ended source to differential, a circuit using the dual op amp OPA2686 may be considered (refer to Figure 7 of the OPA2686 data sheet). The use of this circuit will be limited to approximately 10MHz input frequency. 3rd-Order Spurious (dBc) –60 –65 4Vp-p –70 –75 2Vp-p –80 –85 0 5 10 15 20 25 30 35 40 45 50 Center Frequency (MHz) FIGURE 7. Measured 2-Tone, 3rd-Order Distortion for Differential A/D Converter Driver. The measured 2-tone, 3rd-order distortion for the amplifier portion of the circuit of Figure 6 is shown in Figure 7. The upper curve is for a total 2-tone envelope of 4Vp-p, requiring +5V VCM 100Ω 20Ω OPA687 –5V +5V 1.7pF T1 50Ω Source 1:2 39pF 850Ω IN 80pF < 6dB Noise Figure 39pF ADS5422 850Ω IN 1.7pF 80pF 100Ω +5V 20Ω OPA687 VCM –5V FIGURE 6. High Dynamic Range Interface Circuit with the OPA687 Set for a Gain of +8.5V/V. ADS5422 SBAS250 www.ti.com 11 REFERENCE REFERENCE OPERATION Integrated into the ADS5422 is a bandgap reference circuit including logic that provides a +1V, +1.5V, or +2V reference output by selecting the corresponding pin-strap configuration. Table I gives a complete overview of the possible reference options and pin configurations. Figure 8 shows the basic model of the internal reference circuit. The functional blocks are a 1V bandgap voltage reference, a selectable gain amplifier, the drivers for the topand bottom reference (REFT, REFB), and the resistive reference ladder. The ladder resistance measures approximately 1kΩ between the REFT and REFB pin. The ladder is split into two equal segments establishing a common-mode voltage at the ladder midpoint, labeled ‘CM’. The ADS5422 requires solid bypassing for all reference pins to keep the effects of clock feedthrough to a minimum and to achieve the specified level of performance. Figure 8 shows the recommended DESIRED FULL-SCALE RANGE (FSR) (DIFFERENTIAL) decoupling scheme. All 0.1µF capacitors should be located as close to the pins as possible. In addition, pins REFT, CM, and REFB should be decoupled with tantalum surface-mount capacitors (2.2µF or 4.7µF). When operating the ADS5422 with the internal reference, the effective full-scale input span for each of the inputs, IN and IN, is determined by the voltage at the VREF pin, given to: (1) Input Span (differential, each input) = VREF = (REFT – REFB) in Vp-p (2) Input Span (single-ended) = 2 • VREF = 2 • (REFT – REFB) in Vp-p The top and bottom reference outputs may be used to provide up to 1mA of current (sink or source) to external circuits. Degradation of the Differential Linearity (DNL) and, consequently, the dynamic performance, of the ADS5422 may occur if this limit is exceeded. CONNECT SEL1 (PIN 45) TO: CONNECT SEL2 (PIN 44) TO: VOLTAGE AT VREF (PIN 46) 4Vp-p (+16dBm) GND GND +2.0V +3.5V +1.5V 3Vp-p (+13dBm) GND +Vs +1.5V +3.25V +1.75V 2Vp-p (+10dBm) VREF GND +1.0V +3.0V +2.0V – – > +3.5V +2.75V to +4.5V +0.5V to +2.25V External Reference VOLTAGE AT REFT (PIN 52) VOLTAGE AT REFB (PIN 50) TABLE I. Reference Pin Configurations and Corresponding Voltages on the Reference Pins. SEL1 SEL2 45 REFBY 61 0.1µF 44 Range Select and Gain Amplifier Top Reference Driver REFT 52 0.1µF + 2.2µF 500Ω CM +1VDC Bandgap Reference 51 0.1µF + 2.2µF 500Ω Bottom Reference Driver ADS5422 REFB 50 0.1µF + 2.2µF 46 VREF 0.1µF FIGURE 8. Internal Reference Circuit of the ADS5422 and Recommended Bypass Scheme. 12 ADS5422 www.ti.com SBAS250 USING EXTERNAL REFERENCES while the complementary clock input (CLK) should be bypassed to ground by a low-inductance ceramic chip capacitor, as shown in Figure 11. Depending on the quality of the signal, inserting a series, damping resistor may be beneficial to reduce ringing. When digitizing at high sampling rates the clock should have a 50% duty cycle (tH = tL) to maintain a good distortion performance. For even more design flexibility, the ADS5422 can be operated with external reference. The utilization of an external reference voltage may be considered for applications requiring higher accuracy, improved temperature stability, or a continuous adjustment of the converter’s full-scale range. Especially in multichannel applications, the use of a common external reference offers the benefit of improving the gain matching between converters. Selection between internal or external reference operation is controlled through the VREF pin. The internal reference will become disabled if the voltage applied to the VREF pin exceeds +3.5VDC. Once selected, the ADS5422 requires two reference voltages—a top reference voltage applied to the REFT pin and a bottom reference voltage applied to the REFB pin (see Table I). As illustrated in Figure 9, a micropower reference (REF1004) and a dual, singlesupply amplifier (OPA2234) may be used to generate a precision external reference. Note that the function of the range select pins, SEL1 and SEL2, are disabled while the converter is operating in external reference mode. +5V ADS5422 R3 8.5kΩ R1 8.5kΩ CLK CLK R2 4kΩ R4 4kΩ FIGURE 10. The Differential Clock Inputs are Internally Biased. DIGITAL INPUTS AND OUTPUTS CLOCK INPUT CLK TTL/CMOS Clock Source (3V/5V) Unlike most A/D converters, the ADS5422 contains an internal clock conditioning circuitry. This enables the converter to adapt to a variety of application requirements and different clock sources. With no input signal connected to either clock pin, the threshold level is set to approximately +1.6V by the on-chip resistive voltage divider, as shown in Figure 10. The parallel combination of R1 || R2 and R3 || R4 sets the input impedance of the clock inputs (CLK, CLK) to approximately 2.7kΩ single-ended, or 5.5kΩ differentially. The associated ground referenced input capacitance is approximately 5pF for each input. If a logic voltage other than the nominal +1.6V is desired, the clock inputs can be externally driven to establish an alternate threshold voltage. CLK 47nF FIGURE 11. Single-Ended TTL/CMOS Clock Source. Applying a single-ended clock signal will provide satisfactory results in many applications. However, unbalanced high-speed logic signals can introduce a high amount of disturbances, such as ringing or ground bouncing. In addition, a high amplitude may cause the clock signal to have unsymmetrical rise and fall times, potentially effecting the converter distortion performance. Proper termination practice and a clean PC board layout will help to keep those effects to a minimum. The ADS5422 can be interfaced to standard TTL or CMOS logic and accepts 3V or 5V compliant logic levels. In this case, the clock signal should be applied to the CLK input, +5V +5V 1/2 OPA2234 4.7kΩ REFT + R3 + 2.2µF 0.1µF ADS5422 R4 R1 REF1004 +2.5V ADS5422 10µF 1/2 OPA2234 R2 REFB + 0.1µF 2.2µF 0.1µF FIGURE 9. Example for an External Reference Circuit Using a Dual, Single-Supply Op Amp. ADS5422 SBAS250 www.ti.com 13 To take full advantage of the excellent distortion performance of the ADS5422, it is recommended to drive the clock inputs differentially. A low level, differential clock improves the digital feedthrough immunity and minimizes the effect of modulation between the signal and the clock. Figure 12 illustrates a simple method of converting a square wave clock from single-ended to differential using an RF transformer. Small surface-mount transformers are readily available from several manufacturers (e.g., model ADT1-1 by Mini-Circuits). A capacitor in series with the primary side may be inserted to block any DC voltage present in the signal. Since the clock inputs are self-biased, the secondary side connects directly to the two clock inputs of the converter. Figure 13. To calculate the correct value for this resistor, consider the impedance ratio of the selected transformer and the differential clock input impedance of the ADS5422, which is approximately 5.5kΩ. XFR 1:1 RF Sine Source CLK ADS5422 RT CLK FIGURE 13. Applying a Sinusoidal Clock to the ADS5422. Square Wave Clock Source RS 0.1µF XFR 1:1 RT CLK ADS5422 It is not recommended to employ any type of differential TTL logic which suffers from mismatch in delay time and slew rate, leading to performance degradation. Alternatively, a low jitter ECL or PECL clock may be AC-coupled directly to the clock inputs using small (0.1µF) capacitors. CLK MINIMUM SAMPLING RATE FIGURE 12. Connecting a Ground Referenced Square Wave Clock Source to the ADS5422 Using a RF Transformer. The clock inputs of the ADS5422 can be connected in a number of ways. However, the best performance is obtained when the clock input pins are driven differentially. Operating in this mode, the clock inputs accommodate signal swings ranging from 2.5Vp-p down to 0.5Vp-p differentially. This allows direct interfacing of clock sources such as voltagecontrolled crystal oscillators (VCXO) to the ADS5422. The advantage here is the elimination of external logic, usually necessary to convert the clock signal into a suitable logic (TTL or CMOS) signal which otherwise would create an additional source of jitter. In any case, a very low-jitter clock is fundamental to preserving the excellent AC performance of the ADS5422. The converter itself is specified for a very low 0.25ps (rms) jitter, characterizing the outstanding capability of the internal clock and track-and-hold circuitry. Generally, as the input frequency increases, the clock jitter becomes more dominant for maintaining a good signal-tonoise ratio. This is particularly critical in IF sampling applications where the sampling frequency is lower than input frequency (undersampling). The following equation can be used to calculate the achievable SNR for a given input frequency and clock jitter (tJA in ps rms): SNR = 20 log10 1 (2π fINt JA ) (3) Depending on the nature of the clock source’s output impedance, an impedance matching might become necessary. For this, a termination resistor, RT, may be installed, as shown in 14 The pipeline architecture of the ADS5422 uses a switched capacitor technique in its internal track-and-hold stages. With each clock cycle, charges representing the captured signal level are moved within the A/D pipeline core. The high sampling speed necessitates the use of very small capacitor values. In order to hold the droop errors LOW, the capacitors require a minimum ‘refresh rate’. To maintain accuracy of the acquired sample charge the sampling clock on the ADS5422 should not drop below the specified minimum of 1MHz. DATA OUTPUT FORMAT (BTC) The ADS5422 makes two data output formats available, either the Straight Offset Binary (SOB) code or the Binary Two’s Complement (BTC) code. The selection of the output coding is controlled through the BTC pin. Applying a logic HIGH will enable the BTC coding, while a logic LOW will enable for the Straight Offset Binary code. The BTC output format is widely used to interface to microprocessors for example. The two code structures are identical with the exception that the MSB is inverted for the BTC format, see Tables II and III. SINGLE-ENDED INPUT (IN = VCM) STRAIGHT OFFSET BINARY (SOB) BINARY TWO’S COMPLEMENT (BTC) +FS – 1LSB (IN = VCM + FSR/2) 11 1111 1111 1111 01 1111 1111 1111 +1/2 FS 11 0000 0000 0000 01 0000 0000 0000 Bipolar Zero (IN = VCM) 10 0000 0000 0000 00 0000 0000 0000 –1/2 FS 01 0000 0000 0000 11 0000 0000 0000 –FS (IN = VCM – FSR/2) 00 0000 0000 0000 10 0000 0000 0000 TABLE II. Coding Table for Single-Ended Input Configuration with IN Tied to the Common-Mode Voltage (VCM). ADS5422 www.ti.com SBAS250 DIFFERENTIAL INPUT STRAIGHT OFFSET BINARY (SOB) BINARY TWO’S COMPLEMENT (BTC) +FS – 1LSB (IN = +3.5V, IN = +1.5V) 11 1111 1111 1111 01 1111 1111 1111 +1/2 FS 11 0000 0000 0000 01 0000 0000 0000 Bipolar Zero (IN = IN = VCM) 10 0000 0000 0000 00 0000 0000 0000 –1/2 FS 01 0000 0000 0000 11 0000 0000 0000 –FS (IN = +1.5V, IN = +3.5V) 00 0000 0000 0000 10 0000 0000 0000 TABLE III. Coding Table for Differential Input Configuration and 4Vp-p Full-Scale Input Range. OUTPUT ENABLE (OE ) The digital outputs of the ADS5422 can be set to high impedance (tri-state) exercising the output enable pin (OE). For normal operation, this pin must be at a logic LOW potential while a logic HIGH voltage disables the outputs. Even though this function effects the output driver stage, the threshold voltages for the OE pin does not depend on the output driver supply (VDRV), but are fixed (see the Electrical Characteristics Table and the Digital Inputs Sections). Operating the OE function dynamically (e.g., high-speed multiplexing) should be avoided as it will corrupt the conversion process. capacitance of external logic buffer, and 1pF PC board parasitics), a bit transition can cause a dynamic current of (10pF • 0.8V/1ns = 8mA). These high current surges can feed back to the analog portion of the ADS5422 and adversely affect the performance. If necessary, external buffers or latches close to the converter’s output pins may be used to minimize the capacitive loading. They also provide the added benefit of isolating the ADS5422 from any digital activities on the bus coupling back high frequency noise. POWER SUPPLIES When defining the power supplies for the ADS5422, it is highly recommended to consider linear supplies instead of switching types. Even with good filtering, switching supplies may radiate noise that could interfere with any high frequency input signal and cause unwanted modulation products. At its full conversion rate of 62MSPS, the ADS5422 typically requires 240mA of supply current on the +5V supply (+VS). Note that this supply voltage should stay within a 5% tolerance. The ADS5422 does not require separate analog and digital supplies, but only one single +5V supply to be connected to all its +VS pins. This is with the exception of the output driver supply pin, VDRV. POWER DISSIPATION POWER-DOWN (PD) A power-down pin is provided which, when taken HIGH, shuts down portions within the ADS5422 and reduces the power dissipation to less than 40mW. The remaining active blocks include the internal reference ensuring a fast reactivation time. During power-down, data in the converter pipeline will be lost and new valid data will be subject to the specified pipeline delay. If the PD pin is not used, it should be tied to ground or a logic LOW level. A majority of the ADS5422’s total power consumption is used for biasing, therefore, independent of the applied clock frequency. Figure 14 shows the typical variation in power consumption versus the clock speed. The current on the VDRV supply is directly related to the capacitive loading of the data output pins and care should be taken to minimize such loading. POWER DISSIPATION vs CLOCK FREQUENCY 45 fIN = 10MHz OVER RANGE INDICATOR (OVR) 40 Sample Rate (MSPS) If the analog input voltage exceeds the full-scale range set by the reference voltages, an over range condition exists. The ADS5422 incorporates a function that monitors the input voltage and detects any such out-of-range condition. The current state can be read at the over range indicator pin (OVR). This output is LOW when the input voltage is within the defined input range. It will change to a HIGH if the applied signal exceeds the full-scale range. It should be noted that the OVR output is updated along with the data output corresponding to the particular sampled analog input voltage. Therefore, the OVR data is subject to the same pipeline delay as the digital data (10 clock cycles). 35 30 25 20 15 700 720 740 760 780 800 820 840 880 Power Dissipation (mW) FIGURE 14. Power Dissipation versus Clock Frequency. OUTPUT LOADING It is recommended to keep the capacitive loading on the data output lines as low as possible, preferably below 15pF. Higher capacitive loading will cause larger dynamic currents as the digital outputs are changing. For example, with a typical output slew rate of 0.8V/ns and a total capacitive loading of 10pF (including 4pF output capacitance, 5pF input ADS5422 SBAS250 www.ti.com 15 DIGITAL OUTPUT DRIVER SUPPLY (VDRV) swing and reduce current glitches on the supply line that may affect the AC performance of the converter. The analog supply (+VS) and driver supply (VDRV) may be tied together, with a ferrite bead or inductor between the supply pins. Each of the these supply pins must be bypassed separately with at least one 0.1µF ceramic chip capacitor, forming a pi-filter, as shown in Figure 15. The recommended operation for the ADS5422 is +5V for the +VS pins and +3.3V on the output driver pin (VDRV). A dedicated supply pin, VDRV, provides power to the logic output drivers of the ADS5422 and may be operated with a supply voltage in the range of +3.0V to +5.0V. This can simplify interfacing to various logic families, in particular lowvoltage CMOS. It is recommended to operate the ADS5422 with a +3.3V supply voltage on VDRV. This will lower the power dissipation in the output stages due to the lower output VIN 50Ω ADT2-1 4.7µF + +VA (5V) 0.1µF 0.1µF 22Ω 59 58 57 56 55 54 53 52 51 50 49 GND IN GND IN GND GND GND GND REFT CM REFB GND 1 +VS GND 48 2 +VS GND 47 3 +VS VREF 46 4 +VS SEL1 45 5 +VS SEL2 44 6 +VS GND 43 7 GND GND 42 8 GND BTC 41 PD 40 ADS5422 38 GNDRV 37 13 GNDRV GNDRV 36 14 GNDRV VDRV 35 15 OVR VDRV 34 16 DV VDRV 33 NC GNDRV GND NC GND 12 B14 11 B13 39 B12 OE B11 CLK B10 10 B9 CLK B8 9 B7 RT 60 B6 50Ω 0.1µF ADT2-1 61 B5 RS 62 B4 CLKIN 0.1µF B3 0.1µF 0.1µF B2 0.01µF 10pF B1 0.1µF 63 10pF 4.7µF + GND +VS 64 +VS 10µF + 0.1µF 4.7µF + REFBY 0.1µF 22Ω 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 0.1µF 0.01µF NC NC D13 D12 D11 D9 D10 D8 D7 D6 D5 D4 D3 D2 D1 OVR DV DO 0.1µF 10µF + 0.1µF +VD (3.3V) FIGURE 15. Basic Application Circuit of the ADS5422 Includes Recommended Supply and Reference Bypassing. 16 ADS5422 www.ti.com SBAS250 LAYOUT AND DECOUPLING CONSIDERATIONS Proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for high frequency designs. Achieving optimum performance with a fast sampling converter like the ADS5422 requires careful attention to the PC board layout to minimize the effect of board parasitics and optimize component placement. A multilayer board usually ensures best results and allows convenient component placement. The ADS5422 should be treated as an analog component and the +VS pins connected to a clean analog supply. This will ensure the most consistent results, since digital supplies often carry a high level of switching noise which could couple into the converter and degrade the performance. As mentioned previously, the driver supply pins (VDRV) should also be connected to a low-noise supply. Supplies of adjacent digital circuits may carry substantial current transients. The supply voltage must be thoroughly filtered before connecting to the VDRV supply of the converter. All ground connections on the ADS5422 are internally bonded to the metal flag (bottom of package) that forms a large ground plane. All ground pins should directly connect to an analog ground plane that covers the PC board area under the converter. Because of its high sampling frequency, the ADS5422 generates high frequency current transients and noise (clock feedthrough) that are fed back into the supply and reference lines. If not sufficiently bypassed, this will add noise to the conversion process. See Figure 15 for the recommended supply decoupling scheme for the ADS5422. All +VS pins may be connected together and bypassed with a combination of 10nF, 0.1µF ceramic chip capacitors (0805, low ESR) and a 10µF tantalum tank capacitor. A similar approach may be used on the driver supply pins, VDRV. In order to minimize the lead and trace inductance, the capacitors should be located as close to the supply pins as possible. They are best placed directly under the package where double-sided component mounting is allowed. In addition, larger bipolar decoupling capacitors (2.2µF to 10µF), effective at lower frequencies, should also be used on the main supply pins. They can be placed on the PC board in proximity (< 0.5") of the A/D converter. If the analog inputs to the ADS5422 are driven differentially, it is especially important to optimize towards a highly symmetrical layout. Small trace length differences may create phase shifts compromising a good distortion performance. For this reason, the use of two single op amps rather than one dual amplifier, enables a more symmetrical layout and a better match of parasitic capacitances. The pin orientation of the ADS5422 package follows a ‘flow-through’ design with the analog inputs located on one side of the package while the digital outputs are located on the opposite side of the quad-flat package. This provides a good physical isolation between the analog and digital connections. While designing the layout, it is important to keep the analog signal traces separated from any digital lines to prevent noise coupling onto the analog portion. Try to match trace length for the differential clock signal (if used) to avoid mismatches in propagation delays. Singleended clock lines must be short and should not cross any other signal traces. Short circuit traces on the digital outputs will minimize capacitive loading. Trace length should be kept short to the receiving gate (< 2") with only one CMOS gate connected to one digital output. If possible, the digital data outputs should be buffered (with 74LCX571, for example). Dynamic performance may also be improved with the insertion of series resistors at each data output line. This sets a defined time constant and reduces the slew rate that would otherwise flow due to the fast edge rate. The resistor value may be chosen to result in a time constant of 15% to 25% of the used data rate. ADS5422 SBAS250 www.ti.com 17 PACKAGE DRAWING MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. 18 All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads. 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