LTC1750 14-Bit, 80Msps Wide Bandwidth ADC DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®1750 is an 80Msps, 14-bit A/D converter designed for digitizing wide dynamic range signals up to frequencies of 500MHz. The input range of the ADC can be optimized with the on-chip PGA sample-and-hold circuit and flexible reference circuitry. Sample Rate: 80Msps 500MHz Full Power Bandwidth S/H Direct IF Sampling Up to 500MHz PGA Front End (2.25VP-P or 1.35VP-P Input Range) 75.5dB SNR and 90dB SFDR (PGA = 0) 73dB SNR and 90dB SFDR (PGA = 1) No Missing Codes Single 5V Supply Power Dissipation: 1.45W Two Pin Selectable Reference Values Two’s Complement or Offset Binary Outputs Out-of-Range Indicator Data Ready Output Clock Pin-for-Pin Family 48-Pin TSSOP Package The LTC1750 has a highly linear sample-and-hold circuit with a bandwidth of 500MHz. The SFDR is 82dB with an input frequency of 250MHz. Ultralow jitter of 0.12psRMS allows undersampling of IF frequencies with minimal degradation in SNR. DC specs include ±3LSB INL and no missing codes. The digital interface is compatible with 5V, 3V, 2V and LVDS logic systems. The ENC and ENC inputs may be driven differentially from PECL, GTL and other low swing logic families or from single-ended TTL or CMOS. The low noise, high gain ENC and ENC inputs may also be driven by a sinusoidal signal without degrading performance. A separate output power supply can be operated from 0.5V to 5V, making it easy to connect directly to any low voltage DSPs or FIFOs. U APPLICATIO S ■ ■ ■ ■ ■ ■ Telecommunications Receivers Cellular Base Stations Spectrum Analysis Imaging Systems MRI Tomography The 48-pin TSSOP package with a flow-through pinout simplifies the board layout. , LTC and LT are registered trademarks of Linear Technology Corporation. W ■ BLOCK DIAGRA 80Msps, 14-Bit ADC with a 2.25V Differential Input Range OVDD PGA 0.1µF AIN+ ±1.125V DIFFERENTIAL – ANALOG INPUT AIN S/H CIRCUIT CORRECTION LOGIC AND SHIFT REGISTER 14-BIT PIPELINED ADC 14 OUTPUT LATCHES SENSE • • • 0.5V TO 5V 0.1µF OF D13 D0 CLKOUT OGND BUFFER VDD RANGE SELECT VCM 1µF 1µF 5V 1µF DIFF AMP GND 2VREF CONTROL LOGIC 4.7µF 1750 BD REFLB REFHA 4.7µF REFLA 0.1µF 1µF REFHB 0.1µF 1µF ENC ENC MSBINV DIFFERENTIAL ENCODE INPUT 1750f 1 LTC1750 W U PACKAGE/ORDER INFORMATION W W U W OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ............................................. 5.5V Analog Input Voltage (Note 3) .... – 0.3V to (VDD + 0.3V) Digital Input Voltage (Note 4) ..... – 0.3V to (VDD + 0.3V) Digital Output Voltage ................. – 0.3V to (VDD + 0.3V) OGND Voltage ..............................................– 0.3V to 1V Power Dissipation ............................................ 2000mW Operating Temperature Range LTC1750C ............................................... 0°C to 70°C LTC1750I ............................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C U ABSOLUTE MAXIMUM RATINGS ORDER PART NUMBER TOP VIEW SENSE VCM GND AIN+ AIN– GND VDD VDD GND REFLB REFHA GND GND REFLA REFHB GND VDD VDD GND VDD GND MSBINV ENC ENC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 OF OGND D13 D12 D11 OVDD D10 D9 D8 D7 OGND GND GND D6 D5 D4 OVDD D3 D2 D1 D0 OGND CLKOUT PGA LTC1750CFW LTC1750IFW FW PACKAGE 48-LEAD PLASTIC TSSOP TJMAX = 150°C, θJA = 35°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. U CO VERTER CHARACTERISTICS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Full-Scale Tempco Offset Tempco Input Referred Noise (Transition Noise) CONDITIONS ● (Note 6) ● (Note 7) External Reference (VSENSE = 1.125V, PGA = 0) External Reference (VSENSE = 1.125V, PGA = 0) Internal Reference External Reference (VSENSE = 1.125V) MIN 14 –3 –1 –35 –3.5 VSENSE = 1.125V, PGA = 0 TYP MAX ±0.75 ±0.5 ±8 ±1 ±40 ±20 ±20 0.92 3 1.5 35 3.5 UNITS Bits LSB LSB mV %FS ppm/°C ppm/°C µV/°C LSBRMS U U A ALOG I PUT The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL VIN IIN CIN PARAMETER Analog Input Range (Note 8) Analog Input Leakage Current Analog Input Capacitance tACQ tAP tJITTER CMRR Sample-and-Hold Acquisition Time Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Time Jitter Analog Input Common Mode Rejection Ratio CONDITIONS 4.75V ≤ VDD ≤ 5.25V 0 < AIN+, AIN– < VDD Sample Mode ENC < ENC Hold Mode ENC > ENC MIN ● ● ● 1.5V < (AIN– = AIN+) < 3V –1 TYP MAX ±0.7 to ±1.125 1 6.9 2.4 5 6 0 0.12 80 UNITS V µA pF pF ns ns psRMS dB 1750f 2 LTC1750 W U DY A IC ACCURACY TA = 25°C, AIN = –1dBFS (Note 5), VSENSE = VDD SYMBOL PARAMETER CONDITIONS SNR Signal-to-Noise Ratio 5MHz Input Signal (PGA = 0) 5MHz Input Signal (PGA = 1) MIN 75.3 72.9 dB dB 74.6 72.8 dB dB 140MHz Input Signal (PGA = 1) 72 dB 250MHz Input Signal (PGA = 1) 70.6 dB 350MHz Input Signal (PGA = 1) 69 dB 73 70 5MHz Input Signal (PGA = 0) 90 dB 5MHz Input Signal (PGA = 1) 90 dB 90 dB 30MHz Input Signal (PGA = 0) (HD2 and HD3) 80 30MHz Input Signal (PGA = 0) Other 85 30MHz Input Signal (PGA = 1) 70MHz Input Signal (PGA = 0) S/(N + D) THD IMD Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion UNITS dB dB 70MHz Input Signal (PGA = 0) 70MHz Input Signal (PGA = 1) Spurious Free Dynamic Range MAX 75.5 73.0 30MHz Input Signal (PGA = 0) 30MHz Input Signal (PGA = 1) SFDR TYP 95 dB 90 dB 85 dB 70MHz Input Signal (PGA = 1) (HD2 and HD3) 80 90 dB 70MHz Input Signal (PGA = 1) Other 83 95 dB 140MHz Input Signal (PGA = 1) 84 dB 250MHz Input Signal (PGA = 1) 82 dB 350MHz Input Signal (PGA = 1) 74 dB 5MHz Input Signal (PGA = 0) 5MHz Input Signal (PGA = 1) 75.2 72.8 dB dB 30MHz Input Signal (PGA = 0) 30MHz Input Signal (PGA = 1) 75.1 72.6 dB dB 70MHz Input Signal (PGA = 0) 70MHz Input Signal (PGA = 1) 74.3 72.4 dB dB 250MHz Input Signal (PGA = 1) 70 dB 5MHz Input Signal, First 5 Harmonics (PGA = 0) 5MHz Input Signal, First 5 Harmonics (PGA = 1) –90 –90 dB dB 30MHz Input Signal, First 5 Harmonics (PGA = 0) 30MHz Input Signal, First 5 Harmonics (PGA = 1) –90 –90 dB dB 70MHz Input Signal, First 5 Harmonics (PGA = 0) 70MHz Input Signal, First 5 Harmonics (PGA = 1) –85 –90 dB dB 250MHz Input Signal (PGA = 1) 78 dB Intermodulation Distortion fIN1 = 2.52MHz, fIN2 = 5.2MHz (PGA = 0) fIN1 = 2.52MHz, fIN2 = 5.2MHz (PGA = 1) – 90 – 90 dBc dBc Sample-and-Hold Bandwidth RSOURCE = 50Ω 500 MHz U U U I TER AL REFERE CE CHARACTERISTICS (Note 5) PARAMETER CONDITIONS MIN TYP MAX UNITS VCM Output Voltage IOUT = 0 1.95 2 2.05 V VCM Output Tempco IOUT = 0 ±30 ppm/°C VCM Line Regulation 4.75V ≤ VDD ≤ 5.25V 3 mV/V VCM Output Resistance 1mA ≤ IOUT ≤ 1mA 4 Ω 1750f 3 LTC1750 U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN VIH High Level Input Voltage VDD = 5.25V, MSBINV and PGA ● VIL Low Level Input Voltage VDD = 4.75V, MSBINV and PGA IIN Digital Input Current VIN = 0V to VDD CIN Digital Input Capacitance MSBINV and PGA Only VOH High Level Output Voltage OVDD = 4.75V VOL Low Level Output Voltage OVDD = 4.75V MAX UNITS ● 0.8 V ● ±10 µA 2.4 IO = –10µA IO = – 200µA ● 4 IO = 160µA IO = 1.6mA TYP V 1.5 pF 4.74 V 4.74 V 0.05 0.1 ● V 0.4 V ISOURCE Output Source Current VOUT = 0V – 50 mA ISINK Output Sink Current VOUT = 5V 50 mA U W POWER REQUIRE E TS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER VDD Positive Supply Voltage CONDITIONS MIN IDD Positive Supply Current ● PDIS Power Dissipation ● OVDD Digital Output Supply Voltage TYP MAX UNITS 5.25 V 290 338 mA 1.45 1.69 W VDD V 4.75 0.5 WU TI I G CHARACTERISTICS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN t0 ENC Period (Note 9) ● t1 ENC High (Note 8) t2 ENC Low (Note 8) t3 Aperture Delay (Note 8) t4 ENC to CLKOUT Falling CL = 10pF (Note 8) t5 ENC to CLKOUT Rising CL = 10pF (Note 8) TYP MAX UNITS 12.5 2000 ns ● 6 1000 ns ● 6 1000 ns 0 ● 1 2.4 ns 4 t1 + t 4 ns ns For 80Msps 50% Duty Cycle CL = 10pF (Note 8) ● 7.25 8.65 10.25 ns t6 ENC to DATA Delay CL = 10pF (Note 8) ● 2 4.9 7.2 ns t7 ENC to DATA Delay (Hold Time) (Note 8) ● 1.4 3.4 4.7 ns t8 ENC to DATA Delay (Setup Time) CL = 10pF (Note 8) For 80Msps 50% Duty Cycle CL = 10pF (Note 8) ● 5.3 10.5 ns t9 CLKOUT to DATA Delay (Hold Time), 80Msps 50% Duty Cycle (Note 8) ● 6 ns t10 CLKOUT to DATA Delay (Setup Time), 80Msps 50% Duty Cycle CL = 10pF (Note 8) ● 2.1 ns Data Latency t0 – t 6 7.6 5 ns cycles 1750f 4 LTC1750 ELECTRICAL CHARACTERISTICS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND, they will be clamped by internal diodes. This product can handle input currents of >100mA below GND without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, fSAMPLE = 80MHz, differential ENC/ENC = 2VP-P 80MHz sine wave, input range = ±1.125V differential, unless otherwise specified. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Bipolar offset is the offset voltage measured from – 0.5 LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111. Note 8: Guaranteed by design, not subject to test. Note 9: Recommended operating conditions. U W TYPICAL PERFOR A CE CHARACTERISTICS INL 2.5 1.0 2.0 0.8 1.5 0.6 –20 0.4 –30 –40 0.5 0 –0.5 –1.0 0 –10 AMPLITUDE (dBFS) ERROR (LSB) 1.0 ERROR (LSB) 8192 Point FFT, fIN = 15.2MHz, –1dB, PGA = 0 DNL 0.2 0 –0.2 –0.4 –1.5 –0.6 –2.0 –0.8 –2.5 –1.0 0 4096 12288 8192 OUTPUT CODE –80 –100 –110 4096 12288 8192 OUTPUT CODE 1750 G01 –120 16384 0 –10 –20 –30 –40 AMPLITUDE (dBFS) –20 –30 –40 AMPLITUDE (dBFS) –20 –80 –50 –60 –70 –80 –60 –70 –80 –90 –90 –100 –100 –100 –110 –110 –110 –120 –120 –120 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 1750 G04 40 35 –50 –90 0 15 20 25 30 FREQUENCY (MHz) 0 –10 –30 –40 –70 10 8192 Point FFT, fIN = 30.2MHz, –1dB, PGA = 0 0 –10 –60 5 1750 G03 8192 Point FFT, fIN = 15.2MHz, –20dB, PGA = 0 –50 0 1750 G02 8192 Point FFT, fIN = 15.2MHz, –10dB, PGA = 0 AMPLITUDE (dBFS) –60 –70 –90 0 16384 –50 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 1750 G05 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 1750 G06 1750f 5 LTC1750 U W TYPICAL PERFOR A CE CHARACTERISTICS 8192 Point FFT, fIN = 30.2MHz, –10dB, PGA = 0 8192 Point FFT, fIN = 30.2MHz, –20dB, PGA = 0 0 –10 0 –10 –20 –20 –30 –40 –30 –40 –50 –60 –70 –80 AMPLITUDE (dBFS) –20 –30 –40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 0 –10 –50 –60 –70 –80 –60 –70 –80 –90 –90 –100 –100 –100 –110 –110 –110 –120 –120 –120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 0 –10 –20 –30 –40 AMPLITUDE (dBFS) –20 –30 –40 AMPLITUDE (dBFS) –20 –80 –50 –60 –70 –80 –60 –70 –80 –90 –90 –100 –100 –100 –110 –110 –110 –120 –120 –120 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 0 5 10 15 20 25 30 FREQUENCY (MHz) 1750 G10 35 40 0 –10 –20 –30 –40 AMPLITUDE (dBFS) –20 –30 –40 AMPLITUDE (dBFS) –20 –80 –50 –60 –70 –80 –60 –70 –80 –90 –90 –100 –100 –100 –110 –110 –110 –120 –120 –120 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 1750 G13 40 35 –50 –90 0 15 20 25 30 FREQUENCY (MHz) 0 –10 –30 –40 –70 10 8192 Point FFT, fIN = 250.2MHz, –1dB, PGA = 1 0 –10 –60 5 1750 G12 8192 Point FFT, fIN = 140.2MHz, –20dB, PGA = 1 –50 0 1750 G11 8192 Point FFT, fIN = 140.2MHz, –10dB, PGA = 1 40 35 –50 –90 0 15 20 25 30 FREQUENCY (MHz) 0 –10 –30 –40 –70 10 8192 Point FFT, fIN = 140.2MHz, –1dB, PGA = 1 0 –10 –60 5 1750 G09 8192 Point FFT, fIN = 70.2MHz, –20dB, PGA = 0 –50 0 1750 G08 8192 Point FFT, fIN = 70.2MHz, –10dB, PGA = 0 AMPLITUDE (dBFS) –50 –90 1750 G07 AMPLITUDE (dBFS) 8192 Point FFT, fIN = 70.2MHz, –1dB, PGA = 0 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 1750 G14 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 1750 G15 1750f 6 LTC1750 U W TYPICAL PERFOR A CE CHARACTERISTICS 8192 Point FFT, fIN = 250.2MHz, –10dB, PGA = 1 0 –10 0 –10 0 –10 –20 –20 –30 –40 –30 –40 –50 –60 –70 –80 AMPLITUDE (dBFS) –20 –30 –40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 8192 Point 2-Tone FFT, fIN = 26.4MHz and 27.5MHz, –7dB Each Tone, PGA = 1 8192 Point FFT, fIN = 250.2MHz, –20dB, PGA = 1 –50 –60 –70 –80 –50 –60 –70 –80 –90 –90 –90 –100 –100 –100 –110 –110 –110 –120 –120 –120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 0 5 10 15 20 25 30 FREQUENCY (MHz) 1750 G16 –20 100 100 –30 –40 90 80 90 80 –70 –80 SFDR (dBc AND dBFS) 120 110 –60 70 60 50 40 40 20 20 10 10 15 20 25 30 FREQUENCY (MHz) 35 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 40 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 SFDR vs 140.2MHz Input Level, PGA = 0 SFDR vs 250.2MHz Input Level, PGA = 0 SNR vs Input Frequency and Amplitude, PGA = 0 76 100 100 75 90 80 90 80 74 60 50 40 70 60 50 40 30 30 20 20 10 10 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 1750 G22 SNR (dBFS) 120 110 SFDR (dBc AND dBFS) 120 110 70 0 1750 G21 1750 G20 1750 G19 40 30 –110 10 35 60 –100 5 15 20 25 30 FREQUENCY (MHz) 50 30 0 10 70 –90 –120 5 SFDR vs 40.2MHz Input Level SFDR vs 15MHz Input Level 120 110 –50 0 1750 G18 0 –10 SFDR (dBc AND dBFS) AMPLITUDE (dBFS) 40 1750 G17 8192 Point 2-Tone FFT, fIN = 69.4MHz and 65.2MHz, –7dB Each Tone, PGA = 1 SFDR (dBc AND dBFS) 35 –20dB –10dB –1dB 73 72 71 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 1750 G23 70 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300 1750 G24 1750f 7 LTC1750 U W TYPICAL PERFOR A CE CHARACTERISTICS SNR vs Input Frequency and Amplitude, PGA = 1 SFDR (HD2 and HD3) vs Input Frequency and Amplitude, PGA = 0 110 74 110 –20dB 73 –20dB 100 100 –10dB 72 –20dB SFDR (dBFS) –1dB 70 69 SFDR (dBFS) –10dB 71 SNR (dBFS) SFDR (HD2 and HD3) vs Input Frequency and Amplitude, PGA = 1 90 –1dB 80 90 –10dB 80 –1dB 70 68 67 70 60 66 60 65 0 500 400 100 300 200 INPUT FREQUENCY (MHz) 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 50 300 0 100 200 300 400 INPUT FREQUENCY (Hz) 1750 G26 1750 G25 SFDR and SNR vs Sample Rate, 15.2MHz, –1dB Input 500 1750 G27 SFDR and SNR vs VDD, 15.2MHz, –1dB Input 100 100 95 95 SFDR SFDR AND SNR (dBFS) SFDR AND SNR (dBFS) SFDR 90 85 80 SNR 75 70 85 80 SNR 75 70 65 65 60 90 0 20 40 80 60 SAMPLE RATE (Msps) 100 120 1750 G28 60 4.1 4.3 4.5 4.7 4.9 VDD (V) 5.1 5.3 5.5 1750 G29 1750f 8 LTC1750 U U U PI FU CTIO S SENSE (Pin 1): Reference Sense Pin. GND selects a VREF of 0.7V. VDD selects 1.125V. When VSENSE is between 0.7V and 1.125V, VSENSE is used as VREF. The ADC input range is ±VREF/PGA gain. VCM (Pin 2): 2.0V Output and Input Common Mode Bias. Bypass to ground with 4.7µF ceramic chip capacitor. GND (Pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37): ADC Power Ground. AIN+ (Pin 4): Positive Differential Analog Input. AIN– (Pin 5): Negative Differential Analog Input. VDD (Pins 7, 8, 17, 18, 20): 5V Supply. Bypass to AGND with 1µF ceramic chip capacitors at Pin 8 and Pin 18. REFLB (Pin 10): ADC Low Reference. Bypass to Pin 11 with 0.1µF ceramic chip capacitor. Do not connect to Pin␣ 14. REFHA (Pin 11): ADC High Reference. Bypass to Pin 10 with 0.1µF ceramic chip capacitor, to Pin 14 with a 4.7µF ceramic capacitor and to ground with 1µF ceramic capacitor. REFLA (Pin 14): ADC Low Reference. Bypass to Pin 15 with 0.1µF ceramic chip capacitor, to Pin 11 with a 4.7µF ceramic capacitor and to ground with 1µF ceramic capacitor. REFHB (Pin 15): ADC High Reference. Bypass to Pin 14 with 0.1µF ceramic chip capacitor. Do not connect to Pin␣ 11. MSBINV (Pin 22): MSB Inversion Control. Low inverts the MSB, 2’s complement output format. High does not invert the MSB, offset binary output format. ENC (Pin 23): Encode Input. The input sample starts on the positive edge. ENC (Pin 24): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1µF ceramic for single-ended ENCODE signal. PGA (Pin 25): Programmable Gain Amplifier Control. Low selects an effective front-end gain of 1. High selects an effective gain of 1 2/3. The ADC input range is ±VREF/PGA gain. CLKOUT (Pin 26): Data Valid Output. Latch data on the rising edge of CLKOUT. OGND (Pins 27, 38, 47): Output Driver Ground. D0-D3 (Pins 28 to 31): Digital Outputs. OVDD (Pins 32, 43): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. D4-D6 (Pins 33 to 35): Digital Outputs. D7-D10 (Pins 39 to 42): Digital Outputs. D11-D13 (Pins 44 to 46): Digital Outputs. OF (Pin 48): Over/Under Flow Output. High when an over or under flow has occurred. 1750f 9 LTC1750 WU W TI I G DIAGRA N ANALOG INPUT • t3 t1 t2 t0 ENC t7 t8 DATA (N – 4) DB13 TO DB0 DATA (N – 5) DB13 TO DB0 DATA DATA (N – 3) t6 CLKOUT 1750 TD t4 t5 t10 t9 U W U U APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log V22 + V32 + V 42 + ...Vn2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. 1750f 10 LTC1750 U W U U APPLICATIO S I FOR ATIO Spurious Free Dynamic Range (SFDR) when sampling an AC input. The signal to noise ratio due to the jitter alone will be: Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. SNRJITTER = –20log (2π) • FIN • TJITTER CONVERTER OPERATION The LTC1750 is a CMOS pipelined multistep converter with a front-end PGA. The converter has four pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later, see the Timing Diagram section. The analog input is differential for improved common mode noise immunity and to maximize the input range. Additionally, the differential input drive will reduce even order harmonics of the sample-and-hold circuit. The encode input is also differential for improved common mode noise immunity. Input Bandwidth The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Time The time from when a rising ENC equals the ENC voltage to the instant that the input signal is held by the sample and hold circuit. The LTC1750 has two phases of operation, determined by the state of the differential ENC/ENC input pins. For brevity, the text will refer to ENC greater than ENC as ENC high and ENC less than ENC as ENC low. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. PGA AIN+ AIN– VCM FIRST PIPELINED ADC STAGE (5 BITS) INPUT S/H SECOND PIPELINED ADC STAGE (4 BITS) THIRD PIPELINED ADC STAGE (4 BITS) FOURTH PIPELINED ADC STAGE (4 BITS) 2.0V REFERENCE 4.7µF SHIFT REGISTER AND CORRECTION RANGE SELECT REFL SENSE REFH INTERNAL CLOCK SIGNALS OVDD 0.5V TO 5V OF REF BUF DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER DIFF REF AMP D13 CONTROL LOGIC AND CALIBRATION LOGIC OUTPUT DRIVERS D0 CLKOUT 1750 F01 REFLB REFHA 4.7µF 0.1µF 1µF REFLA REFHB ENC ENC MSBINV OGND 0.1µF 1µF Figure 1. Functional Block Diagram 1750f 11 LTC1750 U W U U APPLICATIO S I FOR ATIO In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and visa versa. When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that ENC transitions from low to high, the sampled input is held. While ENC is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of ENC. When ENC goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third stage, resulting in a third stage residue that is sent to the fourth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC1750 CMOS differential sample-and-hold. The differential analog inputs are sampled directly onto sampling capacitors (CSAMPLE) through NMOS switches. This direct capacitor sampling results in lowest possible noise for a given sampling capacitor size. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when ENC/ENC is low, the NMOS switch connects the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. When ENC/ENC transitions from low to high the LTC1750 VDD CSAMPLE 3.5pF AIN+ RON 30Ω CPARASITIC 2.4pF VDD CPARASITIC 1pF CSAMPLE 3.5pF RON 30Ω AIN– CPARASITIC 2.4pF CPARASITIC 1pF 5V BIAS 2V 6k ENC ENC 6k 2V 1750 F02 Figure 2. Equivalent Input Circuit sampled input voltage is held on the sampling capacitors. During the hold phase when ENC/ENC is high the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC/ENC transitions from high to low the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Common Mode Bias The ADC sample-and-hold circuit requires differential drive to achieve specified performance. Each input should swing within the valid input range, around a common mode voltage of 2.0V. The VCM output pin (Pin␣ 2) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 4.7µF or greater capacitor. 1750f 12 LTC1750 U W U U APPLICATIO S I FOR ATIO Input Drive Circuits The LTC1750 requires differential drive for the analog inputs. A balanced input drive will minimize even order harmonics that are due to nonlinear behavior of the input drive circuits and the S/H circuit. The S/H circuit of the LTC1750 is a switched capacitor circuit (Figure 2). The input drive circuitry will see a sampling glitch at the start of the sampling period, when ENC/ENC falls. Although designed to be linear as possible, a small fraction of this glitch is nonlinear and can result in additional observed distortion if the input drive circuitry is too slow. For most practical circuits the glitch nonlinearity is more than 100dB below the fundamental. The glitch will decay during the sampling period with a time constant determined by the input drive and S/H circuitry. For fast settling and wide bandwidth, a low drive impedance is required. The S/H bandwidth is partially determined by the source impedance. The full 500MHz bandwidth is valid for source impedance (each input) less than 30Ω. Higher source impedance can be used but full amplitude distortion will be better with source impedance less than 100Ω. signal at its optimum DC level of 2V. In this example a 1:1 transformer is used; however, other transformer impedance ratios may be substituted. Figure 3b shows the use of a transformer without a center tapped secondary. In this example the secondary is biased with the addition of two resistors placed in series across the secondary winding. The center tap of the secondary resistors is connected to the ADC VCM output to set the DC bias. This circuit is better suited for high input frequency applications since center tapped transformers generally have less bandwidth and poor balance at high frequencies than noncenter tapped transformers. VCM 4.7µF LTC1750 0.1µF 100Ω Transformers should be selected to have –3dB corners at least one octave away from the desired operating frequency. Transformers with larger cores usually have better performance at lower frequency and perform better when driving heavy loads. Figure 3a shows the LTC1750 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC-biased with VCM, setting the ADC input 100Ω 25Ω 12pF 25Ω AIN+ 25Ω AIN– 12pF 1750 F03 Figure 3a. Single-Ended to Differential Conversion Using a Transformer Transformers Transformers provide a simple method for converting a single-ended signal to a differential signal; however, they have poor performance characteristics at low and high input frequencies. The lower –3dB corner of RF transformers can range from tens of kHz to tens of MHz. Operation near this corner results in poor 2nd order harmonic performance due to nonlinear transformer core behavior. The upper –3dB corner can vary from tens of MHz to several GHz. Operation near the upper corner can result in poor 2nd order performance due to poor balance on the secondary. 25Ω 1:1 ANALOG INPUT 12pF VCM 4.7µF 0.1µF ANALOG INPUT 10Ω 1:4 25Ω LTC1750 AIN+ 8.4pF 200Ω 100Ω 200Ω 25Ω 10Ω AIN– 8.4pF 1750 F03b Figure 3b. Using a Transformer Without a Center Tapped Secondary Active Drive Circuits Active circuits, open loop or closed loop, can be used to drive the ADC inputs. Closed-loop circuits such as op amps have excellent DC and low frequency accuracy, but have poor high frequency performance. Figure 4 shows the dual LT®1818 op amp used for single-ended to differential 1750f 13 LTC1750 U W U U APPLICATIO S I FOR ATIO LTC1750 VCM 4.7µF 5V SINGLE-ENDED INPUT 2V ±1/2 RANGE 25Ω 25Ω 1/2 LT1818 – AIN+ 12pF 25Ω 25Ω 1/2 LT1818 – 500Ω 2V BANDGAP REFERENCE 1.125V 0.7V RANGE DETECT AND CONTROL LTC1750 + 4Ω 4.7µF 12pF + 100Ω VCM 2V TIE TO VDD FOR VREF = 1.125; TIE TO GND FOR VREF = 0.7V; VREF = VSENSE FOR 0.7V < VSENSE < 1.125V AIN– 1µF 12pF VREF SENSE REFLB 0.1µF REFHA BUFFER INTERNAL ADC HIGH REFERENCE 500Ω 1750 F04 4.7µF DIFF AMP Figure 4. Differential Drive with Op Amps 1µF REFLA signal conversion. Note that the two op amps do not have the same noise gain, which can result in poor balance at higher frequencies. The op amp configured in a gain of +1 can be configured in a noise gain of +2 with the addition of two equal valued resistors between the output and inverting input and between the two inputs. This however will raise the noise contributed by the op amps. Reference Operation Figure 5 shows the LTC1750 equivalent reference circuitry consisting of a 2V bandgap reference, a 3-to-1 switch, a switch control circuit and a difference amplifier. The 2V bandgap reference serves two functions. First, it is assessable at the VCM pin to provide a DC bias point for setting the common mode voltage of any external input circuitry. Second, it is used to derive internal reference levels that may be used to set the input range of the ADC. An external bypass capacitor is required for the 2V reference output at the VCM pin. This provides a high frequency low impedance path to ground for internal and external circuitry. This is also the compensation capacitor for the reference, which will not be stable without this capacitor. To achieve the optimal input range for an application, the internal reference voltage (VREF) is flexible. The reference switch shown in Figure 5 connects VREF to one of two internally derived reference voltages, or to an externally derived reference voltage. The internally derived 0.1µF REFHB INTERNAL ADC LOW REFERENCE 1750 F05 Figure 5. Equivalent Reference Circuit references are selected by strapping the SENSE pin to GND for 0.7V, or to VDD for 1.125V. When 0.7V > VSENSE > 1.125V, VSENSE is directly connected to VREF. Because of the dual nature of the SENSE pin, driving it with a logic device is not recommended. Reference voltages between 0.7V and 1.125V may be programmed with two external resistors as shown in Figure 6a. An external reference may be used by applying its output directly or through a resistor divider to the SENSE pin (Figure 6b). When the SENSE pin is driven with an externally derived reference voltage, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor. A difference amplifier generates the high and low references for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins: REFHA and REFHB for the high reference and REFLA and REFLB for the low reference. The doubled output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 5. 1750f 14 LTC1750 U W U U APPLICATIO S I FOR ATIO 2V PGA gain. Table 1 shows the input range of the ADC versus the state of the two pins, PGA and SENSE. VCM 4.7µF 10k 1V SENSE Driving the Encode Inputs LTC1750 The noise performance of the LTC1750 can depend on the encode signal quality as much as on the analog input. The ENC/ENC inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 2V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. 1µF 10k 1750 F06a Figure 6a. 2V Range ADC 2V VCM 4.7µF 4 5V LT1790-1.25 0.1µF 1, 2 6 2.5k 1µF SENSE 10k LTC1750 Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. 1µF In applications where jitter is critical (high input frequencies) take the following into consideration: 1750 F06b Figure 6b. 2V Range ADC with External Reference 1. Differential drive should be used. Input Range The LTC1750 performance may be optimized by adjusting the ADC’s input range to meet the requirements of the application. For lower input frequency applications (<80MHz), the highest input range of ±1.125V (2.25V) will provide the best SNR while maintaining excellent SFDR. For higher input frequencies (>80MHz), a lower input range will provide better SFDR performance with a reduction in SNR. The input range of the ADC is determined as ±VREF/APGA, where VREF is the reference voltage (described in the Reference Operation section) and APGA is the effective 2. Use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. 3. If the ADC is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.8V to VDD. Each input may be driven from ground to VDD for single-ended drive. Table 1 PGA VSENSE INPUT RANGE COMMENTS 0 = VDD 2.25VP-P Differential Best Noise, SNR = 75.5dB. Good SFDR, >82dB Up to 100MHz 1 = VDD 1.35VP-P Differential Improved High Frequency Distortion. SNR = 73dB. SFDR > 80dB Up to 250MHz 0 = GND 1.4VP-P Differential Reduced Internal Reference Mode with PGA = 0. Provides Similar Input Range as VSENSE = VDD and PGA = 0 But with Worse Noise. SNR = 71.4dB 1 = GND 0.84VP-P Differential Smallest Possible Input Span. Useful for Improved Distortion at Very High Frequencies, But with Reduced Noise Performance. SNR = 69dB 0 0.7V < VSENSE < 1.125V 2 × VSENSE Peak-to-Peak Differential Adjustable Input Range with Better Noise Performance. SNR = 75.5dB with VSENSE = 1.125V, SNR = 71.4dB with VSENSE = 0.7V 1 0.7V < VSENSE < 1.125V 1.2 × VSENSE Peak-to-Peak Differential Adjustable Input Range with Better High Frequency Distortion. SNR = 73dB with VSENSE = 1.125V, SNR = 69dB with VSENSE = 0.7V 1750f 15 LTC1750 U W U U APPLICATIO S I FOR ATIO LTC1750 5V BIAS VDD TO INTERNAL ADC CIRCUITS 2V BIAS 6k ANALOG INPUT ENC 0.1µF 1:4 CLOCK INPUT 50Ω VDD 2V BIAS 6k ENC 1750 F07 Figure 7. Transformer Driven ENC/ENC 3.3V ENC VTHRESHOLD = 2V MC100LVELT22 2V ENC 3.3V LTC1750 0.1µF 130Ω Q0 ENC D0 1750 F08a ENC Q0 Figure 8a. Single-Ended ENC Drive, Not Recommended for Low Jitter Maximum and Minimum Encode Rates The maximum encode rate for the LTC1750 is 80Msps. For the ADC to operate properly the encode signal should have a 50% (±4%) duty cycle. Each half cycle must have at least 6ns for the ADC internal circuitry to have sufficient settling time for proper operation. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. When using a single-ended encode signal asymmetric rise and fall times can result in duty cycles that are far from 50%. At sample rates slower than 80Msps the duty cycle can vary from 50% as long as each half cycle is at least 6ns. The lower limit of the LTC1750 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on 130Ω 83Ω LTC1750 83Ω 1750 F08b Figure 8b. ENC Drive Using a CMOS-to-PECL Translator small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC1750 is 1Msps. DIGITAL OUTPUTS Digital Output Buffers Figure 9 shows an equivalent circuit for a single output buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and may eliminate the need for external damping resistors. 1750f 16 LTC1750 U W U U APPLICATIO S I FOR ATIO LTC1750 VDD OVDD VDD 0.5V TO VDD 0.1µF OVDD DATA FROM LATCH PREDRIVER LOGIC 43Ω TYPICAL DATA OUTPUT OGND 1750 F09 Figure 9. Equivalent Circuit for a Digital Output Buffer Output Loading As with all high speed/high resolution converters the digital output loading can affect the performance. The digital outputs of the LTC1750 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. A resistor in series with the output may be used but is not required since the ADC has a series resistor of 43Ω on chip. Lower OVDD voltages will also help reduce interference from the digital outputs. Format The LTC1750 parallel digital output can be selected for offset binary or 2’s complement format. The format is selected with the MSBINV pin; high selects offset binary. Overflow Bit An overflow output bit indicates when the converter is overranged or underranged. When OF outputs a logic high the converter is either overranged or underranged. Output Clock The ADC has a delayed version of the ENC input available as a digital output, CLKOUT. The CLKOUT pin can be used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode signal. Data will be updated just after CLKOUT falls and can be latched on the rising edge of CLKOUT. Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example if the converter is driving a DSP powered by a 3V supply then OVDD should be tied to that same 3V supply. OVDD can be powered with any voltage up to 5V. The logic outputs will swing between OGND and OVDD. GROUNDING AND BYPASSING The LTC1750 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane is recommended. The pinout of the LTC1750 has been optimized for a flowthrough layout so that the interaction between inputs and digital outputs is minimized. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, VCM, REFHA, REFHB, REFLA and REFLB pins as shown in the block diagram on the front page of this data sheet. Bypass capacitors must be located as close to the pins as possible. Of particular importance are the capacitors between REFHA and REFLB and between REFHB and 1750f 17 LTC1750 U W U U APPLICATIO S I FOR ATIO REFLA. These capacitors should be as close to the device as possible (1.5mm or less). Size 0402 ceramic capacitors are recomended. The large 4.7µF capacitor between REFHA and REFLA can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. processing system supply. OVDD bypass capacitors should bypass to the digital system ground. The digital processing system ground should be connected to the analog plane at ADC OGND (Pin 38). The LTC1750 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. Most of the heat generated by the LTC1750 is transferred from the die through the package leads onto the printed circuit board. In particular, ground pins 12, 13, 36 and 37 are fused to the die attach pad. These pins have the lowest thermal resistance between the die and the outside environment. It is critical that all ground pins are connected to a ground plane of sufficient area. The layout of the evaluation circuit shown on the following pages has a low thermal resistance path to the internal ground plane by using multiple vias near the ground pins. A ground plane of this size results in a thermal resistance from the die to ambient of 35°C/W. Smaller area ground planes or poorly connected ground pins will result in higher thermal resistance. An analog ground plane separate from the digital processing system ground should be used. All ADC ground pins labeled GND should connect to this plane. All ADC VDD bypass capacitors, reference bypass capacitors and input filter capacitors should connect to this analog plane. The LTC1750 has three output driver ground pins, labeled OGND (Pins 27, 38 and 47). These grounds should connect to the digital processing system ground. The output driver supply, OVDD should be connected to the digital HEAT TRANSFER 1750f 18 LTC1750 U PACKAGE DESCRIPTIO FW Package 48-Lead Plastic TSSOP (6.1mm) (Reference LTC DWG # 05-08-1651) 12.4 – 12.6* (.488 – .496) 0.95 ±0.10 8.1 ±0.10 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 6.2 ±0.10 7.9 – 8.3 (.311 – .327) 0.32 ±0.05 0.50 TYP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 RECOMMENDED SOLDER PAD LAYOUT 1.20 (.0473) MAX 6.0 – 6.2** (.236 – .244) 0° – 8° -T.10 C -C0.09 – 0.20 (.0035 – .008) 0.45 – 0.75 (.018 – .029) 0.50 (.0197) BSC NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 0.17 – 0.27 (.0067 – .0106) 0.05 – 0.15 (.002 – .006) FW48 TSSOP 0502 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE 1750f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC1750 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1405 12-Bit, 5Msps Sampling ADC with Parallel Output Pin Compatible with the LTC1420 LTC1406 8-Bit, 20Msps ADC Undersampling Capability up to 70MHz LTC1411 14-Bit, 2.5Msps ADC 5V, No Pipeline Delay, 80dB SINAD LTC1412 12-Bit, 3Msps, Sampling ADC ±5V, No Pipeline Delay, 72dB SINAD LTC1414 14-Bit, 2.2Msps ADC ±5V, 81dB SINAD and 95dB SFDR LTC1420 12-Bit, 10Msps ADC 71dB SINAD and 83dB SFDR at Nyquist LT®1461 Micropower Precision Series Reference 0.04% Max Initial Accuracy, 3ppm/°C Drift LTC1666 12-Bit, 50Msps DAC Pin Compatible with the LTC1668, LTC1667 LTC1667 14-Bit, 50Msps DAC Pin Compatible with the LTC1668, LTC1666 LTC1668 16-Bit, 50Msps DAC 16-Bit Monotonic, 87dB SFDR, 5pV-s Glitch Impulse LTC1741 12-Bit, 65Msps ADC Pin Compatible with the LTC1743, LTC1745, LTC1747 LTC1742 14-Bit, 65Msps ADC Pin Compatible with the LTC1744, LTC1746, LTC1748 LTC1743 12-Bit, 50Msps ADC Pin Compatible with the LTC1741, LTC1745, LTC1747 LTC1744 14-Bit, 50Msps ADC Pin Compatible with the LTC1742, LTC1746, LTC1748 LTC1745 12-Bit, 25Msps ADC Pin Compatible with the LTC1741, LTC1743, LTC1747 LTC1746 14-Bit, 25Msps ADC Pin Compatible with the LTC1742, LTC1744, LTC1748 LTC1747 12-Bit, 80Msps ADC Pin Compatible with the LTC1741, LTC1743, LTC1745 LTC1748 14-Bit, 80Msps ADC Pin Compatible with the LTC1742, LTC1744, LTC1746 LTC1749 12-Bit, 80Msps ADC with Wide Bandwidth Pin Compatible with the LTC1750 LT1807 325MHz, Low Distortion Dual Op Amp Rail-to-Rail Input and Output LT5512 High Signal Level Down Converting Mixer DC to 3GHz, 17dBm IIP3, Integrated LO Buffer LT5515 Direct Conversion Demodulator 1.5GHz to 2.5GHz, 21.5dBm IIP3, Integrated LO Quadrature Generator LT5516 Direct Conversion Quadrature Demodulator 800MHz to 3GHz, 17dBm IIP3, Integrated LO Buffer LT5522 High Signal Level Down Converting Mixer 600MHz to 3GHz, 25dBm IIP3, Integrated LO Buffer 1750f 20 Linear Technology Corporation LT/TP 0204 1K • PRINTED IN THE USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2004