LINER LTC2205UK-14

LTC2205-14
14-Bit, 65Msps ADC
U
DESCRIPTIO
FEATURES
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Sample Rate: 65Msps
78.3dB SNR and 98dB SFDR (2.25VP-P Range)
SFDR >90dB at 140MHz (1.5VP-P Input Range)
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
700MHz Full Power Bandwidth S/H
Optional Internal Dither
Optional Data Output Randomizer
Single 3.3V Supply
Power Dissipation: 600mW
Optional Clock Duty Cycle Stabilizer
Out-of-Range Indicator
Pin Compatible Family
105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit)
80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit)
65Msps: LTC2205 (16-Bit)
40Msps: LTC2204 (16-Bit)
48-Pin (7mm × 7mm) QFN Package
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APPLICATIO S
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Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
ATE
The LTC®2205-14 is a sampling 14-bit A/D converter designed for digitizing high frequency, wide dynamic range
signals up to input frequencies of 700MHz. The input range
of the ADC can be optimized with the PGA front end.
The LTC2205-14 is perfect for demanding communications
applications, with AC performance that includes 78.3dB
SNR and 98dB spurious free dynamic range (SFDR).
Ultralow jitter of 90fsRMS allows undersampling of high
input frequencies with excellent noise performance.
Maximum DC specs include ±1.5LSB INL, ±1LSB DNL
(no missing codes).
A separate output power supply allows the CMOS output
swing to range from 0.5V to 3.6V.
The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of
clock duty cycles.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
U
TYPICAL APPLICATIO
LTC2205-14: 32K Point FFT,
fIN = 5.1MHz, –1dBFS,
PGA = 0, DITH = 0
3.3V
SENSE
OVDD
2.2µF
AIN+
1.25V
COMMON MODE
BIAS VOLTAGE
+
ANALOG
INPUT
AIN–
INTERNAL ADC
REFERENCE
GENERATOR
14-BIT
PIPELINED
ADC CORE
S/H
AMP
–
0.5V TO 3.6V
0.1µF
OF
CLKOUT
D13
•
•
•
D0
OUTPUT
DRIVERS
CORRECTION
LOGIC AND
SHIFT REGISTER
OGND
CLOCK/DUTY
CYCLE
CONTROL
3.3V
0.1µF
VDD
0.1µF
GND
0.1µF
220514 TA01
ENC
ENC
PGA
SHDN
DITH
MODE
OE
ADC CONTROL INPUTS
RAND
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
AMPLITUDE (dBFS)
VCM
0
5
10
20
25
15
FREQUENCY (MHz)
30
220514 G04
220514fa
1
LTC2205-14
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
OVDD = VDD (Notes 1 and 2)
Supply Voltage (VDD) ................................... –0.3V to 4V
Digital Output Ground Voltage (OGND)........ –0.3V to 1V
Analog Input Voltage (Note 3) ......–0.3V to (VDD + 0.3V)
Digital Input Voltage .....................–0.3V to (VDD + 0.3V)
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Power Dissipation............................................ 2000mW
Operating Temperature Range
LTC2205-14C ........................................... 0°C to 70°C
LTC2205-14I ........................................ –40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Digital Output Supply Voltage (OVDD) .......... –0.3V to 4V
48 GND
47 PGA
46 RAND
45 MODE
44 OE
43 OF
42 D13
41 D12
40 D11
39 D10
38 OGND
37 OVDD
TOP VIEW
SENSE 1
VCM 2
VDD 3
VDD 4
GND 5
AIN+ 6
AIN– 7
GND 8
ENC+ 9
ENC– 10
GND 11
VDD 12
36 OVDD
35 D9
34 D8
33 D7
32 D6
31 OGND
30 CLKOUT+
29 CLKOUT–
28 D5
27 D4
26 D3
25 OVDD
VDD 13
VDD 14
GND 15
SHDN 16
DITH 17
NC 18
NC 19
D0 20
D1 21
D2 22
OGND 23
OVDD 24
49
UK PACKAGE
48-LEAD (7mm × 7mm) PLASTIC QFN
TJMAX = 125°C, θJA = 29°C/W
EXPOSED PAD IS GND (PIN 49), MUST BE SOLDERED TO PCB BOARD
ORDER PART NUMBER
UK PART MARKING
LTC2205CUK-14
LTC2205IUK-14
LTC2205UK-14
LTC2205UK-14
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
CONVERTER CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Offset Drift
Gain Error
Full-Scale Drift
Transition Noise
CONDITIONS
MIN
●
Differential Analog Input (Note 5)
Differential Analog Input
(Note 6)
●
External Reference
Internal Reference
External Reference
●
●
●
TYP
MAX
14
±0.6
±0.2
±1
±10
±0.3
±30
±10
0.7
±1.5
±1
±8.5
±1.9
UNITS
Bits
LSB
LSB
mV
V/°C
%FS
ppm/°C
ppm/°C
LSBRMS
220514fa
2
LTC2205-14
ANALOG INPUT
The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
VIN
VIN, CM
IIN
ISENSE
IMODE
CIN
PARAMETER
Analog Input Range (AIN+ – AIN–)
Analog Input Common Mode
Analog Input Leakage Current
SENSE Input Leakage Current
MODE Pin Pull-Down Current to GND
Analog Input Capacitance
tAP
Sample-and-Hold
Aperature Delay Time
Sample-and-Hold
Aperature Delay Time Jitter
Analog Input
Common Mode Rejection Ratio
Full Power Bandwidth
tJITTER
CMRR
BW-3dB
CONDITIONS
3.135V ≤ VDD ≤ 3.465V
Differential Input (Note 7)
0V ≤ AIN+, AIN– ≤ VDD
0V ≤ SENSE ≤ VDD
MIN
●
●
1
–1
–3
●
●
Sample Mode ENC+ < ENC–
Hold Mode ENC+ > ENC–
1V < (AIN+ = AIN–) <1.5V
TYP
1.5 to 2.25
1.25
MAX
10
6.5
1.8
0.7
UNITS
VP-P
V
µA
µA
µA
pF
pF
ns
90
fsRMS
60
dB
700
MHz
1.5
1
3
DYNAMIC ACCURACY
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER
CONDITIONS
SNR
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
Signal-to-Noise Ratio
MAX
UNITS
dBFS
dBFS
78.2
78.2
76.0
dBFS
dBFS
dBFS
77.7
75.7
dBFS
dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
76.4
74.9
dBFS
dBFS
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
75.6
74.2
dBFS
dBFS
98
98
dBc
dBc
98
98
98
dBc
dBc
dBc
90
92
92
dBc
dBc
dBc
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
88
90
dBc
dBc
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
80
82
dBc
dBc
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
70MHz Input (1.5V Range, PGA = 1)
Spurious Free Dynamic Range
2nd or 3rd Harmonic
TYP
78.3
76.0
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
SFDR
MIN
●
76.8
77.2
●
74.2
74.7
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (2.25V Range, PGA = 0
15MHz Input (1.5V Range, PGA = 1)
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
70MHz Input (1.5V Range, PGA = 1)
●
85
86
●
82
83
220514fa
3
LTC2205-14
DYNAMIC ACCURACY
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS unless otherwise noted. (Note 4)
SYMBOL PARAMETER
CONDITIONS
SFDR
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
Spurious Free Dynamic Range
4th Harmonic or Higher
dBc
dBc
98
98
dBc
dBc
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
95
95
dBc
dBc
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
93
93
dBc
dBc
78.2
75.9
dBFS
dBFS
78.1
78.1
75.9
dBFS
dBFS
dBFS
77.4
75.5
75.5
dBFS
dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
75.9
74.7
dBFS
dBFS
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
73.6
73.2
dBFS
dBFS
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
103
103
dBFS
dBFS
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
103
103
dBFS
dBFS
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
103
103
dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
98
98
dBFS
dBFS
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
98
98
dBFS
dBFS
SFDR
Spurious Free Dynamic Range
at –25dBFS Dither “ON”
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
113
113
dBFS
dBFS
113
113
dBFS
dBFS
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
110
110
dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
110
110
dBFS
dBFS
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
103
103
dBFS
dBFS
●
87
●
86.5
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
70MHz Input (1.5V Range, PGA = 1)
Spurious Free Dynamic Range
at –25dBFS Dither “OFF”
UNITS
98
98
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
SFDR
MAX
dBc
dBc
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
Signal-to-Noise Plus Distortion Ratio
TYP
103
103
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
S/(N+D)
MIN
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
●
76.7
77.1
●
73.5
74.0
●
95
220514fa
4
LTC2205-14
COMMON MODE BIAS CHARACTERISTICS
The ● denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
VCM Output Voltage
VCM Output Tempco
VCM Line Regulation
CONDITIONS
IOUT = 0
IOUT = 0
3.135V ≤ VDD ≤ 3.465V
VCM Output Resistance
1mA ≤ | IOUT | ≤ 1mA
MIN
1.15
TYP
1.25
±40
1
MAX
1.35
UNITS
V
ppm/°C
mV/ V
1
DIGITAL INPUTS AND DIGITAL OUTPUTS
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
ENCODE INPUTS (ENC+, ENC–)
VID
Differential Input Voltage (Note 7)
VICM
Common Mode Input Voltage
RIN
Input Resistance
CIN
Input Capacitance
LOGIC INPUTS (DITH, PGA, SHDN, RAND)
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIN
Digital Input Current
CIN
Digital Input Capacitance
LOGIC OUTPUTS
OVDD = 3.3V
VOH
High Level Output Voltage
CONDITIONS
MIN
●
Internally Set
Externally Set (Note 7)
MAX
UNITS
0.2
V
1.6
1.2
(See Figure 2)
(Note 7)
V
V
3.0
6
3
●
VDD = 3.3V
VDD = 3.3V
VIN = 0V to VDD
(Note 7)
VDD = 3.3V
TYP
2
0.8
±10
1.5
V
V
µA
pF
3.299
3.29
0.01
0.10
–50
50
0.4
V
V
V
V
mA
mA
●
●
IO = –10µA
IO = –200µA
●
IO = 160µA
IO = 1.6mA
●
k
pF
3.1
VOL
Low Level Output Voltage
VDD = 3.3V
ISOURCE
ISINK
OVDD = 2.5V
VOH
VOL
OVDD = 1.8V
VOH
VOL
Output Source Current
Output Sink Current
VOUT = 0V
VOUT = 3.3V
High Level Output Voltage
Low Level Output Voltage
VDD = 3.3V
VDD = 3.3V
IO = –200µA
IO = 1.60mA
2.49
0.1
V
V
High Level Output Voltage
Low Level Output Voltage
VDD = 3.3V
VDD = 3.3V
IO = –200µA
IO = 1.60mA
1.79
0.1
V
V
POWER REQUIREMENTS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VDD
Analog Supply Voltage
PSHDN
Shutdown Power
OVDD
Output Supply Voltage
●
IVDD
Analog Supply Current
PDIS
Power Dissipation
MIN
TYP
MAX
3.315
3.3
3.465
SHDN = VDD
0.2
0.5
UNITS
V
mW
3.3
3.6
V
●
181
212
mA
●
597
700
mW
220514fa
5
LTC2205-14
TIMING CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
fS
Sampling Frequency
●
1
65
MHz
tL
ENC Low Time
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
●
●
6.40
4.60
7.69
7.69
500
500
ns
ns
tH
ENC High Time
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
●
●
6.40
4.60
7.69
7.69
500
500
ns
ns
tAP
Sample-and-Hold
Aperture Delay
tD
ENC to DATA Delay
0.7
UNITS
ns
(Note 7)
●
1.3
2.7
4.0
ns
1.3
2.7
4.0
ns
–0.6
0
0.6
ns
5
5
15
15
ns
ns
tC
ENC to CLKOUT Delay
(Note 7)
●
tSKEW
DATA to CLKOUT Skew
(tD – tC) (Note 7)
●
tOE
DATA Access Time
Bus Relinquish Time
CL = 5pf (Note 7)
(Note 7)
●
●
Pipeline
Latency
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND, with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3.3V, fSAMPLE = 65MHz differential ENC+/ENC– = 2VP-P sine
wave with 1.6V common mode, input range = 2.25VP-P with differential
drive (PGA = 0), unless otherwise specified.
7
Cycles
Note 5: Integral nonlinearity is defined as the deviation of a code from
a “best fit straight line” to the transfer curve. The deviation is measured
from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –1/2LSB when the
output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111
in 2’s complement output mode.
Note 7: Guaranteed by design, not subject to test.
220514fa
6
LTC2205-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2205-14: INL (Integral
Nonlinearity) vs Code
LTC2205-14: DNL (Differential
Nonlinearity) vs Code
1.5
LTC2205-14: Grounded Input
Histogram
250,000
1.00
0.75
1.0
200,000
0.50
0
0.25
COUNT
DNL (LSB)
INL (LSB)
0.5
0
100,000
–0.25
–0.5
150,000
–0.50
50,000
–1.0
–0.75
–1.5
0
4096
8192
CODE
12288
16384
–1.00
0
0
4096
8192
CODE
220514 G01
10
20
25
15
FREQUENCY (MHz)
30
5
10
20
25
15
FREQUENCY (MHz)
220514 G04
30
30
220514 G07
10
20
25
15
FREQUENCY (MHz)
30
220514 G06
LTC2205-14: 32K Point FFT,
–40dBFS, fIN = 5.1MHz,
PGA = 0, DITH = 1
AMPLITUDE (dBFS)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
10
20
25
15
FREQUENCY (MHz)
5
220514 G05
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
5
0
LTC2205-14: 32K Point FFT,
–40dBFS, fIN = 5.1MHz,
PGA = 0, DITH = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
220514 G03
AMPLITUDE (dBFS)
0
LTC2205-14: 32K Point FFT,
–25dBFS, fIN = 5.1MHz,
PGA = 0, DITH = 1
8180
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
AMPLITUDE (dBFS)
5
8179
LTC2205-14: 32K Point FFT,
–25dBFS, fIN = 5.1MHz,
PGA = 0, DITH = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
AMPLITUDE (dBFS)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
8177 8178
CODE
220514 G02
LTC2205-14: 32K Point FFT,
–1dBFS, fIN = 5.1MHz,
PGA = 1, DITH = 0
LTC2205-14: 32K Point FFT,
–1dBFS, fIN = 5.1MHz,
PGA = 0, DITH = 0
0
8176
8175
16384
12288
0
5
10
20
25
15
FREQUENCY (MHz)
30
220514 G08
0
5
10
20
25
15
FREQUENCY (MHz)
30
220514 G09
220514fa
7
LTC2205-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2205-14: 32K Point FFT,
–1dBFS, fIN = 15.1MHz,
PGA = 0, DITH = 0
LTC2205-14: 32K Point FFT,
–25dBFS, fIN = 15.1MHz,
PGA = 0, DITH = 0
LTC2205-14: 32K Point FFT,
–1dBFS, fIN = 15.1MHz,
PGA = 1, DITH = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
5
10
20
25
15
FREQUENCY (MHz)
30
AMPLITUDE (dBFS)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
5
10
20
25
15
FREQUENCY (MHz)
220514 G10
30
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
10
20
25
15
FREQUENCY (MHz)
0
30
5
10
20
25
15
FREQUENCY (MHz)
30
30
220514 G16
30
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
10
20
25
15
FREQUENCY (MHz)
10
20
25
15
FREQUENCY (MHz)
LTC2205-14: 32K Point FFT,
–25dBFS, fIN = 70.1MHz,
PGA = 0, DITH = 1
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
5
5
220514 G15
LTC2205-14: 32K Point FFT,
–25dBFS, fIN = 70.1MHz,
PGA = 1, DITH = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
0
220514 G14
220514 G13
LTC2205-14: 32K Point FFT,
–1dBFS, fIN = 70.1MHz,
PGA = 0, DITH = 0
30
LTC2205-14: 32K Point FFT,
–40dBFS, fIN = 15.1MHz,
PGA = 0, DITH = 1
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
5
10
20
25
15
FREQUENCY (MHz)
220514 G12
LTC2205-14: 32K Point FFT,
–40dBFS, fIN = 15.1MHz,
PGA = 0, DITH = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
5
220514 G11
LTC2205-14: 32K Point FFT,
–25dBFS, fIN = 15.1MHz,
PGA = 0, DITH = 1
0
0
0
5
10
20
25
15
FREQUENCY (MHz)
30
220514 G17
0
5
10
20
25
15
FREQUENCY (MHz)
30
220514 G19
220514fa
8
LTC2205-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2205-14: 32K Point FFT,
–40dBFS, fIN = 70.1MHz,
PGA = 0, DITH = 0
LTC2205-14: 32K Point FFT,
–1dBFS, fIN = 140.1MHz,
PGA = 0, DITH = 0
LTC2205-14: 32K Point FFT,
–40dBFS, fIN = 70.1MHz,
PGA = 0, DITH = 1
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
5
15
10
20
25
FREQUENCY (MHz)
30
0
5
10
20
25
15
FREQUENCY (MHz)
220514 G20
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
30
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
10
20
25
15
FREQUENCY (MHz)
0
5
10
20
25
15
FREQUENCY (MHz)
220514 G23
30
30
220514 G26
30
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
10
20
25
15
FREQUENCY (MHz)
10
20
25
15
FREQUENCY (MHz)
LTC2205-14: 32K Point FFT, fIN1 =
14.9MHz, –7dBFS, fIN2 = 20.1MHz,
–7dBFS, PGA = 0, DITH = 1
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
5
5
220514 G25
LTC2205-14: 32K Point FFT,
–40dBFS, fIN = 140.1MHz,
PGA = 0, DITH = 1
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
0
220514 G24
LTC2205-14: 32K Point FFT,
–40dBFS, fIN = 140.1MHz,
PGA = 0, DITH = 0
30
LTC2205-14: 32K Point FFT,
–25dBFS, fIN = 140.1MHz,
PGA = 0, DITH = 1
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
5
10
20
25
15
FREQUENCY (MHz)
220514 G22
LTC2205-14: 32K Point FFT,
–25dBFS, fIN = 140.1MHz,
PGA = 0, DITH = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
5
220514 G21
LTC2205-14: 32K Point FFT,
–1dBFS, fIN = 140.1MHz,
PGA = 1, DITH = 0
0
0
30
0
5
10
20
25
15
FREQUENCY (MHz)
30
220514 G27
0
5
10
20
25
15
FREQUENCY (MHz)
30
220514 G28
220514fa
9
LTC2205-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2205-14: 32K Point FFT, fIN1 =
64.1MHz, –7dBFS, fIN2 = 70.1MHz,
–7dBFS, PGA = 0, DITH = 0
0
5
15
10
20
25
FREQUENCY (MHz)
120
120
110
110
100
100
90
80
70
60
50
60
50
30
30
20
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
LTC2205-14: SFDR vs Input Level,
fIN = 14.9MHz, RAND = 1, DITH = 1
LTC2205-14: SFDR vs Input Level,
fIN = 70.1MHz, RAND = 1, DITH = 0
120
110
110
100
100
100
80
70
60
50
SFDR (dBFS AND dBc)
120
110
SFDR (dBFS AND dBc)
120
90
90
80
70
60
50
90
80
70
60
50
40
40
40
30
30
30
20
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
20
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
220514 G32
LTC2205-14: SFDR vs Input Level,
fIN = 70.9MHz, RAND = 1, DITH = 1
20
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
220514 G34
LTC2205-14: SFDR vs Input Level,
fIN = 140.1MHz, RAND = 1,
DITH = 0
LTC2205-14: SFDR vs Input Level,
fIN = 140.1MHz, RAND = 1,
DITH = 1
120
110
100
100
100
70
60
50
SFDR (dBFS AND dBc)
120
110
SFDR (dBFS AND dBc)
120
80
90
80
70
60
50
90
80
70
60
50
40
40
40
30
30
30
20
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
220514 G35
0
220514 G33
110
90
0
220514 G31
220514 G30
LTC2205-14: SFDR vs Input Level,
fIN = 14.9MHz, RAND = 1, DITH = 0
SFDR (dBFS AND dBc)
70
40
20
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
30
90
80
40
220514 G29
SFDR (dBFS AND dBc)
SFDR (dBFS AND dBc)
AMPLITUDE (dBFS)
SFDR (dBFS AND dBc)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
LTC2205-14: SFDR vs Input Level,
fIN = 5.1MHz, RAND = 1, DITH = 1
LTC2205-14: SFDR vs Input Level,
fIN = 5.1MHz, RAND = 1, DITH = 0
20
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
220514 G36
20
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
220514 G37
220514fa
10
LTC2205-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2205-14: SFDR vs Input
Frequency, RAND = 1, DITH = 1
LTC2205-14: SFDR and SNR vs
Sample Rate, fIN = 5.1MHz,
RAND = 0, DITH = 0
LTC2205-14: SNR vs Input
Frequency, RAND = 1, DITH = 0
110
110
79
SFDR (dBc) AND SNR (dBFS)
78
77
PGA = 1
SNR (dBFS)
SFDR (dBc)
100
90
PGA = 0
PGA = 0
76
75
PGA = 1
80
SFDR
100
90
80
74
70
SNR
70
73
0
50
150
200
100
INPUT FREQUENCY (MHz)
250
0
50
220414 G38
LTC2205-14: Gain Drift
with Internal Reference vs
Temperature
220
110
210
SFDR
0.05
0
VDD = 3.47V
200
100
–0.05
GAIN DRIFT (% FS)
VDD = 3.3V
IVDD (mA)
190
180
VDD = 3.13V
170
160
80
SNR
2.4
2.6
2.8
3.0
3.2
SUPPLY VOLTAGE (V)
3.4
3.6
220514 G41
–0.10
–0.15
–0.20
150
–0.25
140
–0.30
130
70
10 20 30 40 50 60 70 80 90 100
SAMPLE RATE (Msps)
220514 G40
LTC2205-14: IVDD vs Sample
Rate, fIN = 5.1MHz, RAND = 0,
DITH = 0
90
0
220514 G39
LTC2205-14: SFDR and SNR vs
Supply Voltage, fIN = 5.1MHz,
RAND = 0, DITH = 0
SFDR (dBc) AND SNR (dBFS)
250
100
150
200
INPUT FREQUENCY (MHz)
0 10 20 30 40 50 60 70 80 90 100 100
SAMPLE RATE (Msps)
220214 G42
–0.35
20 40 60
–60 –40 –20 0
TEMPERATURE (°C)
80
100
220514 G43
220514fa
11
LTC2205-14
PIN FUNCTIONS
SENSE (Pin 1): Reference Mode Select and External
Reference Input. Tie SENSE to VDD to select the internal
2.5V bandgap reference. An external reference of 2.5V or
1.25V may be used; both reference values will set a full
scale ADC range of 2.25V (PGA = 0).
VCM (Pin 2): 1.25V Output. Optimum voltage for input common mode. Must be bypassed to ground with a minimum
of 2.2µF. Ceramic chip capacitors are recommended.
VDD (Pins 3, 4, 12, 13, 14): 3.3V Analog Supply Pin.
Bypass to GND with 0.1µF ceramic chip capacitors.
GND (Pins 5, 8, 11, 15, 48): ADC Power Ground.
AIN+ (Pin 6): Positive Differential Analog Input.
AIN– (Pin 7): Negative Differential Analog Input.
ENC+ (Pin 9): Positive Differential Encode Input. The
sampled analog input is held on the rising edge of ENC+.
Internally biased to 1.6V through a 6.2k resistor. Output
data can be latched on the rising edge of ENC+.
ENC– (Pin 10): Negative Differential Encode Input. The
sampled analog input is held on the falling edge of ENC–.
Internally biased to 1.6V through a 6.2k resistor. Bypass to ground with a 0.1µF capacitor for a single-ended
Encode signal.
SHDN (Pin 16): Power Shutdown Pin. SHDN = low results
in normal operation. SHDN = high results in powered down
analog circuitry and the digital outputs placed in a high
impedance state.
DITH (Pin 17): Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal
dither. Refer to Internal Dither section of this data sheet
for details on dither operation.
NC (Pins 18, 19): No Connect.
D0-D13 (Pins 20-22, 26-28, 32-35 and 39-42): Digital
Outputs. D13 is the MSB.
OGND (Pins 23, 31 and 38): Output Driver Ground.
OVDD (Pins 24, 25, 36, 37): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip
capacitors.
CLKOUT– (Pin 29): Data Valid Output. CLKOUT– will toggle
at the sample rate. Latch the data on the falling edge of
CLKOUT–.
CLKOUT+ (Pin 30): Inverted Data Valid Output. CLKOUT+
will toggle at the sample rate. Latch the data on the rising
edge of CLKOUT+.
OF (Pin 43): Over/Under Flow Digital Output. OF is high
when an over or under flow has occurred.
⎯
O⎯E (Pin 44): Output Enable Pin. Low enables the digital
output drivers. High puts digital outputs in Hi-Z state.
MODE (Pin 45): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty
cycle stabilizer. Connecting MODE to 1/3VDD selects offset
binary output format and enables the clock duty cycle stabilizer. Connecting MODE to 2/3VDD selects 2’s complement
output format and enables the clock duty cycle stabilizer.
Connecting MODE to VDD selects 2’s complement output
format and disables the clock duty cycle stabilizer.
RAND (Pin 46): Digital Output Randomization Selection
Pin. RAND low results in normal operation. RAND high
selects D1-D13 to be EXCLUSIVE-ORed with D0 (the
LSB). The output can be decoded by again applying an
XOR operation between the LSB and all other bits. This
mode of operation reduces the effects of digital output
interferance.
PGA (Pin 47): Programmable Gain Amplifier Control
Pin. Low selects a front-end gain of 1, input range of
2.25VP-P. High selects a front-end gain of 1.5, input
range of 1.5VP-P.
GND (Exposed Pad, Pin 49): ADC Power Ground. The
exposed pad on the bottom of the package must be soldered to ground.
220514fa
12
LTC2205-14
BLOCK DIAGRAM
AIN+
AIN–
VDD
INPUT
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
GND
DITHER
SIGNAL
GENERATOR
CORRECTION LOGIC
AND
SHIFT REGISTER
ADC CLOCKS
RANGE
SELECT
OVDD
SENSE
ADC
REFERENCE
PGA
VCM
BUFFER
CLKOUT+
CLKOUT–
OF
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
CONTROL
LOGIC
OUTPUT
DRIVERS
•
•
•
VOLTAGE
REFERENCE
OGND
ENC+
ENC–
SHDN PGA RAND M0DE
OE
D13
D12
D1
D0
220514 F01
DITH
Figure 1. Functional Block Diagram
TIMING DIAGRAM
tAP
ANALOG
INPUT
N+1
N+4
N
N+3
N+2
tH
tL
–
ENC
ENC+
tD
N–7
D0-D13, OF
CLKOUT+
CLKOUT –
N–6
N–5
N–4
N–3
tC
220514 TD01
220514fa
13
LTC2205-14
OPERATION
DYNAMIC PERFORMANCE
by the presence of another sinusoidal input at a different
frequency.
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N+D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise (SNR) is the ratio between the RMS
amplitude of the fundamental input frequency and the RMS
amplitude of all other frequency components, except the
first five harmonics.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
THD = –20Log
(V
2
2
2
2
+ V3 + V4 + ...VN
2
)
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function
can create distortion products at the sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 3rd order IMD terms include (2fa + fb),
(fa + 2fb), (2fa – fb) and (fa – 2fb). The 3rd order IMD is
defined as the ratio of the RMS value of either input tone
to the RMS value of the largest 3rd order IMD product.
Spurious Free Dynamic Range (SFDR)
The ratio of the RMS input signal amplitude to the RMS
value of the peak spurious spectral component expressed
in dBc. SFDR may also be calculated relative to full scale
and expressed in dBFS.
Full Power Bandwidth
The Full Power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced
by 3dB for a full scale input signal.
Aperture Delay Time
/ V12
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second
through nth harmonics.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
The time from when a rising ENC+ equals the ENC– voltage
to the instant that the input signal is held by the sampleand-hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from convertion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π • fIN • tJITTER)
220514fa
14
LTC2205-14
APPLICATIONS INFORMATION
CONVERTER OPERATION
The LTC2205-14 is a CMOS pipelined multi-step converter
with a front-end PGA. As shown in Figure 1, the converter
has five pipelined ADC stages; a sampled analog input
will result in a digitized value seven cycles later (see the
Timing Diagram section). The analog input is differential for
improved common mode noise immunity and to maximize
the input range. Additionally, the differential input drive
will reduce even order harmonics of the sample and hold
circuit. The encode input is also differential for improved
common mode noise immunity.
The LTC2205-14 has two phases of operation, determined
by the state of the differential ENC+/ENC– input pins. For
brevity, the text will refer to ENC+ greater than ENC– as
ENC high and ENC+ less than ENC– as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and a residue amplifier. In operation, the ADC quantizes the input to the stage, and the
quantized value is subtracted from the input by the DAC
to produce a residue. The residue is amplified and output
by the residue amplifier. Successive stages operate out
of phase so that when odd stages are outputting their
residue, the even stages are acquiring that residue and
vice versa.
When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors,
inside the “input S/H” shown in the block diagram. At the
instant that ENC transitions from low to high, the voltage
on the sample capacitors is held. While ENC is high, the
held input voltage is buffered by the S/H amplifier which
drives the first pipelined ADC stage. The first stage acquires
the output of the S/H amplifier during the high phase of
ENC. When ENC goes back low, the first stage produces
its residue which is acquired by the second stage. At
the same time, the input S/H goes back to acquiring the
analog input. When ENC goes high, the second stage
produces its residue which is acquired by the third stage.
An identical process is repeated for the third and fourth
stages, resulting in a fourth stage residue that is sent to
the fifth stage for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2205-14
CMOS differential sample and hold. The differential analog inputs are sampled directly onto sampling capacitors
(CSAMPLE) through NMOS transitors. The capacitors shown
attached to each input (CPARASITIC) are the summation of
all other capacitance associated with each input.
During the sample phase when ENC is low, the NMOS
transistors connect the analog inputs to the sampling
capacitors which charge to, and track the differential input voltage. When ENC transitions from low to high, the
sampled input voltage is held on the sampling capacitors.
LTC2005-14
VDD
RON
20Ω
RPARASITIC
3Ω
CSAMPLE
4.9pF
AIN+
CPARASITIC
1.8pF
VDD
RPARASITIC
3Ω
RON
20Ω
CSAMPLE
4.9pF
AIN–
CPARASITIC
1.8pF
VDD
1.6V
6k
ENC+
ENC–
6k
1.6V
220514 F02
Figure 2. Equivalent Input Circuit
220514fa
15
LTC2205-14
APPLICATIONS INFORMATION
During the hold phase when ENC is high, the sampling
capacitors are disconnected from the input and the held
voltage is passed to the ADC core for processing. As ENC
transitions from high to low, the inputs are reconnected to
the sampling capacitors to acquire a new sample. Since
the sampling capacitors still hold the previous sample,
a charging glitch proportional to the change in voltage
between samples will be seen at this time. If the change
between the last sample and the new sample is small,
the charging glitch seen at the input will be small. If the
input change is large, such as the change seen with input
frequencies near Nyquist, then a larger charging glitch
will be seen.
Common Mode Bias
The ADC sample-and-hold circuit requires differential
drive to achieve specified performance. Each input should
swing ±0.5625V for the 2.25V range (PGA = 0) or ±0.375V
for the 1.5V range (PGA = 1), around a common mode
voltage of 1.25V. The VCM output pin (Pin 2) is designed
to provide the common mode bias level. VCM can be tied
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The VCM pin must be bypassed to ground
close to the ADC with 2.2µF or greater.
Input Drive Impedence
As with all high performance, high speed ADCs the dynamic performance of the LTC2205-14 can be influenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and input reactance
can influence SFDR. At the falling edge of ENC the
sample-and-hold circuit will connect the 4.9pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when ENC rises, holding the
sampled input on the sampling capacitor. Ideally, the
input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2FENCODE); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance it is recomended to have a source
impedence of 100 or less for each input. The source
impedence should be matched for the differential inputs.
Poor matching will result in higher even order harmonics,
especially the second.
INPUT DRIVE CIRCUITS
Input Filtering
A first order RC lowpass filter at the input of the ADC can
serve two functions: limit the noise from input circuitry and
provide isolation from ADC S/H switching. The LTC2205-14
has a very broadband S/H circuit, DC to 700MHz; it can
be used in a wide range of applications; therefore, it is not
possible to provide a single recommended RC filter.
Figures 3, 4a and 4b show three examples of input RC
filtering at three ranges of input frequencies. In general
it is desirable to make the capacitors as large as can be
tolerated—this will help suppress random noise as well as
noise coupled from the digital circuitry. The LTC2205-14
does not require any input filter to achieve data sheet
specifications; however, no filtering will put more stringent
noise requirements on the input drive circuitry.
Transformer Coupled Circuits
Figure 3 shows the LTC2205-14 being driven by an RF
transformer with a center-tapped secondary. The secondary
center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used; however,
as the turns ratio increases so does the impedance seen by
the ADC. Source impedance greater than 50 can reduce
the input bandwidth and increase high frequency distortion. A disadvantage of using a transformer is the loss of
low frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
220514fa
16
LTC2205-14
APPLICATIONS INFORMATION
Center-tapped transformers provide a convenient means
of DC biasing the secondary; however, they often show
poor balance at high input frequencies, resulting in large
2nd order harmonics.
Figure 4a shows transformer coupling using a transmission line balun transformer. This type of transformer has
much better high frequency response and balance than
flux coupled center tap transformers. Coupling capacitors
are added at the ground and input primary terminals to
allow the secondary terminals to be biased at 1.25V. Figure
4b shows the same circuit with components suitable for
higher input frequencies.
Direct Coupled Circuits
Figure 5 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides
low frequency input response; however, the limited gain
bandwidth of any op amp or closed-loop amplifier will degrade the ADC SFDR at high input frequencies. Additionally,
wideband op amps or differential amplifiers tend to have
high noise. As a result, the SNR will be degraded unless
the noise bandwidth is limited prior to the ADC input.
VCM
2.2µF
5Ω
5Ω AIN+
10Ω
T1
LTC2205-14
8.2pF
35Ω
8.2pF
0.1µF
35Ω
5Ω AIN–
10Ω
8.2pF
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2µF
220514 F03
Figure 3. Single-Ended to Differential Conversion Using a Transformer.
Recommended for Input Frequencies from 5MHz to 150MHz
VCM
VCM
2.2µF
0.1mF
10Ω
ANALOG
INPUT
5Ω
2.2µF
0.1µF
AIN+
LTC2205-14
25Ω
0.1mF
0.1µF
T1
1:1
25Ω
10Ω
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2mF
5Ω
ANALOG
INPUT
LTC2205-14
25Ω
4.7pF
4.7pF
5Ω
4.7pF
0.1µF
AIN–
220514 F04a
Figure 4a. Using a Transmission Line Balun Transformer.
Recommended for Input Frequencies from 150MHz to 250MHz
AIN+
T1
1:1
0.1µF
25Ω
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2µF
2.2pF
5Ω
2.2pF
AIN–
22054 F04b
Figure 4b. Using a Transmission Line Balun Transformer.
Recommended for Input Frequencies from 250MHz to 500MHz
220514fa
17
LTC2205-14
APPLICATIONS INFORMATION
VCM
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
ANALOG
INPUT
+
LTC2205-14
AIN+
25Ω
LTC2205-14
12pF
+
CM
–
RANGE
SELECT
AND GAIN
CONTROL
2.2µF
–
AIN–
25Ω
AMPLIFIER = LTC6600-20,
LTC1993, ETC.
12pF
TIE TO VDD TO USE
INTERNAL 2.5V
REFERENCE
OR INPUT FOR
EXTERNAL 2.5V
REFERENCE
OR INPUT FOR
EXTERNAL 1.25V
REFERENCE
INTERNAL
ADC
REFERENCE
SENSE
PGA
2.5V
BANDGAP
REFERENCE
220514 F05
VCM
Figure 5. DC Coupled Input with Differential Amplifier
BUFFER
1.25V
2.2µF
Reference Operation
220514 F06
Figure 6 shows the LTC2205-14 reference circuitry consisting of a 2.5V bandgap reference, a programmable gain
amplifier and control circuit. The LTC2205-14 has three
modes of reference operation: Internal Reference, 1.25V
external reference or 2.5V external reference. To use the
internal reference, tie the SENSE pin to VDD. To use an
external reference, simply apply either a 1.25V or 2.5V
reference voltage to the SENSE input pin. Both 1.25V
and 2.5V applied to SENSE will result in a full-scale range
of 2.25VP-P (PGA = 0). A 1.25V output, VCM is provided
for a common mode bias for input drive circuitry. An
external bypass capacitor is required for the VCM output.
This provides a high frequency low impedance path to
ground for internal and external circuitry. This is also the
compensation capacitor for the reference; it will not be
stable without this capacitor. The minimum value required
for stability is 2.2µF.
The internal programmable gain amplifier provides the
internal reference voltage for the ADC. This amplifier has
very stringent settling requirements and is not accessible
for external use.
Figure 6. Reference Circuit
VCM
1.25V
2.2µF
3.3V
1µF
2
LTC1461-2.5
4
6
SENSE
LTC2205-14
2.2µF
220514 F07
Figure 7. A 2.25V Range ADC with an External 2.5V Reference
The SENSE pin can be driven ±5% around the nominal 2.5V
or 1.25V external reference inputs. This adjustment range
can be used to trim the ADC gain error or other system
gain errors. When selecting the internal reference, the
SENSE pin should be tied to VDD as close to the converter
as possible. If the sense pin is driven externally it should
be bypassed to ground as close to the device as possible
with 1µF (or larger) ceramic capacitor.
220514fa
18
LTC2205-14
APPLICATIONS INFORMATION
PGA Pin
Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
The PGA pin selects between two gain settings for the ADC
front-end. PGA = 0 selects an input range of 2.25VP-P;
PGA = 1 selects an input range of 1.5VP-P. The 2.25V input
range has the best SNR; however, the distortion will be
higher for input frequencies above 100MHz. For applications with high input frequencies, the low input range will
have improved distortion; however, the SNR will be worse
by up to approximately 2dB. See the Typical Performance
Characteristics section.
In applications where jitter is critical (high input frequencies), take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude possible. If using transformer coupling, use a higher turns ratio to increase the
amplitude.
3. If the ADC is clocked with a fixed frequency sinusoidal
signal, filter the encode signal to reduce wideband
noise.
Driving the Encode Inputs
The noise performance of the LTC2205-14 can depend on
the encode signal quality as much as on the analog input.
The encode inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a
1.6V bias. The bias resistors set the DC operating point
for transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
4. Balance the capacitance and series resistance at both
encode inputs such that any coupled noise will appear
at both inputs as common mode noise.
The encode inputs have a common mode range of 1.2V
to 3V. Each input may be driven from ground to VDD for
single-ended drive.
LTC2205-14
VDD
TO INTERNAL
ADC CLOCK
DRIVERS
VDD 1.6V
ENC+
6k
0.1µF
ENCODE
INPUT
ETC1-1T
50Ω
100Ω
•
•
VDD 1.6V
50Ω
0.1µF
33pF
6k
ENC–
220514 F08
Figure 8. Transformer Driven Encode
220514fa
19
LTC2205-14
APPLICATIONS INFORMATION
ENC+
VTHRESHOLD = 1.6V
1.6V ENC– LTC2205-14
0.1µF
220514 F09
Figure 9. Single-Ended ENC Drive,
Not Recommended for Low Jitter
DIGITAL OUTPUTS
3.3V
MC100LVELT22
The lower limit of the LTC2205-14 sample rate is determined
by droop of the sample and hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating frequency
for the LTC2205-14 is 1Msps.
Digital Output Buffers
3.3V
130Ω
Q0
130Ω
ENC+
D0
ENC– LTC2205-14
Q0
83Ω
83Ω
Figure 11 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated
from the ADC power and ground. The additional N-channel
transistor in the output driver allows operation down to
low voltages. The internal resistor in series with the output
eliminates the need for external damping resistors.
220514 F10
Figure 10. ENC Drive Using a CMOS to PECL Translator
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC2205-14 is 65Msps.
For the ADC to operate properly the encode signal should
have a 50% (±2.5%) duty cycle. Achieving a precise 50%
duty cycle is easy with differential sinusoidal drive using
a transformer or using symmetric differential logic such
as PECL or LVDS. When using a single-ended ENCODE
signal asymmetric rise and fall times can result in duty
cycles that are far from 50%.
An optional clock duty cycle stabilizer can be used if the
input clock does not have a 50% duty cycle. This circuit
uses the rising edge of ENC pin to sample the analog input.
The falling edge of ENC is ignored and an internal falling
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 30% to 70% and the clock duty
cycle stabilizer will maintain a constant 50% internal duty
cycle. If the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin must be
connected to 1/3VDD or 2/3VDD using external resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2205-14 should drive a minimum
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as a ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF. A resistor in series with the
output may be used but is not required since the ADC has
a series resistor of 33 on chip.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
OVDD
LTC2205-14
VDD
0.5V
TO 3.6V
VDD
0.1µF
OVDD
DATA
FROM
LATCH
PREDRIVER
LOGIC
33Ω
TYPICAL
DATA
OUTPUT
OGND
220514 F11
Figure 11. Equivalent Circuit for a Digital Output Buffer
220514fa
20
LTC2205-14
APPLICATIONS INFORMATION
Data Format
LTC2205-14
The LTC2205-14 parallel digital output can be selected
for offset binary or 2’s complement format. The format
is selected with the MODE pin. This pin has a four level
logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An
external resistor divider can be user to set the 1/3VDD
and 2/3VDD logic levels. Table 1 shows the logic states
for the MODE pin.
CLKOUT
OF
OF
D13
D13/D0
D12
Table 1. MODE Pin Function
OUTPUT FORMAT
CLOCK DUTY CYCLE
STABILIZER
0(GND)
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
MODE
CLKOUT
Overflow Bit
An overflow output bit (OF) indicates when the converter
is over-ranged or under-ranged. A logic high on the OF
pin indicates an overflow or underflow.
D2
D12/D0
•
•
•
D2/D0
D1
RAND = HIGH,
SCRAMBLE
ENABLED
D1/D0
RAND
D0
D0
220514 F12
Output Clock
The ADC has a delayed version of the encode input available
as a digital output. Both a noninverted version, CLKOUT+
and an inverted version CLKOUT– are provided. The
CLKOUT+/CLKOUT– can be used to synchronize the converter data to the digital system. This is necessary when
using a sinusoidal encode. Data can be latched on the
rising edge of CLKOUT+ or the falling edge of CLKOUT–.
CLKOUT+ falls and CLKOUT– rises as the data outputs
are updated.
Figure 12. Functional Equivalent of Digital Output Randomizer
The digital output is “Randomized” by applying an exclusive-OR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied;
that is, an exclusive-OR operation is applied between the
LSB and all other bits. The LSB, OF and CLKOUT output
are not affected. The output Randomizer function is active
when the RAND pin is high.
Output Driver Power
Digital Output Randomizer
Interference from the ADC digital outputs is sometimes
unavoidable. Interference from the digital outputs may be
from capacitive or inductive coupling or coupling through
the ground plane. Even a tiny coupling factor can result in
discernible unwanted tones in the ADC output spectrum.
By randomizing the digital output before it is transmitted
off chip, these unwanted tones can be randomized, trading
a slight increase in the noise floor for a large reduction in
unwanted tone amplitude.
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven.
OVDD can be powered with any logic voltage up to the VDD
of the ADC. OGND can be powered with any voltage from
ground up to 1V and must be less than OVDD. The logic
outputs will swing between OGND and OVDD.
220514fa
21
LTC2205-14
APPLICATIONS INFORMATION
Internal Dither
PC BOARD
FPGA
The LTC2205-14 is a 14-bit ADC with a very linear transfer
function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones.
Small errors in the transfer function are usually a result
of ADC element mismatches. An optional internal dither
mode can be enabled to randomize the input location on
the ADC transfer curve, resulting in improved SFDR for
low signal levels.
CLKOUT
OF
D13/D0
D13
D12/D0
As shown in Figure 14, the output of the sample-and-hold
amplifier is summed with the output of a dither DAC. The
dither DAC is driven by a long sequence pseudo-random
number generator; the random number fed to the dither
DAC is also subtracted from the ADC result. If the dither
DAC is precisely calibrated to the ADC, very little of the
dither signal will be seen at the output. The dither signal
that does leak through will appear as white noise. The dither
DAC is calibrated to result in less than 0.5dB elevation
in the noise floor of the ADC, as compared to the noise
floor with dither off.
D12
•
•
•
LTC2205-14
D2/D0
D2
D1/D0
D1
D0
D0
22054 F13
Figure 13. Descrambling a Scrambled Digital Output
LTC2205-14
AIN+
ANALOG
INPUT
AIN–
14-BIT
PIPELINED
ADC CORE
S/H
AMP
CLOCK/DUTY
CYCLE
CONTROL
PRECISION
DAC
DIGITAL
SUMMATION
CLKOUT
OF
D13
•
•
•
D0
OUTPUT
DRIVERS
MULTIBIT DEEP
PSEUDO-RANDOM
NUMBER
GENERATOR
220514 F14
ENC +
ENC –
DITH
DITHER ENABLE
HIGH = DITHER ON
LOW = DITHER OFF
Figure 14. Functional Equivalent Block Diagram of Internal Dither Circuit
220514fa
22
LTC2205-14
APPLICATIONS INFORMATION
Grounding and Bypassing
The LTC2205-14 requires a printed circuit board with a
clean unbroken ground plane; a multilayer board with an
internal ground plane is recommended. The pinout of the
LTC2205-14 has been optimized for a flowthrough layout
so that the interaction between inputs and digital outputs
is minimized. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track
or underneath the ADC.
High quality ceramic bypass capacitors should be used
at the VDD, VCM, and OVDD pins. Bypass capacitors must
be located as close to the pins as possible. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC2205-14 differential inputs should run parallel
and close to each other. The input traces should be as
short as possible to minimize capacitance and to minimize
noise pickup.
Heat Transfer
Most of the heat generated by the LTC2205-14 is transferred from the die through the bottom-side exposed pad.
For good electrical and thermal performance, the exposed
pad must be soldered to a large grounded pad on the PC
board. It is critical that the exposed pad and all ground
pins are connected to a ground plane of sufficient area
with as many vias as possible.
220514fa
23
LTC2205-14
APPLICATIONS INFORMATION
Ordering Guide:
DEMO BOARD NUMBER
PART NUMBER
RESOLUTION
SPEED
INPUT FREQUENCY
USB I/F BOARD
DC918A-A
LTC2207CUK
16-Bit
105Msps
1MHz to 70MHz
DC718
DC918A-B
LTC2207CUK
16-Bit
105Msps
70MHz to 140MHz
DC718
DC918A-C
LTC2206CUK
16-Bit
80Msps
1MHz to 70MHz
DC718
DC918A-D
LTC2206CUK
16-Bit
80Msps
70MHz to 140MHz
DC718
DC918A-E
LTC2205CUK
16-Bit
65Msps
1MHz to 70MHz
DC718
DC918A-F
LTC2205CUK
16-Bit
65Msps
70MHz to 140MHz
DC718
DC918A-G
LTC2204CUK
16-Bit
40Msps
1MHz to 70MHz
DC718
DC918A-H
LTC2207CUK-14
14-Bit
105Msps
1MHz to 70MHz
DC718
DC918A-I
LTC2207CUK-14
14-Bit
105Msps
70MHz to 140MHz
DC718
DC918A-J
LTC2206CUK-14
14-Bit
80Msps
1MHz to 70MHz
DC718
DC918A-K
LTC2206CUK-14
14-Bit
80Msps
70MHz to 140MHz
DC718
DC918A-L
LTC2205CUK-14
14-Bit
65Msps
1MHz to 70MHz
DC718
See Web site for ordering details or contact local sales.
220514fa
24
LTC2205-14
APPLICATIONS INFORMATION
Silkscreen Top
Top Side
Inner Layer 2
Inner Layer 3
220514fa
25
LTC2205-14
APPLICATIONS INFORMATION
Inner Layer 4
Inner Layer 5
Bottom Side
Silkscreen Bottom
220514fa
26
LTC2205-14
PACKAGE DESCRIPTION
UK Package
48-Lead Plastic QFN (7mm × 7mm)
(Reference LTC DWG # 05-08-1704)
0.70 ±0.05
5.15 ± 0.05
5.50 REF
6.10 ±0.05 7.50 ±0.05
(4 SIDES)
5.15 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
7.00 ± 0.10
(4 SIDES)
0.75 ± 0.05
R = 0.10
TYP
R = 0.115
TYP
47 48
0.40 ± 0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1
CHAMFER
C = 0.35
5.15 ± 0.10
5.50 REF
(4-SIDES)
5.15 ± 0.10
(UK48) QFN 0406 REV C
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
220514fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC2205-14
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
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LT1993-2
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LTC2203
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LTC2204
16-Bit, 40Msps, 3.3V ADC
480mW, 79.1dB SNR, 100dB SFDR, 48-pin QFN
LTC2205
16-Bit, 65Msps, 3.3V ADC
610mW, 79dB SNR, 100dB SFDR, 48-pin QFN
LTC2206
16-Bit, 80Msps, 3.3V ADC
725mW, 77.9dB SNR, 100dB SFDR, 48-pin QFN
LTC2207
16-Bit, 105Msps, 3.3V ADC
900mW, 77.9dB SNR, 100dB SFDR, 48-pin QFN
LTC2208
16-Bit, 130Msps, 3,3V ADC, LVDS Outputs
1250mW, 77.9dB SNR, 100dB SFDR, 64-pin QFN
LTC2220-1
12-Bit, 185Msps, 3.3V ADC, LVDS Outputs
910mW, 67.7dB SNR, 80dB SFDR, 64-pin QFN
LTC2224
12-Bit, 135Msps, 3.3V ADC, High IF Sampling
630mW, 67.6dB SNR, 84dB SFDR, 48-pin QFN
LTC2255
14-Bit, 125Msps, 3V ADC, Lowest Power
395mW, 72.5dB SNR, 88dB SFDR, 32-pin QFN
LTC2284
14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk
540mW, 72.4dB SNR, 88dB SFDR, 64-pin QFN
LT5512
DC-3GHz High Signal Level Downconverting Mixer DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LT5514
Ultralow Distortion IF Amplifier/ADC Driver with
Digitally Controlled Gain
450MHz to 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step
LT5515
1.5GHz to 2.5GHz Direct Conversion Quadrature
Demodulator
High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator
LT5516
800MHz to 1.5GHz Direct Conversion Quadrature
Demodulator
High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator
LT5517
40MHz to 900MHz Direct Conversion Quadrature
Demodulator
High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
LT5522
600MHz to 2.7GHz High Linearity Downconverting
Mixer
4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz. NF = 12.5dB, 50W Single Ended RF
and LO Ports
220514fa
28 Linear Technology Corporation
LT 0506 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006