47 CY29947 2.5V or 3.3V, 200-MHz, 1:9 Clock Distribution Buffer Features • • • • • • • • • • Description 2.5V or 3.3V operation 200-MHz clock support LVCMOS-/LVTTL-compatible inputs 9 clock outputs: drive up to 18 clock lines Synchronous Output Enable Output three-state control 250 ps max. output-to-output skew Pin compatible with MPC947, MPC9447 Available in Industrial and Commercial temp. range 32-pin TQFP package The CY29947 is a low-voltage 200-MHz clock distribution buffer with the capability to select one of two LVCMOS/LVTTL compatible clock inputs. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible. The 9 outputs are LVCMOS or LVTTL compatible and can drive 50Ω series or parallel terminated transmission lines.For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:18. The outputs can also be three-stated via the three-state input TS#. Low output-to-output skews make the CY29947 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. The CY29947 also provides a synchronous output enable input for enabling or disabling the output clocks. Since this input is internally synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. Block Diagram Cypress Semiconductor Corporation Document #: 38-07287 Rev. *C • 3901 North First Street • VSS VDDC Q0 VSS Q1 VDDC Q2 VSS 31 30 29 28 27 26 25 San Jose 12 13 14 15 16 Q7 VDDC Q6 VSS TS# CY29947 VSS SYNC_OE 1 2 3 4 5 6 7 8 11 1 TCLK_SEL VSS TCLK_SEL TCLK0 TCLK1 SYNC_OE TS# VDD VSS Q8 Q0-Q8 9 9 10 TCLK1 0 VSS TCLK0 VDDC VDDC VDD 32 Pin Configuration • 24 23 22 21 20 19 18 17 VSS Q3 VDDC Q4 VSS Q5 VDDC VSS CA 95134 • 408-943-2600 Revised December 22, 2002 CY29947 Pin Description[1] Pin Name PWR 3 TCLK0 I, PU Test Clock Input 4 TCLK1 I, PU Test Clock Input 2 TCLK_SEL I, PU Test Clock Select Input. When LOW, TCLK0 is selected. When asserted HIGH, TCLK1 is selected. 11, 13, 15, 19, 21, 23, 26, 28, 30 Q(8:0) 5 SYNC_OE I, PU Output Enable Input. When asserted HIGH, the outputs are enabled and when set LOW the outputs are disabled in a LOW state. 6 TS# I, PU Three-state Control Input. When asserted LOW, the output buffers are three-stated. When set HIGH, the output buffers are enabled. 10, 14, 18, 22, 27, 31 VDDC 7 VDD 3.3V or 2.5V Power Supply 1, 8, 9, 12, 16, 17, 20, 24, 25, 29, 32 VSS Common Ground VDDC I/O O Description Clock Outputs 3.3V or 2.5V Power Supply for Output Clock Buffers Note: 1. PD = internal pull-down, PU = internal pull-up. Output Enable/Disable The CY29947 features a control input to enable or disable the outputs. This data is latched on the falling edge of the input clock. When SYNC_OE is asserted LOW, the outputs are disabled in a LOW state. When SYNC_OE is set HIGH, the outputs are enabled as shown in Figure 1. TCLK SYNC_OE Q Figure 1. SYNC_OE Timing Diagram Document #: 38-07287 Rev. *C Page 2 of 7 CY29947 Maximum Ratings [2] Operating Temperature: ................................ –40°C to +85°C This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: Maximum ESD protection ................................................ 2kV VSS < (Vin or Vout) < VDD Maximum Power Supply: ................................................5.5V Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Maximum Input Voltage Relative to VSS: ............. VSS – 0.3V Maximum Input Voltage Relative to VDD:............. VDD + 0.3V Storage Temperature: ................................ –65°C to + 150°C Maximum Input Current: ............................................±20 mA DC Parameters: VDD = VDDC = 3.3V ±10% or 2.5V ±5%, Over the specified temperature range Parameter Description Conditions Min. Typ. Max. Unit VIL Input Low Voltage VSS 0.8 V VIH Input High Voltage 2.0 VDD V –100 µA 10 µA 0.4 V Current[3] IIL Input Low IIH Input High Current[3] Output Low Voltage[4] IOL = 20 mA VOH Output High Voltage[4] IOH = –20 mA, VDD = 3.3V 2.5 IOH = –20 mA, VDD = 2.5V 1.8 IDDQ Quiescent Supply Current IDD Dynamic Supply Current VOL Zout Cin Output Impedance Input Capacitance V 5 VDD = 3.3V, Outputs @ 100 MHz, CL = 30 pF 120 VDD = 3.3V, Outputs @ 160 MHz, CL = 30 pF 200 VDD = 2.5V, Outputs @ 100 MHz, CL = 30 pF 85 VDD = 2.5V, Outputs @ 160 MHz, CL = 30 pF 140 7 mA mA VDD = 3.3V 12 15 18 VDD = 2.5V 14 18 22 Ω 4 pF Notes: 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Inputs have pull-up/pull-down resistors that effect input current. 4. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines. Document #: 38-07287 Rev. *C Page 3 of 7 CY29947 AC Parameters[5]: VDD = VDDC = 3.3V ±10% or 2.5V ±5%, Over the specified temperature range Parameter Fmax Tpd Description Input Frequency Conditions [6] TCLK To Q Delay[6] [6, 7] Min. Typ. Max. Unit VDD = 3.3V 200 MHz VDD = 2.5V 170 VDD = 3.3V 4.75 9.25 VDD = 2.5V 6.50 10.50 FoutDC Output Duty Cycle 45 55 % tpZL, tpZH Output Enable Time (all outputs) 2 10 ns tpLZ, tpHZ Output Disable Time (all outputs) 2 10 ns 250 ps 2.0 ns Tskew [6, 8] [9] Part-to-Part Skew Ts Set-up Time[6, 10] Tr/Tf 150 Output-to-Output Skew Tskew(pp) Th Measured at VDD/2 ns Hold Time [6, 10] Output Clocks Rise/Fall Time [8] SYNC_OE to TCLK 0.0 ps TCLK to SYNC_OE 1.0 ps 0.8V to 2.0V, VDD = 3.3V 0.20 1.0 0.6V to 1.8V, VDD = 2.5V 0.20 1.3 ns Notes: 5. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 6. Outputs driving 50Ω transmission lines. 7. 50% input duty cycle. 8. See Figure 2. 9. Part-to-Part skew at a given temperature and voltage. 10. Set-up and hold times are relative to the falling edge of the input clock Document #: 38-07287 Rev. *C Page 4 of 7 CY29947 CY29947 DUT Zo = 50 ohm Pulse Generator Z = 50 ohm Zo = 50 ohm RT = 50 ohm RT = 50 ohm VTT VTT Figure 2. LVCMOS_CLK CY29947 Test Reference for VCC = 3.3V and VCC = 2.5V VCC LVCMOS_CLK VCC /2 GND VCC Q VCC /2 tPD GND Figure 3. LVCMOS Propagation Delay (TPD) Test Reference VCC VCC /2 tP GND T0 DC = tP / T0 x 100% Figure 4. Output Duty Cycle (FoutDC) VCC VCC /2 GND VCC VCC /2 tSK(0) GND Figure 5. Output-to-Output Skew tsk(0). Document #: 38-07287 Rev. *C Page 5 of 7 CY29947 Ordering Information Part Number CY29947AI CY29947AIT CY29947AC CY29947ACT Package Type Production Flow 32 Pin TQFP Industrial, –40°C to +85°C 32 Pin TQFP - Tape and Reel Industrial, –40°C to +85°C 32 Pin TQFP Commercial, 0°C to +70°C 32 Pin TQFP - Tape and Reel Commercial, 0°C to +70°C Package Drawing and Dimensions 32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.0mm A32 51-85063-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07287 Rev. *C Page 6 of 7 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY29947 Revision History Document Title: CY29947 2.5V or 3.3V, 200-MHz, 1:9 Clock Distribution Buffer Document Number: 38-07287 REV. ECN NO. Issue Date Orig. of Change ** 111098 02/07/02 BRK New data sheet *A 116781 08/14/02 HWT Added Commercial Temperature Range in the ordering information *B 118462 09/09/02 HWT Corrected the Package Drawing and Dimension in page 6 from 32 LQFP to 32 TQFP *C 122879 12/22/02 RBI Document #: 38-07287 Rev. *C Description of Change Added power up requirements to Maximum Ratings Page 7 of 7