CY29946
2.5 V or 3.3 V, 200 MHz,
1:10 Clock Distribution Buffer
2.5 V or 3.3 V, 200 MHz, 1:10 Clock Distribution Buffer
Features
Functional Description
■
2.5 V or 3.3 V operation
The CY29946 is a low-voltage 200-MHz clock distribution buffer
with the capability to select one of two LVCMOS/LVTTL
compatible input clocks. These clock sources can be used to
provide for test clocks as well as the primary system clocks. All
other control inputs are LVCMOS/LVTTL compatible. The
10 outputs are LVCMOS or LVTTL compatible and can drive
50 series or parallel terminated transmission lines. For series
terminated transmission lines, each output can drive one or two
traces giving the device an effective fanout of 1:20.
■
200-MHz clock support
■
Two LVCMOS-/LVTTL-compatible inputs
■
Ten clock outputs: drive up to 20 clock lines
■
1× or 1/2× configurable outputs
■
Output three-state control
■
250-ps max output-to-output skew
■
Pin-compatible with MPC946, MPC9446
■
Available in commercial and industrial temperature range
■
32-pin TQFP package
The CY29946 is capable of generating 1× and 1/2× signals from
a 1× source. These signals are generated and retimed internally
to ensure minimal skew between the 1× and 1/2× signals.
SEL(A:C) inputs allow flexibility in selecting the ratio of 1× to1/2×
outputs.
The CY29946 outputs can also be three-stated via MR/OE#
input. When MR/OE# is set HIGH, it resets the internal flip-flops
and three-states the outputs.
For a complete list of related documentation, click here.
Block Diagram
TCLK_SEL
/1
TCLK0
TCLK1
R
0
/2
1
/1
0
3
QA0:2
DSELA
R /2
1
/1
0
3
QB0:2
4
QC0:3
DSELB
R
/2
1
DSELC
MR/OE#
Cypress Semiconductor Corporation
Document Number: 38-07286 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 13, 2016
CY29946
32
31
30
29
28
27
26
25
MR/OE#
VSS
QA0
VDDC
QA1
VSS
QA2
VDDC
Pin Configuration
1
2
3
4
5
6
7
8
CY29946
24
23
22
21
20
19
18
17
VSS
QB0
VDDC
QB1
VSS
QB2
VDDC
VDDC
VDDC
QC0
VSS
QC1
VDDC
QC2
VSS
QC3
9
10
11
12
13
14
15
16
TCLK_SEL
VDD
TCLK0
TCLK1
DSELA
DSELB
DSELC
VSS
Pin Description
Pin
Name
PWR
I/O [1]
I, PU
Description
3, 4
TCLK(0,1)
26, 28, 30
QA(2:0)
VDDC
O
Clock Outputs
External Reference/Test Clock Input
19, 21, 23
QB(2:0)
VDDC
O
Clock Outputs
10, 12, 14, 16
QC(0:3)
VDDC
O
Clock Outputs
5, 6, 7
DSEL(A:C)
I, PD
Divider Select Inputs. When HIGH, selects 2 input divider. When LOW,
selects 1 input divider.
1
TCLK_SEL
I, PD
TCLK Select Input. When LOW, TCLK0 clock is selected and when HIGH
TCLK1 is selected.
32
MR/OE#
I, PD
Output Enable Input. When asserted LOW, the outputs are enabled and
when asserted HIGH, internal flip-flops are reset and the outputs are
three-stated. If more than 1 Bank is being used in /2 Mode, a reset must be
performed (MR/OE# Asserted High) after power-up to ensure all internal
flip-flops are set to the same state.
9, 13, 17, 18, 22,
25, 29
VDDC
2.5 V or 3.3 V Power Supply for Output Clock Buffers
2
VDD
2.5 V or 3.3 V Power Supply
8, 11, 15, 20, 24,
27, 31
VSS
Common Ground
Note
1. PD = Internal pull-down. PU = Internal pull-up.
Document Number: 38-07286 Rev. *J
Page 2 of 9
CY29946
Absolute Maximum Conditions[2]
Maximum Input Voltage Relative to VSS ............. VSS – 0.3 V
Maximum Input Voltage Relative to VDD............. VDD + 0.3 V
Storage Temperature ................................ –65 C to +150 C
Operating Temperature............................... –40 C to +85 C
Maximum ESD protection............................................... 2 kV
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For proper
operation, Vin and Vout should be constrained to the range:
VSS < (Vin or Vout) < VDD .
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
Maximum Power Supply................................................ 5.5 V
Maximum Input Current ............................................. ±20 mA
DC Electrical Specifications
VDD = VDDC = 3.3 V ± 10% or 2.5 V ± 5%, over the specified temperature range
Parameter
Description
Conditions
Min
Typ
Max
Unit
VIL
Input Low Voltage
VSS
–
0.8
V
VIH
Input High Voltage
2.0
–
VDD
V
IIL
Input Low
Current[3]
–
–
–100
µA
IIH
Input High Current[3]
–
–
100
µA
Voltage[4]
VOL
Output Low
VOH
Output High Voltage[4]
IDDQ
Quiescent Supply Current
IDD
Dynamic Supply Current
ZOut
Cin
Output Impedance
IOL = 20 mA
–
–
0.4
V
IOH = –20 mA, VDD = 3.3 V
2.5
–
–
V
IOH = –20 mA, VDD = 2.5 V
1.8
–
–
–
5
7
mA
VDD = 3.3 V, Outputs @ 100 MHz, CL = 30 pF
–
130
–
mA
VDD = 3.3 V, Outputs @ 160 MHz, CL = 30 pF
–
225
–
VDD = 2.5 V, Outputs @ 100 MHz, CL = 30 pF
–
95
–
VDD = 2.5 V, Outputs @ 160 MHz, CL = 30 pF
–
160
–
VDD = 3.3 V
12
15
18
VDD = 2.5 V
14
18
22
–
4
–
Input Capacitance
W
pF
Thermal Resistance
Parameter [5]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
32-pin TQFP
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
65
°C/W
12
°C/W
Notes
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. Driving series or parallel terminated 50 (or 50 to VDD/2) transmission lines.
5. These parameters are guaranteed by design and are not tested.
Document Number: 38-07286 Rev. *J
Page 3 of 9
CY29946
AC Electrical Specifications
VDD = VDDC = 3.3 V ± 10% or 2.5 V ± 5%, over the specified temperature range[6]
Parameter
Description
Fmax
Input Frequency[7]
Tpd
TTL_CLK To Q Delay[7]
Conditions
VDD = 3.3 V
VDD = 2.5 V
[7, 8]
Min
Typ
Max
Unit
–
–
200
MHz
–
–
170
5.0
–
11.5
ns
FoutDC
Output Duty Cycle
45
–
55
%
tpZL, tpZH
Output enable time (all outputs)
2
–
10
ns
tpLZ, tpHZ
Output disable time (all outputs)
2
–
10
ns
Tskew
Output-to-Output Skew[7, 9]
–
150
250
ps
Measured at VDD/2
Skew[10]
Tskew(pp)
Part-to-Part
–
2.0
4.5
ns
Tr/Tf
Output Clocks Rise/Fall Time[9] 0.8 V to 2.0 V, VDD = 3.3 V
0.10
–
1.0
ns
0.6 V to 1.8 V, VDD = 2.5 V
0.10
–
1.3
Notes
6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
7. Outputs driving 50 transmission lines.
8. 50% input duty cycle.
9. See Figure 1 on page 5.
10. Part-to-Part skew at a given temperature and voltage.
Document Number: 38-07286 Rev. *J
Page 4 of 9
CY29946
Figure 1. LVCMOS_CLK CY29946 Test Reference for VCC = 3.3 V and VCC = 2.5 V
CY29946 DUT
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 2. LVCMOS Propagation Delay (TPD) Test Reference
VCC
LVCMOS_CLK
VCC /2
GND
VCC
Q
VCC /2
t PD
GND
Figure 3. Output Duty Cycle (FoutDC)
VCC
VCC /2
tP
G ND
T0
DC = tP / T0 x 100%
Figure 4. Output-to-Output Skew tsk(0)
VCC
VCC /2
GND
VCC
VCC /2
tSK(0)
Document Number: 38-07286 Rev. *J
GND
Page 5 of 9
CY29946
Ordering Information
Part Number
Package Type
Production Flow
CY29946AXC
32-pin TQFP
Commercial, 0 C to +70 C
CY29946AXCT
32-pin TQFP – Tape and Reel
Commercial, 0 C to +70 C
CY29946AXI
32-pin TQFP
Industrial, –40 C to +85 C
CY29946AXIT
32-pin TQFP – Tape and Reel
Industrial, –40 C to +85 C
Ordering Code Definitions
CY 29946 A
X
X
T
T = Tape and Reel; blank = Tube
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package: A = 32-pin TQFP
Base part number
Company ID: CY = Cypress
Package Drawing and Dimensions
Figure 5. 32-pin TQFP 7 × 7 × 1.0 mm A3210
51-85063 *E
Document Number: 38-07286 Rev. *J
Page 6 of 9
CY29946
Acronyms
Acronym
Document Conventions
Description
ESD
electrostatic discharge
I/O
input/output
LVCMOS
low voltage complementary metal oxide
semiconductor
Units of Measure
Symbol
Unit of Measure
°C
degree Celsius
kV
kilovolt
megahertz
LVTTL
low-voltage transistor-transistor logic
MHz
TQFP
thin quad flat pack
µA
microampere
mA
milliampere
mm
millimeter
mV
millivolt
ns
nanosecond
ohm
Document Number: 38-07286 Rev. *J
%
percent
pF
picofarad
ps
picosecond
V
volt
W
watt
Page 7 of 9
CY29946
Document History Page
Document Title: CY29946, 2.5 V or 3.3 V, 200 MHz, 1:10 Clock Distribution Buffer
Document Number: 38-07286
Rev.
ECN No.
Issue Date
Orig. of
Change
**
111097
02/07/02
BRK
*A
116780
08/15/02
HWT
*B
122878
12/22/02
RBI
Added power-up requirements to Maximum Ratings
*C
130007
10/15/03
RGL
Fixed the block diagram.
Fixed the MK/OE# description in the pin description table.
*D
131375
11/21/03
RGL
Updated document history page (revision *C) to reflect changes that were
not listed.
*E
221587
See ECN
RGL
Minor Change: Moved up the word Block Diagram in the first page.
*F
2899714
03/26/10
*G
3254185
05/11/2011
CXQ
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Updated to new template.
*H
4389717
05/30/2014
XHT
Updated Package Drawing and Dimensions:
spec 51-85063 – Changed revision from *C to *D.
Completing Sunset Review.
*I
4586288
12/03/2014
XHT
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*J
5270507
05/13/2016
PSR
Added Thermal Resistance.
Updated Package Drawing and Dimensions:
spec 51-85063 – Changed revision from *D to *E.
Updated to new template.
Document Number: 38-07286 Rev. *J
Description of Change
New data sheet
Added the commercial temperature range in the Ordering Information
BRIJ / CXQ Removed inactive parts from the ordering table.
Updated package diagram
Page 8 of 9
CY29946
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Document Number: 38-07286 Rev. *J
Revised May 13, 2016
Page 9 of 9