CY29948
2.5 V or 3.3 V, 200 MHz,
1:12 Clock Distribution Buffer
2.5 V or 3.3 V, 200 MHz, 1:12 Clock Distribution Buffer
Features
Functional Description
■
2.5 V or 3.3 V operation
■
200 MHz clock support
■
LVPECL or LVCMOS/LVTTL clock input
■
LVCMOS-/LVTTL-compatible inputs
■
12 clock outputs: drive up to 24 clock lines
■
Synchronous Output Enable
■
Output three-state control
■
150 ps typical output-to-output skew
■
Pin compatible with MPC948, MPC948L, MPC9448
■
Available in Commercial and Industrial temp. range
■
32-pin TQFP package
The CY29948 is a low-voltage 200 MHz clock distribution buffer
with the capability to select either a differential LVPECL or a
LVCMOS/LVTTL compatible input clock. The two clock sources
can be used to provide for a test clock as well as the primary
system clock. All other control inputs are LVCMOS/LVTTL
compatible. The 12 outputs are LVCMOS or LVTTL compatible
and can drive 50 series or parallel terminated transmission
lines. For series terminated transmission lines, each output can
drive one or two traces giving the device an effective fanout of
1:24. The outputs can also be three-stated via the three-state
input TS#. Low output-to-output skews make the CY29948 an
ideal clock distribution buffer for nested clock trees in the most
demanding of synchronous systems.
The CY29948 also provides a synchronous output enable input
for enabling or disabling the output clocks. Since this input is
internally synchronized to the input clock, potential output
glitching or runt pulse generation is eliminated.
For a complete list of related documentation, click here.
Block Diagram
VDD
PECL_CLK
PECL_CLK#
0
TCLK
1
VDDC
12
Q0-Q11
TCLK_SEL
SYNC_OE
TS#
Cypress Semiconductor Corporation
Document Number: 38-07288 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 18, 2016
CY29948
Contents
Pin Configuration ............................................................. 3
Pin Description ................................................................. 3
Output Enable/Disable ..................................................... 4
Maximum Ratings ............................................................. 5
DC Parameters .................................................................. 5
Thermal Resistance .......................................................... 6
AC Parameters .................................................................. 6
Ordering Information ........................................................ 9
Ordering Code Definitions ........................................... 9
Package Drawing and Dimensions ............................... 10
Document Number: 38-07288 Rev. *I
Acronyms ........................................................................ 11
Document Conventions ................................................. 11
Units of Measure ....................................................... 11
Document Revision History ........................................... 12
Sales, Solutions, and Legal Information ...................... 13
Worldwide Sales and Design Support ....................... 13
Products .................................................................... 13
PSoC®Solutions ....................................................... 13
Cypress Developer Community ................................. 13
Technical Support ..................................................... 13
Page 2 of 13
CY29948
Pin Configuration
VSS
Q0
VDDC
Q1
VSS
Q2
VDDC
Q3
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
VSS
Q9
VDDC
Q8
VSS
CY29948
Q11
1
2
3
4
5
6
7
8
VDDC
Q10
TCLK_SEL
TCLK
PECL_CLK
PECL_CLK#
SYNC_OE
TS#
VDD
VSS
32
Figure 1. 32-pin TQFP pinout
24
23
22
21
20
19
18
17
VSS
Q4
VDDC
Q5
VSS
Q6
VDDC
Q7
Pin Description
Pin
Name
PWR
I/O [1]
Description
3
PECL_CLK
–
I, PU
PECL Input Clock
4
PECL_CLK#
–
I, PD
PECL Input Clock
2
TCLK
–
I, PU
External Reference/Test Clock Input
9, 11, 13, 15,
17, 19, 21, 23,
25, 27, 29, 31
Q(11:0)
VDDC
O
1
TCLK_SEL
–
I, PU
Clock Select Input. When LOW, PECL clock is selected. When HIGH
TCLK is selected.
5
SYNC_OE
–
I, PU
Output Enable Input. When asserted HIGH, the outputs are enabled.
When set LOW the outputs are disabled in a LOW state.
6
TS#
–
I, PU
Three-state Control Input. When asserted LOW, the output buffers are
three-stated. When set HIGH, the output buffers are enabled.
10, 14, 18, 22,
26, 30
VDDC
–
–
7
VDD
–
–
2.5 V or 3.3 V Power Supply
8, 12, 16, 20,
24, 28, 32
VSS
–
–
Common Ground
Clock Outputs
2.5 V or 3.3 V Power Supply for Output Clock Buffers
Note
1. PD = Internal pull-down, PU = Internal pull-up.
Document Number: 38-07288 Rev. *I
Page 3 of 13
CY29948
Output Enable/Disable
The CY29948 features a control input to enable or disable the outputs. This data is latched on the falling edge of the input clock. When
SYNC_OE is asserted LOW, the outputs are disabled in a LOW state. When SYNC_OE is set HIGH, the outputs are enabled as shown
in Figure 2.
Figure 2. SYNC_OE Timing Diagram
TCLK
SYNC_OE
Q
Document Number: 38-07288 Rev. *I
Page 4 of 13
CY29948
Maximum Ratings
Maximum Power Supply ............................................... 5.5 V
Exceeding maximum ratings [2] may shorten the useful life of the
device. User guidelines are not tested.
Maximum Input Voltage Relative to VSS ............ VSS – 0.3 V
Maximum Input Voltage Relative to VDD ............ VDD + 0.3 V
Storage Temperature .............................. –65 °C to + 150 °C
Operating Temperature .............................. –40 °C to +85 °C
Maximum ESD protection .............................................. 2 kV
Maximum Input Current ............................................ ±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For proper
operation, Vin and Vout should be constrained to the range:
VSS < (Vin or Vout) < VDD
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Parameters
VDD = VDDC = 3.3 V ± 10% or 2.5 V ± 5%, over the specified temperature range.
Parameter
VIL
VIH
Description
Input Low Voltage
Input High Voltage
Conditions
Min
Typ
Max
Unit
VDD = 3.3 V, PECL_CLK single ended
1.49
–
1.825
V
VDD = 2.5 V, PECL_CLK single ended
1.10
–
1.45
All other inputs
VSS
–
0.8
VDD = 3.3 V, PECL_CLK single ended
2.135
–
2.42
VDD = 2.5 V, PECL_CLK single ended
1.75
–
2.0
All other inputs
2.0
–
VDD
V
IIL
Input Low Current [3]
–
–
–100
IIH
Input High Current
[3]
–
–
100
VPP
Peak-to-Peak Input Voltage
PECL_CLK
300
–
1000
mV
VCMR
Common Mode Range [4]
PECL_CLK
VDD = 3.3 V
VDD – 2.0
–
VDD – 0.6
V
VDD = 2.5 V
VDD – 1.2
–
VDD – 0.6
VOL
Output Low Voltage [5]
IOL = 20 mA
–
–
0.4
V
VOH
[5]
IOH = –20 mA, VDD = 3.3 V
2.5
–
–
V
IOH = –20 mA, VDD = 2.5 V
1.8
–
–
Output High Voltage
IDDQ
Quiescent Supply Current
IDD
Dynamic Supply Current
Zout
Cin
Output Impedance
Input Capacitance
µA
–
5
7
mA
VDD = 3.3 V, Outputs @ 100 MHz,
CL = 30 pF
–
180
–
mA
VDD = 3.3 V, Outputs @ 160 MHz,
CL = 30 pF
–
270
–
VDD = 2.5 V, Outputs @ 100 MHz,
CL = 30 pF
–
125
–
VDD = 2.5 V, Outputs @ 160 MHz,
CL = 30 pF
–
190
–
VDD = 3.3 V
12
15
18
VDD = 2.5 V
14
18
22
–
4
–
pF
Notes
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range
and the input lies within the VPP specification.
5. Driving series or parallel terminated 50 (or 50 to VDD/2) transmission lines.
Document Number: 38-07288 Rev. *I
Page 5 of 13
CY29948
Thermal Resistance
Parameter [6]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
32-pin TQFP
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
65
°C/W
12
°C/W
AC Parameters
VDD = VDDC = 3.3 V ± 10% or 2.5 V ± 5%, over the specified operating range.
Parameter [7]
Fmax
Tpd
Description
Conditions
Input Frequency [8]
Min
Typ
Max
Unit
VDD = 3.3 V
–
–
200
MHz
VDD = 2.5 V
–
–
170
[8]
VDD = 3.3 V
4.0
–
8.0
4.4
–
8.9
PECL_CLK to Q Delay [8]
VDD = 2.5 V
6.0
–
10.0
6.4
–
10.9
45
–
55
%
PECL_CLK to Q Delay
TCLK to Q Delay
[8]
TCLK to Q Delay [8]
[8, 9, 10]
FoutDC
Output Duty Cycle
tpZL, tpZH
Output Enable Time (all outputs)
2
–
10
ns
tpLZ, tpHZ
Output Disable Time (all outputs)
2
–
10
ns
–
150
250
ps
–
–
1.5
ns
Tskew
Output-to-Output Skew
Tskew(pp)
Part-to-Part Skew
Ts
Set-up Time [8, 12]
[11]
Measured at VDD/2
ns
[8, 10]
PECL_CLK to Q
TCLK to Q
[8, 12]
–
–
2.0
SYNC_OE to PECL_CLK
1.0
–
–
SYNC_OE to TCLK
0.0
–
–
PECL_CLK to SYNC_OE
0.0
–
–
Th
Hold Time
1.0
–
–
Tr/Tf
Output Clocks Rise/Fall Time [10] 0.8 V to 2.0 V, VDD = 3.3 V
0.20
–
1.0
0.6 V to 1.8 V, VDD = 2.5 V
0.20
–
1.3
TCLK to SYNC_OE
ns
ns
ns
Notes
6. These parameters are guaranteed by design and are not tested.
7. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
8. Outputs driving 50 transmission lines.
9. 50% input duty cycle.
10. See Figure 3 and Figure 4 on page 7.
11. Part-to-Part skew at a given temperature and voltage.
12. Setup and hold times are relative to the falling edge of the input clock.
Document Number: 38-07288 Rev. *I
Page 6 of 13
CY29948
Figure 3. LVCMOS_CLK CY29948 Test Reference for VCC = 3.3 V and VCC = 2.5 V
CY29948 DUT
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
R T = 50 ohm
R T = 50 ohm
VTT
VTT
Figure 4. PECL_CLK CY29948 Test Reference for VCC = 3.3 V and VCC = 2.5 V
CY29948 DUT
Zo = 50 ohm
Differential
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
Zo = 50 ohm
R T = 50 ohm
VTT
R T = 50 ohm
VTT
Figure 5. Propagation Delay (tPD) Test Reference
PEC L_C LK
V CMR
VPP
PEC L_C LK
VCC
Q
V C C /2
t
PD
GND
Figure 6. LVCMOS Propagation Delay (tPD) Test Reference
VCC
LVCMOS_CLK
VCC /2
GND
VCC
Q
VCC /2
t PD
Document Number: 38-07288 Rev. *I
GND
Page 7 of 13
CY29948
Figure 7. Output Duty Cycle (FoutDC)
VCC
VCC /2
tP
GND
T0
DC = tP / T0 x 100%
Figure 8. Output-to-Output Skew tsk(0)
VCC
VCC /2
GND
VCC
VCC /2
t SK(0)
Document Number: 38-07288 Rev. *I
GND
Page 8 of 13
CY29948
Ordering Information
Part Number
Package Type
Production Flow
Pb-free
CY29948AXC
32-pin TQFP
Commercial, 0 °C to +70 °C
CY29948AXCT
32-pin TQFP – Tape and Reel
Commercial, 0 °C to +70 °C
CY29948AXI
32-pin TQFP
Industrial, –40 °C to +85 °C
CY29948AXIT
32-pin TQFP – Tape and Reel
Industrial, –40 °C to +85 °C
Ordering Code Definitions
CY 29948
A
X
X
X
X = blank or T
blank = Tube; T = Tape and Reel
Temperature: X = C or I
C = Commercial; I = Industrial
X = Pb-free
Package: A = 32-pin TQFP
Device part number
Company ID: CY = Cypress
Document Number: 38-07288 Rev. *I
Page 9 of 13
CY29948
Package Drawing and Dimensions
Figure 9. 32-pin TQFP (7 × 7 × 1.0 mm) Package Outline, 51-85063
51-85063 *E
Document Number: 38-07288 Rev. *I
Page 10 of 13
CY29948
Acronyms
Acronym
Document Conventions
Description
CMOS
Complementary Metal Oxide Semiconductor
ESD
Electrostatic Discharge
Units of Measure
Symbol
Unit of Measure
°C
degree Celsius
kV
kilovolt
MHz
megahertz
I/O
Input/Output
LVCMOS
Low Voltage Complementary Metal Oxide
Semiconductor
LVPECL
Low Voltage Positive Emitter Coupled Logic
µA
microampere
LVTTL
Low Voltage Transistor-Transistor Logic
mA
milliampere
PLL
Phase Locked Loop
mm
millimeter
Thin Quad Flat Pack
mV
millivolt
ns
nanosecond
ohm
TQFP
Document Number: 38-07288 Rev. *I
%
percent
pF
picofarad
ps
picosecond
V
volt
Page 11 of 13
CY29948
Document Revision History
Document Title: CY29948, 2.5 V or 3.3 V, 200 MHz, 1:12 Clock Distribution Buffer
Document Number: 38-07288
Rev.
ECN No.
Submission
Date
Orig. of
Change
**
111099
02/13/02
BRK
Description of Change
New data sheet.
*A
116782
08/14/02
HWT
*B
122880
12/22/02
RBI
Added power up requirements to Maximum Ratings
*C
428221
See ECN
RGL
Added Lead-free devices
*D
2904731
04/05/10
CXQ
Removed inactive part numbers - CY29948AI and CY29948AIT.
Updated package diagram.
*E
3246222
05/02/2011
CXQ
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Updated in new template.
*F
3859773
01/07/2013
AJU
Updated Ordering Information (Updated part numbers).
Updated Package Drawing and Dimensions:
spec 51-85063 – Changed revision from *C to *D.
*G
4345036
04/14/2014
XHT
Updated to new template.
Completing Sunset Review.
*H
4586288
12/03/2014
XHT
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*I
5275785
05/18/2016
PSR
Added Thermal Resistance.
Updated Package Drawing and Dimensions:
spec 51-85063 – Changed revision from *D to *E.
Updated to new template.
Document Number: 38-07288 Rev. *I
Added Commercial Temperature Range
Page 12 of 13
CY29948
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Document Number: 38-07288 Rev. *I
Revised May 18, 2016
Page 13 of 13