CY7C106D CY7C1006D 1-Mbit (256K x 4) Static RAM Functional Description [1] Features • Pin- and function-compatible with CY7C106B/CY7C1006B • High speed — tAA = 10 ns • Low active power — ICC = 80 mA @ 10 ns • Low CMOS standby power — ISB2 = 3.0 mA The CY7C106D and CY7C1006D are high-performance CMOS static RAMs organized as 262,144 words by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. These devices have an automatic power-down feature that reduces power consumption by more than 65% when the devices are deselected. The four input and output pins (IO0 through IO3) are placed in a high-impedance state when: • Deselected (CE HIGH) • 2.0V Data Retention • Outputs are disabled (OE HIGH) • Automatic power-down when deselected • When the write operation is active (CE and WE LOW) • CMOS for optimum speed/power • TTL-compatible inputs and outputs • CY7C106D available in Pb-free 28-pin 400-Mil wide Molded SOJ package. CY7C1006D available in Pb-free 28-pin 300-Mil wide Molded SOJ package Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the four IO pins (IO0 through IO3) is then written into the location specified on the address pins (A0 through A17). Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appears on the four IO pins. Logic Block Diagram 256K x 4 ARRAY CE COLUMN DECODER WE IO1 IO2 IO3 POWER DOWN A0 A10 A11 A12 A13 A14 A15 A16 A17 OE IO0 SENSE AMPS A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER Note 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05459 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 22, 2007 [+] Feedback CY7C106D CY7C1006D Pin Configuration [2] SOJ Top View A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CE OE GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A17 A16 A15 A14 A13 A12 A11 NC IO3 IO2 IO1 IO0 WE Selection Guide CY7C106D-10 CY7C1006D-10 Unit Maximum Access Time 10 ns Maximum Operating Current 80 mA Maximum Standby Current 3 mA Note 2. NC pins are not connected on the die. Document #: 38-05459 Rev. *E Page 2 of 11 [+] Feedback CY7C106D CY7C1006D DC Input Voltage [3] ............................... –0.5V to VCC + 0.5V Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static Discharge Voltage .......................................... > 2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-up Current .................................................... > 200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage on VCC Relative to GND [3] ... –0.5V to +6.0V DC Voltage Applied to Outputs in High-Z State [3] ...................................–0.5V to VCC + 0.5V Range Ambient Temperature VCC Speed Industrial –40°C to +85°C 5V ± 0.5V 10 ns Electrical Characteristics (Over the Operating Range) Parameter Description 7C106D-10 7C1006D-10 Test Conditions Min VOH Output HIGH Voltage IOH = –4.0 mA VOL Output LOW Voltage IOL = 8.0 mA VIH Input HIGH Voltage Unit Max 2.4 [3] V 0.4 V 2.2 VCC + 0.5 V –0.5 0.8 V VIL Input LOW Voltage IIX Input Leakage Current GND < VI < VCC –1 +1 µA IOZ Output Leakage Current GND < VI < VCC, Output Disabled –1 +1 µA ICC VCC Operating Supply Current VCC = Max, IOUT = 0 mA, f = fmax = 1/tRC 100 MHz 80 mA 83 MHz 72 mA 66 MHz 58 mA 40 MHz 37 mA ISB1 Automatic CE Power-Down Current—TTL Inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fmax 10 mA ISB2 Automatic CE Power-Down Current—CMOS Inputs Max VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V, f=0 3 mA Note 3. VIL (min) = –2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns. Document #: 38-05459 Rev. *E Page 3 of 11 [+] Feedback CY7C106D CY7C1006D Capacitance [4] Parameter CIN: Addresses Description Test Conditions Input Capacitance Max Unit 7 pF TA = 25°C, f = 1 MHz, VCC = 5.0V CIN: Controls COUT Output Capacitance 10 pF 10 pF Thermal Resistance [4] Parameter Description Test Conditions ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 300-Mil Wide SOJ 400-Mil Wide SOJ Unit 59.16 58.76 °C/W 40.84 40.54 °C/W AC Test Loads and Waveforms [5] ALL INPUT PULSES 3.0V Z = 50Ω 90% OUTPUT 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 30 pF* 90% 10% 10% GND 1.5V Rise Time: ≤ 3 ns (a) (b) Fall Time: ≤ 3 ns High-Z characteristics: R1 480Ω 5V OUTPUT INCLUDING JIG AND SCOPE R2 255Ω 5 pF (c) Notes 4. Tested initially and after any design or process changes that may affect these parameters. 5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). Document #: 38-05459 Rev. *E Page 4 of 11 [+] Feedback CY7C106D CY7C1006D Switching Characteristics (Over the Operating Range) [6] Parameter 7C106D-10 7C1006D-10 Description Min Unit Max Read Cycle tpower [7] VCC(typical) to the first access 100 µs tRC Read Cycle Time 10 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z tHZOE tLZCE tHZCE tPU [10] tPD [10] Write Cycle 3 [8, 9] [9] 10 ns 5 ns CE HIGH to High Z CE LOW to Power-Up ns 5 3 [8, 9] ns ns 5 0 CE HIGH to Power-Down ns ns 0 OE HIGH to High Z CE LOW to Low Z 10 ns ns 10 ns [11, 12] tWC Write Cycle Time 10 ns tSCE CE LOW to Write End 7 ns tAW Address Set-Up to Write End 7 ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WE Pulse Width 7 ns tSD Data Set-Up to Write End 6 ns tHD Data Hold from Write End 0 ns [9] tLZWE WE HIGH to Low Z tHZWE WE LOW to High Z [8, 9] 3 ns 5 ns Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of “AC Test Loads and Waveforms [5]” on page 4. Transition is measured when the outputs enter a high impedance state. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. This parameter is guaranteed by design and is not tested. 11. The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. Document #: 38-05459 Rev. *E Page 5 of 11 [+] Feedback CY7C106D CY7C1006D Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR [4] Chip Deselect to Data Retention Time tR [13, 14] Min Max 2.0 V VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Operation Recovery Time Unit 3 mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 4.5V VCC 4.5V VDR > 2V tR tCDR CE Switching Waveforms Read Cycle No.1 (Address Transition Controlled) [15, 16] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled) [16, 17] ADDRESS tRC CE tACE OE tHZOE tDOE tLZOE HIGH IMPEDANCE DATA OUT VCC SUPPLY CURRENT tHZCE HIGH IMPEDANCE DATA VALID tLZCE tPD tPU 50% 50% ICC ISB Notes 13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 µs or stable at VCC(min) > 50 µs. 14. tr < 3 ns for all speeds. 15. Device is continuously selected, OE and CE = VIL. 16. WE is HIGH for read cycle. Document #: 38-05459 Rev. *E Page 6 of 11 [+] Feedback CY7C106D CY7C1006D Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled) [18, 19] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA IO tHD DATA VALID Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [18, 19] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD tHD DATA VALID DATA IO tHZOE Notes 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 19. Data IO is high impedance if OE = VIH. Document #: 38-05459 Rev. *E Page 7 of 11 [+] Feedback CY7C106D CY7C1006D Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) [12, 19] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD tHD DATA VALID DATA IO tLZWE tHZWE Truth Table CE OE WE Input/Output Mode Power H X X High Z Power-Down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 Ordering Code Package Diagram Package Type CY7C106D-10VXI 51-85032 28-pin (400-Mil) Molded SOJ (Pb-free) CY7C1006D-10VXI 51-85031 28-pin (300-Mil) Molded SOJ (Pb-free) Operating Range Industrial Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05459 Rev. *E Page 8 of 11 [+] Feedback CY7C106D CY7C1006D Package Diagrams Figure 1. 28-pin (300-Mil) Molded SOJ, 51-85031 NOTE : 1. JEDEC STD REF MO088 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE MIN. MAX. 3. DIMENSIONS IN INCHES DETAIL A EXTERNAL LEAD DESIGN PIN 1 ID 14 1 0.291 0.300 15 0.330 0.350 28 OPTION 1 0.697 0.713 A Document #: 38-05459 Rev. *E 0.014 0.020 OPTION 2 SEATING PLANE 0.120 0.140 0.050 TYP. 0.026 0.032 0.013 0.019 0.007 0.013 0.004 0.025 MIN. 0.262 0.272 51-85031-*C Page 9 of 11 [+] Feedback CY7C106D CY7C1006D Package Diagrams Figure 2. 28-pin (400-Mil) Molded SOJ, 51-85032 PIN 1 I.D 14 1 .395 .405 15 DIMENSIONS IN INCHES .435 .445 MIN. MAX. 28 .720 .730 SEATING PLANE .128 .148 .026 .032 .007 .013 0.004 .025 MIN. .360 .380 51-85032-*B .015 .020 All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05459 Rev. *E Page 10 of 11 © Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C106D CY7C1006D Document History Page Document Title: CY7C106D/CY7C1006D, 1-Mbit (256K x 4) Static RAM Document Number: 38-05459 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 201560 See ECN SWI Advance information data sheet for C9 IPP *A 233693 See ECN RKF ICC,ISB1,ISB2 Specs are modified as per EROS (Spec # 01-2165) Pb-free offering in the ‘ordering information’ *B 262950 See ECN RKF Added Tpower Spec in Switching Characteristics table Shaded ‘Ordering Information’ *C See ECN See ECN RKF Reduced Speed bins to -10 and -12 ns *D 560995 See ECN VKN Converted from Preliminary to Final Removed Commercial Operating range Removed 12 ns speed bin Added ICC values for the frequencies 83MHz, 66MHz and 40MHz Updated Thermal Resistance table Updated Ordering Information table Changed Overshoot spec from VCC+2V to VCC+1V in footnote #3 *E 802877 See ECN VKN Changed ICC spec from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz Document #: 38-05459 Rev. *E Page 11 of 11 [+] Feedback