LINER LTC6416CDDB

LTC6416
2 GHz Low Noise Differential
16-Bit ADC Buffer
DESCRIPTION
FEATURES
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2GHz –3dB Small Signal Bandwidth
300MHz ±0.1dB Bandwidth
1.8nV/√Hz Output Noise
46.25dBm Equivalent OIP3 at 140MHz
40.25dBm Equivalent OIP3 Up to 300MHz
–81dBc/–72dBc HD2/HD3 at 140MHz, 2VP-P Out
–84.5dBc IM3 at 140MHz, 2VP-P Out Composite
–74dBc/–67.5dBc HD2/HD3 at 300MHz, 2VP-P Out
–72.5dBc IM3 at 300MHz, 2VP-P Out Composite
Programmable High Speed, Fast Recovery
Output Clamping
DC-Coupled Signal Path
Operates on Single 2.7V to 3.9V Supply
Low Power: 150mW on 3.6V
2mm × 3mm 10-Pin DFN Package
The LTC®6416 is a differential unity gain buffer designed
to drive 16-bit ADCs with extremely low output noise
and excellent linearity beyond 300MHz. Differential input
impedance is 12kΩ, allowing 1:4 and 1:8 transformers to
be used at the input to achieve additional system gain.
With no external biasing or gain setting components and
a flow-through pinout, the LTC6416 is very easy to use.
It can be DC-coupled and has a common mode output
offset of –40mV. If the input signals are AC-coupled, the
LTC6416 input pins are internally biased to provide an
output common mode voltage that is set by the voltage
on the VCM pin.
In addition the LTC6416 has high speed, fast recovery
clamping circuitry to limit output signal swing. Both the
high and low clamp voltages are internally biased to allow
maximum output swing but are also user programmable
via the CLLO and CLHI pins.
APPLICATIONS
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Differential ADC Driver
IF Sampling Receivers
Impedance Transformer
SAW Filter Interface
CCD Buffer
Supply current is nominally 42mA and the LTC6416 operates on supply voltages ranging from 2.7V to 3.9V.
The LTC6416 is packaged in a 10-lead 3mm × 2mm DFN
package. Pinout is optimized for placement directly adjacent
to Linear’s high speed 12-, 14- and 16-bit ADCs.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
LTC6416 Driving LTC2208 ADC
with 1:8 Transformer fIN =140MHz,
fS = 130MHz, –1dBFS, PGA = 1
TYPICAL APPLICATION
0
LTC6416 Driving LTC2208 ADC – 140MHz IF
–20
–30
0.1μF
2.2μF
CLHI
1:8
50Ω
200Ω
V+
IN+
VCM
25Ω
+
–
200Ω
MINI-CIRCUITS
TCM8-1+
IN–
GND
0.1μF CLLO
3.3V
1.5pF
AIN+
OUT+
LTC6416
OUT–
GND
LTC2208
1pF
1.5pF
16
–40
–50
–60
–70
–80
–90
–100
AIN–
25Ω
AMPLITUDE (dBFS)
3.6V
680pF
V+ = 3.6V
HD2 = –94dBc
HD3 = –89.1dBc
SFDR = 89.1dB
SNR = 70.7dB
MEASURED USING DC1257B
WITH MINI-CIRCUIT TCM8-1+
1:8 TRANSFORMER
–10
PGA = 1
6416 TA01a
CLOCK
(130MHz)
–110
–120
0
10
20
30
40
FREQUENCY (MHz)
50
60
6416 TA01b
6416f
1
LTC6416
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Total Supply Voltage (V+ to GND)................................4V
Input Current (CLLO, CLHI, VCM, IN+, IN–)...........±10mA
Output Current (OUT+, OUT–) ...........................±22.5mA
Operating Temperature Range (Note 2).... –40°C to 85°C
Specified Temperature Range (Note 3) .... –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
Junction Temperature ........................................... 150°C
10 V+
VCM 1
CLHI 2
9
GND
8
OUT+
IN– 4
7
OUT–
CLLO 5
6
GND
IN+ 3
11
DDB PACKAGE
10-LEAD (3mm s 2mm) PLASTIC DFN
TJMAX = 150°C, θJA = 76°C/W, θJC = 13.5°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI)
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC6416CDDB#TRMPBF
LTC6416CDDB#TRPBF
LDDY
10-Lead (3mm × 2mm) Plastic DFN
LTC6416IDDB#TRMPBF
LTC6416IDDB#TRPBF
LDDY
10-Lead (3mm × 2mm) Plastic DFN
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
0°C to 70°C
–40°C to 85°C
3.6V ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.6V, GND = 0V, No RLOAD, CLOAD = 6pF. VCM = 1.25V,
CLHI = V+, CLLO = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as (OUT+ + OUT–)/2. VINDIFF is
defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
–0.3
–0.4
–0.15
0
0
UNITS
Input/Output Characteristics
GDIFF
Differential Gain
TCGDIFF
Differential Gain Temperature Coefficient
VSWINGDIFF
Differential Output Voltage Swing
VOUTDIFF, VINDIFF = ±2.3V
VSWINGMIN
Output Voltage Swing Low
Single-Ended Measurement of OUT+,
OUT–. VINDIFF = ±2.3V
l
VSWINGMAX
Output Voltage Swing High
Single-Ended Measurement of OUT+,
OUT–. VINDIFF = ±2.3V
l
2.15
2
IOUT
Output Current Drive
Single-Ended Measurement of OUT+,
OUT–
l
±20
Differential Input Offset Voltage
IN+ = IN– = 1.25V, V
l
–5
–10
–0.5
–65
–75
–47
VOS
VINDIFF = ±1.2V Differential
l
GDIFF
TCVOS
Differential Input Offset Voltage Drift
VIOCM
Common Mode Offset Voltage, Input to
Output
l
OS = VOUTDIFF/
l
3.7
3.3
l
–0.00033
dB/°C
4.2
VP-P
VP-P
0.2
l
VOUTCM – VINCM
dB
dB
0.3
0.35
2.3
V
V
V
V
mA
5
10
1
mV
mV
μV/°C
–15
–5
mV
mV
6416f
2
LTC6416
3.6V ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.6V, GND = 0V, No RLOAD, CLOAD = 6pF. VCM = 1.25V,
CLHI = V+, CLLO = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as (OUT+ + OUT–)/2. VINDIFF is
defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic.
SYMBOL
PARAMETER
CONDITIONS
IVRMIN
Input Voltage Range, IN+, IN–
(Minimum) (Single-Ended)
Defined by Output Voltage Swing Test
l
IVRMAX
Input Voltage Range IN+, IN–
(Maximum) (Single-Ended)
Defined by Output Voltage Swing Test
l
2.4
IB
Input Bias Current, IN+, IN–
IN+ = IN– = 1.25V
l
–15
–5
15
μA
RINDIFF
Differential Input Resistance
VINDIFF = ±1.2V
l
9
12
15
kΩ
CINDIFF
Differential Input Capacitance
RINCM
Input Common Mode Resistance
IN+ = IN– = 0.65V to 1.85V
CMRR
Common Mode Rejection Ratio
IN+ = IN– = 0.65V to 1.85V,
CMRR = (VOUTDIFF/GDIFF/1.2V)
eN
Input Noise Voltage Density
iN
Input Noise Current Density
MIN
TYP
MAX
0.1
UNITS
V
V
1
pF
6
kΩ
83
dB
dB
f = 100kHz
1.8
nV/√Hz
f = 100kHz
6.5
pA/√Hz
l
63.5
59.6
Output Common Mode Voltage Control
VCM Pin Common Mode Gain
VCM = 0.65V to 1.85V
l
0.9
0.96
1.05
VINCMDEFAULT
Default Input Common Mode Voltage
VINCM. IN+, IN–, VCM Pin Floating
l
1.3
1.38
1.45
VOS (VCM – VINCM)
Offset Voltage, VCM to VINCM
VCM – VINCM, VCM = 1.25V
l
–70
–28
70
GCM
VOUTCMDEFAULT
Default Output Common Mode Voltage
Inputs Floating, VCM Pin Floating
l
1.25
1.34
1.45
VOS (VCM – VOUTCM)
Offset Voltage, VCM to VOUTCM
VCM – VOUTCM, VCM = 1.25V
l
–60
15
60
VOUTCMMIN
Output Common Mode Voltage Range
(Minimum)
VCM = 0.1V
0.37
0.5
0.55
VOUTCMMAX
Output Common Mode Voltage Range
(Maximum)
VCM = 2.7V
VCMDEFAULT
l
V/V
V
mV
V
mV
V
V
l
2.3
2.25
2.46
V
V
VCM Pin Default Voltage
l
1.325
1.36
1.425
RVCM
VCM Pin Input Resistance
l
2.5
3.8
5.1
kΩ
CVCM
VCM Pin Input Capacitance
IBVCM
VCM Pin Bias Current
l
–50
–32
50
μA
l
2.3
2.45
2.6
V
l
–55
13
55
mV
l
0.125
0.265
0.425
l
–120
–70
0
mV
1
VCM = 1.25V
V
pF
DC Clamping Characteristics
VCLHIDEFAULT
Default Output Clamp Voltage, High
VOS (CLHI – VOUTCM) Offset Voltage, CLHI to VOUTCM
VCLLODEFAULT
Default Output Clamp Voltage, Low
VOS (CLLO – VOUTCM) Offset Voltage, CLLO to VOUTCM
V
RCLHI
CLHI Pin Input Resistance
VCLHI = 2.45V
l
3
4.1
5
kΩ
IBCLHI
CLHI Pin Bias Current
VCLHI = 2.45V
l
–25
–1
25
μA
RCLLO
CLLO Pin Input Resistance
VCLLO = 0.275V
l
1.5
2.3
3.2
kΩ
IBCLLO
CLLO Pin Bias Current
VCLLO = 0.275V
l
–25
4.5
25
μA
l
2.7
3.9
V
51
54
mA
mA
Power Supply
VS
Supply Voltage Range
IS
Supply Current
PSRR
Power Supply Rejection Ratio
l
VS = 2.7V to 3.6V
l
33
42
57.5
80
dB
6416f
3
LTC6416
3.3V ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V, GND = 0V, No RLOAD, CLOAD = 6pF. VCM = 1.25V,
CLHI = V+, CLLO = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as (OUT+ + OUT–)/2. VINDIFF is
defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
–0.3
–0.4
–0.15
0
0
UNITS
Input/Output Characteristics
GDIFF
Differential Gain
VINDIFF = ±1.2V
TCGDIFF
Differential Gain Temperature Coefficient
VOUTDIFF
Differential Output Voltage Swing
VINDIFF = ±2.3V
VOUTMIN
Output Voltage Swing Low
Single-Ended Measurement of OUT+,
OUT–. VINDIFF = ±2.3V
l
VOUTMAX
Output Voltage Swing High
Single-Ended Measurement of OUT+,
OUT–. VINDIFF = ±2.3V
l
2.05
1.95
IOUT
Output Current Drive (Note 4)
Single-Ended Measurement of OUT+,
OUT–
l
±20
VOS
Differential Input Offset Voltage
IN+ = IN– = 1.25V, V
l
–5
–10
TCVOS
Differential Input Offset Voltage Drift
VIOCM
Common Mode Offset Voltage, Input to
Output
VOUTCM – VINCM
IVRMIN
Input Voltage Range, IN+, IN–
(Minimum) (Single-Ended)
Defined by Output Voltage Swing Test l
IVRMAX
Input Voltage Range, IN+, IN–
(Maximum) (Single-Ended)
Defined by Output Voltage Swing Test l
2.4
IB
Input Bias Current, IN+, IN–
IN+ = IN– = 1.25V
l
–15
–4
15
μA
RINDIFF
Differential Input Resistance
VINDIFF = ±1.2V
l
9
12
15
kΩ
CINDIFF
Differential Input Capacitance
l
l
l
OS = VOUTDIFF/
GDIFF
3.5
3.2
l
–0.00033
dB/°C
4
VP-P
VP-P
0.2
l
0.3
0.35
2.2
V
V
V
V
mA
–0.1
5
10
1
–65
–75
dB
dB
–40
mV
mV
μV/°C
–15
–5
mV
mV
0.1
V
V
1
pF
6
kΩ
83
dB
dB
Input Common Mode Resistance
IN+ = IN– = 0.65V to 1.85V
CMRR
Common Mode Rejection Ratio
IN+ = IN– = 0.65V to 1.85V = ΔVINCM,
CMRR = (VOUTDIFF/GDIFF/ΔVINCM)
eN
Input Noise Voltage Density
f = 100kHz
1.8
nV/√Hz
iN
Input Noise Current Density
f = 100kHz
6.5
pA/√Hz
RINCM
l
63.5
59.6
Output Common Mode Voltage Control
GCM
VCM Pin Common Mode Gain
VCM = 0.65V to 1.85V
l
0.9
0.96
1.05
V/V
VINCMDEFAULT
Default Input Common Mode Voltage
VINCM. IN+, IN–, VCM Pin Floating
l
1.2
1.28
1.35
V
VOS (VCM – VINCM)
Offset Voltage, VCM to VINCM
VCM – VINCM, VCM = 1.25V
l
–70
–26
70
VOUTCMDEFAULT
Default Output Common Mode Voltage
Inputs Floating, VCM Pin Floating
l
1.15
1.24
1.35
VOS (VCM – VOUTCM)
Offset Voltage, VCM to VOUTCM
VCM – VOUTCM, VCM = 1.25V
l
–60
14
60
VOUTCMMIN
Output Common Mode Voltage
(Minimum)
VCM = 0.1V
0.34
0.5
0.55
VOUTCMMAX
Output Common Mode Voltage
(Maximum)
VCM = 2.4V
VCMDEFAULT
l
mV
V
mV
V
V
l
2.05
2
2.16
V
V
VCM Pin Default Voltage
l
1.2
1.25
1.3
V
RVCM
VCM Pin Input Resistance
l
2.5
3.8
5.1
kΩ
CVCM
VCM Pin Input Capacitance
IBVCM
VCM Pin Bias Current
1
VCM = 1.25V
l
–10
0.2
pF
10
μA
6416f
4
LTC6416
3.3V ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V, GND = 0V, No RLOAD, CLOAD = 6pF. VCM = 1.25V,
CLHI = V+, CLLO = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as (OUT+ + OUT–)/2. VINDIFF is
defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
2.23
2.4
V
DC Clamping Characteristics
Default Output Clamp Voltage, High
l
2.1
VOS (CLHI – VOUTCM)
Offset Voltage, CLHI to VOUTCM
l
–55
4
55
mV
VCLLODEFAULT
Default Output Clamp Voltage, Low
l
0.1
0.25
0.4
V
VCLHIDEFAULT
l
–120
–72
0
mV
RCLHI
CLHI Pin Input Resistance
VCLHI = 2.25V
l
3
4.1
5
kΩ
IBCLHI
CLHI Pin Bias Current
VCLHI = 2.25V
l
–25
–1
25
μA
RCLLO
CLLO Pin Input Resistance
VCLLO = 0.25V
l
1.5
2.3
3.2
kΩ
IBCLLO
CLLO Pin Bias Current
VCLLO = 0.25V
l
–25
3
25
μA
l
2.7
3.9
V
51
54
mA
mA
VOS (CLLO – VOUTCM) Offset Voltage, CLLO to VOUTCM
Power Supply
VS
Supply Voltage Range
IS
Supply Current
PSRR
Power Supply Rejection Ratio
l
VS = 2.7V to 3.6V
l
33
42
57.5
80
dB
AC ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V and 3.6V unless otherwise noted, GND = 0V, No RLOAD,
CLOAD = 6pF. VCM = 1.25V, CLHI = VCC, CLLO = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as
(OUT+ + OUT–)/2. VINDIFF is defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Differential AC Characteristics
–3dBBW
–3dB Bandwidth
200mVP-P,OUT Differential
2
GHz
0.1dBBW
±0.1dB Bandwidth
200mVP-P,OUT Differential
0.3
GHz
0.5dBBW
±0.5dB Bandwidth
200mVP-P,OUT Differential
1.4
GHz
1/f
1/f Noise Corner
25
kHz
SR
Slew Rate
Differential
3.4
V/ns
tS1%
1% Settling Time
2VP-P,OUT
1.8
ns
Common Mode AC Characteristics (VCM Pin)
–3dBBWVCM
VCM Pin Small Signal –3dB BW
VCM = 0.1VP-P, Measured Single-Ended
at Output
9
MHz
SRCM
Common Mode Slew Rate
Measured Single-Ended at Output
40
V/μs
Overdrive Recovery Time
1.9VP-P,OUT
5
ns
Second Harmonic Distortion
V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P
V+ = 3.3V, VCM = 1.25V, VOUTDIFF = 2VP-P
V+ = 3.6V, VCM = 1.05V, VOUTDIFF = 2VP-P
V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P
–83.5
–71
–78.5
–88.5
dBc
dBc
dBc
dBc
AC Clamping Characteristics
tOVDR
AC Linearity
70MHz Signal
HD2
6416f
5
LTC6416
AC ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V and 3.6V unless otherwise noted, GND = 0V, No RLOAD,
CLOAD = 6pF. VCM = 1.25V, CLHI = VCC, CLLO = 0V unless otherwise noted. VINCM is defined as (IN+ + IN–)/2. VOUTCM is defined as
(OUT+ + OUT–)/2. VINDIFF is defined as (IN+ – IN–). VOUTDIFF is defined as (OUT+ – OUT–). See DC test circuit schematic.
SYMBOL
PARAMETER
CONDITIONS
HD3
Third Harmonic Distortion
V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P
V+ = 3.3V, VCM = 1.25V, VOUTDIFF = 2VP-P
V+ = 3.6V, VCM = 1.05V, VOUTDIFF = 2VP-P
V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P
MIN
TYP
–73
–60
–94.5
–83
MAX
UNITS
dBc
dBc
dBc
dBc
IM3
Output Third Order Intermodulation
Distortion
V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P
V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P
–76.5
–86
dBc
dBc
OIP3
Output Third Order Intercept (Equivalent)
(Note 5)
V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P
V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P
42.25
47
dBm
dBm
P1dB
Output 1dB Compression Point (Equivalent)
(Note 5)
V+ = 3.6V, VCM = 1.25V
14.1
dBm
140MHz Signal
HD2
Second Harmonic Distortion
V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P
V+ = 3.3V, VCM = 1.25V, VOUTDIFF = 2VP-P
V+ = 3.6V, VCM = 1.05V, VOUTDIFF = 2VP-P
V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P
–79.5
–75.5
–73
–81
dBc
dBc
dBc
dBc
HD3
Third Harmonic Distortion
V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P
V+ = 3.3V, VCM = 1.25V, VOUTDIFF = 2VP-P
V+ = 3.6V, VCM = 1.05V, VOUTDIFF = 2VP-P
V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P
–64
–55
–70
–72
dBc
dBc
dBc
dBc
IM3
Output Third Order Intermodulation
Distortion
V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P
V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P
–75
–84.5
dBc
dBc
OIP3
Output Third Order Intercept (Equivalent)
(Note 5)
V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P
V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P
41.5
46.25
dBm
dBm
P1dB
Output 1dB Compression Point (Equivalent)
(Note 5)
V+ = 3.6V, VCM = 1.25V
14.1
dBm
300MHz Signal
HD2
Second Harmonic Distortion
V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P
V+ = 3.3V, VCM = 1.25V, VOUTDIFF = 2VP-P
V+ = 3.6V, VCM = 1.05V, VOUTDIFF = 2VP-P
V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P
–75
–65
–69.5
–74
dBc
dBc
dBc
dBc
HD3
Third Harmonic Distortion
V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P
V+ = 3.3V, VCM = 1.25V, VOUTDIFF = 2VP-P
V+ = 3.6V, VCM = 1.05V, VOUTDIFF = 2VP-P
V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P
–59
–51.5
–63
–67.5
dBc
dBc
dBc
dBc
IM3
Output Third Order Intermodulation
Distortion
V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P
V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P
–68.5
–72.5
Output Third Order Intercept (Equivalent)
(Note 5)
V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-P
V+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P
Output 1dB Compression Point (Equivalent)
(Note 5)
V+ = 3.6V, VCM = 1.25V
OIP3
P1dB
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6416C/LTC6416I is guaranteed functional over the
operating temperature range of –40°C to 85°C.
Note 3: The LTC6416C is guaranteed to meet specified performance from
0°C to 70°C. It is designed, characterized and expected to meet specified
performance from –40°C and 85°C but is not tested or QA sampled
36
–64
dBc
dBc
38.25
40.25
dBm
dBm
12.9
dBm
at these temperatures. The LT6416I is guaranteed to meet specified
performance from –40°C to 85°C.
Note 4: This parameter is pulse tested.
Note 5: Since the LTC6416 is a voltage-output buffer, a resistive load is not
required when driving an AD converter. Therefore, typical output power is very
small. In order to compare the LTC6416 with amplifiers that require a 50Ω
output load, the LTC6416 output voltage swing driving a given RL is converted
to OIP3 and P1dB as if it were driving a 50Ω load. Using this modified
convention, 2VP-P is by definition equal to 10dBm, regardless of actual RL.
6416f
6
LTC6416
TYPICAL PERFORMANCE CHARACTERISTICS
2
Differential Input Return Loss
(S11) vs Frequency
0
V+ = 3.3V
0
V+ = 3.3V
–5
–2
–10
–4
S11 (dB)
–6
–8
–10
–15
–20
–25
–12
–30
–14
–16
10
100
1000
FREQUENCY (MHz)
–35
10000
10
100
FREQUENCY (MHz)
6416 G01
–6
–7
–8
–9
–60
–70
–80
–70
–90
6416 G04
HD2
–80
–90
1000
100
FREQUENCY (MHz)
–100
1000
V+ = 3.6V
VCM = 1.25V
RLOAD = 400Ω
–60 V
OUT = 2VP-P DIFFERENTIAL
–60
–40
–50
10
–50
HD3
HD2, HD3 (dBc)
DIFFERENTIAL REVERSE ISOLATION (dB)
–5
Second and Third Harmonic
Distortion vs Frequency
–50
100
FREQUENCY (MHz)
–4
Second and Third Harmonic
Distortion vs Frequency
V+ = 3.3V
10
–3
6416 G03
–30
–100
–2
6416 G02
Differential Reverse Isolation
(S12) vs Frequency
–20
1000
V+ = 3.3V
–1
–10
HD2, HD3 (dBc)
DIFFERENTIAL GAIN (dB)
0
Differential Output Return Loss
(S22) vs Frequency
DIFFERENTIAL OUTPUT RETURN LOSS (dB)
Differential Forward Gain (S21)
vs Frequency
V+ = 3.3V
100
FREQUENCY (MHz)
–80
HD2
–90
VCM = 1.25V
RLOAD = 400Ω
VOUT = 2VP-P DIFFERENTIAL
10
HD3
–70
500
6416 G05
–100
10
100
FREQUENCY (MHz)
500
6416 G06
6416f
7
LTC6416
TYPICAL PERFORMANCE CHARACTERISTICS
Second and Third Harmonic
Distortion vs Output Common
Mode Voltage (140MHz)
Second and Third Harmonic
Distortion vs Output Common
Mode Voltage (75MHz)
–50
–60
–50
V+ = 3.6V
RLOAD = 400Ω
VOUT = 2VP-P DIFFERENTIAL
Second and Third Harmonic
Distortion vs Output Common
Mode Voltage (250MHz)
–50
V+ = 3.6V
RLOAD = 400Ω
VOUT = 2VP-P DIFFERENTIAL
–60
–60
V+ = 3.6V
RLOAD = 400Ω
VOUT = 2VP-P DIFFERENTIAL
HD3
–80
HD2
–90
–70
HD3
–80
HD2
–90
–100
1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45
VCM (V)
–100
1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45
VCM (V)
HD2
–80
–100
1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45
VCM (V)
6416 G08
6416 G09
Third Order Intermodulation
Distortion (IM3) vs Frequency and
Supply Voltage
Second and Third Harmonic
Distortion vs Output Common
Mode Voltage (300MHz)
–60
–70
–90
6416 G07
–50
HD2, HD3 (dBc)
–70
HD2, HD3 (dBc)
HD2, HD3 (dBc)
HD3
Third Order Intermodulation
Distortion (IM3) vs Output
Common Mode Voltage (140MHz)
–50
V+ = 3.6V
RLOAD = 400Ω
VOUT = 2VP-P DIFFERENTIAL
–50
IM3 VCC = 3.3V
IM3 V+ = 3.3V
–60
–60
–70
–70
HD2
–80
–90
IM3 VCC = 3.6V
–80
V+ = 3.3V, 3.6V; VCM = 1.25V
RLOAD = 400Ω
VOUT = 2VP-P DIFFERENTIAL (COMPOSITE)
$f = 1MHz
–90
–100
1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45
VCM (V)
–100
0
IM3 V+ = 3.6V
–80
+
–90 V = 3.3V, 3.6V
RLOAD = 400Ω
VOUT = 2VP-P DIFFERENTIAL (COMPOSITE)
$f = 1MHz
–100
1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45
VCM (V)
50 100 150 200 250 300 350 400 450 500
FREQUENCY (MHz)
6416 G10
6416 G11
6416 G12
Output Third Order Intercept
(OIP3EQUIV) vs Output Common
Mode Voltage and Supply Voltage
(140MHz)
Output Third Order Intercept
(OIP3EQUIV) vs Frequency and
Supply Voltage
Output 1dB Compression
(Equivalent) vs Frequency, VCM
and Supply Voltage
50
45
15.0
45
OIP3EQUIV (dBm)
OIP3 VCC = 3.6V
40
OIP3 VCC = 3.3V
35
V+ = 3.3V, 3.6V
30 VCM = 1.25V
RLOAD = 400Ω
VOUT = 2VP-P DIFFERENTIAL (COMPOSITE)
$f = 1MHz
25
0 50 100 150 200 250 300 350 400 450 500
FREQUENCY (MHz)
6416 G13
OIP3EQUIV V+ = 3.6V
40
35
OIP3EQUIV V+ = 3.3V
+
30 V = 3.3V, 3.6V
RLOAD = 400Ω
VOUT = 2VP-P DIFFERENTIAL (COMPOSITE)
$f = 1MHz
25
1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45
VCM (V)
6416 G14
P1dB COMPRESSION (EQUIVALENT) (dBm)
50
OIP3EQUIV (dB)
IM3 (dBc)
–70
IM3 (dBc)
HD2, HD3 (dBc)
HD3
14.5
V+ = 3.3V
V+ = 3.6V
14.0
13.5
VCM = 1.25V
13.0
12.5
12.0
VCM = 1.05V
11.5
11.0
V+ = 3.3V, 3.6V
10.5 RLOAD = 400Ω
VOUT = 2VP-P DIFFERENTIAL
10.0
0
50 100 150 200 250 300 350 400
FREQUENCY (MHz)
6416 G15
6416f
8
LTC6416
TYPICAL PERFORMANCE CHARACTERISTICS
Noise Figure and Input Referred
Noise Voltage vs Frequency
50
SUPPLY CURRENT (mA)
40
35
30
25
20
15
10
5
0
0.5
1.0 1.5 2.0 2.5 3.0
SUPPLY VOLTAGE (V)
3.5
4.0
12
70
10
8
8
6
6
4
4
eN
10k
Positive Overdrive Recovery
(VCLHI Pin)
IN+
50
40
30
2
100k
1M
10M
FREQUENCY (Hz)
100M
1G
10
0
0.1
0
10
1
100
1000
FREQUENCY (MHz)
6416 G17
6416 G29
Negative Overdrive Recovery
(VCLLO Pin)
Small Signal Transient Response,
Rising Edge
6416 G16
200mV/DIV
60
20
2
1k
V+ = 3.6V
80
12
NF
10
0
90
14
NOISE FIGURE (dB)
INPUT REFERRED NOISE VOLTAGE (nV√Hz)
45
0
PSRR vs Frequency
14
PSRR (dB)
Supply Current vs Supply Voltage
200mV/DIV
10mV/DIV
OUT+
OUT+
IN+
20ns/DIV
6416 G18
6416 G19
20ns/DIV
6416 G30
500ps/DIV
LTC6416 Driving LTC2208 16-Bit
ADC, 64K Point FFT, fIN = 30MHz,
–1dBFS, PGA = 0
500ps/DIV
6416 G31
AMPLITUDE (dBFS)
10mV/DIV
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
V+ = 3.6V
HD2 = –104.9dBc
HD3 = –86.1dBc
SFDR = 86.05dB
SNR = 76.5dB
SEE FIGURE 5/
TABLE 1
1:1 BALUN
3
2
0
10
20
30
40
FREQUENCY (MHz)
LTC6416 Driving LTC2208 16-Bit
ADC, 64K Point FFT, fIN = 30MHz,
–1dBFS, PGA = 1
AMPLITUDE (dBFS)
Small Signal Transient Response,
Falling Edge
50
60
6416 G20
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
V+ = 3.6V
HD2 = –101.9dBc
HD3 = –96.2dBc
SFDR = 96.2dBc
SNR = 74.2dB
SEE FIGURE 5/
TABLE 1
1:1 BALUN
3
2
0
10
20
30
40
FREQUENCY (MHz)
50
60
6416 G21
6416f
9
LTC6416
TYPICAL PERFORMANCE CHARACTERISTICS
V+ = 3.6V
HD2 = –95dBc
HD3 = –86dBc
SFDR = 86dBc
SNR = 74.6dBFS
SEE FIGURE 5/TABLE 1
1:1 BALUN
3
2
0
20
30
40
FREQUENCY (MHz)
10
50
60
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
V+ = 3.6V
HD2 = –99dBc
HD3 = –91dBc
SFDR = 91dBc
SNR = 73dBFS
SEE FIGURE 5/TABLE 1
1:1 BALUN
3
2
0
10
20
30
40
FREQUENCY (MHz)
50
6416 G22
0
10
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
3
20
30
40
FREQUENCY (MHz)
V+ = 3.6V
HD2 = –85.6dBc
HD3 = –95.5dBc
SFDR = 85.6dBc
SNR = 72.6dBFS
SEE FIGURE 5/TABLE 1
1:1 BALUN
2
3
0
10
50
60
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
V+ = 3.6V
IM3 = 86dBc
SEE FIGURE 5/
TABLE 1
1:1 BALUN
0
10
20
30
40
FREQUENCY (MHz)
50
20
30
40
FREQUENCY (MHz)
50
60
AMPLITUDE (dBFS)
6416 G27
60
6416 G26
AMPLITUDE (dBFS)
10
60
LTC6416 Driving LTC2208 16-Bit ADC,
64K Point FFT, fIN = 139.5MHz and
140.5MHz, –7dBFS/Tone, PGA = 0
V+ = 3.6V
IM3 = 81.7dBc
SEE FIGURE 5/TABLE 1
1:1 BALUN
0
50
6416 G24
6416 G25
LTC6416 Driving LTC2208 16-Bit
ADC, 64K Point FFT, fIN = 70MHz
and 71MHz, –7dBFS/Tone, PGA = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
30
40
FREQUENCY (MHz)
20
5
LTC6416 Driving LTC2208 16-Bit
ADC, 64K Point FFT, fIN = 30MHz
and 31MHz, –7dBFS/Tone, PGA = 0
V+ = 3.6V
HD2 = –91.8dBc
HD3 = –93.6dBc
SFDR = 91.8dBc
SNR = 70.9dBFS
SEE FIGURE 5/TABLE 1
1:1 BALUN
2
60
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
6416 G23
LTC6416 Driving LTC2208
16-Bit ADC, 64K Point FFT,
fIN = 140MHz, –1dBFS, PGA = 1
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
LTC6416 Driving LTC2208
16-Bit ADC, 64K Point FFT,
fIN = 140MHz, –1dBFS, PGA = 0
AMPLITUDE (dBFS)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
LTC6416 Driving LTC2208 16-Bit
ADC, 64K Point FFT, fIN = 70MHz,
–1dBFS, PGA = 1
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
LTC6416 Driving LTC2208 16-Bit
ADC, 64K Point FFT, fIN = 70MHz,
–1dBFS, PGA = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
V+ = 3.6V
IM3 = 81.7dBc
SEE FIGURE 5/TABLE 1
1:1 BALUN
0
10
20
30
40
FREQUENCY (MHz)
50
60
6416 G28
6416f
10
LTC6416
PIN FUNCTIONS
VCM (Pin 1): This pin sets the output common mode voltage
seen at OUT+ and OUT– by driving IN+ and IN– through an
internal buffer with a high output resistance of 6k. The VCM
pin has a Thevenin equivalent resistance of approximately
3.8k and can be overdriven by an external voltage. If no
voltage is applied to VCM, it will float to a default voltage
of approximately 1.25V on a 3.3V supply or 1.36V on
a 3.6V supply. The VCM pin should be bypassed with a
high-quality ceramic bypass capacitor of at least 0.1μF.
CLHI (Pin 2): High Side Clamp Voltage. The voltage applied
to the CLHI pin defines the upper voltage limit of the OUT+
and OUT– pins. This voltage should be set at least 300mV
above the upper voltage range of the driven ADC. On a 3.3V
supply, the CLHI pin will float to a 2.23V default voltage.
On a 3.6V supply, the CLHI pin will float to a 2.45V default
voltage. CLHI has a Thevenin equivalent of approximately
4.1kΩ and can be overdriven by an external voltage. The
CLHI pin should be bypassed with a high-quality ceramic
bypass capacitor of at least 0.1μF.
IN+,IN– (Pins 3, 4): Non-inverting and inverting input pins
of the buffer, respectively. These pins are high impedance,
approximately 6kΩ. If AC-coupled, these pins will self bias
to the voltage present at the VCM pin.
CLLO (Pin 5): Low Side Clamp Voltage. The voltage applied to the CLLO pin defines the lower voltage limit of
the OUT+ and OUT– pins. This voltage should be set at
least 300mV below the lower voltage range of the driven
ADC. On a 3.3V supply, the CLLO pin will float to a 0.25V
default voltage. On a 3.6V supply, the CLLO pin will float to
a 0.265V default voltage. CLLO has a Thevenin equivalent
resistance of approximately 2.3k and can be overdriven by
an external voltage. The CLLO pin should be bypassed with
a high quality ceramic bypass capacitor of at least 0.1μF.
GND (Pins 6, 9, 11): Negative power supply, normally
tied to ground. Both pins and the exposed paddle must
be tied to the same voltage. GND may be tied to a voltage
other than ground as long as the voltage between V+ and
GND is 2.7V to 4V. If the GND pins are not tied to ground,
bypass them with 680pF and 0.1μF capacitors as close to
the package as possible.
OUT–, OUT+ (Pins 7, 8): Outputs. The LTC6416 outputs
are low impedance. Each output has an output impedance
of approximately 9Ω at DC.
V+ (Pin 10): Positive Power Supply. Typically 3.3V to 3.6V.
Split supplies are possible as long as the voltage between
V+ and GND is 2.7V to 4V. Bypass capacitors of 680pF
and 0.1μF as close to the part as possible should be used
between the supplies.
Exposed Pad (Pin 11): Ground. The exposed pad must
be soldered to the printed circuit board ground plane for
good heat transfer. If GND is a voltage other than ground,
the Exposed Pad must be connected to a plane with the
same potential as the GND pins – Not to the system
ground plane.
DC TEST CIRCUIT SCHEMATIC
V+
10
V+
VCM
VINDIFF
= IN+ – IN–
VINCM =
IN+ + IN–
2
CLHI
IN+
IN–
CLLO
1
VCM
8
2
CLHI
OUT+
3 + LTC6416
IN
–
OUT
4 –
IN
7
5
CLLO
11
9
6
OUT
CLOAD
–
RLOAD
6416 DC
OUT+
VOUTDIFF = OUT+ – OUT–
+
–
VOUTCM = OUT + OUT
2
6416f
11
LTC6416
BLOCK DIAGRAM
LTC6416 Simplified Schematic
V+
1
VCM
R5
13.5k
I1
R3
6k
I11
x1
2
3
Q2
CLHI
OUT+
Q4
Q3
IN+
4
5
8
R2
9Ω
Q1
R1
6k
IN–
10
I13
Q12
R11
6k
7
R12
9Ω
Q11
CLLO
OUT–
Q14
Q13
Q5
R6
2.5k
R4
13k
I2
I12
GND (6, 9)
6416 BD
6416f
12
LTC6416
APPLICATIONS INFORMATION
Circuit Operation
The LTC6416 is a low noise and low distortion fully differential unity-gain ADC driver with operation from DC to
2GHz (–3dB bandwidth), a differential input impedance of
12kΩ, and a differential output impedance of 18Ω. The
LTC6416 is composed of a fully differential buffer with
output common mode voltage control circuitry and high
speed voltage-limiting clamps at the output. Small output
resistors of 9Ω improve the circuit stability over various
load conditions. They also simplify possible external filtering options, which are often desirable when the load is an
ADC. Lowpass or bandpass filters are easily implemented
with just a few external components. The LTC6416 is very
flexible in terms of I/O coupling. It can be AC- or DCcoupled at the inputs, the outputs or both. When using
the LTC6416 with DC-coupled inputs, best performance is
obtained with an input common mode voltage between 1V
and 1.5V. For AC-coupled operation, the LTC6416 will take
the voltage applied to the VCM pin and use it to bias the
inputs so that the output common mode voltage equals
VCM, thus no external circuitry is needed. The VCM pin
has been designed to directly interface with the VCM pin
found on Linear Technology’s 16-, 14- and 12-bit high
speed ADC families.
Input Impedance and Matching
The LTC6416 has a high differential input impedance of
12kΩ. The differential inputs may need to be terminated
to a lower value impedance, e.g. 50Ω, in order to provide
an impedance match for the source. Figure 1 shows input
matching using a 1:1 balun, while Figure 2 shows matching using a 1:4 balun. These circuits provide a wideband
impedance match. The balun and matching resistors must
be placed close to the input pins in order to minimize the
rejection due to input mismatch. In Figure 1, the capacitor center-tapping the two 24.9Ω resistors improves high
frequency common mode rejection. As an alternative to
this wideband approach, a narrowband impedance match
can be used at the inputs of the LTC6416 for frequency
selection and/or noise reduction.
The noise performance of the LTC6416 also depends upon
the source impedance and termination. For example, the
input 1:4 balun in Figure 2 improves SNR by adding 6dB
of voltage gain at the inputs. A trade-off between gain
and noise is obvious when constant noise figure circle
and constant gain circle are plotted within the same input
Smith Chart. This technique can be used to determine
the optimal source impedance for a given gain and noise
requirement.
Output Match and Filter
The LTC6416 provides a source resistance of 9Ω at each
output. For testing purposes, Figure 3 and Figure 4 show
the LTC6416 driving a differential 400Ω load impedance
using a 1:1 or 1:4 balun, respectively.
The LTC6416 can drive an ADC directly without external
output impedance matching, but improved performance
can usually be obtained with the addition of a few external
components. Figure 5 shows a typical topology used for
driving the LTC2208 16-bit ADC.
0.1μF
3
8
•
•
OUT+
24.9Ω 0.1μF
1:1
50Ω
IN+
LTC6416
VIN
+
–
0.1μF
24.9Ω
4
IN–
OUT–
7
6416 F01
Figure 1. Input Termination for Differential 50Ω Input Impedance Using a 1:1 Balun
6416f
13
LTC6416
APPLICATIONS INFORMATION
0.1μF
3
1:4
8
OUT+
100Ω
0.1μF
•
•
50Ω
IN+
LTC6416
VIN
+
–
100Ω
0.1μF
4
IN–
7
OUT–
6416 F02
Figure 2. Input Termination for Differential 50Ω Input Impedance Using a 1:4 Balun
3
IN+
OUT+
8
0.1μF
165Ω
1:1
0.1μF
50Ω
LTC6416
IN–
7
OUT–
•
•
4
0.1μF
165Ω
6416 F03
Figure 3. Output Termination for Differential 400Ω Load Impedance Using a 1:1 Balun
3
IN+
8
OUT+
0.1μF
90.9Ω
4:1
0.1μF
50Ω
LTC6416
IN–
OUT–
7
•
•
4
0.1μF
90.9Ω
6416 F04
Figure 4. Output Termination for Differential 400Ω Load Impedance Using a 4:1 Balun
3.6V
680pF
T1
TCM4-19+
4
50Ω
6
2.2μF
CLHI
3
2
+
–
0.1μF
1
R36
100Ω
V+
IN+
VCM
IN–
GND
C39
CLLO
0.01μF
1.5pF
16
LTC2208
1pF
OUT–
GND
VCM
AIN+
OUT+
LTC6416
R15
100Ω
25Ω
3.3V
DATA
AIN–
25Ω
1.5pF
6416 F05
CLOCK
(130MHz)
Figure 5. DC1257B Simplified Schematic with Suggested Output Termination for Driving an LTC2208 16-Bit ADC at 140MHz
6416f
14
LTC6416
APPLICATIONS INFORMATION
As seen in Table 1, suggested component values for the
filter will change for differing IF frequencies.
Table 1.
INPUT
FREQUENCY
LTC6416 OUTPUT
RESISTORS
FILTERING
CAPACITORS
30MHz
50Ω
5.6pF/6.8pF/5.6pF
70MHz
25Ω
5.6pF/6.8pF/5.6pF
140MHz
25Ω
1.5pF/1pF/1.5pF
250MHz
5Ω
-/-/-
Output Common Mode Adjustment
The output common mode voltage is set by the VCM pin.
Because the input common mode voltage is approximately
the same as the output common mode voltage, both are
approximately equal to VCM. The VCM pin has a Thevenin
equivalent resistance of 3.8k and can be overdriven by an
external voltage. The VCM pin floats to a default voltage of
1.25V on a 3.3V supply and 1.36V on a 3.6V supply. The
output common mode voltage is capable of tracking VCM
in a range from 0.34V to 2.16V on a 3.3V supply. The VCM
pin can be floated, but it should always be bypassed close
to the LTC6416 with a 0.1μF bypass capacitor to ground.
When interfacing with A/D converters such as the LTC22xx
families, the VCM pin can be connected to the VCM output
pin of the ADC, as shown in Figure 5.
CLLO and CLHI Pins
The CLLO and CLHI pins are used to set the clamping
voltage for high speed internal circuitry. This circuitry
limits the single-ended minimum and maximum voltage
excursion seen at each of the outputs. This feature is
extremely important in applications with input signals
having very large peak-to-average ratios such as cellular
basestation receivers. If a very large peak signal arrives
at the LTC6416, the voltages applied to the CLLO and
CLHI pins will determine the minimum and maximum
output swing respectively. Once the input signal returns
to the normal operating range, the LTC6416 returns to
linear operation within 5ns. Both CLLO and CLHI are high
impedance inputs. CLLO has an input impedance of 2.3k,
while CLHI has an input impedance of 4.1k. On a 3.3V
supply, CLLO self-biases to 0.25V while CLHI self-biases
to 2.23V. On a 3.6V supply, CLLO self-biases to 0.265V
while CLHI self-biases to 2.45V. Both CLLO and CLHI pins
should be bypassed with a 0.1μF capacitor as close to the
LTC6416 as possible.
Interfacing the LTC6416 to A/D Converters
The LTC6416 has been specifically designed to interface
directly with high speed A/D converters. It is possible
to drive the ADC directly from the LTC6416. In practice,
however, better performance may be obtained by adding
a few external components at the output of the LTC6416.
Figure 5 shows the LTC6416 being driven by a 1:8 transformer which provides 9dB of voltage gain while also
performing a single-ended to differential conversion. The
differential outputs of the LTC6416 are lowpass filtered,
then drive the differential inputs of the LTC2208 ADC. In
many applications, an anti-alias filter like this is desirable to limit the wideband noise of the amplifier. This is
especially true in high performance 16-bit designs. The
minimum recommended network between the LTC6416
and the ADC is simply two 5Ω series resistors, which are
used to help eliminate resonances associated with the
stray capacitance of PCB traces and the stray inductance
of the internal bond wires at the ADC input, and the driver
output pins.
Single-Ended Signals
The LTC6416 has not been designed to convert singleended signals to differential signals. A single-ended input
signal can be converted to a differential signal via a balun
connected to the inputs of the LTC6416.
Power Supply Considerations
For best linearity, the LTC6416 should have a positive
supply of V+ = 3.6V. The LTC6416 has an internal edge-triggered supply voltage clamp. The timing mechanism of the
clamp enables the LTC6416 to withstand ESD events. This
internal clamp is also activated by voltage overshoot and
rapid slew rate on the positive supply V+ pin. The LTC6416
should not be hot-plugged into a powered socket. Bypass
capacitors of 680pF and 0.1μF should be placed to the V+
pin, as close as possible to the LTC6416.
6416f
15
LTC6416
APPLICATIONS INFORMATION
Test Circuits
Due to the fully differential design of the LTC6416 and its
usefulness in applications both with and without ADCs,
two test circuits are used to generate the information in
this data sheet. Test circuit A is Demo Board DC1287A,
a two-port demonstration circuit for the LTC6416. The
board layout and the schematic are shown in Figures 6
and 7. This circuit includes input and output 1:1 baluns
for single-ended-to-differential conversion, allowing
direct analysis using a 2-port network analyzer. In this
circuit implementation, there are series resistors at the
output to present the LTC6416 with a 382Ω differential
load, thereby optimizing distortion performance. Including
the 1:1 input and output baluns, the –3dB bandwidth is
approximately 2GHz.
Test circuit B is Demo Circuit DC1257B. It consists of an
LTC6416 driving an LTC2208 ADC. It is intended for use in
conjunction with demo circuit DC890B (computer interface
board) and proprietary Linear Technology evaluation software to evaluate the performance of both parts together.
Both the DC1257B board layout and the schematic can
be seen in Figures 8 and 9.
Figure 6. Demo Board DC1287A Layout
VCM
C1
0.1μF
C2
680pF
C3
0.1μF
V+
2.7V TO 4V
GND
CLHI
T1
MABA-007190-000000
J1
IN+
1
•
•
C7
0.1μF
C8
OPT 5
2
R2
24.9Ω
C4
0.1μF
1
2
R4
0Ω
3
V+
VCM
CLHI
GND
10
LTC6416 OUT+ 8
7
OUT–
IN–
5
6
CLLO
GND
GND
IN+
T2
MABA-007190-000000
9
R1
165Ω
C6
4 OPT
3
2
J3
OUT+
C5
0.1μF
4
J2
IN–
C10
OPT
3
C12
0.1μF
R5
0Ω
C15
0.1μF
CLLO
11
R3
165Ω
1
C14
0.1μF
C13
0.1μF
•
R6
24.9Ω
•
4
5
C11
0.1μF
J4
OUT–
C9
OPT
GND
6416 TA04
Figure 7. Demo Board DC1287A Schematic (Test Circuit A)
6416f
16
LTC6416
APPLICATIONS INFORMATION
Figure 8. Demo Board DC1257B Layout
6416f
17
J3
J2
C23
OPT
C19
0.1μF
C25
0.1μF
C21
OPT
5
4
•
T1
E2
E1
•
CLLO
E3
R18
OPT
R17
OPT
VCC
3
2
1
R12
OPT
R11
OPT
VCC
TCM4−19+
CLHI
VCM
C26
0.1μF
C18
0.1μF
R10
OPT
R8
OPT
VCC
CLK
C27
0.1μF
R14B
100Ω
R14A
100Ω
C13
0.1μF
J4
5
4
3
2
1
C28
0.1μF
CLLO
IN−
IN+
CLHI
VCM
GND
OUT−
OUT+
6
7
8
9
10
VCC
C29
0.1μF
5
4
•
•
1
2
3
T2
MABA-007159-000000
11
GND
V+
GND
LTC6416CDDB
R9
1k
C16
2.2μF
C9
0.1μF
VDD
C10
0.1μF
GND
VS
3.6V TO 20V
R21
100Ω
C24
1.5pF
C22
1pF
C20
1.5pF
C8
0.1μF
E7
VDD
E6
E4
VCM
2
1
2
OFF
VDD
VDD
GND
ENC−
GND
ENC+
GND
AIN−
IN
GND
A +
VDD
VDD
GND
VCM
GND
SENSE
VS
ON
OFF
C32
10μF
25V
2
JP3
SHDN ADC
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SHDN
EN
LOW
R2
10Ω
VDD
VDD
R3
10Ω
1
2
58
IN
2
GND
OUT
LT1963AEST-3.3
JP4
DITH
LTC2208CUP
3
54
C33
10μF
6.3V
49
50
DB10
DB11
DB12
DB13
DB14
DB15
OFB
CLKCOUTB
CLKCOUTA
DA0
DA1
DA2
DA3
DA4
DA5
DA6
OVP
L3
BLM18PG221SN1D
L2
BLM18PG221SN1D
L1(opt.)
BLM18PG221SN1D
OVP
VDD
VCC
OVP
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
C12
0.1μF
Figure 9. Demo Board DC1257B Schematic (Test Circuit B)
C30
0.1μF
R26
51.1Ω
R19
51.1Ω
R15
24.9Ω
R13
24.9Ω
C17
680pF
C14
0.1μF
EXTREF
R4
1k
1
3
HI
R5
JP2
RAND
64
PGA
63
RAND
17
VDD
18
1
JP1
PGA
R6
GND
62
MODE
60
SHDN
OPT
61
19
3
1
3
OPT
R7, 100Ω
59
LVDS
DITH
20
OFA
57
DB3
24
DB0
21
55
26
DA15
22
DA14
DB2
23
DA13
56
DA12
DB4
25
53
DA11
DB5
52
DA10
DB6
27
DA9
DB7
27
DB1
3
GND
51
DA8
DB8
29
DA7
DB9
30
OGND
OGND
31
OVDD
OVDD
32
18
65
VDD
E5
C11
0.1μF
OPT
R27
2k
4
3
2
1
A0
A1
A2
VSS
VCC
WP
SCL
SDA
24LC025
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
5
6
7
8
R29
OPT
R24
4.99k
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
J1
EDGE-CON
(GOLD FINGER)
C31
0.1μF
R28
4.99k
R25
4.99k
R16
5.1k
OVP
6416 F09
LTC6416
APPLICATIONS INFORMATION
6416f
LTC6416
PACKAGE DESCRIPTION
DDB Package
10-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1722 Rev Ø)
0.64 ±0.05
(2 SIDES)
3.00 ±0.10
(2 SIDES)
R = 0.05
TYP
R = 0.115
TYP
6
0.40 ± 0.10
10
0.70 ±0.05
2.55 ±0.05
1.15 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
2.39 ±0.05
(2 SIDES)
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
2.00 ±0.10
(2 SIDES)
0.75 ±0.05
0.64 ± 0.05
(2 SIDES)
5
0.25 ± 0.05
0 – 0.05
PIN 1
R = 0.20 OR
0.25 × 45°
CHAMFER
1
(DDB10) DFN 0905 REV Ø
0.50 BSC
2.39 ±0.05
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6416f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC6416
TYPICAL APPLICATION
DC1257B Simplified Schematic with Suggested Output Termination for Driving an LTC2208 16-Bit ADC at 140MHz
3.6V
680pF
T1
TCM4-19+
4
50Ω
0.1μF
3
R36
100Ω
2
+
–
6
2.2μF
CLHI
V+
IN+
VCM
25Ω
1
IN
–
1.5pF
OUT–
GND
GND
C39
CLLO
0.01μF
VCM
AIN+
OUT+
LTC6416
R15
100Ω
3.3V
16
LTC2208
1pF
DATA
AIN–
25Ω
1.5pF
6416 F05
CLOCK
(130MHz)
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
Fixed Gain IF Amplifiers/ADC Drivers
LT1993-2/LT1993-4/
LT1993-10
800MHz Differential Amplifier/ADC Drivers
–72dBc IM3 at 70MHz 2VP-P Composite, AV = 2V/V, 4V/V, 10V/V
LTC6400-8/LTC6400-14/ 1.8GHz Low Noise, Low Distortion Differential
LTC6400-20/LTC6400-26 ADC Drivers
–71dBc IM3 at 240MHz 2VP-P Composite, IS = 90mA, AV = 8dB,
14dB, 20dB, 26dB
LTC6401-8/LTC6401-14/ 1.3GHz Low Noise, Low Distortion Differential
LTC6401-20/LTC6401-26 ADC Drivers
–74dBc IM3 at 140MHz 2VP-P Composite, IS = 50mA, AV = 8dB,
14dB, 20dB, 26dB
LT6402-6/LT6402-12/
LT6402-20
300MHz Differential Amplifier/ADC Drivers
–71dBc IM3 at 20MHz 2VP-P Composite, AV = 6dB, 12dB, 20dB
LTC6420-XX
Dual 1.8GHz Low Noise, Low Distortion Differential
ADC Drivers
Dual Version of the LTC6400-XX, AV = 8dB, 14dB, 20dB, 26dB
LTC6421-XX
Dual 1.3GHz Low Noise, Low Distortion Differential
ADC Drivers
Dual Version of the LTC6401-XX, AV = 8dB, 14dB, 20dB, 26dB
IF Amplifiers/ADC Drivers with Digitally Controlled Gain
LT5514
Ultra-Low Distortion IF Amplifier/ADC Driver with
Digitally Controlled Gain
OIP3 = 47dBm at 100MHz, Gain Range 10.5dB to 33dB 1.5dB steps
LT5524
Low Distortion IF Amplifier/ADC Driver with Digitally
Controlled Gain
OIP3 = 40dBm at 100MHz, Gain Range 4.5dB to 37dB 1.5dB steps
LT5554
High Dynamic Range 7-bit Digitally Controlled IF
VGA/ADC Driver
OIP3 = 46dBm at 200MHz, Gain Range 1.725 to 17.6dB 0.125dB
steps
Baseband Differential Amplifiers
LT1994
Low Noise, Low Distortion Differential Amplifier/
ADC Driver
16-Bit SNR and SFDR at 1MHz, Rail-to-Rail Outputs
LTC6403-1
Low Noise Rail-to-Rail Output Differential Amplifier/
ADC Driver
16-Bit SNR and SFDR at 3MHz, Rail-to-Rail Outputs, eN = 2.8nV/√Hz
LTC6404-1/LTC6404-2
Low Noise Rail-to-Rail Output Differential Amplifier/
ADC Driver
16-Bit SNR and SFDR at 10MHz, Rail-to-Rail Outputs, eN = 1.5nV/
√Hz, LTC6404-1 is unity-gain stable, LTC6404-2 is Gain-of-2 Stable
LTC6406
3GHz Rail-to-Rail Input Differential Amplifier/
ADC Driver
–65dBc IM3 at 50MHz 2VP-P Composite, Rail-to-Rail Inputs,
eN = 1.6nV/√Hz, 18mA
LT6411
Low Power Differential ADC Driver/Dual Selectable
Gain Amplifier
–83dBc IM3 at 70MHz 2VP-P Composite, AV = 1, –1 or 2, 16mA,
Excellent for Single-Ended to Differential Conversion
6416f
20 Linear Technology Corporation
LT 1108 • PRINTED IN USA
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