W530 Frequency Multiplying, Peak Reducing EMI Solution Features • Cypress PREMIS™ family offering • Generates an EMI optimized clocking signal at the output • Selectable output frequency range • Single 1.25%, 2.5%, 5% or 10% down or center spread output • Integrated loop filter components • Operates with a 3.3 or 5V supply • Low power CMOS design • Available in 20-pin SSOP (Small Shrunk Outline Package) Simplified Block Diagram Key Specifications Supply Voltages: ......................................... VDD = 3.3V±0.3V or VDD = 5V±10% Frequency range: ............................13 MHz ≤ Fin ≤ 120 MHz Cycle to Cycle Jitter: .........................................250 ps (max) Output duty cycle: ................................. 40/60% (worst case) Pin Configuration [1] 3.3V or 5.0V SSOP X1 XTAL Input X2 W530 3.3V or 5.0V Oscillator or Reference Input REFOUT VDD GND IR1* IR2* 15 SSOUT 8 14 13 MW1* GND 9 12 VDD 10 11 MW2^ 1 2 3 4 5 OR1^ NC GND 6 OR2* SSON#^ W530 Spread Spectrum O u tp u t (EMI suppressed) 20 19 18 17 16 X1 X2 AVDD MW0^ STOP^ 7 X1 W530 Spread Spectrum O utpu t (EMI suppressed) Note: 1. Pins marked with ^ are internal pull-down resistors with weak 250 Ω. Pins marked with * are internal pull-up resistors with weak 250 Ω. PREMIS is a trademark of Cypress Semiconductor. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 November 22, 2000 W530 Pin Definitions Pin No. Pin Type SSOUT 15 I Spread Spectrum Control. REFOUT 20 O Non-Modulated Output: This pin provides a copy of the reference frequency. This output will not have the Spread Spectrum feature enabled regardless of the state of logic input SSON#. X1 1 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It may either be connected to an external crystal, or to an external reference clock. X2 2 I Crystal Connection: Input connection for an external crystal. If using an external reference, this pin must be left unconnected. SSON# 10 I Spread Spectrum Control (Active LOW): Asserting this signal (active LOW) turns the internal modulation waveform on. This pin has an internal pull-down resistor. MW0:2 4, 14, 11 I Modulation Width Selection: When the Spread Spectrum feature is turned on, these pins are used to select the amount of variation and peak EMI reduction that is desired on the output signal. MW0: Down, MW1: Up, MW2: Down. (See Table 2.) IR1:2 17, 16 I Reference Frequency Selection: Logic level provided at this input indicates to the internal logic what range the reference frequency is in and determines the factor by which the device multiplies the input frequency. Refer to Table 1. These pins have internal pull-up resistors. OR1:2 6, 9 I Output Frequency Selection Bits: These pins select the frequency operation for the output. Refer to Table 1. OR1: DOWN, OR2: UP. NC 7 NC STOP 5 I Output Disable: When pulled HIGH, stops all outputs at logic low voltage level. This pin has an internal pull-down. VDD 12, 19 P Power Connection: Connected to 3.3V or 5V power supply. AVDD 3 P Analog Power Connection: Connected to 3.3V or 5V power supply. GND 8, 13, 18 G Ground Connection: Connect all ground pins to the common ground plane. Pin Name Pin Description No Connection: Leave this pin unconnected. 2 W530 Table 1. Frequency Configuration Table Range of Fin Frequency Multiplier Settings Min. Max. OR2 OR1 14 30 0 1 14 30 1 0 14 30 1 25 60 0 25 60 25 60 50 50 50 Output / Input Range of Fout Required R Settings Modulation & Power Down Settings MW2 Min. Max. IR2 IR1 1 14 30 0 1 Table 2 2 28 60 0 1 Table 2 1 4 56 120 0 1 Table 2 1 0.5 13 30 1 0 Table 2 1 0 1 25 60 1 0 Table 2 1 1 2 50 120 1 0 Table 2 120 0 1 0.25 13 30 1 1 Table 2 120 1 0 0.5 25 60 1 1 Table 2 120 Reserved MW1 1 1 1 50 120 1 1 0 0 N/A N/A N/A As Set As Set 1 Table 2 0 Power Down Hi-Z 0 0 N/A N/A N/A As Set As Set 1 1 Power Down 0 0 0 N/A N/A N/A As Set As Set 0 0 Power Down 1 0 0 N/A N/A N/A As Set As Set 0 1 Table 2. Modulation Percentage Selection Table Bandwith Limit Frequencies as a % Value of Fout EMI Reduction Modulation Setting MW2 MW0 = 0 MW1 Low MW0 = 1 High Low High Minimum EMI Control 0 0 98.75% 100% 99.375% 100.625% Suggested Setting 0 1 97.5% 100% 98.75% 101.25% Alternate Setting 1 0 95.0% 100% 97.5% 102.5% Maximum EMI reduction 1 1 90.0% 100% 95% 105% times the reference frequency. (Note: For the W530 the output frequency is nominally equal to the input frequency.) The unique feature of the Spread Spectrum Frequency Timing Generator is that a modulating waveform is superimposed at the input to the VCO. This causes the VCO output to be slowly swept across a predetermined frequency band. Overview The W530 product is one of a series of devices in the Cypress PREMIS family. The PREMIS family incorporates the latest advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a low frequency carrier, peak EMI is greatly reduced. Use of this technology allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. Because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has little impact on system performance. In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Simplified Block Diagram shows a simple implementation. Frequency Selection With SSFTG In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating waveform are fixed for a given frequency, the modulation percentage may be varied. Functional Description Using frequency select bits (FS2:1 pins), the frequency range can be set (see Table 2). Spreading percentage is set with pins MW as shown in Table 2. The W530 uses a Phase Locked Loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. The input reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. For these reasons, spreading percentage options are provided. 3 W530 VDD Clock Input Reference Input Freq. Divider Q Phase Detector Σ Charge Pump VCO Post Dividers SSOUT (EMI suppressed) Modulating Waveform Feedback Divider P PLL GND Figure 1. Functional Block Diagram Spread Spectrum Frequency Timing Generator Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Table 2. The output clock is modulated with a waveform depicted in Figure 3. This waveform, as discussed in “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions” by Bush, Fessler, and Hardin, produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is described in Table 2. Figure 3 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. As shown in Table 2, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is: dB = 6.5 + 9*log10(P) + 9*log10(F) 4 W530 EMI Reduction Typical Clock Amplitude (dB) Amplitude (dB) S SFTG Spread Spectrum Enabled NonSpread Spectrum Frequency Span (MHz) Down Spread Frequency Span (MHz) Center Spread Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation MIN. Figure 3. Typical Modulation Profile 5 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% FREQUENCY MAX. W530 Absolute Maximum Ratings above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions . Parameter Description Rating Unit V VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 –65 to +150 °C 0 to +70 °C –55 to +125 °C 0.5 W TSTG Storage Temperature TA Operating Temperature TB Ambient Temperature under Bias PD Power Dissipation DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 3.3V ± 0.3V Parameter Description IDD Supply Current tON Power Up Time VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage Test Condition Min. Typ. Max. Unit 18 32 mA 5 ms First locked clock cycle after Power Good 0.8 2.4 V V 0.4 2.4 V V IIL Input Low Current Note 2 –100 µA IIH Input High Current Note 2 10 µA IOL Output Low Current @ 0.4V, VDD = 3.3V 15 mA IOH Output High Current @ 2.4V, VDD = 3.3V 15 mA CI Input Capacitance RP Input Pull-Up Resistor 250 kΩ ZOUT Clock Output Impedance 25 Ω 7 Note: 2. Inputs OR1:2 and IR1:2 have a pull-up resistor, Input SSON# has a pull-down resistor. 6 pF W530 DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 5V ±10% Parameter Description IDD Supply Current tON Power Up Time Test Condition Min. Typ. Max. Unit 30 50 mA 5 ms 0.15VDD V First locked clock cycle after Power Good VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage IIL Input Low Current Note 2 –100 µA IIH Input High Current Note 2 10 µA IOL Output Low Current IOH Output High Current @ 0.4V, VDD = 5V @ 2.4V, VDD = 5V CI Input Capacitance RP Input Pull-Up Resistor 250 kΩ ZOUT Clock Output Impedance 25 Ω 0.7VDD V 0.4 2.4 V V 24 mA 24 mA 7 pF AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±0.3V or 5V±10% Symbol Parameter Test Condition Min. Typ. Max. Unit fIN Input Frequency Input Clock 14 120 MHz fOUT Output Frequency Spread Off 13 120 MHz tR Output Rise Time 15-pF load, 0.8V–2.4V 2 5 ns tF Output Fall Time 15-pF load, 2.4 –0.8V 2 5 ns tOD Output Duty Cycle 15-pF load 40 60 % tID Input Duty Cycle 40 60 % tJCYC Jitter, Cycle-to-Cycle 300 ps 250 Ordering Information Ordering Code W530 Package Name H Package Type 20-Pin Plastic SSOP (209-mil) Document #: 38-00913-*A 7 W530 Package Diagram 20-Pin Small Shrink Outline Package (SSOP, 209-mil) © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.