RENESAS M66335FP

M66335FP
Facsimile Image Data Processor
REJ03F0276-0200
Rev.2.00
Jun 16, 2008
Description
The M66335 is a facsimile image processing controller to turn into binary signals analog signals which have been
output through photo-electric conversion by the image sensor.
The image processing functions includes peak value detection, uniformity correction, resolution change, MTF
compensation, γ correction, detection of background/character levels, error diffusion, separation of image zones, and
designation of regions.
This controller contains not only the analog processing circuit, the A/D converter of a 7-bit flash type and image
processing memory, but also the image sensor and the interface circuit to the CODEC (Coder and Decoder). Therefore,
this LSI alone is capable of image processing.
Features
• High speed scan (Max 2 ms/line, Typ 5 ms/line)
• Compatibility with up to the B4 (8 pixels/mm, 16 pixels/mm) image sensor
• Generation of control signals for the image sensor (CCD, CIS)
For CCD: SH, CK1, CK2, RS
For the contact sensor (CIS): SH, CK1, CK2
• Built-in analog processing circuit (equivalent to the M64291)
Sample and hold circuit
Gain control circuit
Black level clamping circuit
Reference internal power supply for the A/D converter
• Built-in A/D converter of a 7-bit flash type
• Built-in image processing memories
Uniformity correction memory, Line memory, Error memory, γ correction memory
• External output interface for converted binary data
Serial output (→ M66330)
DMA output
• External output interface for multivalued data
DMA transfer of data compensated for uniformity
• Various image processing functions
Uniformity correction
Resolution change from 50% to 200% (by the 1% step)
MTF compensation (2-dimensional processing, capable of correction for each character/photo)
γ correction (capable of correction for each character/photo)
Detection of background/character levels
Change to pseudo-halftone
 Error diffusion (64 tone steps through 6-bit processing)
 Organized dither (64 tone steps through the 8 × 8 matrix)
Image zone separation (2-dimensional processing)
• 5 V single power supply
Application
Facsimile, word processor and image scanner
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 1 of 58
M66335FP
Block Diagram
ADIN VWL VBL Vri+ Vri−
35
36
37
33
PTIMB
RS
CK1
CK2
SH
27
28
29
Image zone
separation
7-bit
A/D converter
22
Vcc
3 11 17 42 52 62
4
20
Analog
signal
processing
circuit
38
Image processing sequence control signal
19
26
DVcc
18 34
78
Analog
control
AIN
LEVAJ
C1
C2
BCMI
BCMV
GCAO
BCMO
AVcc
31
Resolution
change
Uniformity
correction
8
Detection of
background/
character levels
γ correction
table
MTF
compensation
Selection of
conversion to
binary processing
Image bus
interface
75
DMA
control
9
13
14
Sensor
control
Correction
data memory
Dither
matrix
Error
memory
Line
memory
Conversion
table memory
6
7
Error
diffusion
30
12
5
76
77
SYSCK
ACCK
SRDYB
SVID
SCLK
STIMB
DAKB
DRQ
INT
Organized
dither
71
RESETB
WRB
RDB
CSB
65
70
A0 to A4
74
73
72
15
MPU bus
interface
54
61
21 32
39
10 16 41 53 63 79
AGND
DGND
GND
D0 to D7
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
39
67
38
68
37
69
36
70
35
71
34
72
33
M66335FP
73
32
(Top view)
Outline: PRQP0080GB-A (80P6N-A)
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 2 of 58
NC
DGND
DVCC
VBL ADC black reference output
VWL ADC white reference output
ADIN ADC input
AVCC
Vri+ ADC white reference input
AGND
Vri−
ADC black reference input
BCMO
BCMV Control signal for
BCMI analog signal
processing
C2
C1
NC
24
23
22
21
20
19
18
17
16
15
14
13
12
NC
NC
VCC
Single-line
ACCK
cycle clock
SVID
CODEC
SCLK
interface
STIM
SRDY
Sensor
PTIM
interface
GND
VCC
RS
Sensor
CK1
interface
CK2
SH
GND
VCC
AVCC
AIN
Control
LEVAJ
signal for
analog signal AGND
processing
GCAO
NC
NC
11
25
10
26
80
9
27
79
8
28
78
7
29
77
6
30
76
5
31
75
4
74
1
System clock
40
66
3
DMA
interface
65
2
MPU
interface
NC
A0
A1
A2
A3
A4
CS
RD
WR
RESET
DAK
DRQ
INT
SYSCK
GND
NC
63
64
NC
GND
Vcc
D7
D6
D5
MPU
D4
interface
D3
D2
D1
D0
GND
VCC
TEST6
TEST5
TEST4
TEST3
TEST2 Test pin
TEST1
TEST0
TESTI
TESTO
VCC
GND
Pin Arrangement
NC: No Connection
M66335FP
Table 1 Image Processing Functions
Image Processing Functions
Reading range
Resolution
Specifications
• A4, B4
• 8 pixels/mm, 16 pixels/mm
Reading speed
• Typ: 5 ms/line; Max: 2 ms/line
Remarks
(for the horizontal scanning direction)
Uniformity correction
γ correction
MTF compensation
• White correction, black correction
• Correction range: 50%
• Logarithmic correction
• Laplacian filter circuit through 2dimensional processing
Simple conversion to binary
• Controlled through the system
clock
Correction memory is built-in
Readable from/writable in MPU
•
•
• γ correction memory is built-in
• Capable of correction for each
•
•
character/photo
Correction memory is built-in
Capable of correction for each
character/photo
• Floating slice system through the
detection circuit for
background/character levels
Pseudo-halftone
• Error diffusion: 6-bit processing (for 64
•
Image zone separation
tone steps)
Organized dither: 8 × 8 matrix (for 64
tone steps)
• Error buffer memory is built-in
• 64 W × 6 bits dither memory is
built-in
• 2-dimensional processing through
luminance difference
Image reduction
• Range of the reduction rate: 50% to
100%
(by the 1% step)
Image enlargement
• Range of the enlargement rate: 100% to
200%
(by the 1% step)
Image sensor control signal
Analog processing
• CIS image sensor (clock duty: 75%)
• CCD image sensor
• The sample/hold circuit, gain control
amplifier, black level clamping circuit,
and 7-bit A/D converter are built-in.
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 3 of 58
• Capable of outputting the average
line of a dropped line and the
subsequent line instead of both
lines
• Capable of outputting the average
line of a repeated line and the
subsequent line instead of the
repeated line
M66335FP
Pin Description
Item
Sensor
interface
CODEC
interface
DMA
interface
Clock
MPU
interface
Others
Power
supply
GND
Sensor
signal
input part
Gain
control
circuit
Pin Name
SH
Input/Output
Output
CK1
Output
CK2
RS
Output
Output
PTIM
SRDY
STIM
SCLK
SVID
DRQ
Output
Input
Output
Output
Output
Output
DAK
Input
INT
SYSCK
ACCK
RESET
Output
Input
Output
Input
CS
RD
WR
A0 to A4
Input
Input
Input
Input
Input of the system reset. The cycle counter, register, F/F, and latch are
reset.
Chip select signal for MPU to access the M66335
Control signal for MPU to read data from the M66335
Control signal for MPU to write data to the M66335
Address signal to access various registers inside the M66335
D0 to D7
VCC
GND
TESTI, 0 to 6
Input/Output
—
—
Input
8-bit two way buffer
Positive power supply pin
GND pin
Test input pin. Hold this at "L".
TESTO
AVCC
DVCC
AGND
DGND
AIN
Output
—
—
—
—
Input
Test output pin. Set this open.
Analog power supply pin (rated supply voltage: 5 V)
Digital power supply pin (rated supply voltage: 5 V)
Analog ground pin
Digital ground pin
C1, C2
LEVAJ
Input
Input
GCAO
Output
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 4 of 58
Function
Outputs the shift pulse signal to transfer electric charges from the
sensor’s photoconductor component to its transferring component for
CCD and the start signal to start the sensor reading circuit for CIS.
Outputs the clock pulse signal to sequentially transfer out signaling
electric charges from the sensor’s transferring component for CCD and
the clock pulse signal for the shift register of the sensor reading circuit for
CIS.
Reversed-phase pulses of CK1
Outputs the reset pulse to return the voltage at the floating capacitor of
the CCD sensor to the initial one.
Outputs the pulse motor control signal for the reading roller.
Transfer start ready signal for data from CODEC
Defines the data transfer section to CODEC
Clock signal to transfer image data to CODEC
Outputs image data in serial to CODEC
DMA request signal to the external DMA controller to output in parallel
image data through the MPU bus
DMA acknowledge signal from the external DMA controller in response to
the above DRQ signal
Single-line termination interrupt
System clock input pin
Single-line cycle clock
Pin to input analog signals output from CCD or CIS (Signals from CCD
are input through capacity coupling and those from CIS, with no
clamping levels, are input directly.)
Pin to control the frequency characteristic of the gain control circuit
Pin to control the DC level of output signals of the gain control circuit.
The output voltage, VGCAO, is obtained by the following equation:
VGCAO = VLEVAJ + GV × VIN,
where,
VLEVAJ: voltage at LEVAJ
VIN: input signal
GV: gain of the gain control circuit
VIN is the signal element corresponding to the signal level clamped
through the input clamping circuit for CCD • CIS3 input or to the GND
level for CIS1 • CIS2 input.
Signal output pin of the gain control circuit
M66335FP
Pin Description (cont.)
Item
Black level
clamping
circuit
A/D converter
Pin Name
BCMI
Input/Output
Input
Function
BCMV
Input
BCMO
Vri+
Output
Input
Vri–
Input
Output of the circuit to generate the A/D zero point reference voltage (1.8
V). Connected with VBL through the buffer inside the IC. To change the
A/D reference voltage range, input a DC voltage from this pin.
ADIN
Input
Signal input pin to the A/D converting circuit. Use this by connecting with
the BCMO pin for CCD or with the GCAO pin for CIS. Input signals in the
voltage range (1.8 V to 3.8 V) set through VWL and VBL.
VWL
Output
Output of the circuit generating the A/D full-scale reference voltage (3.8
V). Connected inside the IC with the A/D converter.
VBL
Output
Output of the circuit generating the A/D zero point reference voltage (1.8
V). Connected inside the IC with the A/D converter.
Signal input pin to the black clamping circuit. Use this with capacity
coupling with the GCAO pin.
Pin to set the black level clamping voltage. Sets the black level of signals
output from the BCMO pin for CCD signal processing.
Signal output pin of the black level clamping circuit
Output of the circuit to generate the A/D full-scale point reference voltage
(3.8 V). Connected with VWL through the buffer inside the IC. To change
the A/D reference voltage range, input a DC voltage from this pin.
Absolute Maximum Ratings
(Ta = –20 to +75°C, unless otherwise noted)
Item
Supply voltage
Input voltage
Output voltage
Analog supply voltage
Supply voltage
Reference voltage (white)
Reference voltage (black)
Analog input voltage
Storage temperature
Symbol
VCC
VI
VO
AVCC
DVCC
VWL
VBL
VAIN
Tstg
Ratings
–0.3 to +6.5
–0.3 to VCC + 0.3
0 to VCC
VCC – 0.3 to VCC + 0.3
VCC – 0.3 to VCC + 0.3
–0.3 to AVCC + 0.3
–0.3 to AVCC + 0.3
–0.3 to AVCC + 0.3
–55 to +150
Unit
V
V
V
V
V
V
V
V
°C
Recommended Operational Conditions
Item
Supply voltage (for the digital system component)
GND voltage
Input voltage
Analog supply voltage
Analog GND voltage
Supply voltage (for the digital system component)
Symbol
VCC
GND
VI
AVCC
AGND
DVCC
Min
4.75
—
0
4.75
—
4.75
Typ
5.0
0.0
—
5.0
0.0
5.0
Max
5.25
—
VCC
5.25
—
5.25
Unit
V
V
V
V
V
V
GND voltage
Input range: VWL ≤ AVCC; VBL ≥ AGND
Operating temperature
DGND
VAIN
Topr
—
1.8
–20
0.0
2.0
—
—
2.2
+75
V
Vp-p
°C
Note:
Connect the analog system component and the digital system component separately to power supply on the
evaluation board for noise prevention.
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 5 of 58
M66335FP
Electrical Characteristics
(Ta = –20 to +75°C, VCC = 5 V ± 5%, unless otherwise noted)
Item
"H" input voltage
"L" input voltage
Positive direction input threshold
Negative direction input threshold
Hysteresis value
"H" output voltage
"L" output voltage
"H" output voltage
"L" output voltage
"H" input current
Symbol
VIH
VIL
VT+
VT–
VH
VOH
VOL
VOH
VOL
IIH
"L" input current
IIL
"H" input current in the off state
IOZH
"L" input current in the off state
IOZL
Analog input current
Reference resistance
Differential non-linear error
Static current dissipation
(during standby)
IAIN
RL
Ed
ICCS
Min
2.0
—
—
0.6
—
VCC – 0.8
—
VCC – 0.8
—
Typ
—
—
—
—
0.2
—
—
—
—
Max
—
0.8
2.4
—
—
—
0.55
—
0.55
Unit
V
V
V
V
V
V
V
V
V
—
—
1.0
mA
—
—
–1.0
mA
—
—
5.0
mA
—
—
–5.0
mA
—
—
—
—
120
±1.0
1.0
—
—
mA
Ω
LSB
—
21
35
mA
Test Conditions
IOH = –12 mA
IOL = 12 mA
IOH = –4 mA
IOL = 4 mA
VCC = 5.25 V
VI = 5.25 V
VCC = 5.25 V
VI = 0 V
VCC = 5.25 V
VO = 5.25 V
VCC = 5.25 V
VO = 0 V
VCC = 5.25 V
VI = VCC, GND
Timing Conditions
(Ta = –20 to +75°C, VCC = 5 V ± 5%, unless otherwise noted)
Item
System clock cycle
System clock "H" pulse width
System clock "L" pulse width
System clock rise time
System clock fall time
Read pulse width
Set-up time before read
CS
Set-up time before read
A0 to A4
Set-up time before read
DAK
Hold time after read
CS
Hold time after read
A0 to A4
Hold time after read
DAK
Write pulse width
Set-up time before write
CS
Set-up time before write
A0 to A4
Set-up time before write
D0 to D7
Hold time after write
CS
Hold time after write
A0 to A4
Symbol
tc (SYS)
tw+ (SYS)
tw– (SYS)
tr (SYS)
tf (SYS)
tw (RD)
tsu (CS-RD)
tsu (A-RD)
tsu (DAK-RD)
th (RD-CS)
th (RD-A)
th (RD-DAK)
tw (WR)
tsu (CS-WR)
tsu (A-WR)
tsu (D-WR)
th (WR-CS)
th (WR-A)
Min
50
25
25
—
—
100
20
20
20
10
10
10
100
20
20
50
20
10
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
—
—
—
20
20
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hold time after write
Hold time after STIM
th (WR-D)
th (STIM-SRDY)
0
0
—
—
—
—
ns
ns
D0 to D7
SRDY
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 6 of 58
M66335FP
Switching Characteristics
(Ta = –20 to +75°C, VCC = 5 V ± 5%, unless otherwise noted)
Item
Symbol
Enable time for data output
after read
Disable time for data output
after read
Propagation time of DRO output
after read
tPZL (RD-D)
Min
—
Typ
—
Max
75
tPZH (RD-D)
tPLZ (RD-D)
10
—
50
tPHZ (RD-D)
tPHL (RD-DRO)
—
—
50
Unit
ns
ns
ns
ns
ns
Test Conditions
CL = 150 pF
CL = 50 pF
Test Circuit
Input
Output
Vcc
Vcc
RL = 1 kΩ
SW1
Tested device
P.G
SW2
CL
50 Ω
RL = 1 kΩ
GND
Item
tPLH, tPHL
tPLZ
tPHZ
tPZL
tPZH
SW1
Open
Closed
Closed
Closed
Open
SW2
Open
Open
Closed
Open
Closed
(1) Characteristics (10% to 90%) of the pulse generator
(PG): tr = 3 ns; tf = 3 ns
(2) Capacitance CL (= 150 pF) includes the stray
capacitance of connections and input capacitance of
the probe.
System Clock
tc (SYS)
tf (SYS)
tr (SYS)
tW− (SYS)
tW+ (SYS)
3V
90%
SYSCK
1.3 V
1.3 V
90%
1.3 V
10%
10%
0V
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 7 of 58
M66335FP
(1) Operation Mode
The M66335 has three basic operations.
• Peak value detection: Adjusting the peak value of analog signals output from the analog circuit to the white
reference voltage (VWL) of the A/D converter built in the M66335.
• Generation of data for uniformity correction: Generating data on a white reference original sheet for uniformity
correction by the sensor unit and writing them to the memory for correction built-in the M66335.
• Read: Reading original sheets, performing image processing of the read image data, and outputting in serial or
parallel the indicated converted binary data.
The M66335 is capable of performing the DMA transfer of multivalued data (6-bit data = D7 to D2, D1 = D0 = 0)
after correction about uniformities.
These three basic operations are performed in the following mode sequences for the CCD sensor and CIS sensor. The
sensor is set through the register 00 (SENS).
For the CCD Sensor
AGC mode
UNIF mode (white)
SCAN mode
The peak value of the 16 line cycle is detected by setting the AGC command in
the register 00 at "H".
To escape this mode, set the AGC command at "L" after a 20 line cycle (or a
cycle of 16 lines or more) passed since the start.
This operation mode is started by setting the UNIF command in the register 00 at
"H" after setting UMODE: "H" (white correction) in the register 00 and UNIFM:
"L" (only white correction) in the register 01.
Starting by the UNIF command also makes the system generate data for nonuniformity correction for white correction (for the 8 line cycle).
To escape this mode, set the UNIF command at "L" after a 10 line cycle (or a
cycle of 8 lines or more) passed since the start.
The read operation mode is started by setting the SCAN command in the register
00 at "H". To escape this mode, set the SCAN command at "L".
For the CIS Sensor
AGC mode
The peak value of the 16 line cycle is detected by setting the AGC command in
the register 00 at "H".
To escape this mode, set the AGC command at "L" after a 20 line cycle (or a
cycle of 16 lines or more) passed since the start.
UNIF mode (black)
When this operation mode is started by the UNIF command after setting
UMODE: "L" (black correction) in the register 00 and UNIFM: "H" (black and
white correction) in the register 01, the system also generates black data for nonuniformity correction for black correction (for the 8 line cycle).
To escape this mode, set the UNIF command at "L" after a 10 line cycle (or a
cycle of 8 lines or more) passed since the start.
In the case of only white correction, the setting is not necessary. Follow the
instruction below.
UNIF mode (white)
When this operation mode is started by the UNIF command in the register 00
after setting UMODE: "H" (white correction) in the register 00 and UNIFM: "L"
(only white correction) in the register 01, the system also generates white data for
non-uniformity correction for white correction (for the 8 line cycle).
To escape this mode, set the UNIF command at "L" after a 10 line cycle (or a
cycle of 8 lines or more) passed since the start.
SCAN mode
The reading operation is started by setting the SCAN command in the register 00
at "H". To escape this mode, set the SCAN mode at "L".
The signal operations and data flow in each basic operation are shown in the page
9 and 10, and the flowchart is in the page 26 and 27.
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 8 of 58
M66335FP
Operations of Signals in the Peak Value Detection Operation
BCAO
GCAO
VWL, VBL
ADIN Vri+, Vri−
Analog
control
Image sensor
C1
C2
BCMV
BCMI
LEVAJ
AIN
SH
CK1
CK2
RS
PTIMB
Sensor
control
Uniformity
correction
Correction
data memory
STIMB
SCLK
SVID
Image zone
separation
7-bit A/D
converter
Analog signal
processing
circuit
ACCK
SYSCK
Image processing sequence control signal
Resolution
change
Conversion
table memory
MTF
compensation
Line
memory
Detection of
background/
character levels
γ correction
table
Error
memory
Error
diffusion
Selection of
processing for
conversion to
binary
Image bus
interface
DMA
control
Dither
matrix
Organized
dither
MPU bus
interface
SRDYB
INT
DRQ
DAKB
RESETB
CSB
WRB
RDB
A0 to A4
D0 to D7
CODEC
DMA
MPU
Flow of Data in the Creation of Data for Uniformity Correction
BCAO
GCAO
ADIN
VWL, VBL
Vri+, Vri−
Analog
control
Image sensor
C1
C2
BCMV
BCMI
LEVAJ
AIN
SH
CK1
CK2
RS
PTIMB
Sensor
control
Uniformity
correction
STIMB
SCLK
SVID
Image zone
separation
7-bit A/D
converter
Analog signal
processing
circuit
ACCK
SYSCK
Image processing sequence control signal
Detection of
background/
character levels
Resolution
change
MTF
compensation
γ correction
table
Error
diffusion
Selection of
processing for
conversion to
binary
Image bus
interface
DMA
control
Correction
data memory
Conversion
table memory
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 9 of 58
Line
memory
Error
memory
Dither
matrix
Organized
dither
MPU bus
interface
SRDYB
INT
DRQ
DAKB
RESETB
CSB
WRB
RDB
A0 to A4
D0 to D7
CODEC
DMA
MPU
M66335FP
Flow of Data in the Reading Operation (for Output in Serial: Binary Data)
BCAO
GCAO
ADIN
VWL, VBL
Vri+, Vri−
Analog
control
Image sensor
C1
C2
BCMV
BCMI
LEVAJ
AIN
SH
CK1
CK2
RS
PTIMB
Sensor
control
Uniformity
correction
Correction
data memory
STIMB
SCLK
SVID
Image zone
separation
7-bit A/D
converter
Analog signal
processing
circuit
ACCK
SYSCK
Image processing sequence control signal
Detection of
background/
character levels
Resolution
change
Conversion
table memory
MTF
compensation
Line
memory
γ correction
table
Error
memory
Error
diffusion
Selection of
processing for
conversion to
binary
Image bus
interface
DMA
control
Dither
matrix
Organized
dither
MPU bus
interface
SRDYB
INT
DRQ
DAKB
RESETB
CSB
WRB
RDB
A0 to A4
D0 to D7
CODEC
DMA
MPU
: image data
: correction of compensation data
Flow of Data in the Reading Operation (for Output in Parallel: Binary Data)
BCAO
GCAO
ADIN
VWL, VBL
Vri+, Vri−
Analog
control
Image sensor
C1
C2
BCMV
BCMI
LEVAJ
AIN
SH
CK1
CK2
RS
PTIMB
Sensor
control
Uniformity
correction
Correction
data memory
STIMB
SCLK
SVID
Image zone
separation
7-bit A/D
converter
Analog signal
processing
circuit
ACCK
SYSCK
Image processing sequence control signal
Detection of
background/
character levels
Resolution
change
Conversion
table memory
MTF
compensation
Line
memory
γ correction
table
Error
memory
Error
diffusion
Selection of
processing for
conversion to
binary
Image bus
interface
DMA
control
Dither
matrix
Organized
dither
MPU bus
interface
SRDYB
INT
DRQ
DAKB
RESETB
CSB
WRB
RDB
A0 to A4
D0 to D7
CODEC
DMA
MPU
: image data
: correction of compensation data
Flow of Signals in the Reading Operation (for Multivated Data)
BCAO
GCAO
ADIN
VWL, VBL
Vri+, Vri−
Analog
control
Image sensor
C1
C2
BCMV
BCMI
LEVAJ
AIN
SH
CK1
CK2
RS
PTIMB
Sensor
control
Uniformity
correction
STIMB
SCLK
SVID
Image zone
separation
7-bit A/D
converter
Analog signal
processing
circuit
ACCK
SYSCK
Image processing sequence control signal
Detection of
background/
character levels
Resolution
change
MTF
compensation
γ correction
table
Error
diffusion
Selection of
processing for
conversion to
binary
Image bus
interface
DMA
control
Correction
data memory
Conversion
table memory
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 10 of 58
Line
memory
Error
memory
Dither
matrix
Organized
dither
MPU bus
interface
SRDYB
INT
DRQ
DAKB
RESETB
CSB
WRB
RDB
A0 to A4
D0 to D7
CODEC
DMA
MPU
M66335FP
(2) Line Cycle and Reading Sequence
The relationship between the line cycle and the reading sequence of the M66335 is shown in figure 1.
The relationship between the CODEC interface operations and the reading sequence is shown in figure 2 and that
between the DMA interface operations and the reading sequence is shown in figure 3.
• Single-line cycle (1/ACCK)
Defines the processing time per line of the M66335.
The single-line cycle is decided by the line cycle counter value registers 03 and 04 (PRE_DATA), and the pixel
transfer clock.
The pixel transfer clock is 1/16 of SYSCK.
1 line cycle (1/ACCK) [NS]
= line cycle counter value × pixel transfer clock cycle [NS]
= (PRE_DATA + 1) × pixel transfer clock cycle [NS]
= (PRE_DATA + 1) × 16/SYSCK [NS]
After loading the PRE_DATA value, the line cycle counter generates the addresses of the following gate signals
while counting down with the pixel transfer clock.
• Sensor start pulse (SH)
Image sensor start pulse. The point of the start pulse is decided by the uniformity correction range (UNIFG) and the
value of the register 05.
[ST_PL]
The ST_PL value must be set according to the following formulas for each image sensor type.
CCD: ST_PL = dummy pixels of the sensor + 2
CIS: ST_PL = 2
• Uniformity correction range (UNIFG)
Defines the range where uniformity correction is performed. This range corresponds to the width of the sensor (B4
to A4).
For the relationship between the sensor width and the uniformity correction range, see table 2.
• AGC range (AGCG)
Defines the range where peak value detection is performed. This range corresponds to the sensor width (B4 to A4).
Auto gain control is performed for the whole width of the sensor (solid line) in the AGC mode and for the narrower
width (dashed line) than the sensor width in the SCAN mode.
For the relationship between the sensor width and the AGC range, see table 2.
• Original sheet reading width
Defines the reading width for original sheets.
For original sheet widths narrower than the sensor width, the reading range (dashed line) is set, using the sensor
center as the base center point. Therefore, the points for the original sheet should be based on the sensor center.
For the relationship between the sensor width and the original sheet reading width, see table 3.
• Pulse motor control signal (PTIM)
Generates control signals for the pulse motor for the reading roller.
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M66335FP
PRE_DATA loading
0
Relationship with the registers
Countdown
Registers 03 and 04
(PRE_DATA)
Line cycle
(ACCK)
Register 00 (SENS_W)
Register 05 (ST_PL)
Sensor start pulse
(SH)
ST_PL
Uniformity
correction range
(UNIFG)
Register 00 (SENS_W)
AGC range
(AGCG)
Register 00 (SENS_W)
Register 01 (SOURCE)
Register 00 (SENS_W)
Register 11, 12 (OFFSET)
Original sheet
reading range
Pulse motor
control
(PTIM)
1 line cycle
Figure 1 Line Cycle and the Reading Sequence
ACCK
SH
SRDYB
<SRDYB>
(SSCAN)
3
1
4
INT
STIMB
2
SCLK
SVID
PTIMB
<INTCLR>
5
: Output section
1.
2.
3.
4.
5.
<INTCLR> : Register setting
(SSCAN) : Internal signal
SRDYB: L is taken in with a ↑ flow of SH, when scanning is started and PTIMB is output. (SSCAN: H)
During the period that STIMB is L, converted binary data are output.
SRDYB: H is taken in with a ↑ flow of ACCK, when the reading of one line ends. (SSCAN: L)
INT is asserted with a ↓ flow of SSCAN. (INT: H)
When CPU is ready for reading the next line, INTCLR is generated and INT is negated, and then SRDYB is set L.
Figure 2 CODEC Interface Operations and the Reading Sequence (Binary Data Output: Serial Output)
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M66335FP
ACCK
SH
<SRDYB>
(SSCAN)
1
2
INT
4
DRQ
DAKB
RDB
(Counter reset)
3
(DMAFIN)
5
<INTCLR>
6
PTIMB
: Output section
<SRDYB>, <INTCLR> : Register setting
(SSCAN), (DMAFIN), (counter reset) : Internal signal
SRDYB: L is taken in with a ↑ flow of SH, when scanning is started and PTIMB is output. (SSCAN: H)
SRDYB: H is taken in with a ↑ flow of ACCK, when the reading of one line ends. (SSCAN: L)
The internal counter reset signal is generated with a ↓ flow of SSCAN, and DRQ is asserted with a ↑ flow of SSCAN.
After the internal counter is reset, DMA transfer is started. (The internal counter is counted up by one each time a
pixel is transferred.)
5. When the value of the internal counter reaches the output pixel number, DMAFIN shifts to H, and DRQ is negated
with a ↑ flow form DMAFIN and INT is asserted with a ↓ flow of DMAFIN.
6. When CPU is ready for reading the next line, INTCLR is generated and INT is negated, and then SRDYB is set L.
1.
2.
3.
4.
Figure 3 DMA Interface Operations and the Reading Sequence (Multivated Data Output)
Table 2 Gate Signal Ranges for the Sensor Widths
Sensor Width
Gate Signal
Uniformity correction range (UNIFG)
AGC range (AGCG)
AGC mode
SCAN mode
Resolution
200 dpi
400 dpi
200 dpi
400 dpi
200 dpi
400 dpi
B4
2103/55
4207/111
2103/55
4207/111
2018/130
4037/261
A4
1943/215
3887/431
1943/215
3887/431
1584/564
3169/1129
Table 3 Original Sheet Reading Widths According to the Original Sheet Widths for the Sensor Widths
Sensor Width
Original Sheet Width
B4
Resolution
200 dpi
400 dpi
200 dpi
400 dpi
A4
B4
2102/54
4206/110
2102/54
4206/110
A4
—
1942/214
3886/430
When original sheets narrower than the sensor width, cut out the original sheet width with the registers 11 to 14.
(OFFSET, OUTLENGTH): (Region designation function)
X/Y
X: Left end address
Y: Right end address
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
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X
Y
M66335FP
(3) Image Processing Function
The M66335 converts image signals input from the image sensor into binary data. This includes the simple conversion
of characters and the change of images with various densities into pseudo-half-tone.
Before the conversion, distortions and characteristic degradations which signals from the image sensor almost always
have must be corrected or compensated.
Image zone separation must also be performed to realize optimal conversion-to-binary of the image for the possible
shortest transmission time.
Functions required for image processing are as follows.
•
•
•
•
•
•
•
Peak value detection
Uniformity correction
Resolution change (enlargement, reduction and averaging)
MTF compensation
γ correction
Background/character level detection (simple conversion to binary)
Change to pseudo-halftone
Organized dither
Error diffusion
• Image zone separation
• Designation of regions
Peak Value Detection
Because the A/D converter of the M66335 uses the input dynamic range at 2 Vp-p, the reference voltages (VWL, VBL)
corresponding to the peak value are fixed. The peak value of analog signals output from the analog processing circuit
must be detected before those signals are input to the A/D converter in order to adjust the analog signal peak value to
the full-scale value of the converter.
The peak value detection is performed by reading white data from the sensor in the AGC mode selected from its three
modes (AGC, UNIF and SCAN) of the M66335.
As shown in figure 4, preprocessing of peak value detection to increase the gain at the gain control is performed for a 8
line cycle and gain control processing to decrease the gain when the A/D converter over-flows is performed for another
8 line cycle after the start command (register 00: AGC) in the AGC mode.
As a result, the gain changes as shown in figure 5.
Peak value detection
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Line cycle
Preprocessing of peak
value detection
(increasing the gain)
Gain control on the
peak value
(decreasing the gain)
Figure 4 Peak Value Detection
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M66335FP
Preprocessing of peak value detection
Gain control on the peak value
After the completion of
preprocessing of peak
value detection
After the completion of
gain control on the
peak value
VWL
VWL
White data
The peak value of the
sensor output in the
line is adjusted to VWL.
The output level of the
last pixel of the line
is adjusted to VWL.
VBL
VBL
One line
One line
Figure 5 Changes of the Gain in Peak Value Detection
Uniformity Correction
Uniformity correction is to correct shading distortion due to less light at each end of the light source and faded light
around the lens, or high frequency distortion due to characteristic variations pixel by pixel in the image sensor.
As shown in figure 7, the M66335 makes blocks each of two pixels, creates a set of uniformity correction data for each
block, and write them to the built-in correction memory (SRAM: 1024 word × 6 bits) in the UNIF mode selected from
its three modes (AGC, UNIF and SCAN).
The correction data created each for two pixels are read from the built-in correction memory to correct the input image
data consecutively in the SCAN mode. With the register 01 (UNIFS) set at "1", the uniformity is not implemented.
With the register 02 (RES) set at "1", uniformity correction is performed on a block for 4 pixels.
For uniformity correction, white correction or the combination of black correction and white correction can be selected
according to the types of image sensors as shown in table 4.
This is set in the register 00 (SENS, UMODE) and register 01 (UNIFM).
To perform both black correction and white correction, the black correction must be done first.
The M66335 implements the correction in the correction range of 50% as shown in figure 7. If a set of white correction
data is beyond the correction range of 50%, the correction are not exactly performed as shown in figure 7. Therefore,
ensure that input signals are within the range.
Black level
High frequency
distortion
Shading distortion
White level
1 line
Figure 6 Waveform of White Data Output from the Image Sensor
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M66335FP
Table 4 Uniformity Correction due to the Image Sensor
Register
Image Sensor
CCD
CIS
Type of the Sensor
Register 00 (SENS)
0
1
Correction
White correction
White correction
1
Black correction
White correction
VWL
26 − 1
VBL
0
Selection of
Correction Mode
Register 01 (UNIFM)
1
1
0
0
Period of black correction: 0
Period of white correction: 1
1
White correction
White correction + black correction
Analog signal input White data
27 − 1
50%
Creation of Uniformity
Correction Data
Register 00 (UMODE)
Analog signal input
VWL
26 − 1
50%
VBL
0
Black data
1 line
1 line
Correction on over-range data (in white correction)
Analog signal input White data
27 − 1
VWL
26 − 1
50%
0
VBL
White data over the
correction range
Section over the correction range
1 line
Figure 7 Uniformity Correction
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White data
27 − 1
M66335FP
Resolution Change
Resolution change is controlled through H/W in the horizontal scanning direction and through S/W in the vertical
scanning direction.
The sequence for resolution change is shown in figure 8.
Horizontal Scanning Direction
The scaling factor is written from the register 15 (CNV_D) to the built-in resolution change memory (100 W × 1 bit) bit
by bit by 100 operations.
MSSEL of the register 6 must be set at "0" (which specifies the horizontal scanning direction) before the scaling factor
is written in the memory.
The procedure to specify CNV_D is as follows.
In the Case of Reduction
Data written in the resolution change memory have the following meaning.
"0": 1 pixel is output.
"1": No pixel is output.
(Example of reduction to 75%)
75 0's and 25 1's are written in the memory. The intervals of 1's should be as equal as possible to obtain the image with
better quality.
In the Case of Enlargement
Data written in the resolution change memory have the following meaning.
"0": 1 pixel is output.
"1": 2 pixels are output.
(Example of enlargement to 150%)
50 0's and 50 1's are written in the memory. The intervals of 1's should be as equal as possible to obtain the image with
better quality as in the reduction.
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M66335FP
Vertical Scanning Direction
Processing of lines to implement the scaling factor in the vertical scanning direction is decided for each line through the
register.
MSSEL of the register 6 must be set at "1" (which specifies the vertical scanning direction), and either "0" or "1"
written in the register 15 (CNV_D) before the processing of each line.
The timing for this setting is in the period between the first transition of the INT signal (synchronized with that of
ACCK) and that of the SH signal (the start of taking the SRDY signal in).
The procedure to specify CNV_D is as follows.
In the Case of Reduction
CNV_D indicates the current line read.
"0": 1 line of data are output.
"1": No line of data are output.
In the Case of Enlargement
CNV_D indicates the next line read.
"0": 1 line of data are output with PTIM generated (paper driven).
"1": 1 line of data are output with PTIM generated (paper not driven).
(Paper not driven: the same line is read again.)
Resolution change
Enlargement/reduction
is set in CONVX/CONVY.
MSSEL is set at 0.
Specifying enlargement/reduction
for horizontal/vertical scanning
Specifying horizontal scanning
Data setting in CNV_D
(100 bits in quantity)
Setting the scaling factor for
resolution change in the
horizontal scanning direction
MSSEL is set at 1.
Specifying vertical scanning
Data setting in CNV_D
(1 bit in quantity)
NO
Setting the scaling factor for
resolution change in the vertical
scanning direction
Setting of SRDY
Start of reading a single line
INT generated?
End of reading a single line
YES
NO
Page end?
YES
END
Figure 8 Sequence of Resolution Change Setting
Use the PTIMB signal as control signals for the pulse motor for the reading roller. The sequence for reduction is shown
in figure 9 and that for enlargement in figure 10.
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M66335FP
ACCK
SH
<SCAN>
1
(START)
2
5
<SRDYB>
(SSCAN)
3
6
INT
STIMB
Reduced
line
Reduced
line
4
SCLK
SVID
PTIMB
0
<CNV_D>
1
0
0
1
7
<INTCLR>
: Output section <SCAN>, <SRDYB>, <CNV_D>, <INTCLR>: register setting
(START), (SSCAN): internal signals
1. At the initial setting, the enlargement/reduction setting (CNV_D) in horizontal scanning is implemented. Then, after the system is switched into
the setting mode for enlargement/reduction in vertical scanning, the first line is set.
2. With a ↓ flow of ACCK, the SCAN command is taken in, when the system comes into the standby mode for SRDYB. (START: H)
3. With a ↑ flow of SH, SRDYB: L is taken in, when scanning starts and PTIMB is output. (SSCAN: H)
4. During the period that STIMB is at L, converted binary data are output while the data for reduced lines are not output because STIMB for them
are at H.
5. With a ↑ flow of ACCK, SRDYB: H is taken in, when the reading of the single line is completed. (SSCAN: L)
6. With a ↓ flow of SSCAN, INT is asserted. (INT: H)
7. With CPU ready for reading the next line, the enlargement/reduction setting (CNV_D) in vertical scanning is implemented; INTCLR is generated;
INT is negated; and then SRDYB is set at L.
Figure 9 Reduction Processing Sequence
ACCK
SH
<SCAN>
(START)
1
2
5
<SRDYB>
(SSCAN)
3
6
INT
STIMB
Enlarged
line
Enlarged
line
4
SCLK
SVID
PTIMB
<CNV_D>
0
1
0
1
0
7
<INTCLR>
: Output section
<SCAN>, <SRDYB>, <CNV_D>, <INTCLR>:
(START), (SSCAN):
register setting
internal signals
1. At the initial setting, the enlargement/reduction setting (CNV_D) in horizontal scanning is implemented. Then, after the system is switched into the setting
mode for enlargement/reduction in vertical scanning, the first line is set.
2. With a ↓ flow of ACCK, the SCAN command is taken in, when the system comes into the standby mode for SRDYB. (START: H)
3. With a ↓ flow of SH, SRDYB: L is taken in, when scanning starts and PTIMB is output while it is not output for enlarged lines. (SSCAN: H)
4. During the period that STIMB is at L, converted binary data are output.
5. With a ↑ flow of ACCK, SRDYB: H is taken in, when the reading of the single line is completed. (SSCAN: L)
6. With a ↓ flow of SSCAN, INT is asserted. (INT: H)
7. With CPU ready for reading the next line, the enlargement/reduction setting (CNV_D) in vertical scanning is implemented; INTCLR is generated; INT is
negated; and then SRDYB is set at L.
Figure 10 Enlargement Processing Sequence
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M66335FP
MTF Compensation
As shown in figure 11, image data of characters or pictures photoelectrically converted by the sensor unit show
degradation in resolution.
MTF compensation function of the M66335 restores the resolution of those data and expands the apparent dynamic
range by strengthening the high-pass frequency constituent with the Laplacian filter.
Photoelectric conversion
Photoelectric
conversion
Original (character)
Image signal
MTF
compensation
Data after compensation
Photoelectric
conversion
Original (photo)
Image signal
MTF
compensation
Data after compensation
Resolution compensation
X' = X + α ((X − A) + (X − B) + (X − C) + (X − D))
Where, α: MTF compensation coefficient in the register 08 (MTF_C, MTF_I)
In the above equation, α is set according to the register 07: MODE (selection of conversion-into-binary mode) as follows:
MODE: 00 (simple binary)
α = MTF_C
MODE: 01 (organized dither)
α = MTF_I
MODE: 10 (image zone separation) separation (character) α = MTF_C for image zone
separation (photo)
α = MTF_I for image zone
MODE: 11 (error diffusion)
α = MTF_I
Figure 11 MTF Compensation
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M66335FP
γ Correction
γ correction according to the sensitivity characteristics (logarithmic characteristics) of human eyes is implemented to
approximate the image data to natural images.
To do this, the M66335 writes the γ correction table to the built-in SRAM and read the corrected values corresponding
to read image data values from the SRAM.
γ = 0.45 is considered to be the optimal for γ correction for thermal head printers. Figure 12 shows a characteristics
example at γ = 0.45.
γ correction processing is set through the register 06: GAMMA as follows.
γ=1
γ = conversion table value
γ = 1 for image zone separation (character)
γ = conversion table value for image zone separation (photo)
GAMMA: 11
γ = conversion table value for image zone separation (character)
γ = 1 for image zone separation (photo)
For the procedures of inputting/outputting of data, refer to the section on writing to/reading from the γ correction
memory.
GAMMA: 00
GAMMA: 01
GAMMA: 10
Image data
6
A <5, 0>
DO <5, 0> 6
(Address) (Output)
γ correction memory
Data after
γ correction
1.0
White 63
Image data after γ correction
(memory output)
56
DOUT
47
γ = 0.45
34
γ=1
25
0
Dlow
DIN
Dup
IF (DIN < Dlow)
DOUT = 0
Black 0
Black: 0
8
16
32
48
White: 63
Image data (address)
Figure 12 γ Correction by Means of the Conversion Table
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IF (Dlow ≤ DIN < Dup)
γ
DOUT = DIN − Dlow
Dup − Dlow
IF (Dup ≤ DIN)
DOUT = 1.0
(
)
1.0
M66335FP
Background/Character Level Detection
The M66335 uses not the fixed threshold system but the floating threshold system, where the optimal threshold for
simple conversion-to-binary of objective pixels are continually generated by constantly detecting background/character
levels.
Accordingly, the threshold value proper for image data is generated without processing the data.
The threshold value is used for the areas to be converted to binary when simple conversion-to-binary or image zone
separation is selected as the mode of conversion to binary in reading data.
: register 07 (MODE)
• Background level counter
When image data greater (lighter in light) than the current value are input, this counter counts up to approximate to
the data.
When image data smaller (darker in light) than the current value are input, this counter counts down to approximate
to the data.
 Setting of the rate of count-up/count-down following data input: register 0C (MAX_UP, MAX_DOWN)
 Setting of the lowest limit for background levels: register 0E (LL_MAX)
• Character level counter
When image data greater (lighter in light) than the current value are input, this counter counts up to approximate to
the data.
When image data smaller (darker in light) than the current value are input, this counter counts down to approximate
to the data.
 Setting of the rate of count-down following data input: register 0C (MIN_UP)
 Setting of the highest limit for character levels: register 0D (UL_MIN)
Background level
detection counter
Image data
Generation of
the threshold
value
Comparison
Converted
binary data
Character level
detection counter
This slope is decided through MAX_UP.
This slope is decided through
MAX_DOWN.
Fixing of the background level
White level
Background level
Lowest limit of the
background level
(LL_MAX)
Threshold
level
Input data
Highest limit of
the character level
(UL_MIN)
Character level
This slope is decided
through MIN_UP.
Fixing of the
character level
Black level
Threshold level = (background level point − character level) × K + character level
K = threshold factor for conversion to binary: register 07 (SLICE)
Lowest limit of the background level (LL_MAX) > highest limit of the character level (UL_MIN)
Figure 13 Background/Character Levels
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M66335FP
Error Diffusion
The error diffusion, which is a conditional determination method, locally diffuses density errors between the original
image and the result to obtain the best approximation. This generates images with good compatibility of gradation and
resolution.
This is operated by selecting the error diffusion in conversion-into-binary mode selection.
: register 07 (MODE)
In error diffusion, dithers as well as density errors are added to image data. The dithers are data as commonly used for
the dither matrix.
: register 08 (ERROR)
γ correction must be performed in the error diffusion.
• Organized dither
The M66335 has built-in SRAM with a configuration of 64 words × 6 bits for organized dither memory.
In the initial setting, write the threshold value proper for the preferred dither pattern to the dither memory after
setting the dither matrix size.
: register 07 (DITH)
: register 10 (DITH_D)
For the procedure of inputting/outputting data, refer to the section on writing to/reading from the dither memory.
Dither matrix
−32
m
m
17
9
12
20
25
10
11
8
15
19
2
5
*
K2
Fmn
Fmn
Gmn
*
n
n
Integrated error
ΣαklEm − k, n − 1 (Note 2)
K1
Weighting of the 1
error filter
αkl
2
2
4
4
*
Error buffer memory
Preceding line
*
Current line
Fmn > 32 → Gmn = 63 (white)
Fmn < 32 → Gmn = 0 (black)
+ −
2
1
Error Emn = Fmn − Gmn (Note 1)
Notes 1: Characterized by using the difference
from the corrected value Fmn rather
than that from the original pixel Fmn.
2: Errors before the point of remark are
integrated.
Fmn = Fmn + K1 (1 / Σαkl) ΣαklEm − k, n − 1 + K2 (dither − 32)
k, 1
k, 1
K1 = register 08 (error)
K2 = register 08 (dither addition factor)
Figure 14 Error Diffusion Method
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M66335FP
Image Zone Separation
To make data conversion fit for each image zone, a black and white image is separated into the zones to be converted to
binary and the gradation zones. The binary zone is processed through simple conversion to binary and the gradation
zone through the error diffusion.
: register 08 to 0E
In the black and white image, each window of the gradation zone (photo) does not have a large difference of luminance in it.
With this characteristic of the gradation zone, it is distinguished from the conversion-into-binary zone through the following method.
Lmax: maximum illumination in window
Lmin: minimum illumination in window
Determining inequality 1: Lmax − Lmin > A (because the zone to be converted to binary has
a large difference in luminance in it.): register 09 Difference (SEPA_A)
Determining inequality 2:
Lmin > B (for the wholly white area):
register 0A Minimum (SEPA_B)
Determining inequality 3:
Lmax < C (for the wholly black area):
register 0B Maximum (SEPA_C)
If the window satisfies determination inequalities 1, 2 or 3, simple conversion to binary is applied.
If the window does not satisfy any of determination inequalities 1, 2 and 3, change to pseudo-halftone is applied.
White level = 63
Difference
Minimum
Lmin
Maximum
Lmax
A
Input data
B
C
Lmin
Black level = 0
Lmax − Lmin
Lmax
Figure 15 Image Zone Separation
Region Designation Function
The sensor width is fixed for A4 and B4.
The region designation function is to output only the data for a region defined and designated in terms of output data
after resolution change (or after uniformity correction for multivalued data).
Registers 11 to 14 (OFFSET, OUTLENGTH)
Output width
Designated region
OFFSET
OUTLENGTH
Figure 16 Cut-out Function
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
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M66335FP
(4) CODEC Interface (Binary Data Output)
Serial Output
SRDYB
SH
A
B
STIMB
10
4
(Equal scale,
reduced scale)
SCLK
12
2
2
10
SVID
4
4
4
4
(Enlarged scale)
SCLK
2
2
2
SVID
Unit: 1/SYSCK
Note:
A is decided through the registers 05 (ST_PL) 11 and 12 (OFFSET), and B through the registers 13 and 14
(OUTLENGTH).
Parallel Output
Pixel
1
2
3
4
5
6
7
8
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
SCLK
SVID
N−1
N+8
DRQ
DAK
RD
Note:
D0
N−1
D1
N−2
D2
N−3
D3
N−4
D4
N−5
D5
N−6
D6
N−7
D7
N−8
The 3-line handshake of SRDY, SH and STIM, which is the interface with CODEC, is the same as serial output.
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
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M66335FP
(5) DMA Interface (Multivalued Output)
The DMA transfer of data after non-uniformity correction can be performed by setting P_O) of the register 01: at "1"
(existence of DMA output) and M_B of that register at "1" (multivalue). With this setting, neither enlargement, nor
reduction, nor 400 dpi of resolution can be set.
SSCAN
DRQ
2
(DMA counter
reset signal)
1
4
DAKB
RDB
3
(DMA
counter signal)
(DMAFIN)
INT
5
6
D <7:2>
(XXXX): internal signal
1. On completion of reading one line, with a ↓ flow of SSCAN, the reset signal is entered in the DMA counter.
2. With a ↑ flow of the reset signal, DRQ shifts to "H", when the DMA transfer becomes ready.
3. With DAKB at "L" and a ↓ flow of RDB, DRQ shifts to "L", when multivalued data are output to D <7:2> during
the period that RDB is at "L".
4. With a ↑ flow of DAKB, the DMA counter counts up and DRQ shifts to "H", when the DMA transfer becomes
ready again.
5. The cycle of the above 3 and 4 is repeated until the DMA counter counts up to reach the number of output pixels set
in the registers 13 and 14 OUTLENGTH subtracted by one. By that repetitive operation, DMAFIN shifts to "H" to
terminate the DMA transfer when it reaches the set number.
6. With a ↓ flow of DMAFIN, INT shifts to "H", when CPU has an interrupt.
7. Reading is resumed from the next line by negating the INT signal through the register 17 (INTCLR).
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M66335FP
(6) Writing to/Reading from the Dither Memory, γ Correction Memory, Uniformity
Correction Memory, and Resolution Change Memory
The sequences of writing a dither pattern to and reading it from SRAM with a configuration of 64 words × 6 bits which
is built in the M66335 for organized dither are shown below.
Writing to the dither memory (MPU → M66335)
Initial setting (1)
Initial setting (2)
Memory address (0)
Memory address (1)
07H
01H
10H
10H
D6, D5
D0 = "1"
DATA (0)
DATA (1)
1
2
3
3
Initial setting (1)
Initial setting (2)
Memory address (0)
Memory address (1)
07H
01H
D6, D5
D0 = "1"
CSB
A4 to A0
WRB
D7 to D0
(Input)
Reading from the dither memory (M66335 → MPU)
CSB
A4 to A0
10H
10H
DATA (0)
DATA (1)
4
4
WRB
D7 to D0
(Input)
RDB
D7 to D0
(Output)
1
2
1. D6 and D5 (DITH) of the register 07 are set to define the dither matrix size.
2. D0 (CNTRST) of the register 01 is set at "1" to reset the address counter of the dither memory.
3. DITH_D is selected in the register 10, and DATA (0) of the MPU bus (D5 to D0) is written in the memory. The
address counter of the dither memory is incremented at the edge of the first transition of WR. (For writing)
4. DITH_D is selected in the register 10, and DATA (0) of the dither memory is read into the MPU bus (D5 to D0).
The address counter of the dither memory is incremented at the edge of the first transition of RD. (For reading)
A1
A2
A1
A2
A3
A0
A1
A2
A3
A4
A5
A6
A7
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A8
A9
A10
A11
A16
A17
A18
A19
A20
A21
A22
A23
A12
A13
A14
A15
A24
A25
A26
A27
A28
A29
A30
A31
A3
A16
A17
A18
A19
A32
A33
A34
A35
A36
A37
A38
A39
Dither Matrix Addresses
A0
A0
A4
A5
A6
A7
A20
A21
A22
A23
A40
A41
A42
A43
A44
A45
A46
A47
A8
A9
A10
A11
A24
A25
A26
A27
A48
A49
A50
A51
A52
A53
A54
A55
A13
A14
A15
A28
A29
A30
A31
A56
A57
A58
A59
A60
A61
A62
A63
A12
4 × 4 Matrix
4 × 8 Matrix
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
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8 × 8 Matrix
M66335FP
The sequences of writing γ correction table to and reading it from SRAM with a configuration of 64 words × 6 bits
which is built in the M66335 for γ correction are shown below.
Writing to the γ correction memory (MPU → M66335)
Initial setting (1)
Memory address (0)
Memory address (1)
01H
0FH
0FH
D0 = "1"
DATA (0)
DATA (1)
1
2
2
Initial setting (2)
Memory address (0)
Memory address (1)
01H
0FH
0FH
DATA (0)
DATA (1)
3
3
CSB
A4 to A0
WRB
D7 to D0
(Input)
Reading from the γ correction memory (M66335 → MPU)
CSB
A4 to A0
WRB
D7 to D0
(Input)
D0 = "1"
RDB
D7 to D0
(Output)
1
1. D0 (CNTRST) of the register 01 is set at "1" to reset the address counter of the γ correction memory.
2. GAMMA_D is selected in the register 0F, and DATA (0) of the MPU bus (D5 to D0) is written in the memory. The
address counter of the γ correction memory is incremented at the edge of the first transition of WRB. (For writing)
3. GAMMA_D is selected in the register 0F, and DATA (0) of the γ correction memory is read into the MPU bus (D5
to D0). The address counter of the γ correction memory is incremented at the edge of the first transition of RDB.
(For reading)
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
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M66335FP
Uniformity correction data can be written to and read from SRAM for uniformity correction built in the M66335
through the MPU bus. With this operation, the uniformity data can be temporarily saved in the backup memory when
the power is off. The sequences of writing and reading uniformity correction data are shown below.
Writing to the uniformity correction memory (MPU → M66335)
Initial setting (1)
Initial setting (2)
Memory address (0)
Memory address (1)
CSB
A4 to A0
00H
01H
19H
19H
D1
D0 = "1"
DATA (0)
DATA (1)
1
2
3
3
WRB
D7 to D0
(Input)
Reading from the uniformity correction memory (M66335 → MPU)
Initial setting (1)
Initial setting (2)
Memory address (0)
Memory address (1)
00H
01H
19H
19H
D1
D0 = "1"
DATA (0)
DATA (1)
4
4
CSB
A4 to A0
WRB
D7 to D0
(Input)
RDB
D7 to D0
(Output)
1
2
1. "0" (black correction) or "1" (white correction) is set in D1 (Umode) of the register 00.
2. D0 (CNTRST) of the register 01 is set at "1" to reset the address counter of the uniformity correction memory.
3. UNIF_D is selected in the register 19, and DATA (0) of the MPU bus (D5 to D0) is written in the memory. The
address counter of the uniformity correction memory is incremented at the edge of the first transition of WRB. (For
writing)
4. UNIF_D is selected in the register 19, and DATA (0) of the uniformity correction memory is read into the MPU bus
(D5 to D0). The address counter of the uniformity correction memory is incremented at the edge of the first
transition of RDB. (For reading)
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
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M66335FP
The sequences of writing a resolution change table to and reading it from SRAM with a configuration of 100 words × 1
bit which is built in the M66335 for resolution change are shown below.
Writing to the resolution change memory (MPU → M66335)
Initial setting (1)
Initial setting (2)
06H
01H
15H
15H
D7 = "0"
D0 = "1"
DATA (0)
DATA (1)
1
2
3
3
Memory address (0)
Memory address (1)
Memory address (0)
Memory address (1)
CSB
A4 to A0
WRB
D7 to D0
(Input)
Reading from the resolution change memory (M66335 → MPU)
Initial setting (1)
Initial setting (2)
06H
01H
D7 = "0"
D0 = "1"
CSB
A4 to A0
15H
15H
DATA (0)
DATA (1)
4
4
WRB
D7 to D0
(Input)
RDB
D7 to D0
(Output)
1
2
1. "0" (horizontal scan) is set in D7 (MSSEL) of the register 06.
2. D0 (CNTRST) of the register 01 is set at "1" to reset the address counter of the resolution change memory.
3. CNV_D is selected in the register 15, and DATA (0) of the MPU bus (D0) is written in the memory. The address
counter of the resolution change memory is incremented at the edge of the first transition of WRB. (For writing)
4. CNV_D is selected in the register 15, and DATA (0) of the resolution change memory is read into the MPU bus
(D0). The address counter of the resolution change memory is incremented at the edge of the first transition of RDB.
(For reading)
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M66335FP
List of the M66335FP Registers
R/W
A4 to A0
Default
D7
D6
D5
D4
D3
D2
D1
D0
R/W
00H
00H
RESET
SENS
SENS_W
AGC
UNIF
SCAN
UMODE
"L"
R/W
01H
00H
SOURCE
S/H_W
SH_W
UNIFS
P_O
M_B
UNIFM
CNTRST
RES
LCMPS
BLS
BLCMPS
CCD
CIS3
CIS2
CIS1
W
02H
00H
W
03H
00H
W
04H
00H
W
05H
00H
W
06H
00H
MSSEL
W
07H
00H
POL
W
08H
00H
W
09H
00H
W
0AH
00H
SEPA_B (5:0)
W
0BH
00H
SEPA_C (5:0)
W
0CH
00H
W
0DH
1FH
UL_MIN <5:0>
W
0EH
20H
LL_MAX <5:0>
R/W
0FH
—
GAMMA_D (5:0)
R/W
10H
—
W
11H
00H
W
12H
00H
W
13H
00H
W
14H
00H
PRE_DATA (7:0)
PRE_DATA (13:8)
ST_PL (7:0)
AVE
CONVX <1:0>
DITH <1:0>
CONVY <1:0>
MODE <1:0>
ERROR <1:0>
MTF_C <1:0>
MTF_I <1:0>
SEPA_A (5:0)
MAX_UP <1:0>
MAX_DOWN <1:0>
MIN_UP <1:0>
DITH_D (5:0)
OFFSET <7:0>
OFFSET <12:8>
OUTLENGTH <7:0>
OUTLENGTH <12:8>
W
15H
—
R/W
16H
00H
W
17H
—
INTCLR
R/W
18H
00H
GAIN <7:0>
R/W
19H
00H
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Page 31 of 58
GAMMA <1:0>
SLICE <2:0>
CNV_D
AGCSTP
UNIF_D <5:0>
SRDYS
SRDYB
M66335FP
Register Structure
Address
00H
R/W
R/W
Description
D7
D6
D5
D4
D3
D2
D1
D0
RESET
SENS
SENS_W
AGC
UNIF
SCAN
UMODE
"L"
D7
0
1
SENS: Sensor Type
CCD
CIS: (75% of clock duty)
D5
0
1
SENS_W: Reading Width of the Sensor
A4
B4
D3
0
1
Stop
Start
D2
0
1
Stop
Start
0
1
R/W
AGC: AGC Mode
Controls start/stop of the AGC mode.
UNIF: UNIF Mode
Controls start/stop of the UNIF mode.
SCAN: SCAN Mode
Controls start/stop of the SCAN mode.
Stop
Start
UMODE: Uniformity Correction in the UNIF Mode
Black Correction + White Correction
Only White Correction
D1
01H
With D7 = 1, the system is reset during the
period that the write pulse is "L".
(*) Write only
RESET: System Reset
Normal mode
Reset mode
D6
0
1
D4
0
1
Black correction
White correction
—
White correction
D7
D6
D5
D4
D3
D2
D1
SOURCE
S/H_W
S/H_W
UNIFS
P_O
M_B
UNIFM
D7
0
1
D6
0
1
(Default value: 00H)
SOURCE: Reading Width of the Original
A4
B4
S/H_W: S/W Pulse Width
Normal (quadruple the system clock cycle)
Normal multiplied by 0.5
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Page 32 of 58
D0
CNTRST (Default value: 00H)
M66335FP
Address
01H
02H
R/W
R/W
W
Description
D5
0
1
SH_W: SH Pulse Width
Normal (16 times the system clock cycle)
Reverse of normal multiplied by 2
D4
0
1
UNIFS: Uniformity Correction
Valid
Invalid
D3
0
1
P_O: DMA Output
Without DMA output
With DMA output
D0 is output in the form of LSB and D7 in the
form of MSB.
With the multivalue selected, data (6-bit) after
nonuniformity correction can be output through
the DMA transfer.
D2
0
1
M_B: Processing Mode
Binary
Multivalue
D1
0
1
UNIF: Uniformity Correction in SCAN
White correction
Black correction + white correction
D0
0
1
CNTRST: Address Counter Reset
Normal mode
Reset mode
With D0 = 1, the counter is reset during the
period that the write pulse is "L".
All the built-in RAM addresses are reset.
(*) Write only
D7
D6
D5
D4
D3
D2
D1
D0
RES
LCMPS
BLS
BLCMPS
CCD
CIS3
CIS2
CIS1
D7
0
1
RES: Resolution
200 dpi
400 dpi
D6
D5
0
1
BLS: Bit Clamping
Invalid
Valid
D4
D3
0
0
0
1
D2
0
0
1
0
D1
0
1
0
0
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 33 of 58
D0
1
0
0
0
0
1
0
1
(Default value: 00H)
LCMPS: Line Clamping
Invalid
Valid
BLCMPS: Black Level Line Clamping
Invalid
Valid
Sensors Compatible with Image Sensor Interfaces
CIS1: sensors with the input level of 2 V or higher
CIS2: sensors with the input level of under 2 V
CIS3: sensors capable of line clamping
CCD
M66335FP
Address
03H
R/W
W
Description
D7
D6
D5
D4
D3
D2
D1
D0
PRE_DATA <7:0>
(Default value: 00H)
D7 to D0: PRE_DATA <7:0> the lowest order 8 bits of the single-line cycle counter value
04H
W
D7
D6
D5
D4
D3
D2
D1
D0
PRE_DATA <13:8>
(Default value: 00H)
D5 to D0: PRE_DATA <13:8> the highest order 6 bits of the single-line cycle counter value
05H
W
D7
D6
D5
D4
D3
D2
D1
D0
ST_PL <7:0>
(Default value: 00H)
D7 to D0: ST_PL <7:0> start pulse position to the sensor
Set ST_PL = (dummy pixels of the sensor + 2).
06H
W
D7
D6
MSSEL
AVE
D5
D4
CONVX
D3
D2
CONVY
D7
0
1
MSSEL: Horizontal and Vertical Setting
Horizontal
Vertical
D6
0
1
AVE: Averaging Processing
With averaging
Without averaging
D5
D4
0
0
1
1
0
1
0
1
D3
D2
0
0
1
1
0
1
0
1
Original scale
Enlargement
Reduction
CONVY: Enlargement/Reduction Mode
in the Horizontal Scanning Direction
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Page 34 of 58
D0
GAMMA
(Default value: 00H)
When "with averaging" selected:
For enlargement: inserted lines are the average of the
preceding one and the current one.
For reduction: the subsequent lines from removed lines
are the average of the removed one and
the current one.
CONVX: Enlargement/Reduction Mode
in the Horizontal Scanning Direction
Original scale
Enlargement
Reduction
D1
RES = 1
With the setting of 400 dpi,
enlargement cannot be set.
M66335FP
Address
06H
R/W
W
Description
D1
0
0
1
1
D0
0
1
0
1
GAMMA: γ Correction Processing
Character, photo: γ = 1
Character, photo: γ = download value
Character: γ = 1; photo: γ = download value
Character: γ = download value; photo: γ = 1
Note: Judgment between character and photo is based on the result of image zone separation.
07H
W
D7
D6
POL
D7
0
1
D5
D4
DITH
D3
D2
MODE
D1
D0
SLICE
(Default value: 00H)
POL: Conversion-to-Binary Output Mode
White: 1; black: 0
White: 0; black: 1
D6
0
0
1
1
D5
0
1
0
1
4×4
4×8
8×8
—
DITH: Dither Matrix Size
D4
0
0
1
1
D3
0
1
0
1
MODE: Selection of the Conversion-to-Binary Mode
Simple binary
Organized dither
Image zone separation (simple binary + error diffusion)
Error diffusion
D2
D1
D0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
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Page 35 of 58
SLICE: Threshold Factor for Conversion to Binary
6/16
7/16
8/16
9/16
10/16
11/16
12/16
13/16
M66335FP
Address
08H
R/W
W
Description
D7
D6
D5
D4
D3
ERROR
D5
D4
0
0
1
1
0
1
0
1
D3
0
0
1
D2
0
1
0
1
1
Error (Base)
Strong (7/8)
Strong (7/8)
Weak (3/4)
Weak (3/4)
D2
D1
MTF_C
D0
MTF_I
(Default value: 00H)
ERROR
Rate of Dither Addition to Errors
Weak (1/8)
Strong (1/4)
Weak (1/8)
Strong (1/4)
MTF_C: MTF Compensation Factor
1/4
1/2
1
0
Note: This is valid when MODE is simple binary or image zone separation (character).
D1
0
0
1
1
D0
0
1
0
1
MTF_I: MTF Compensation Factor
1/4
1/2
1
0
Note: This is valid when MODE is organized dither, error diffusion or image zone separation (photo).
09H
W
D7
D6
D5
D4
D3
D2
D1
D0
SEPA_A
(Default value: 00H)
D5 to D0: SEPA_A Image zone separation parameter (differential)
0AH
W
D7
D6
D5
D4
D3
D2
D1
D0
SEPA_B
(Default value: 00H)
D5 to D0: SEPA_B Image zone separation parameter (minimum)
0BH
W
D7
D6
D5
D4
D3
D2
D1
SEPA_C
D5 to D0: SEPA_C Image zone separation parameter (maximum)
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
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D0
(Default value: 00H)
M66335FP
Address
0CH
R/W
W
Description
D7
D6
D5
D4
MAX_UP
0DH
W
D3
D2
MAX_DOWN
D1
D0
MIN_UP
(Default value: 00H)
D5
0
0
1
1
D4
0
1
0
1
MAX_UP: Background Level Detection Clock for the Up Counter
Ordinary (T = (single pixel cycle) × 32)
Slow (T = (single pixel cycle) × 64)
Fast (T = (single pixel cycle) × 16)
Fastest (T = (single pixel cycle) × 8)
D3
0
0
1
1
D2
0
1
0
1
MAX_DOWN: Background Level Detection Clock for the Down Counter
Ordinary (T = (single pixel cycle) × 128)
Slow (T = (single pixel cycle) × 256)
Fast (T = (single pixel cycle) × 64)
Fastest (T = (single pixel cycle) × 32)
D1
D0
0
0
1
1
0
1
0
1
D7
MIN_UP: Character Level Detection Clock for the Up Counter
Ordinary (T = (single pixel cycle) × 128)
Slow (T = (single pixel cycle) × 256)
Fast (T = (single pixel cycle) × 64)
Fastest (T = (single pixel cycle) × 32)
D6
D5
D4
D3
D2
D1
D0
UL_MIN
(Default value: 1FH)
D5 to D0: UL_MIN Detection of background/character levels
Highest limit of character levels
0EH
W
D7
D6
D5
D4
D3
D2
D1
D0
LL_MAX
(Default value: 20H)
D5 to D0: LL_MAX Detection of background/character levels
Lowest limit of background levels
Lowest limit of background levels (LL_MAX) > highest limit of character levels (UL_MIN)
0FH
R/W
D7
D6
D5
D4
D3
D2
D1
D0
D1
D0
GAMMA_D <5:0>
D5 to D0: GAMMA_D Built-in γ memory data
10H
R/W
D7
D6
D5
D4
D3
D2
DITH_D <5:0>
D5 to D0: DITH_D Built-in dither memory data
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 37 of 58
M66335FP
Address
11H
R/W
W
Description
D7
D6
D5
D4
D3
D2
D1
D0
OFFSET <7:0>
(Default value: 00H)
D7 to D0: OFFSET <7:0> Offset for cut-out Lowest order 8 bits
12H
W
D7
D6
D5
D4
D3
D2
D1
D0
OFFSET <12:8>
(Default value: 00H)
D3 to D0: OFFSET <12:8> Offset for cut-out Highest order 5 bits
13H
W
D7
D6
D5
D4
D3
D2
D1
D0
OUTLENGTH <7:0>
(Default value: 00H)
D7 to D0: OUTLENGTH <7:0> No. of output pixels Lowest order 8 bits
14H
W
D7
D6
D5
D4
D3
D2
D1
D0
OUTLENGTH <12:8>
(Default value: 00H)
D3 to D0: OUTLENGTH <12:8> No. of output pixels Highest order 5 bits
Note: OUTLENGTH <12:8> must be a multiple of 8. If a number of output pixels is not a multiple of 8,
the remainder of the division must be omitted.
15H
R/W
D7
D6
D5
D4
D3
D2
D1
D0
CNV_D
D0: CNV_D Indication of enlargement/reduction
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
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M66335FP
Address
16H
17H
R/W
R/W
W
Description
D7
D6
D5
D4
D3
D2
0
1
AGCSTP: Gain Control Counter
Gain control counter valid.
Gain fixed.
D1
0
1
SRDYS: SRDY Control
SRDY control through the register
SRDY control through the external pin
D0
0
1
SRDYB: Data Transfer Start Ready
Transfer allowed.
Transfer not allowed.
D7
D6
D5
D4
D3
D2
D1
D0
AGCSTP
SRDYS
SRDYB
(Default value: 00H)
In the case of data control through the
register, the SDRYB input pin must be
always set at "H".
For the control through the register, the
SRDY register must be controlled line by
line.
(*) Write only
D2
D1
D0
D1
D0
INTCLR
INT signals are negated by accessing to this address.
18H
R/W
D7
D6
D5
D4
D3
D2
GAIN <7:0>
In reading: the current gain value of the gain control counter can be read.
In writing: the gain value of the gain control counter can be set.
However, this is valid only if AGCSTP = 1.
19H
R/W
D7
D6
D5
D4
D3
D2
UNIF <5:0>
D5 to D0: UNIF_D Built- in uniformity correction memory data
D1
D0
With UMODE = 0,
access to the
uniformity correction
memory for black
correction is available.
With UMODE = 1,
access to the
uniformity correction
memory for white
correction is available.
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 39 of 58
M66335FP
Description of the Operations of the Analog Circuits
The configuration of the analog processing circuits is shown in figure 17.
(1) Sensor Selection Circuit
The four types of sensors in the table can be connected to the circuit.
Register 02H
Sensor Type
CCD
CIS1
CIS2
CIS3
CCD sensor
CIS sensor which outputs light voltages (white voltage) of 3.5 V or lower
CIS sensor which outputs light voltages (white voltage) of 2 V or lower
CIS sensor which output shielding pixels for each line
<CCD mode>
Black
Max 500 mVp-p
White
Blanking element
Signaling element
The amplitudes of sensor signals are multiplied by –4 through
the two operating amplifiers directly after the switch to select
the CCD mode. (The waveforms of the signals are inverted at
the same time.)
As a result, the sensor signals input to the sample and hold
circuit have a dark voltage of 2.2 V.
Shielding pixel part
Effective pixel part
<CIS1 mode>
White Max 3.5 V
Black
The amplitude of signals input from the sensor are halved.
Then, their reference potential is shifted up to 2.2 V.
±200 mV
Signaling element
As a result, the sensor signals input to the sample and hold
circuit have a dark voltage of 2.2 V.
<CIS2 mode>
White Max 2 V
The reference potential of signals input from the sensor is
shifted up to 2.2 V.
Black ±200 mV
Signaling element
As a result, the sensor signals input to the sample and hold
circuit have a dark voltage of 2.2 V.
<CIS3 mode>
White
Sensor signals with a dark voltage of 2.2 V clamped by line
clamping input are directly input to the sample and hold circuit.
2 Vp-p
Black
Signaling element
Clamping level
Shielding pixel part
Effective pixel part
(2) Line Clamping Circuit
This circuit is used for CCD (line clamping mode) and CIS3.
The reference voltage (dark voltage) output in the shielding pixel part of the sensor is sampled by LCMP (line clamping
pulses) and shifted up to the internal reference voltage of 2.2 V. This is not used for the CIS1 or CIS2 input sensor (set
off constantly).
: register 02 (LCMPS)
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
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M66335FP
(3) Sample and Hold Circuit and Bit Clamping Circuit
In the CCD mode, bit clamping, as well as line clamping, can be performed. The blanking elements of each pixel of
sensor output is sampled by BTCMP (bit clamping pulses). The differences of signals from the reference potential
sampled by the bit clamping circuit are input to the gain control circuit of next step as signaling elements. To turn off bit
clamping, set BLS invalid, so that the reference potential will be fixed at the internal reference potential of 2.2 V.
: register 02 (BLS)
(4) Gain Control Circuit
The amplifying factor (gain) must be adjusted so that the amplitudes of sensor signals can come within the dynamic
range of the A/D converter. The gain is set through the automatic gain control in the AGC mode (register 00) or directly
through the register 18 (GAIN <7:0>).
The gain changes within the following ranges according to the sensor used.
Mode
CCD
CIS1
CIS2
CIS3
Amplifying Factor of Signals (Gain)
4 to 20
0.5 to 2.5
1 to 5
1 to 5
In the AGC mode, the gain control counter is set at the greatest gain in the initial state and then counted down each time
an overflow bit is output from the A/D converter. The count (gain) of the gain control counter is directly read/written
through the register 18 (GAIN <7:0>). The counting operation of the counter can be controlled through the register 16
(AGCSTP).
(5) Internal Reference Voltage
Internal reference voltage source for the analog circuits:
this generates the reference voltage (2.2 V) for the line clamping circuit, the sample and hold circuit, and the bit
clamping circuit.
A/D converter reference voltage generation circuit:
this generates VWL (white level reference voltage of 3.8 V) and VBL (black level reference voltage of 1.8 V) for
the A/D converter.
(6) Black Level Clamping Circuit
This circuit adjust the level of reference voltage to the A/D converter from analog circuits.
The black clamping circuit is used in the CCD or CID3 mode. (See figure 18, 19 and 22) The GCAO pin and the BCMI
pin are capacity-coupled. The output reference potential in the shielding pixel part of sensor signals are applied to the
BCMV pin as the VBL (black level reference voltage of 1.8 V) for the A/D converter.
BLCMP (black level clamping pulses) are generated concurrently with the shielding pixel part of each line. To turn off
this circuit, set BLCMPS invalid and apply the black level reference voltage of the A/D converter to the BCMV pin.
: register 02 (BLCMPS)
In the CIS1 or CIS2 mode, the LEVAJ pin is used. (See figure 20 and 21) Voltage is applied to the LEVAJ pin so that
the reference potential of output at the GCAO pin can be adjusted to the VBL (black level reference voltage of 1.8 V) of
the A/D converter. Set voltage input to the LEVAJ pin as follows.
VLEVAJ = VVBL – A × GV + 0.2 [V]
VGCAO = VLEVAJ + GV × VIN [V]
where,
A: the lowest limit of dark voltage of the sensor [V]
GV: gain (multiplying factor) of the gain control circuit
VIN: signals input from the sensor [V]
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 41 of 58
AIN
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 42 of 58
LCMP
AIN
Figure 17 Circuit Configuration of the Analog Part of the M66335FP
−
+
MCIS3
MCIS2
Level shift
circuit (2.2 V)
MCIS1
MCCD
AGND
AGND
Vcc
−
+
MCIS <3:1>, MCCD
DVcc
DGND
GND
Input clamping circuit
+
−
AVDD
AVcc
+
−
−
+
2.2 V
Bit clamping circuit
−
+
8
Vri−
VBL
VWL
3.8 V
VVBL = 1.8 [V]
Vri+
1.8 V
Internal reference voltage
source for the analog circuits
−
+
+
−
Vri−
ADIN
−
+
−
+
RESET
ADCK
ADIN
AGND
DGND
A/D converter
OF
B <7:1>
Vref+
VREFL
DVcc
+
−
VREFH
AVcc
Vref− Vri+
V
BCMO
BCMO
AGCSEL <7:0>
Reference voltage generating circuit
for the A/D converter
+
−
BCMI
BCMI
Black level
clamping circuit
−
+
C1 C2 GCAO LEVAJ BCMV BLCMP
Gain control circuit
GCA
Sample and hold circuit
S/H BTCMP BLS
GCAO
C1 C2
LEVAJ BCMV
DIN <6:0>
OF
GND
Digital circuit
GAIN <7:0>
RESET
ADCK
BLCMP
BLS
BTCMP
S/H
LCMP
MCIS <3:1>, MCCD
Vcc
M66335FP
M66335FP
Analog Circuit Timing Chart (for CCD Mode/Bit Clamping)
Register
Mode
CCD (bit clamping)
Address
Bit
Signal
Setting
00H
D6
SENS
1
D6
LCMPS
1
D5
BLS
1
Shielding pixel part
Non-signaling part
02H
D3
CCD
1
D4
BLCMPS
1
D2
CIS3
0
D1
CIS2
0
D0
CIS1
0
Effective pixel part
SH
CK1
CCD
signal output
LCMP
BTCMP
S/H
GCAO
signal output
BLCMP
BCMO
signal output
A/D clock
A/D output
Non-signaling part
2
Shielding pixel part
Unit: 1/SYSCK
Effective pixel part
2
SH
12
16
CK1
CCD
signal output
N
16
3
4
9
LCMP
16
BTCMP
1
13
16
2
S/H
3
GCAO
signal output
4
9
N
8
8
BLCMP
BCMO
signal output
N
A/D clock
A/D output
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 43 of 58
N
M66335FP
Analog Circuit Timing Chart (for CCD Mode/Line Clamping)
Register
Mode
CCD (line clamping)
Address
Bit
Signal
Setting
00H
D6
SENS
1
D6
LCMPS
1
Non-signaling part
D5
BLS
0
02H
D3
CCD
1
D4
BLCMPS
1
Shielding pixel part
D2
CIS3
0
D1
CIS2
0
Effective pixel part
SH
CK1
CCD
signal output
LCMP
BTCMP = "H"
S/H
GCAO
signal output
BLCMP
BCMO
signal output
A/D clock
A/D output
Non-signaling part
SH
2
Shielding pixel part
Effective pixel part
Unit: 1/SYSCK
2
12
16
CK1
CCD
signal output
N
16
3
4
9
LCMP
BTCMP = "H"
16
S/H
3
GCAO
signal output
4
9
N
8
8
BLCMP
BCMO
signal output
N
A/D clock
A/D output
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 44 of 58
N
D0
CIS1
0
M66335FP
Analog Circuit Timing Chart (for CIS1 Mode)
Register
Mode
CIS1
Address
00H
Bit
D6
D6
D5
D4
02H
D3
D2
D1
D0
Signal
Setting
SENS
0
LCMPS
0
BLS
0
BLCMPS
0
CCD
0
CIS3
0
CIS2
0
CIS1
1
SH
CK1
CIS
signal output
LCMP = "H"
BTCMP = "H"
S/H
GCAO
signal output
A/D clock
A/D output
Unit: 1/SYSCK
SH
16
CK1
10
4
2
CIS
signal output
16
N
LCMP = "H"
BTCMP = "H"
16
7
S/H
4
GCAO
signal output
1
N
A/D clock
A/D output
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 45 of 58
N
M66335FP
Analog Circuit Timing Chart (for CIS2 Mode)
Register
Mode
CIS2
Address
Bit
Signal
Setting
00H
D6
SENS
0
D6
LCMPS
0
D5
BLS
0
02H
D3
CCD
0
D4
BLCMPS
0
D2
CIS3
0
D1
CIS2
1
SH
CK1
CIS
signal output
LCMP = "H"
BTCMP = "H"
S/H
GCAO
signal output
A/D clock
A/D output
Unit: 1/SYSCK
SH
16
CK1
10
4
2
CIS
signal output
16
N
LCMP = "H"
BTCMP = "H"
16
7
S/H
4
GCAO
signal output
1
N
A/D clock
A/D output
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 46 of 58
N
D0
CIS1
0
M66335FP
Analog Circuit Timing Chart (for CIS3 Mode)
Register
Address
Bit
Signal
Setting
Mode
CIS3
00H
D6
SENS
1
Non-signaling part
D6
LCMPS
1
D5
BLS
0
D4
BLCMPS
1
Shielding pixel part
02H
D3
CCD
0
D2
CIS3
1
D1
CIS2
0
Effective pixel part
SH
CK1
CIS
signal output
LCMP
BTCMP = "H"
S/H
GCAO
signal output
BLCMP
BCMO
signal output
A/D clock
A/D output
Non-signaling part
Shielding pixel part
Unit: 1/SYSCK
Effective pixel part
SH
16
CK1
CIS
signal output
4
10
16
2
N
LCMP
4
1
BTCMP = "H"
7
16
S/H
4
GCAO
signal output
1
N
8
8
BLCMP
BCMO
signal output
N
A/D clock
A/D output
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Page 47 of 58
N
D0
CIS1
0
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 48 of 58
Max 500 mVp-p
Blanking element
AIN
LCMP
White
Black
AIN
Signaling element
Sensor output
0.1 µF
MCCD
DGND
−
+
MCIS3
MCIS2
Level shift
circuit (2.2 V)
MCIS1
AGND
AGND
Vcc
GND
−
+
MCIS <3:1>, MCCD
Input clamping
circuit
+
−
AVDD
4
DVcc
−
+
+
−
8
Vri−
Vri+
3.8 V
VBL VWL
1.8 V
Internal reference voltage
source for the analog circuits
−
+
Bit clamping circuit
2.2 V
−
+
+
−
BCMI BCMO
−
+
−
+
AGCSEL <7:0>
DGND
A/D converter
AGND
RESET
ADCK
ADIN
OF
B <7:1>
DVcc
Vref+
VREFL
AVcc
Vref− Vri+
+
−
VREFH
+
−
V
Black level
clamping circuit
Reference voltage generating circuit
for the A/D converter
Vri−
ADIN
BCMV
BCMV = VBL
C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO
Gain control circuit
GCA
Sample and hold circuit
S/H BTCMP BLS
H
GCAO
LEVAJ
C1 C2
0.1 µF
−
+
AVcc
LEVAJ = VBL
DIN <6:0>
OF
GND
Digital circuit
GAIN <7:0>
RESET
ADCK
BLCMP
BLS
BTCMP
S/H
LCMP
MCIS <3:1>, MCCD
Vcc
(dashed line): clock line
(bold line): signal line
M66335FP
Figure 18 External Pin Connections of the Analog Part (for the CCD Mode/Bit Clamping)
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 49 of 58
Max 500 mVp-p
AIN
LCMP
White
Black
AIN
Signaling element
Blanking element
0.1 µF
MCCD
DGND
−
+
MCIS3
MCIS2
Level shift
circuit (2.2 V)
MCIS1
AGND
AGND
Vcc
GND
−
+
MCIS <3:1>, MCCD
Input clamping
circuit
+
−
AVDD
4
DVcc
−
+
+
−
Vri−
Vri+
3.8 V
VBL VWL
1.8 V
Internal reference voltage
source for the analog circuits
−
+
8
+
−
BCMI BCMO
−
+
−
+
AGCSEL <7:0>
DGND
A/D converter
AGND
RESET
ADCK
ADIN
OF
B <7:1>
DVcc
Vref+
VREFL
AVcc
Vref− Vri+
+
−
VREFH
+
−
V
Black level
clamping circuit
Reference voltage generating circuit
for the A/D converter
Vri−
ADIN
BCMV
BCMV = VBL
C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO
Gain control circuit
GCA
Sample and hold circuit
Bit clamping circuit
2.2 V
−
+
L
S/H BTCMP BLS
H
C1 C2
GCAO
LEVAJ
0.1 µF
−
+
AVcc
LEVAJ = VBL
(bold line): signal line
DIN <6:0>
OF
GND
Digital circuit
RESET
ADCK
GAIN <7:0>
BLCMP
BLS
BTCMP
S/H
LCMP
MCIS <3:1>, MCCD
Vcc
(dashed line): clock line
M66335FP
Figure 19 External Pin Connections of the Analog Part (for the CCD Mode/Line Clamping)
AIN
LCMP
AVDD
MCCD
−
+
MCIS3
MCIS2
Level shift
circuit (2.2 V)
MCIS1
Input clamping
circuit
AGND
Vcc
−
+
MCIS <3:1>, MCCD
4
DVcc
Figure 20 External Pin Connections of the Analog Part (for the CIS1 Mode)
AGND
Gr: gain of the gain control circuit
DGND
GND
A: minimum limit for dark voltage of the sensor
Set R1 and R2 so that the following equation will hold.
VLEVAJ = VVBL − A B + 0.2 [V]
(1.8 V)
Where,
±200 mV
Max 3.5 V
Sensor output
Sensor output
H
AVcc
−
+
+
−
Vri−
Vri+
3.8 V
VLEVAJ
R1 R2
VBL VWL
1.8 V
Internal reference voltage
source for the analog circuits
−
+
8
+
−
L
BCMI BCMO
−
+
−
+
AGCSEL <7:0>
DGND
A/D converter
AGND
RESET
ADCK
ADIN
OF
B <7:1>
DVcc
Vref+
VREFL
AVcc
Vref− Vri+
+
−
VREFH
+
−
V
Black level
clamping circuit
Reference voltage generating circuit
for the A/D converter
Vri−
ADIN
BCMV
C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO
Gain control circuit
GCA
Sample and hold circuit
Bit clamping circuit
2.2 V
−
+
L
S/H BTCMP BLS
H
GCAO
LEVAJ
C1 C2
BCMV = VBL
−
+
+
−
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 50 of 58
Black White
Max 5 pF
DIN <6:0>
OF
GND
Digital circuit
RESET
ADCK
GAIN <7:0>
BLCMP
BLS
BTCMP
S/H
LCMP
MCIS <3:1>, MCCD
Vcc
(dashed line): clock line
(bold line): signal line
M66335FP
LCMP
AIN
AVDD
−
+
MCIS3
MCIS2
Level shift
circuit (2.2 V)
MCIS1
MCCD
Input clamping
circuit
AGND
Vcc
−
+
MCIS <3:1>, MCCD
4
DVcc
Figure 21 External Pin Connections of the Analog Part (for the CIS2 Mode)
AGND
Gr: gain of the gain control circuit
DGND
GND
A: minimum limit for dark voltage of the sensor
Set R1 and R2 so that the following equation will hold.
VLEVAJ = VVBL − A B + 0.2 [V]
(1.8 V)
Where,
±200 mV
Max 2 V
Sensor output
AIN
H
AVcc
−
+
+
−
Vri−
Vri+
3.8 V
VLEVAJ
R1 R2
VBL VWL
1.8 V
Internal reference voltage
source for the analog circuits
−
+
8
+
−
L
BCMI BCMO
−
+
−
+
AGCSEL <7:0>
Black level
clamping circuit
DGND
A/D converter
AGND
RESET
ADCK
ADIN
OF
B <7:1>
DVcc
Vref+
VREFL
AVcc
Vref− Vri+
+
−
VREFH
+
−
V
C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO
BCMV
Reference voltage generating circuit
for the A/D converter
Vri−
ADIN
GCAO
LEVAJ
C1 C2
Gain control circuit
GCA
Sample and hold circuit
Bit clamping circuit
2.2 V
−
+
L
S/H BTCMP BLS
H
(In the case of the pixel clock of 1 MHz)
BCMV = VBL
−
+
+
−
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 51 of 58
Black White
Max 5 pF
DIN <6:0>
OF
GND
Digital circuit
RESET
ADCK
GAIN <7:0>
BLCMP
BLS
BTCMP
S/H
LCMP
MCIS <3:1>, MCCD
Vcc
(dashed line): clock line
(bold line): signal line
M66335FP
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 52 of 58
Max 2 Vp-p
Shielding
pixel part
AIN
LCMP
Black
White
AIN
Signaling
part
Sensor output
0.1 µF
Figure 22 External Pin Connections of the Analog Part (for the CIS3 Mode)
MCCD
DGND
−
+
MCIS3
MCIS2
Level shift
circuit (2.2 V)
MCIS1
AGND
AGND
Vcc
GND
−
+
MCIS <3:1>, MCCD
Input clamping
circuit
+
−
AVDD
4
DVcc
−
+
+
−
Vri−
Vri+
3.8 V
VBL VWL
1.8 V
Internal reference voltage
source for the analog circuits
−
+
8
+
−
BCMI BCMO
−
+
−
+
AGCSEL <7:0>
DGND
A/D converter
AGND
RESET
ADCK
ADIN
OF
B <7:1>
DVcc
Vref+
VREFL
AVcc
Vref− Vri+
+
−
VREFH
+
−
V
Black level
clamping circuit
Reference voltage generating circuit
for the A/D converter
Vri−
ADIN
BCMV
BCMV = VBL
C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO
Gain control circuit
GCA
Sample and hold circuit
Bit clamping circuit
2.2 V
−
+
L
S/H BTCMP BLS
H
C1 C2
GCAO
LEVAJ
0.1 µF
−
+
AVcc
LEVAJ = VBL
(bold line): signal line
DIN <6:0>
OF
GND
Digital circuit
RESET
ADCK
GAIN <7:0>
BLCMP
BLS
BTCMP
S/H
LCMP
MCIS <3:1>, MCCD
Vcc
(dashed line): clock line
M66335FP
M66335FP
Flowchart
Reading Operations (for the CCD Sensor)
Start
Power on
Software reset
S/H: SH pulse width
Cycle counter
Start pulse
Register 00
Register 01
Register 16
N
INT generated?
Register 17
Y
N
Page end?
Y
Register 0F
Y
Becomes stable.
Register 00
AGC: 16 times
AGC ends.
Uniformity correction starts.
Uniformity correction ends.
Register 00
Register 00
White correction
: 8 times
Register 00
Specifying the vertical
scanning resolution
Register 06
Specifying the horizontal
scanning resolution
Register 15
Register 06
Original sheet width
and output width
Registers 01
and 11 to 14
Setting for the original sheet
Y
Specifying the vertical
scanning resolution
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 53 of 58
N
Power off?
N
Next original
sheet
Y
Next original
sheet?
N
Power off
End
Completed?
A
Peak value
detection White correction
AGC starts.
Transfer to be
continued?
1 line cycle
× 2 wait
The light source
is turned off.
Y
N
SRDY setting
Reading the original sheet ends.
Completed?
Next original sheet
1 line cycle
× 10 (or 8 or more) wait
Register 15
Completed?
Y
1 line cycle
× 20 (or 16 or more) wait
Specifying the scaling factor
for vertical scanning
Initial setting
Register 10
The light source is turned on.
(white reference)
Register 00
Register 05
Writing the dither pattern
N
Reading an original sheet starts.
Register 03 and 04
Register 08 to 0E
Writing γ correction table
Register 06 and 07
Register 02
Image processing parameters
N
Image processing function
Y
Register 00
Reading a single page
Sensor control
A
M66335FP
Reading Operations (for the CIS Sensor)
Start
Power on
Software reset
S/H: SH pulse width
Register 00
Image processing function
Register 06
and 07
Reading an original sheet starts.
Register 00
Register 01
Register 02
Specifying the scaling factor
for vertical scanning
Cycle counter
Register 05
Image processing parameters
Registers 08 to 0E
Writing the dither pattern
Register 10
Initial setting
Start pulse
Register 15
Registers 03 and 04
N
SRDY setting
Register 16
INT generated?
Register 17
Y
N
Page end?
Y
N
Completed?
Reading the original sheet ends.
Y
Writing γ correction table
N
Y
Register 0F
N
Completed?
Next original sheet
Y
AGC starts.
Register 00
AGC: 16 times
1 line cycle
× 20 (or 16 or more) wait
AGC ends.
Peak value
detection
The light source is turned on.
(white reference)
Becomes stable.
Transfer to be
continued?
Register 00
1 line cycle
× 2 wait
The light source is
turned off.
Power off?
N
Next original
sheet
Y
Next original
sheet?
N
The light source is turned off.
Uniformity correction
mode (black)
Uniformity correction starts.
Registers 00 and 01
Register 00
Black correction: 8 times
1 line cycle
× 10 (or 8 or more) wait
Uniformity correction
mode (white)
Uniformity correction starts.
Register 00
Registers 00 and 01
Register 00
White correction: 8 times
1 line cycle
× 10 (or 8 or more) wait
Uniformity correction ends.
Register 00
Specifying the horizontal
scanning resolution
Register 06
N
Completed?
Y
Specifying the vertical
scanning resolution
Register 06
Original sheet width
and output width
Registers 01
and 11 to 14
A
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 54 of 58
Setting for the original sheet
Writing the resolution change table Register 15
White correction
The light source is turned on.
(white reference)
Becomes stable.
Uniformity correction ends.
Black correction
Becomes stable.
Power off
End
Y
Register 00
Reading a single page
Sensor control
A
M66335FP
MPU Interface
Timing for Read Operation (M66335 → MPU)
3V
CS
1.3 V
1.3 V
0V
tSU (CS-RD)
th (RD-CS)
3V
A0 to A4
1.3 V
1.3 V
0V
tSU (A-RD)
tW (RD)
th (RD-A)
3V
RD
1.3 V
1.3 V
tPZL (RD-D)
D0 to D7
50%
10%
tPZH (RD-D)
D0 to D7
0V
tPLZ (RD-D)
VOL
tPHZ (RD-D)
VOH
90%
50%
Timing for Write Operation (MPU → M66335)
3V
CS
1.3 V
1.3 V
0V
tSU (CS-WR)
th (WR-CS)
3V
A0 to A4
1.3 V
1.3 V
0V
tSU (A-WR)
tW (WR)
th (WR-A)
3V
WR
1.3 V
1.3 V
0V
tSU (D-WR)
tSU (WR-D)
3V
D0 to D7
1.3 V
Effective data
1.3 V
0V
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 55 of 58
M66335FP
DMA Timing
Timing for Read Operation (M66335 → System Bus)
VOH
DRQ
50%
50%
VOL
120 / SYSCK
tPHL (RD-DRQ)
3V
DAK
1.3 V
1.3 V
0V
tSU (DAK-RD)
tW (RD)
th (RD-DAK)
3V
RD
1.3 V
1.3 V
tPZL (RD-D)
D0 to D7
50%
tPZH (RD-D)
D0 to D7
0V
tPLZ (RD-D)
10%
VOL
tPHZ (RD-D)
50%
90%
VOH
Timing of CODEC
th (STIM-SRDY)
3V
SRDY
1.3 V
0V
VOH
STIM
50%
VOL
VOH
SCLK
VOL
VOH
SVID
VOL
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 56 of 58
M66335FP
Cautions for Use
(1) Access to Address 00h
To gain access to address 00h, the value of built-in GCC (gain control counter) may be set to FFh.
This requires to read GAIN value at address 18h before access to address 00h and write the GAIN value at address 18h
after the access (see flowchart A).
Start
Read GAIN value at address 18h
Access address 00h
Write GAIN value at address 18h
End
Flowchart A Address 00h Access Flow
(2) Reset
The M66335FP adopts the two types of reset. These reset functions are provided in table A.
Table A Reset Functions
Function
Reset Type
Hardware reset (RESET)
Software reset register 0 (RESET)
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 57 of 58
Register
Initialization
Internal F/F
Initialization
GCC
Initialization
{
{
{
{
{
M66335FP
Package Dimensions
JEITA Package Code
P-QFP80-14x20-0.80
RENESAS Code
PRQP0080GB-A
Previous Code
80P6N-A
MASS[Typ.]
1.6g
HD
*1
D
64
41
65
HE
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
ZE
*2
E
40
Reference
Symbol
80
25
1
ZD
24
D
E
A2
HD
HE
A
A1
bp
c
c
Index mark
A
A2
F
*3
y
bp
L
A1
e
Detail F
REJ03F0276-0200 Rev.2.00 Jun 16, 2008
Page 58 of 58
e
y
ZD
ZE
L
Dimension in Millimeters
Min Nom Max
19.8 20.0 20.2
13.8 14.0 14.2
2.8
22.5 22.8 23.1
16.5 16.8 17.1
3.05
0.1 0.2
0
0.3 0.35 0.45
0.13 0.15 0.2
0°
10°
0.65 0.8 0.95
0.10
0.8
1.0
0.4 0.6 0.8
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