CY62168EV30 MoBL® 16-Mbit (2M x 8) Static RAM Features toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW). The input and output pins (IO0 through IO7) are placed in a high impedance state when: the device is deselected (Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW), outputs are disabled (OE HIGH), or a write operation is in progress (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and WE LOW). • Very high speed: 45 ns • Wide voltage range: 2.20V – 3.60V • Ultra low standby power — Typical standby current: 1.5 µA — Maximum standby current: 12 µA • Ultra low active power • • • • — Typical active current: 2.2 mA @ f = 1 MHz Easy memory expansion with CE1, CE2 and OE features Automatic power down when deselected CMOS for optimum speed/power Offered in Pb-free 48-ball FBGA package. For Pb-free 48-pin TSOP I package, refer to CY62167EV30 data sheet. Functional Description[1] The CY62168EV30 is a high performance CMOS static RAM organized as 2M words by 8 bits. This device features advanced circuit design to provide an ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption by 90% when addresses are not Write to the device by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and the Write Enable (WE) input LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A20). Read from the device by taking Chip Enable 1 (CE1) and Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the IO pins. The eight input and output pins (IO0 through IO7) are placed in a high impedance state when the device is deselected (CE1 LOW and CE2 HIGH), the outputs are disabled (OE HIGH), or a write operation is in progress (CE1 LOW and CE2 HIGH and WE LOW). See the “Truth Table” on page 8 for a complete description of read and write modes. Logic Block Diagram CE1 CE2 IO0 DATA IN DRIVERS IO1 IO2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 2M x 8 ARRAY IO3 IO4 IO5 IO6 COLUMN DECODER WE A18 A19 A20 A13 A14 A15 A16 A17 OE IO7 POWER DOWN Note 1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Cypress Semiconductor Corporation Document #: 001-07721 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 07, 2007 [+] Feedback CY62168EV30 MoBL® Pin Configuration [2] 48-Ball FBGA Top View 1 2 3 4 5 6 NC OE A0 A1 A2 CE2 A NC NC A3 A4 CE1 NC B IO0 NC A5 A6 NC IO4 C VSS IO1 A17 A7 IO5 VCC D VCC IO2 NC A16 IO6 VSS E IO3 NC A14 A15 NC IO7 F NC A20 A12 A13 WE NC G A18 A8 A9 A10 A11 A19 H Product Portfolio Power Dissipation VCC Range (V) Product CY62168EV30LL Speed (ns) Min Typ[3] Max 2.2 3.0 3.6 45 Operating ICC (mA) f = 1 MHz Standby ISB2 (µA) f = fmax Typ[3] Max Typ[3] Max Typ[3] Max 2.2 4.0 25 30 1.5 12 Notes 2. NC pins are not connected on the die. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. Document #: 001-07721 Rev. *B Page 2 of 10 [+] Feedback CY62168EV30 MoBL® DC Input Voltage[4, 5] .................... –0.3V to VCC(max) + 0.3V Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature .................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... > 2001V (MIL-STD-883, Method 3015) Latch up Current..................................................... > 200 mA Operating Range Supply Voltage to Ground Potential ....................................... –0.3V to VCC(max) + 0.3V Range VCC[7] DC Voltage Applied to Outputs in High-Z State[4, 5] ....................... –0.3V to VCC(max) + 0.3V Ambient Temperature (TA)[6] Industrial –40°C to +85°C 2.2V – 3.6V DC Electrical Characteristics Over the Operating Range Parameter Description VOH Output HIGH Voltage VOL Output LOW Voltage VIH VIL Input HIGH Voltage Input LOW Voltage Test Conditions CY62168EV30-45 Min Typ[3] Max 2.2 < VCC < 2.7 IOH = −0.1 mA 2.0 2.7 < VCC < 3.6 IOH = −1.0 mA 2.4 2.2 < VCC < 2.7 IOL = 0.1 mA 0.4 2.7 < VCC < 3.6 IOH = 2.1 mA 0.4 V 2.2 < VCC < 2.7 1.8 VCC + 0.3 2.7 < VCC < 3.6 2.2 VCC + 0.3 2.2 < VCC < 2.7 –0.3 0.6 2.7 < VCC < 3.6 –0.3 0.8 –1 +1 IIX Input Leakage Current GND < VI < VCC IOZ Output Leakage Current GND < VO < VCC, Output disabled ICC VCC Operating Supply Current f = fMAX = 1/tRC f = 1 MHz V V V µA +1 µA 25 30 mA 2.2 4.0 –1 VCC = 3.6V, IOUT = 0 mA, CMOS level Unit ISB1 Automatic CE Power Down CE1 > VCC − 0.2V, CE2 < 0.2V, Current — CMOS Inputs VIN > VCC − 0.2V, VIN < 0.2V, f = fMAX (Address and Data Only), f = 0 (OE, WE) 1.5 12 µA ISB2[8] Automatic CE Power Down CE1 > VCC − 0.2V, CE2 < 0.2V, Current— CMOS Inputs VIN > VCC − 0.2V or VIN < 0.2V, f = 0, VCC = 3.6V 1.5 12 µA Capacitance[9] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max Unit 8 pF 10 pF Notes 4. VIL(min) = –0.2V for pulse durations less than 20 ns. 5. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 6. TA is the “Instant-On” case temperature. 7. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 100 µs wait time after VCC stabilization. 8. Only chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 9. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-07721 Rev. *B Page 3 of 10 [+] Feedback CY62168EV30 MoBL® Thermal Resistance[9] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board BGA Unit 55 °C/W 16 °C/W AC Test Loads and Waveforms R1 VCC ALL INPUT PULSES VCC OUTPUT 30 pF GND R2 90% 10% 90% 10% Rise Time: 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: Fall time: 1 V/ns THÉVENIN EQUIVALENT RTH OUTPUT VTH Parameters 2.5V (2.2V to 2.7V) 3.0V (2.7V to 3.6V) Unit R1 16600 1103 Ω R2 15400 1554 Ω RTH 8000 645 Ω VTH 1.2 1.75 V Data Retention Characteristics Over the Operating Range Parameter Description Conditions VDR VCC for Data Retention ICCDR[8] Data Retention Current tCDR[9] Chip Deselect to Data Retention Time tR[10] Operation Recovery Time Min Typ[3] 1.5 VCC = 1.5V CE1 > VCC − 0.2V or CE2 < 0.2V VIN > VCC − 0.2V or VIN < 0.2V Max Unit 3.6 V 10 µA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC VCC(min) VDR > 1.5 V tCDR VCC(min) tR CE1 or CE2 Note 10. Full Device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs. Document #: 001-07721 Rev. *B Page 4 of 10 [+] Feedback CY62168EV30 MoBL® Switching Characteristics Over the Operating Range [11] Parameter Description 45 ns Min Max Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change 45 ns 45 10 ns ns tACE CE1 LOW and CE2 HIGH to Data Valid 45 ns tDOE OE LOW to Data Valid 22 ns tLZOE OE LOW to Low Z[12] 5 [12, 13] OE HIGH to High Z tHZOE 18 Z[12] tLZCE CE1 LOW and CE2 HIGH to Low tHZCE CE1 HIGH or CE2 LOW to High Z[12, 13] tPU CE1 LOW and CE2 HIGH to Power Up Write Cycle 10 ns ns 18 0 CE1 HIGH or CE2 LOW to Power Down tPD ns ns ns 45 ns [14] tWC Write Cycle Time 45 ns tSCE CE1 LOW and CE2 HIGH to Write End 35 ns tAW Address Setup to Write End 35 ns tHA Address Hold from Write End 0 ns tSA Address Setup to Write Start 0 ns tPWE WE Pulse Width 35 ns tSD Data Setup to Write End 25 ns tHD Data Hold from Write End 0 tHZWE WE LOW to High Z[12, 13] tLZWE [12] WE HIGH to Low Z ns 18 10 ns ns Notes 11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 4. 12. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 13. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 14. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 001-07721 Rev. *B Page 5 of 10 [+] Feedback CY62168EV30 MoBL® Switching Waveforms Figure 1 shows address transition controlled read cycle waveforms.[15, 16] Figure 1. Read Cycle No. 1 tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 2 shows OE controlled read cycle waveforms.[16, 17] Figure 2. Read Cycle No. 2 ADDRESS tRC CE1 tPD tHZCE CE2 tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB Notes 15. The device is continuously selected. OE, CE1 = VIL, and CE2 = VIH. 16. WE is HIGH for read cycle. 17. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH. Document #: 001-07721 Rev. *B Page 6 of 10 [+] Feedback CY62168EV30 MoBL® Switching Waveforms (continued) Figure 3 shows WE controlled write cycle waveforms.[14, 18, 19] Figure 3. Write Cycle No. 1 tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA WE tPWE OE tHD tSD DATA IO NOTE 20 VALID DATA tHZOE Figure 4 shows CE1 or CE2 controlled write cycle waveforms.[14, 18, 19] Figure 4. Write Cycle No. 2 tWC ADDRESS tSCE CE1 CE2 tSA tHA tPWE WE OE DATA IO tAW tSD NOTE 20 tHD VALID DATA tHZOE Notes 18. Data IO is high impedance if OE = VIH. 19. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 20. During this period the IOs are in output state. Do not apply input signals. Document #: 001-07721 Rev. *B Page 7 of 10 [+] Feedback CY62168EV30 MoBL® Switching Waveforms (continued) Figure 5 shows WE controlled, OE LOW write cycle waveforms.[19] Figure 5. Write Cycle No. 3 tWC ADDRESS tSCE CE1 CE2 tAW tSA tHA tPWE WE tSD NOTE 20 DATA IO tHD VALID DATA tLZWE tHZWE Truth Table CE1 CE2 WE OE H X X X High Z Inputs/Outputs Deselect/Power Down Mode Standby (ISB) Power X L X X High Z Deselect/Power Down Standby (ISB) L H H L Data Out (IO0-IO7) Read Active (ICC) L H H H High Z Output Disabled Active (ICC) L H L X Data in (IO0-IO7) Write Active (ICC) Ordering Information Speed (ns) 45 Ordering Code CY62168EV30LL-45BVXI Package Diagram Package Type 51-85150 48-ball Fine Pitch BGA (Pb-free) Operating Range Industrial Contact your local Cypress sales representative for availability of these parts. Document #: 001-07721 Rev. *B Page 8 of 10 [+] Feedback CY62168EV30 MoBL® Package Diagrams Figure 6. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150 BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 2 3 4 5 6 6 5 4 3 2 1 C C E F G D E 2.625 D 0.75 A B 5.25 A B 8.00±0.10 8.00±0.10 1 F G H H A 1.875 A B 0.75 6.00±0.10 3.75 6.00±0.10 0.15(4X) 0.10 C 0.21±0.05 0.25 C 0.55 MAX. B 1.00 MAX 0.26 MAX. SEATING PLANE C Document #: 001-07721 Rev. *B 51-85150-*D Page 9 of 10 © Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. [+] Feedback CY62168EV30 MoBL® Document History Page Document Title: CY62168EV30 MoBL® 16-Mbit (2M x 8) Static RAM Document Number: 001-07721 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 457686 See ECN NXR New Data Sheet *A 464509 See ECN NXR Removed TSOP I package; Added reference to CY62167EV30 TSOP I package which can be used as a 2M x 8 SRAM Changed the ISB2(Typ) value from 1.3 µA to 1.5 µA Changed the ICC(Typ) value from 2 mA to 2.2 mA for f=1MHz Test condition Changed the ICC(Typ) value from 15 mA to 22 mA and ICC(Max) value from 40 mA to 25 mA for f=1MHz Test condition Changed the ICCDR(Max) value from 8.5 µA to 8 µA *B 1138883 See ECN VKN Converted from preliminary to final Changed ICC(max) spec from 2.8 mA to 4.0 mA for f=1MHz Changed ICC(typ) spec from 22 mA to 25 mA for f=fmax Changed ICC(max) spec from 25 mA to 30 mA for f=fmax Added footnote# 8 related to ISB2 and ICCDR Changed ISB1 and ISB2 spec from 8.5 µA to 12 µA Changed ICCDR spec from 8 µA to 10 µA Document #: 001-07721 Rev. *B Page 10 of 10 [+] Feedback