19-1417; Rev 0; 12/98 MAX3693 Evaluation Kit The MAX3693 evaluation kit (EV kit) is an assembled, surface-mount demonstration board that provides easy evaluation of the MAX3693 622Mbps serializer with clock synthesis and LVDS inputs. Component List DESIGNATION QTY C4–C9, C11, C12, C16–C21 C13, C22 ♦ Single +3.3V Supply ♦ Selectable Clock-Reference Frequencies (155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz) ♦ Fully Assembled and Tested Surface-Mount Board DESCRIPTION 14 0.1µF, 10%, 25V min ceramic capacitors 2 1µF, 10%, 10V min ceramic capacitors X7R type C14 1 1µF, 10%, 25V min ceramic capacitor C15 1 33µF, ±10%, 10V min tantalum capacitor AVX TAJD336K010 L1–L5 1 56nH inductors Coilcraft 0805CS-560XKBC R1, R2, R11, C1–C3, C10, JU1, JU2, JU4, JU11–JU15 0 Not installed R3, R4 2 27Ω, 5% resistors R5, R6 2 220Ω, 5% resistors R7, R8 2 130Ω, 5% resistors R9, R10 2 24Ω, 5% resistors R12 1 20kΩ, 5% resistor Ordering Information PART MAX3693EVKIT TEMP. RANGE -40°C to +85°C IC PACKAGE 32 TQFP Detailed Description The MAX3693 EV kit simplifies evaluation of the MAX3693. The EV kit operates from a single +3.3V supply and includes all the external components necessary to interface with LVDS inputs and 3.3V PECL outputs. The LVDS inputs (PD_+, PD_-, PCLKI+, PCLKI-, RCLK+, RCLK-) are internally terminated with 100Ω differential input resistance, and therefore do not require external termination. Ensure that LVDS devices driving these inputs are not redundantly terminated. The LVDS outputs (PCLKO+, PCLKO-) require a differential termination with a 100Ω resistor between complementary outputs. PCLKI+, PCLKI-, PD0+, PD0-, PD1+, PD1-, PD2+, PD2-, PD3+, PD3-, PCLK0+, PCLK0- 12 SMB connectors (PC-mount) RCLK+, RCLK-, SD+, SD- 4 SMA connectors (PC-mount) GND, +3.3V 2 Test points JU3 1 2x3 pin header U1 1 MAX3693ECJ (32 TQFP) 1 MAX3693 PC board 1 MAX3693 data sheet 1 Shunt for JU3 Component Suppliers SUPPLIER Features PHONE FAX AVX 803-946-0690 803-626-3123 Coilcraft 847-639-6400 847-639-1469 The evaluation kit is designed to directly couple an LVDS reference clock. If the reference clock does not have LVDS-compatible levels: 1) Cut the PC board traces shorting capacitors C1 and C2. 2) Install 0.1µF capacitors. 3) Install 4.99kΩ resistors for R1 and R2 and tie the centerpoint of R1 and R2 (available at JU1) to VCC / 2. Install a 0.1µF capacitor at C3 for addtional noise filtering. The PECL outputs have an attenuation (0.6) and impedance matching network on the EV board that allow 50Ω terminations to ground for oscilloscope interfacing. All signal inputs and outputs use coupled 50Ω transmission lines. All input signal lines are of equal length to minimize propagation-delay skew. Likewise, all output signal lines are of equal length. The MAX3693 EV kit allows use of multiple reference clock frequencies with the appropriate setting on JU3. See Table 1 for jumper settings. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. Evaluates: MAX3693 General Description Evaluates: MAX3693 MAX3693 Evaluation Kit 1 C12 0.1µF C13 1µF JU3 3 5 +3.3V 4 6 R12 20k VCCVCO C11 0.1µF VCCPLL JU2 +3.3V 2 R11 OPEN JU4 RCLKC2 SHORT (PC TRACE) 28 VCCPLL 29 VCCDIG J3 30 PCLKI+ C5 0.1µF 31 J4 32 J5 GND GND GND CKSET SD- VCC VCC MAX3693 VCC VCC PCLKI+ PCLKO+ PCLKI- PCLKO- GND GND 1 PDO+ VCC RCLK- PD0+ PCLKI- C7 0.1µF SD+ RCLK+ 2 3 4 5 6 7 PD3- 27 8 C21 0.1µF +3.3V R7 130Ω 16 56nH R10 24Ω 14 13 12 VCCLVDS 10 9 +3.3V R8 130Ω J15 11 C6 0.1µF C9 0.1µF PCLKO+ J16 PCLKOJ11 PD3- VCCPLL 56nH 56nH C14 1µF J8 C18 0.1µF PD2- PD1- J10 PD2+ VCCECL JU14 L4 56nH GND J9 PD1+ VCCDIG JU13 L3 J17 +3.3V C15 33µF J18 J7 C17 0.1µF C19 0.1µF VCCLVDS JU15 L5 56nH C20 0.1µF Figure 1. MAX3693 EV Kit Schematic 2 R4 27Ω J14 SD- VCCECL C16 0.1µF JU12 L2 R6 220Ω C8 0.1µF J12 PD3+ VCCVCO JU11 L1 J13 15 J6 PDO- R3 27Ω SD+ 17 PD3+ C4 0.1µF 18 PD2- R2 OPEN 19 VCC PD2+ 26 20 GND PD1- C3 OPEN 21 PD1+ 25 22 FIL+ R1 OPEN J2 23 FIL- 24 JU1 R9 24Ω C10 OPEN C22 1µF PD0- RCLK+ VCCPLL GND J1 C1 SHORT (PC TRACE) _______________________________________________________________________________________ R5 220Ω MAX3693 Evaluation Kit Evaluates: MAX3693 Table 1. Jumper JU3 Functions SHUNT LOCATION REFERENCE CLOCK FREQUENCY (MHz) JU3 PIN LOCATIONS (SEE FIGURE 2) CKSET PIN JU3 1-2 155.52 Connected to VCC 3-4 51.84 Connected through 20kΩ resistor to GND 5-6 38.88 Connected to GND Open 77.76 Floating 1.0" 1 3 5 2 4 6 U1 MAX3693 1.0" Figure 2. MAX3693 EV Kit Component Placement Guide— Component Side Figure 3. MAX3693 EV Kit PC Board Layout—Component Side _______________________________________________________________________________________ 3 Evaluates: MAX3693 MAX3693 Evaluation Kit 1.0" 1.0" Figure 4. MAX3693 EV Kit PC Board Layout—Solder Side Figure 5. MAX3693 EV Kit PC Board Layout—Power Plane 1.0" Figure 6. MAX3693 EV Kit PC Board Layout—GND Plane Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 4 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.