CYPRESS CY8CLED08

CY8CLED08
EZ-Color™ HB LED Controller
Features
■
HB LED Controller
❐ Configurable Dimmers Support up to Eight
Independent LED Channels
❐ 8 to 32 Bits of Resolution per Channel
❐ Dynamic Reconfiguration Enables LED Controller Plus Other
Features: CapSense, Battery Charging, and Motor Control
■
Visual Embedded Design
❐ LED-Based Drivers
• Binning Compensation
• Temperature Feedback
• Optical Feedback
• DMX512
■
PrISM Modulation Technology
❐ Reduces Radiated EMI
❐ Reduces Low Frequency Blinking
■
Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ 3.0 to 5.25V Operating Voltage
❐ Operating Voltages Down to 1.0V using
On-Chip Switch Mode Pump (SMP)
❐ Industrial Temperature Range: -40°C to +85°C
■
■
Advanced Peripherals (PSoC® Blocks)
❐ Eight Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• Up to Two Full-Duplex UARTs
• Multiple SPI Masters or Slaves
• Connectable to all GPIO pins
❐ 12 Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ Complex peripherals by Combining Blocks
■
Programmable Pin Configurations
❐ 25 mA Sink, 10 mA Source on all GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on all GPIO
❐ Up to 12 Analog Inputs on GPIO
❐ Four 30 mA Analog Outputs on GPIO
❐ Configurable interrupt on all GPIO
■
Complete Development Tools
❐ Free Development Software
• PSoC Designer™
❐ Full Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128 KBytes Trace Memory
Flexible On-Chip Memory
❐ 16K Flash Program Storage 50,000 Erase/Write Cycles
❐ 256 bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
Cypress Semiconductor Corporation
Document Number: 001-12981 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•408-943-2600
Revised January 15, 2010
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Logic Block Diagram
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
Analog
Drivers
PSoC
CORE
System Bus
Global Digital Interconnect
SRAM
256 Bytes
Global Analog Interconnect
SROM
Flash 16K
CPU Core (M8C)
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref.
Digital
Block
Array
Digital
Clocks
Multiply
Accum.
Analog
Block
Array
POR and LVD
Decimator
I 2C
System Resets
Analog
Input
Muxing
Internal
Voltage
Ref.
Switch
Mode
Pump
SYSTEM RESOURCES
Document Number: 001-12981 Rev. *E
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Contents
1. EZ-Color™ Functional Overview ................................... 4
1.1 Target Applications .................................................. 4
1.2 The PSoC Core ....................................................... 4
1.3 The Digital System .................................................. 4
1.4 The Analog System ................................................. 5
1.1 Additional System Resources ................................. 6
1.2 EZ-Color Device Characteristics ............................. 6
2. Getting Started ................................................................ 6
2.1 Development Kits .................................................... 6
2.2 Technical Training Modules .................................... 6
2.3 Consultants ............................................................. 6
2.4 Technical Support ................................................... 6
2.5 Application Notes .................................................... 6
3. Development Tools ........................................................ 7
3.1 PSoC Designer Software Subsystems .................... 7
3.2 In-Circuit Emulator ................................................... 7
4. Document Conventions ................................................. 8
4.1 Acronyms Used ....................................................... 8
4.2 Units of Measure ..................................................... 8
4.3 Numeric Naming ...................................................... 8
5. Pin Information ............................................................... 9
5.1 Pinouts .................................................................... 9
6. Register Reference ....................................................... 12
6.1 Register Conventions ............................................ 12
6.2 Register Mapping Tables ...................................... 12
Document Number: 001-12981 Rev. *E
7. Electrical Specifications ...............................................15
7.1 Absolute Maximum Ratings ...................................16
7.2 Operating Temperature .........................................16
7.3 DC Electrical Characteristics ..................................17
7.4 AC Electrical Characteristics ..................................26
8. Packaging Information ..................................................35
8.1 Packaging Dimensions ...........................................35
8.1 Thermal Impedances .............................................38
8.2 Capacitance on Crystal Pins .................................38
8.3 Solder Reflow Peak Temperature ..........................38
9. Development Tool Selection ........................................39
9.1 Software Tools .......................................................39
9.2 Hardware Tools ......................................................39
9.3 Evaluation Tools .....................................................39
9.4 Device Programmers ..............................................40
9.5 Accessories (Emulation and Programming) ...........41
9.6 Third Party Tools ....................................................41
9.7 Build a PSoC Emulator into Your Board .................41
10. Ordering Information ...................................................42
10.1 Key Device Features ............................................42
10.2 Ordering Code Definitions ...................................42
11. Document History Page ..............................................43
12. Sales, Solutions, and Legal Information ...................44
12.1 Worldwide Sales and Design Support ..................44
12.2 Products ...............................................................44
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1. EZ-Color™ Functional Overview
Cypress' EZ-Color family of devices offers the ideal control
solution for High Brightness LED applications requiring intelligent dimming control. EZ-Color devices combine the power and
flexibility of PSoC (Programmable System-on-Chip). Cypress'
PrISM (precise illumination signal modulation) modulation
technology provides lighting designers a fully customizable and
integrated lighting solution platform.
The EZ-Color family supports a range of independent LED
channels from 4 channels at 32 bits of resolution each, up to 16
channels at 8 bits of resolution each. This enables lighting
designers the flexibility to choose the LED array size and color
quality. PSoC Designer software, with lighting specific drivers,
can significantly cut development time and simplify implementation of fixed color points through temperature, optical, and LED
binning compensation. EZ-Color's virtually limitless analog and
digital customization enable simple integration of features in
addition to intelligent lighting, such as battery charging, image
stabilization, and motor control during the development process.
These features, along with Cypress' best-in-class quality and
design support, make EZ-Color the ideal choice for intelligent HB
LED control applications.
Resource), provide the flexibility to integrate almost any timing
requirement into the EZ-Color device.
EZ-Color GPIOs provide connection to the CPU, digital and
analog resources of the device. Each pin’s drive mode may be
selected from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
1.3 The Digital System
The Digital System is composed of 8 digital blocks. Each block
is an 8-bit resource that can be used alone or combined with
other blocks to form 8, 16, 24, and 32-bit peripherals, which are
called user module references.
Figure 1-1. Digital System Block Diagram
Port 5
Port 3
Port 2
Digital Clocks
From Core
To System Bus
1.1 Target Applications
■
Large Signs
■
General Lighting
■
Architectural Lighting
■
Camera/Cell Phone Flash
DIGITAL SYSTEM
Row 0
DBB00
8
Row Input
Configuration
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose I/O).
The EZ-Color family incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate
to 2.5% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
Sleep timer and WDT. If crystal accuracy is desired, the ECO
(32.768 kHz external crystal oscillator) is available for use as a
Real Time Clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Document Number: 001-12981 Rev. *E
DCB03
Row 1
DBB10
DBB11
DCB12
8
4
Row Output
Configuration
1.2 The PSoC Core
Memory encompasses 16K of Flash for program storage, 256
bytes of SRAM for data storage, and up to 2K of EEPROM
emulated using the Flash. Program Flash uses four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
DCB02
8
Flashlights
The M8C CPU core is a powerful processor with speeds up to 48
MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with 17 vectors, to
simplify programming of real time embedded events. Program
execution is timed and protected using the included Sleep and
Watch Dog Timers (WDT).
DBB01
4
4
8
■
To Analog
System
Digital PSoC Block Array
Row Input
Configuration
LCD Backlight
Port 0
Row Output
Configuration
■
Port 1
Port 4
DCB13
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Digital peripheral configurations include the following:
■
PrISM (8 to 32 bit)
■
PWMs (8 to 32 bit)
■
PWMs with Dead band (8 to 32 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
UART 8 bit with selectable parity (up to 2)
■
SPI slave and master (up to 2)
■
I2C slave and multi-master (1 available as a System Resource)
■
Cyclical Redundancy Checker/Generator (8 to 32 bit)
■
IrDA (up to 2)
■
Generators (8 to 32 bit)
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Digital blocks are provided in rows of four, where the number of
blocks varies by EZ-Color device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in the table titled EZ-Color Device Characteristics.
1.4 The Analog System
The analog system is composed of 12 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common EZ-Color analog functions (most
available as user modules) are as follows:
■
Analog-to-digital converters (up to 4, with 6- to 14-bit resolution,
selectable as Incremental, Delta Sigma, and SAR)
■
Filters (2, 4, 6, and 8 pole band-pass, low-pass, and notch)
■
Amplifiers (up to 4, with selectable gain to 48x)
■
Instrumentation amplifiers (up to 2, with selectable gain to 93x)
■
Comparators (up to 4, with 16 selectable thresholds)
■
DACs (up to 4, with 6- to 9-bit resolution)
■
Multiplying DACs (up to 4, with 6- to 9-bit resolution)
■
High current output drivers (four with 30 mA drive as a Core
Resource)
■
1.3V reference (as a System Resource)
■
DTMF Dialer
■
Modulators
■
Correlators
■
Peak detectors
■
Many other topologies possible
Analog blocks are provided in columns of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in the figure below.
Figure 1-2. Analog System Block Diagram
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
AGNDIn RefIn
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also enable signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
P2[3]
P2[1]
P2[6]
P2[4]
P2[2]
P2[0]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
Block Array
ACB00
ACB01
ACB02
ACB03
ASC10
ASD11
ASC12
ASD13
ASD20
ASC21
ASD22
ASC23
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-12981 Rev. *E
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1.1 Additional System Resources
■
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include a multiplier, decimator, switch mode
pump, low voltage detection, and power on reset. Statements
describing the merits of each system resource are below.
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
■
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital blocks as clock dividers.
■
Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.
■
■
Multiply accumulate (MAC) provides fast 8-bit multiplier with
32-bit accumulate, to assist in general math and digital filters.
An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■
An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
1.2 EZ-Color Device Characteristics
Depending on your EZ-Color device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4
analog blocks. The following table lists the resources available for specific EZ-Color device groups. The device covered by this data
sheet is shown in the highlighted row of the table
CapSense
SRAM
Size
4
8
0
2
4
256 Bytes
4K
No
1
4
48
2
2
6
1K
16K
Yes
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8
44
2
8
12
4
4
12
256 Bytes
16K
No
CY8CLED16
16
44
4
16
12
4
4
12
2K
32K
No
Flash
Size
Analog
Blocks
Analog
Columns
Analog
Outputs
1
56
Digital
Blocks
16
4
Digital
Rows
2
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Digital
I/O
CY8CLED02
Part Number
Analog
Inputs
LED
Channels
Table 1-1. EZ-Color Device Characteristics
2. Getting Started
The quickest path to understanding the EZ-Color silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the EZ-Color integrated circuit and presents specific pin,
register, and electrical specifications.
For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest device data sheets on the web
at http://www.cypress.com/ez-color.
2.1 Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com/store, click Lighting & Power Control to
view a current list of available items.
2.2 Technical Training Modules
2.3 Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com, click on Design
Support located at the center of the web page, and select
CYPros Consultants.
2.4 Technical Support
Application engineers take pride in fast and accurate response.
They can be reached with a 4-hour guaranteed response at
http://www.cypress.com/support.
2.5 Application Notes
A long list of application notes will assist you in every aspect of
your design effort. To view the application notes, go to the
http://www.cypress.com web site and select Application Notes
under the Documentation tab.
Free PSoC technical training modules are available for users
new to PSoC. Training modules cover designing, debugging,
advanced analog and CapSense. Go to
http://www.cypress.com/techtrain.
Document Number: 001-12981 Rev. *E
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3. Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party
assemblers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
3.1 PSoC Designer Software Subsystems
3.1.1 System-Level View
A drag-and-drop visual embedded system design environment
based on PSoC Designer. In the system level view you create a
model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state
based upon any or all other system devices. Based upon the
design, PSoC Designer automatically selects one or more PSoC
Mixed-Signal Controllers that match your system requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
3.1.2 Chip-Level View
The chip-level view is a more traditional Integrated Development
Environment (IDE) based on PSoC Designer. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
blocks. Examples of user modules are ADCs, DACs, Amplifiers,
and Filters. Configure the user modules for your chosen
application and connect them to each other and to the proper
pins. Then generate your project. This prepopulates your project
with APIs and libraries that you can use to program your
application.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
3.1.3 Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder, and common debug, emulation, and programming
tools.
Document Number: 001-12981 Rev. *E
3.1.4 Code Generation Tools
PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
3.1.5 Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
Debugger commands allow the designer to read and program
and read and write data memory, read and write I/O registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.
3.1.6 Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
3.2 In-Circuit Emulator
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
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4. Document Conventions
4.1 Acronyms Used
4.2 Units of Measure
The following table lists the acronyms that are used in this
document.
A units of measure table is located in the Electrical Specifications
section. Table 7-1 on page 15 lists all the abbreviations used to
measure the devices.
Acronym
AC
ADC
API
CPU
CT
DAC
DC
ECO
EEPROM
FSR
GPIO
GUI
HBM
ICE
ILO
IMO
I/O
IPOR
LSb
LVD
MSb
PC
PLL
POR
PPOR
PSoC®
PWM
SC
SLIMO
SMP
SRAM
Description
alternating current
analog-to-digital converter
application programming interface
central processing unit
continuous time
digital-to-analog converter
direct current
external crystal oscillator
electrically erasable programmable read-only
memory
full scale range
general purpose I/O
graphical user interface
human body model
in-circuit emulator
internal low speed oscillator
internal main oscillator
input/output
imprecise power on reset
least-significant bit
low voltage detect
most-significant bit
program counter
phase-locked loop
power on reset
precision power on reset
Programmable System-on-Chip
pulse width modulator
switched capacitor
slow IMO
switch mode pump
static random access memory
Document Number: 001-12981 Rev. *E
4.3 Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.
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5. Pin Information
5.1 Pinouts
5.1.1 48-Pin Part Pinout SSOP
Table 5-1. 48-Pin Part Pinout (SSOP)
Pin
No.
Type
Digital
Analog
Pin
Name
1
I/O
I
P0[7]
Analog column mux input.
2
I/O
I/O
P0[5]
Analog column mux input and column output.
3
I/O
I/O
P0[3]
Analog column mux input and column output.
4
I/O
I
P0[1]
Analog column mux input.
5
I/O
P2[7]
6
I/O
P2[5]
7
I/O
I
P2[3]
Direct switched capacitor block input.
8
I/O
I
P2[1]
Direct switched capacitor block input.
9
I/O
P4[7]
10
I/O
P4[5]
11
I/O
P4[3]
12
I/O
13
P4[1]
Power
SMP
Switch Mode Pump (SMP) connection to external
components required.
14
I/O
P3[7]
15
I/O
P3[5]
16
I/O
P3[3]
17
I/O
P3[1]
18
I/O
P5[3]
19
I/O
P5[1]
20
I/O
P1[7]
I2C Serial Clock (SCL).
21
I/O
P1[5]
I2C Serial Data (SDA).
22
I/O
P1[3]
23
I/O
P1[1]
Crystal Input (XTALin), I2C Serial Clock (SCL),
ISSP SCLK[1].
24
Power
Figure 5-1. 48-Pin Device
Description
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P0[1]
P2[7]
P2[5]
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
SSOP
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Vdd
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6], External VRef
P2[4], External AGND
P2[2], A, I
P2[0], A, I
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P5[2]
P5[0]
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
Vss
Ground connection.
25
I/O
P1[0]
Crystal Output (XTALout), I2C Serial Data (SDA),
ISSP SDATA[1].
26
I/O
P1[2]
27
I/O
P1[4]
28
I/O
P1[6]
39
I/O
29
I/O
P5[0]
39
I/O
30
I/O
P5[2]
40
I/O
I
P2[0]
Direct switched capacitor block input.
31
I/O
P3[0]
41
I/O
I
P2[2]
Direct switched capacitor block input.
32
I/O
P3[2]
42
I/O
P2[4]
External Analog Ground (AGND).
33
I/O
P3[4]
43
I/O
P2[6]
External Voltage Reference (VRef).
34
I/O
35
Optional External Clock Input (EXTCLK).
P3[6]
Input
XRES
Pin
No.
Digital
Analog
Pin
Name
Description
P4[6]
P4[6]
44
I/O
I
P0[0]
Analog column mux input.
Active high external reset with internal pull down. 45
I/O
I/O
P0[2]
Analog column mux input and column output.
Analog column mux input and column output.
36
I/O
P4[0]
46
I/O
I/O
P0[4]
37
I/O
P4[2]
47
I/O
I
P0[6]
Analog column mux input.
38
I/O
P4[4]
48
Vdd
Supply voltage.
Power
LEGEND: A = Analog, I = Input, and O = Output.
Note
1. These are the ISSP pins, which are not High Z at POR.
Document Number: 001-12981 Rev. *E
Page 9 of 44
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CY8CLED08
5.1.2 48-Pin Part Pinout QFN
Table 5-2. 48-Pin Part Pinout (QFN)[2]
Pin
Name
I/O
I
P2[3]
Direct switched capacitor block input.
2
I/O
I
P2[1]
Direct switched capacitor block input.
3
I/O
P4[7]
4
I/O
P4[5]
5
I/O
P4[3]
6
I/O
P2[5]
P2[7]
P0[1], A, I
P0[3], A, IO
P0[5], A, IO
P0[7], A, I
1
8
I/O
P3[7]
9
I/O
P3[5]
10
I/O
P3[3]
11
I/O
P3[1]
12
I/O
P5[3]
13
I/O
P5[1]
14
I/O
P1[7]
I2C Serial Clock (SCL).
15
I/O
P1[5]
I2C Serial Data (SDA).
16
I/O
P1[3]
17
I/O
P1[1]
18
Power
Crystal Input (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK[1].
Vss
Ground connection.
19
I/O
P1[0]
Crystal Output (XTALout), I2C Serial Data (SDA),
ISSP-SDATA[1].
20
I/O
P1[2]
21
I/O
P1[4]
22
I/O
P1[6]
23
I/O
P5[0]
24
I/O
P5[2]
25
I/O
P3[0]
26
I/O
P3[2]
27
I/O
P3[4]
28
I/O
29
Optional External Clock Input (EXTCLK).
1
2
3
4
5
6
7
8
9
10
11
12
QFN
(Top View)
36
35
34
33
32
31
30
29
28
27
26
25
P2[4], External AGND
P2[2], A, I
P2[0], A, I
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P3[6]
Input
XRES
Active high external reset with internal pull down.
30
I/O
P4[0]
31
I/O
P4[2]
32
I/O
P4[4]
33
I/O
34
I/O
I
P2[0]
Direct switched capacitor block input.
35
I/O
I
P2[2]
Direct switched capacitor block input.
36
I/O
P2[4]
External Analog Ground (AGND).
37
I/O
P2[6]
External Voltage Reference (VRef).
38
I/O
I
P0[0]
Analog column mux input.
39
I/O
I/O
P0[2]
Analog column mux input and column output.
40
I/O
I/O
P0[4]
Analog column mux input and column output.
41
I/O
I
P0[6]
Analog column mux input.
42
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
I2C SCL, XTALin, P1[1]
Vss
I2C SDA, XTALout, P1[0]
P1[2]
EXTCLK, P1[4]
P1[6]
P5[0]
P5[2]
Switch Mode Pump (SMP) connection to external
components required.
I2C SDA, P1[5]
P1[3]
SMP
48
47
46
45
44
43
42
41
40
39
38
37
P4[1]
Power
13
14
15
16
17
18
19
20
21
22
23
24
7
Figure 5-2. 48-Pin Device
Description
Analog
Vdd
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6], External VRef
Type
Digital
P5[1]
I2C SCL, P1[7]
Pin
No.
P4[6]
Power
Vdd
Supply voltage.
43
I/O
I
P0[7]
Analog column mux input.
44
I/O
I/O
P0[5]
Analog column mux input and column output.
45
I/O
I/O
P0[3]
Analog column mux input and column output.
46
I/O
I
P0[1]
Analog column mux input.
47
I/O
P2[7]
48
I/O
P2[5]
LEGEND: A = Analog, I = Input, and O = Output.
Note
2. The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
should be electrically floated and not connected to any other signal.
Document Number: 001-12981 Rev. *E
Page 10 of 44
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CY8CLED08
5.0.1 28-Pin Part Pinout
Table 5-3. 28-Pin Part Pinout (SSOP)
Pin
No.
Type
Digital
Analog
Pin
Name
Description
1
I/O
I
P0[7]
Analog column mux input.
2
I/O
I/O
P0[5]
Analog column mux input and column output.
3
I/O
I/O
P0[3]
Analog column mux input and column output.
4
I/O
I
P0[1]
Analog column mux input.
5
I/O
6
I/O
7
I/O
I
P2[3]
Direct switched capacitor block input.
8
I/O
I
P2[1]
Direct switched capacitor block input.
SMP
Switch Mode Pump (SMP) connection to
external components required.
9
P2[7]
P2[5]
Power
10
I/O
P1[7]
I2C Serial Clock (SCL).
11
I/O
P1[5]
I2C Serial Data (SDA).
12
I/O
P1[3]
13
I/O
P1[1]
14
Power
Crystal Input (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK[1].
Vss
Ground connection.
15
I/O
P1[0]
Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA[1].
16
I/O
P1[2]
17
I/O
P1[4]
18
I/O
P1[6]
19
Input
XRES
Active high external reset with internal pull
down.
Direct switched capacitor block input.
I/O
I
P2[0]
21
I/O
I
P2[2]
Direct switched capacitor block input.
22
I/O
P2[4]
External Analog Ground (AGND).
23
I/O
P2[6]
External Voltage Reference (VRef).
24
I/O
I
P0[0]
Analog column mux input.
25
I/O
I/O
P0[2]
Analog column mux input and column output.
26
I/O
I/O
P0[4]
Analog column mux input and column output.
27
I/O
I
P0[6]
Analog column mux input.
Vdd
Supply voltage.
Power
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P0[1]
P2[7]
P2[5]
A, I, P2[3]
A, I,P2[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2CSCL, XTALin, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6], External VRef
P2[4], External AGND
P2[2], A, I
P2[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2CSDA
Optional External Clock Input (EXTCLK).
20
28
Figure 5-3. 28-Pin Device
LEGEND: A = Analog, I = Input, and O = Output.
Document Number: 001-12981 Rev. *E
Page 11 of 44
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CY8CLED08
6. Register Reference
This chapter lists the registers of the CY8CLED08 EZ-Color device.
6.1 Register Conventions
The register conventions specific to this section are listed in the following table. Register Mapping Tables
Convention
R
Description
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
6.2 Register Mapping Tables
The device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two
banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in
Bank 1.
Note In the following register mapping tables, blank fields are reserved and should not be accessed.
Table 6-1. Register Map Bank 0 Table: User Space
Addr (0,Hex)
Access
PRT0DR
Name
00
RW
Name
40
ASC10CR0
80
RW
C0
PRT0IE
01
RW
41
ASC10CR1
81
RW
C1
PRT0GS
02
RW
42
ASC10CR2
82
RW
C2
PRT0DM2
03
RW
43
ASC10CR3
83
RW
C3
PRT1DR
04
RW
44
ASD11CR0
84
RW
C4
PRT1IE
05
RW
45
ASD11CR1
85
RW
C5
PRT1GS
06
RW
46
ASD11CR2
86
RW
C6
PRT1DM2
07
RW
47
ASD11CR3
87
RW
C7
PRT2DR
08
RW
48
ASC12CR0
88
RW
C8
PRT2IE
09
RW
49
ASC12CR1
89
RW
C9
PRT2GS
0A
RW
4A
ASC12CR2
8A
RW
CA
PRT2DM2
0B
RW
4B
ASC12CR3
8B
RW
CB
PRT3DR
0C
RW
4C
ASD13CR0
8C
RW
CC
PRT3IE
0D
RW
4D
ASD13CR1
8D
RW
CD
PRT3GS
0E
RW
4E
ASD13CR2
8E
RW
CE
PRT3DM2
0F
RW
4F
ASD13CR3
8F
RW
CF
PRT4DR
10
RW
50
ASD20CR0
90
RW
D0
PRT4IE
11
RW
51
ASD20CR1
91
RW
D1
PRT4GS
12
RW
52
ASD20CR2
92
RW
D2
PRT4DM2
13
RW
53
ASD20CR3
93
RW
D3
PRT5DR
14
RW
54
ASC21CR0
94
RW
D4
PRT5IE
15
RW
55
ASC21CR1
95
RW
PRT5GS
16
RW
56
ASC21CR2
96
RW
I2C_CFG
D6
RW
PRT5DM2
17
RW
57
ASC21CR3
97
RW
I2C_SCR
D7
#
18
58
ASD22CR0
98
RW
I2C_DR
D8
RW
19
59
ASD22CR1
99
RW
I2C_MSCR
D9
#
1A
5A
ASD22CR2
9A
RW
INT_CLR0
DA
RW
1B
5B
ASD22CR3
9B
RW
INT_CLR1
DB
RW
1C
5C
ASC23CR0
9C
RW
1D
5D
ASC23CR1
9D
RW
INT_CLR3
DD
RW
1E
5E
ASC23CR2
9E
RW
INT_MSK3
DE
RW
1F
5F
ASC23CR3
9F
RW
AMX_IN
Addr (0,Hex)
60
Access
Addr (0,Hex)
Access
Name
Addr (0,Hex)
Access
D5
DC
DF
DBB00DR0
20
#
A0
INT_MSK0
E0
RW
DBB00DR1
21
W
61
A1
INT_MSK1
E1
RW
DBB00DR2
22
RW
62
A2
INT_VC
E2
RC
DBB00CR0
23
#
ARF_CR
63
RW
A3
RES_WDT
E3
W
DBB01DR0
24
#
CMP_CR0
64
#
A4
DEC_DH
E4
RC
DBB01DR1
25
W
ASY_CR
65
#
A5
DEC_DL
E5
RC
DBB01DR2
26
RW
CMP_CR1
66
RW
A6
DEC_CR0
E6
RW
Blank fields are Reserved and should not be accessed.
Document Number: 001-12981 Rev. *E
RW
Name
# Access is bit specific.
Page 12 of 44
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CY8CLED08
Table 6-1. Register Map Bank 0 Table: User Space (continued)
Addr (0,Hex)
Access
DBB01CR0
Name
27
#
Name
67
Addr (0,Hex)
Access
Name
A7
Addr (0,Hex)
Access
DEC_CR1
E7
RW
DCB02DR0
28
#
68
A8
MUL_X
E8
W
DCB02DR1
29
W
69
A9
MUL_Y
E9
W
DCB02DR2
2A
RW
6A
AA
MUL_DH
EA
R
DCB02CR0
2B
#
6B
AB
MUL_DL
EB
R
DCB03DR0
2C
#
6C
AC
ACC_DR1
EC
RW
DCB03DR1
2D
W
6D
AD
ACC_DR0
ED
RW
DCB03DR2
2E
RW
6E
AE
ACC_DR3
EE
RW
DCB03CR0
2F
#
6F
AF
ACC_DR2
EF
RW
DBB10DR0
30
#
ACB00CR3
70
RW
RDI0RI
B0
RW
F0
DBB10DR1
31
W
ACB00CR0
71
RW
RDI0SYN
B1
RW
F1
DBB10DR2
32
RW
ACB00CR1
72
RW
RDI0IS
B2
RW
F2
DBB10CR0
33
#
ACB00CR2
73
RW
RDI0LT0
B3
RW
F3
DBB11DR0
34
#
ACB01CR3
74
RW
RDI0LT1
B4
RW
F4
DBB11DR1
35
W
ACB01CR0
75
RW
RDI0RO0
B5
RW
F5
DBB11DR2
36
RW
ACB01CR1
76
RW
RDI0RO1
B6
RW
DBB11CR0
37
#
ACB01CR2
77
RW
DCB12DR0
38
#
ACB02CR3
78
RW
RDI1RI
B8
RW
F8
DCB12DR1
39
W
ACB02CR0
79
RW
RDI1SYN
B9
RW
F9
DCB12DR2
3A
RW
ACB02CR1
7A
RW
RDI1IS
BA
RW
FA
DCB12CR0
3B
#
ACB02CR2
7B
RW
RDI1LT0
BB
RW
FB
DCB13DR0
3C
#
ACB03CR3
7C
RW
RDI1LT1
BC
RW
FC
DCB13DR1
3D
W
ACB03CR0
7D
RW
RDI1RO0
BD
RW
DCB13DR2
3E
RW
ACB03CR1
7E
RW
RDI1RO1
BE
RW
DCB13CR0
3F
#
ACB03CR2
7F
RW
B7
Name
Access
F6
CPU_F
BF
Addr (0,Hex)
F7
RL
FD
CPU_SCR1
FE
#
CPU_SCR0
FF
#
# Access is bit specific.
Blank fields are Reserved and should not be accessed.
Table 6-2. Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
Add (1,Hex)
00
Access
RW
PRT0DM1
01
RW
PRT0IC0
02
RW
PRT0IC1
03
PRT1DM0
Name
Addr (1,Hex)
40
Access
Name
ASC10CR0
Addr (1,Hex)
80
Access
RW
Name
Addr (1,Hex)
C0
Access
41
ASC10CR1
81
RW
C1
42
ASC10CR2
82
RW
C2
RW
43
ASC10CR3
83
RW
C3
04
RW
44
ASD11CR0
84
RW
C4
PRT1DM1
05
RW
45
ASD11CR1
85
RW
C5
PRT1IC0
06
RW
46
ASD11CR2
86
RW
C6
PRT1IC1
07
RW
47
ASD11CR3
87
RW
C7
PRT2DM0
08
RW
48
ASC12CR0
88
RW
C8
PRT2DM1
09
RW
49
ASC12CR1
89
RW
C9
PRT2IC0
0A
RW
4A
ASC12CR2
8A
RW
CA
PRT2IC1
0B
RW
4B
ASC12CR3
8B
RW
CB
PRT3DM0
0C
RW
4C
ASD13CR0
8C
RW
CC
PRT3DM1
0D
RW
4D
ASD13CR1
8D
RW
CD
PRT3IC0
0E
RW
4E
ASD13CR2
8E
RW
CE
PRT3IC1
0F
RW
4F
ASD13CR3
8F
RW
PRT4DM0
10
RW
50
ASD20CR0
90
RW
GDI_O_IN
D0
RW
PRT4DM1
11
RW
51
ASD20CR1
91
RW
GDI_E_IN
D1
RW
PRT4IC0
12
RW
52
ASD20CR2
92
RW
GDI_O_OU
D2
RW
PRT4IC1
13
RW
53
ASD20CR3
93
RW
GDI_E_OU
D3
RW
PRT5DM0
14
RW
54
ASC21CR0
94
RW
D4
CF
PRT5DM1
15
RW
55
ASC21CR1
95
RW
D5
PRT5IC0
16
RW
56
ASC21CR2
96
RW
D6
PRT5IC1
17
RW
57
ASC21CR3
97
RW
D7
18
58
ASD22CR0
98
RW
D8
19
59
ASD22CR1
99
RW
D9
1A
5A
ASD22CR2
9A
RW
DA
1B
5B
ASD22CR3
9B
RW
DB
1C
5C
ASC23CR0
9C
RW
1D
5D
ASC23CR1
9D
RW
OSC_GO_EN
DD
RW
1E
5E
ASC23CR2
9E
RW
OSC_CR4
DE
RW
1F
5F
ASC23CR3
9F
RW
OSC_CR3
DF
RW
DC
DBB00FN
20
RW
CLK_CR0
60
RW
A0
OSC_CR0
E0
RW
DBB00IN
21
RW
CLK_CR1
61
RW
A1
OSC_CR1
E1
RW
DBB00OU
22
RW
ABF_CR0
62
RW
A2
OSC_CR2
E2
RW
Blank fields are Reserved and should not be accessed.
Document Number: 001-12981 Rev. *E
# Access is bit specific.
Page 13 of 44
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CY8CLED08
Table 6-2. Register Map Bank 1 Table: Configuration Space (continued)
Name
Add (1,Hex)
23
Access
Name
AMD_CR0
Addr (1,Hex)
63
Access
RW
Name
Addr (1,Hex)
A3
Access
Name
VLT_CR
Addr (1,Hex)
E3
Access
RW
VLT_CMP
E4
R
DBB01FN
24
RW
64
A4
DBB01IN
25
RW
65
A5
E5
DBB01OU
26
RW
E6
27
AMD_CR1
66
RW
A6
ALT_CR0
67
RW
A7
E7
DCB02FN
28
RW
ALT_CR1
68
RW
A8
IMO_TR
E8
W
DCB02IN
29
RW
CLK_CR2
69
RW
A9
ILO_TR
E9
W
DCB02OU
2A
RW
6A
AA
BDG_TR
EA
RW
6B
AB
ECO_TR
EB
W
2B
DCB03FN
2C
RW
6C
AC
EC
DCB03IN
2D
RW
6D
AD
ED
DCB03OU
2E
RW
6E
AE
EE
6F
AF
2F
EF
DBB10FN
30
RW
ACB00CR3
70
RW
RDI0RI
B0
RW
F0
DBB10IN
31
RW
ACB00CR0
71
RW
RDI0SYN
B1
RW
F1
DBB10OU
32
RW
ACB00CR1
72
RW
RDI0IS
B2
RW
F2
ACB00CR2
73
RW
RDI0LT0
B3
RW
F3
33
DBB11FN
34
RW
ACB01CR3
74
RW
RDI0LT1
B4
RW
F4
DBB11IN
35
RW
ACB01CR0
75
RW
RDI0RO0
B5
RW
F5
DBB11OU
36
RW
ACB01CR1
76
RW
RDI0RO1
B6
RW
ACB01CR2
77
RW
37
B7
F6
CPU_F
F7
RL
DCB12FN
38
RW
ACB02CR3
78
RW
RDI1RI
B8
RW
F8
DCB12IN
39
RW
ACB02CR0
79
RW
RDI1SYN
B9
RW
F9
DCB12OU
3A
RW
ACB02CR1
7A
RW
RDI1IS
BA
RW
FA
ACB02CR2
7B
RW
RDI1LT0
BB
RW
FB
FC
3B
DCB13FN
3C
RW
ACB03CR3
7C
RW
RDI1LT1
BC
RW
DCB13IN
3D
RW
ACB03CR0
7D
RW
RDI1RO0
BD
RW
DCB13OU
3E
RW
ACB03CR1
7E
RW
RDI1RO1
BE
RW
ACB03CR2
7F
RW
3F
Blank fields are Reserved and should not be accessed.
Document Number: 001-12981 Rev. *E
BF
FD
CPU_SCR1
FE
#
CPU_SCR0
FF
#
# Access is bit specific.
Page 14 of 44
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CY8CLED08
7. Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8CLED08 EZ-Color device. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at
http://www.cypress.com/ez-color.
Specifications are valid for -40°C ≤ TA ≤ 85°C and TJ ≤ 100°C, except where noted. Specifications for devices running at greater than
12 MHz are valid for -40°C ≤ TA ≤ 70°C and TJ ≤ 82°C.
Figure 7-1. Voltage versus CPU Frequency
5.25
Vdd Voltage
lid ng
Va rati n
pe io
O eg
R
4.75
3.00
93 kHz
CPU Frequency
12 MHz
24 MHz
The following table lists the units of measure that are used in this section.
Table 7-1. Units of Measure
Symbol
°C
dB
fF
Hz
KB
Kbit
kHz
kΩ
MHz
MΩ
μA
μF
μH
μs
μV
μVrms
Unit of Measure
degree Celsius
decibels
femto farad
hertz
1024 bytes
1024 bits
kilohertz
kilohm
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microvolts
microvolts root-mean-square
Document Number: 001-12981 Rev. *E
Symbol
μW
mA
ms
mV
nA
ns
nV
Ω
pA
pF
pp
ppm
ps
sps
σ
V
Unit of Measure
microwatts
milli-ampere
milli-second
milli-volts
nanoampere
nanosecond
nanovolts
ohm
picoampere
picofarad
peak-to-peak
parts per million
picosecond
samples per second
sigma: one standard deviation
volts
Page 15 of 44
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CY8CLED08
7.1 Absolute Maximum Ratings
Table 7-2. Absolute Maximum Ratings
Symbol
TSTG
TA
Vdd
VIO
VIOZ
IMIO
IMAIO
ESD
LU
Description
Storage Temperature
Min
-55
Typ
25
Max
+100
Units
°C
Ambient Temperature with Power
Applied
Supply Voltage on Vdd Relative to
Vss
DC Input Voltage
DC Voltage Applied to Tri-state
Maximum Current into any Port Pin
Maximum Current into any Port Pin
Configured as Analog Driver
Electro Static Discharge Voltage
Latch up Current
-40
–
+85
°C
-0.5
–
+6.0
V
Vss- 0.5
Vss - 0.5
-25
-50
–
–
–
–
Vdd + 0.5
Vdd + 0.5
+50
+50
V
V
mA
mA
2000
–
–
–
–
200
V
mA
Min
-40
-40
Typ
–
–
Max
+85
+100
Units
°C
°C
Notes
Higher storage temperatures will
reduce data retention time. Recommended storage temperature is
+25°C ± 25°C. Extended duration
storage temperatures above 65°C will
degrade reliability.
Human Body Model ESD.
7.2 Operating Temperature
Table 7-3. Operating Temperature
Symbol
TA
TJ
Description
Ambient Temperature
Junction Temperature
Document Number: 001-12981 Rev. *E
Notes
The temperature rise from ambient to
junction is package specific. See
“Thermal Impedances” on page 38.
The user must limit the power
consumption to comply with this
requirement.
Page 16 of 44
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CY8CLED08
7.3 DC Electrical Characteristics
7.3.1 DC Chip Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 7-4. DC Chip Level Specifications
Symbol
Vdd
IDD
Description
Supply Voltage
Supply Current
Min
3.00
–
Typ
–
5
Max
5.25
8
Units
V
mA
IDD3
Supply Current
–
3.3
6.0
mA
ISB
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT.[3]
–
3
6.5
μA
ISBH
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT at high temperature.[3]
–
4
25
μA
ISBXTL
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and external crystal.[3]
–
4
7.5
μA
ISBXTLH
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and external crystal at high
temperature.[3]
–
5
26
μA
VREF
VREF
Reference Voltage (Bandgap) for Silicon A [4]
Reference Voltage (Bandgap) for Silicon B [4]
1.275
1.280
1.300
1.300
1.325
1.320
V
V
Notes
Conditions are Vdd = 5.0V, TA = 25
°C, CPU = 3 MHz, SYSCLK
doubler disabled. VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 93.75
kHz.
Conditions are Vdd = 3.3V, TA = 25
°C, CPU = 3 MHz, SYSCLK
doubler disabled. VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 93.75
kHz.
Conditions are with internal slow
speed oscillator, Vdd = 3.3V, -40
°C ≤ TA ≤ 55 °C.
Conditions are with internal slow
speed oscillator, Vdd = 3.3V, 55 °C
< TA ≤ 85 °C.
Conditions are with properly
loaded, 1 μW max, 32.768 kHz
crystal. Vdd = 3.3V, -40 °C ≤ TA ≤
55 °C.
Conditions are with properly
loaded, 1 μW max, 32.768 kHz
crystal. Vdd = 3.3V, 55 °C < TA ≤
85 °C.
Trimmed for appropriate Vdd.
Trimmed for appropriate Vdd.
Notes
3. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar
functions enabled.
4. Refer to the “Ordering Information” on page 42.
Document Number: 001-12981 Rev. *E
Page 17 of 44
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CY8CLED08
7.4 DC General Purpose I/O Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 7-5. DC GPIO Specifications
Symbol
RPU
RPD
VOH
Description
Pull up Resistor
Pull down Resistor
High Output Level
Min
4
4
Vdd - 1.0
Typ
5.6
5.6
–
Max
8
8
–
Units
kΩ
kΩ
V
VOL
Low Output Level
–
–
0.75
V
IOH
High Level Source Current
10
–
–
mA
IOL
Low Level Sink Current
25
–
–
mA
VIL
VIH
VH
IIL
CIN
Input Low Level
Input High Level
Input Hysterisis
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
–
2.1
–
–
–
–
–
60
1
3.5
0.8
–
–
10
V
V
mV
nA
pF
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF
Notes
IOH = 10 mA, Vdd = 4.75 to 5.25V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])).
IOL = 25 mA, Vdd = 4.75 to 5.25V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])).
VOH = Vdd-1.0V. See the limitations
of the total current in the Note for
VOH.
VOL = 0.75V. See the limitations of
the total current in the Note for VOL.
Vdd = 3.0 to 5.25.
Vdd = 3.0 to 5.25.
Gross tested to 1 μA.
Package and pin dependent.
Temp = 25°C.
Package and pin dependent.
Temp = 25°C.
7.4.1 DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at
25°C and are for design guidance only.
Table 7-6. 5V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
TCVOSOA
IEBOA
Average Input Offset Voltage Drift
Input Leakage Current (Port 0 Analog
Pins)
Input Capacitance (Port 0 Analog Pins)
CINOA
Document Number: 001-12981 Rev. *E
Min
Typ
Max
Units
–
–
–
–
–
1.6
1.3
1.2
10
8
7.5
mV
mV
mV
7.0
20
35.0
–
μV/°C
pA
–
4.5
9.5
pF
Notes
Gross tested to 1 μA.
Package and pin dependent.
Temp = 25°C.
Page 18 of 44
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CY8CLED08
Table 7-6. 5V DC Operational Amplifier Specifications (continued)
Symbol
VCMOA
Description
Common Mode Voltage Range
Common Mode Voltage Range (high
power or high opamp bias)
CMRROA
Common Mode Rejection Ratio
Power = Low
Power = Medium
Power = High
Open Loop Gain
Power = Low
Power = Medium
Power = High
GOLOA
VOHIGHOA
VOLOWOA
ISOA
PSRROA
High Output Voltage Swing (internal
signals)
Power = Low
Power = Medium
Power = High
Low Output Voltage Swing (internal
signals)
Power = Low
Power = Medium
Power = High
Supply Current (including associated
AGND buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
Supply Voltage Rejection Ratio
Min
0.0
0.5
Typ
–
–
Max
Vdd
Vdd 0.5
Units
V
–
–
dB
–
–
dB
Vdd - 0.2
Vdd - 0.2
Vdd - 0.5
–
–
–
–
–
–
V
V
V
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
–
–
–
–
–
–
150
300
600
1200
2400
4600
200
400
800
1600
3200
6400
μA
μA
μA
μA
μA
μA
60
–
–
dB
60
60
60
60
60
80
Notes
The common-mode input voltage
range is measured through an
analog output buffer. The specification includes the limitations
imposed by the characteristics of
the analog output buffer.
Specification is applicable at high
power. For all other bias modes
(except high power, high opamp
bias), minimum is 60 dB.
Specification is applicable at high
power. For all other bias modes
(except high power, high opamp
bias), minimum is 60 dB.
Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd 1.25V) ≤ VIN ≤ Vdd.
Table 7-7. 3.3V DC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VOSOA
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
High Power is 5 Volts Only
–
–
1.65
1.32
10
8
mV
mV
TCVOSOA
Average Input Offset Voltage Drift
–
7.0
35.0
μV/°C
IEBOA
Input Leakage Current (Port 0 Analog
Pins)
–
20
–
pA
Gross tested to 1 μA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent. Temp =
25°C.
VCMOA
Common Mode Voltage Range
0.2
–
Vdd 0.2
V
The common-mode input voltage
range is measured through an analog
output buffer. The specification
includes the limitations imposed by
the characteristics of the analog
output buffer.
Document Number: 001-12981 Rev. *E
Page 19 of 44
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CY8CLED08
Table 7-7. 3.3V DC Operational Amplifier Specifications (continued)
Symbol
Description
Min
Typ
Max
Units
Notes
–
–
dB
Specification is applicable at high
power. For all other bias modes
(except high power, high opamp bias),
minimum is 60 dB.
–
–
dB
Specification is applicable at high
power. For all other bias modes
(except high power, high opamp bias),
minimum is 60 dB.
Vdd 0.2
Vdd 0.2
Vdd 0.2
–
–
–
–
–
–
V
V
V
CMRROA
Common Mode Rejection Ratio
Power = Low
Power = Medium
Power = High
50
50
50
GOLOA
Open Loop Gain
Power = Low
Power = Medium
Power = High
60
60
80
VOHIGHOA
High Output Voltage Swing (internal
signals)
Power = Low
Power = Medium
Power = High is 5V only
VOLOWOA
Low Output Voltage Swing (internal
signals)
Power = Low
Power = Medium
Power = High
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
ISOA
Supply Current (including associated
AGND buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
–
–
–
–
–
–
150
300
600
1200
2400
4600
200
400
800
1600
3200
6400
μA
μA
μA
μA
μA
μA
PSRROA
Supply Voltage Rejection Ratio
50
80
–
dB
Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd 1.25V) ≤ VIN ≤ Vdd.
7.4.2 DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.
Table 7-8. DC Low Power Comparator Specifications
Symbol
VREFLPC
ISLPC
VOSLPC
Description
Low power comparator (LPC) reference
voltage range
LPC supply current
LPC voltage offset
Document Number: 001-12981 Rev. *E
Min
0.2
Typ
–
Max
Vdd - 1
Units
V
–
–
10
2.5
40
30
μA
mV
Notes
Page 20 of 44
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CY8CLED08
7.4.3 DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 7-9. 5V DC Analog Output Buffer Specifications
Symbol
VOSOB
TCVOSOB
VCMOB
ROUTOB
VOHIGHOB
VOLOWOB
ISOB
PSRROB
Description
Input Offset Voltage (Absolute Value)
Average Input Offset Voltage Drift
Common-Mode Input Voltage Range
Output Resistance
Power = Low
Power = High
High Output Voltage Swing (Load = 32 ohms
to Vdd/2)
Power = Low
Power = High
Low Output Voltage Swing (Load = 32 ohms
to Vdd/2)
Power = Low
Power = High
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
Supply Voltage Rejection Ratio
Min
–
–
0.5
Typ
3
+6
–
Max
12
–
Vdd - 1.0
Units
mV
μV/°C
V
–
–
1
1
–
–
Ω
Ω
0.5 x Vdd + 1.3
0.5 x Vdd + 1.3
–
–
–
–
V
V
–
–
–
–
0.5 x Vdd - 1.3
0.5 x Vdd - 1.3
V
V
–
–
60
1.1
2.6
64
5.1
8.8
–
mA
mA
dB
Min
–
–
0.5
Typ
3
+6
-
Max
12
–
Vdd - 1.0
Units
mV
μV/°C
V
–
–
1
1
–
–
Ω
Ω
0.5 x Vdd + 1.0
0.5 x Vdd + 1.0
–
–
–
–
V
V
–
–
–
–
0.5 x Vdd - 1.0
0.5 x Vdd - 1.0
V
V
–
0.8
2.0
2.0
4.3
mA
mA
60
64
–
dB
Notes
Table 7-10. 3.3V DC Analog Output Buffer Specifications
Symbol
VOSOB
TCVOSOB
VCMOB
ROUTOB
VOHIGHOB
VOLOWOB
ISOB
PSRROB
Description
Input Offset Voltage (Absolute Value)
Average Input Offset Voltage Drift
Common Mode Input Voltage Range
Output Resistance
Power = Low
Power = High
High Output Voltage Swing (Load = 1k ohms
to Vdd/2)
Power = Low
Power = High
Low Output Voltage Swing (Load = 1k ohms
to Vdd/2)
Power = Low
Power = High
Supply Current Including Bias Cell (No
Load)
Power = Low
Power = High
Supply Voltage Rejection Ratio
Document Number: 001-12981 Rev. *E
Notes
Page 21 of 44
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CY8CLED08
7.4.4 DC Switch Mode Pump Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 7-11. DC Switch Mode Pump (SMP) Specifications
Symbol
VPUMP 5V
Description
5V Output Voltage
Min
4.75
Typ
5.0
Max
5.25
Units
V
VPUMP 3V
3V Output Voltage
3.00
3.25
3.60
V
IPUMP
VBAT5V
Available Output Current
VBAT = 1.5V, VPUMP = 3.25V
VBAT = 1.8V, VPUMP = 5.0V
Input Voltage Range from Battery
8
5
1.8
–
–
–
–
–
5.0
mA
mA
V
VBAT3V
Input Voltage Range from Battery
1.0
–
3.3
V
VBATSTART
1.1
–
–
V
ΔVPUMP_Line
Minimum Input Voltage from Battery to
Start Pump
Line Regulation (over VBAT range)
–
5
–
%VO
ΔVPUMP_Load
Load Regulation
–
5
–
%VO
–
100
–
mVpp
35
50
–
%
–
–
1.3
50
–
–
MHz
%
ΔVPUMP_Ripple Output Voltage Ripple (depends on
capacitor/load)
E3
Efficiency
FPUMP
DCPUMP
Switching Frequency
Switching Duty Cycle
Notes
Configuration of footnote.[5]
Average, neglecting ripple. SMP
trip voltage is set to 5.0V.
Configuration of footnote.[5]
Average, neglecting ripple. SMP
trip voltage is set to 3.25V.
Configuration of footnote.[5]
SMP trip voltage is set to 3.25V.
SMP trip voltage is set to 5.0V.
Configuration of footnote.[5] SMP
trip voltage is set to 5.0V.
Configuration of footnote.[5] SMP
trip voltage is set to 3.25V.
Configuration of footnote.[5]
Configuration of footnote.[5] VO is
the “Vdd Value for PUMP Trip”
specified by the VM[2:0] setting in
the DC POR and LVD Specification, Table 7-15 on page 24.
Configuration of footnote.[5] VO is
the “Vdd Value for PUMP Trip”
specified by the VM[2:0] setting in
the DC POR and LVD Specification, Table 7-15 on page 24.
Configuration of footnote.[5] Load
is 5 mA.
Configuration of footnote.[5] Load
is 5 mA. SMP trip voltage is set to
3.25V.
Figure 7-2. Basic Switch Mode Pump Circuit
D1
Vdd
L1
VBAT
+
VPUMP
C1
SMP
Battery
EZ-Color
Vss
Note
5. L1 = 2 μH inductor, C1 = 10 μF capacitor, D1 = Schottky diode.
Document Number: 001-12981 Rev. *E
Page 22 of 44
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CY8CLED08
7.3.7 DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 7-12. 5V DC Analog Reference Specifications
Symbol
Description
Min
Typ
Max
Units
1.28
1.30
1.32
V
AGND = Vdd/2[6]
Vdd/2 - 0.030
Vdd/2
Vdd/2 + 0.007
V
–
AGND = 2 x BandGap[6]
2 x BG - 0.043
2 x BG
2 x BG + 0.024
V
–
AGND = P2[4] (P2[4] = Vdd/2)[6]
P2[4] - 0.011
P2[4]
P2[4] + 0.011
V
–
AGND = BandGap[6]
BG - 0.009
BG
BG + 0.009
V
–
AGND = 1.6 x BandGap[6]
1.6 x BG - 0.018
1.6 x BG
1.6 x BG + 0.018
V
–
AGND Block to Block Variation (AGND = Vdd/2)[6]
-0.034
0.000
0.034
V
–
RefHi = Vdd/2 + BandGap
Vdd/2 + BG - 0.1
Vdd/2 + BG - 0.01
Vdd/2 + BG + 0.1
V
–
RefHi = 3 x BandGap
3 x BG - 0.06
3 x BG - 0.01
3 x BG + 0.06
V
–
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
–
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
–
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
–
RefHi = 3.2 x BandGap
–
RefLo = Vdd/2 – BandGap
–
RefLo = BandGap
–
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
–
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
–
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
BG
Bandgap Voltage Reference
–
2 x BG + P2[6] - 0.06 2 x BG + P2[6] - 0.01 2 x BG + P2[6] + 0.06
V
P2[4] + BG - 0.06
P2[4] + BG - 0.01
P2[4] + BG + 0.06
V
P2[4] + P2[6] - 0.06
P2[4] + P2[6] - 0.01
P2[4] + P2[6] + 0.06
V
3.2 x BG - 0.06
3.2 x BG - 0.01
3.2 x BG + 0.06
V
Vdd/2 - BG - 0.051
Vdd/2 - BG + 0.01
Vdd/2 - BG + 0.06
V
BG - 0.06
BG + 0.01
BG + 0.06
V
2 x BG - P2[6] - 0.04 2 x BG - P2[6] + 0.01 2 x BG - P2[6] + 0.04
V
P2[4] - BG - 0.056
P2[4] - BG + 0.01
P2[4] - BG + 0.056
V
P2[4] - P2[6] - 0.056
P2[4] - P2[6] + 0.01
P2[4] - P2[6] + 0.056
V
Table 7-13. 3.3V DC Analog Reference Specifications
Symbol
BG
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Description
Bandgap Voltage Reference
AGND = Vdd/2[6]
AGND = 2 x BandGap[6]
AGND = P2[4] (P2[4] = Vdd/2)
AGND = BandGap[6]
AGND = 1.6 x BandGap[6]
AGND Block to Block Variation (AGND = Vdd/2)[6]
RefHi = Vdd/2 + BandGap
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
RefHi = 3.2 x BandGap
RefLo = Vdd/2 - BandGap
RefLo = BandGap
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
Min
1.28
Vdd/2 - 0.027
P2[4] - 0.008
BG - 0.009
1.6 x BG - 0.018
-0.034
P2[4] + P2[6] - 0.06
Not Allowed
Not Allowed
Not Allowed
P2[4] - P2[6] - 0.048
Typ
Max
1.30
1.32
Vdd/2
Vdd/2 + 0.005
Not Allowed
P2[4]
P2[4] + 0.009
BG
BG + 0.009
1.6 x BG
1.6 x BG + 0.018
0.000
0.034
Not Allowed
Not Allowed
Not Allowed
Not Allowed
P2[4] + P2[6] - 0.01 P2[4] + P2[6] + 0.057
Not Allowed
Not Allowed
P2[4] - P2[6] + 0.01
P2[4] - P2[6] + 0.048
Units
V
V
V
V
V
mV
V
V
Note
6. AGND tolerance includes the offsets of the local buffer in the PSoC block.See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range
Operation” for information on trimming for operation at 3.3V.
Document Number: 001-12981 Rev. *E
Page 23 of 44
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7.3.8 DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 7-14. DC Analog PSoC Block Specifications
Symbol
RCT
CSC
Description
Resistor Unit Value (Continuous Time)
Capacitor Unit Value (Switched
Capacitor)
Min
–
–
Typ
12.2
80
Max
–
–
Units
kΩ
fF
Notes
7.3.9 DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register.
Table 7-15. DC POR and LVD Specifications
Symbol
Description
Vdd Value for PPOR Trip (positive
VPPOR0R ramp)
VPPOR1R PORLEV[1:0] = 00b
VPPOR2R PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VPPOR0
VPPOR1
VPPOR2
Vdd Value for PPOR Trip (negative
ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
Min
Typ
Max
Units
–
2.91
4.39
4.55
–
V
V
V
–
2.82
4.39
4.55
–
V
V
V
–
–
–
92
0
0
–
–
–
mV
mV
mV
VPH0
VPH1
VPH2
PPOR Hysteresis
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.86
2.96
3.07
3.92
4.39
4.55
4.63
4.72
2.92
3.02
3.13
4.00
4.48
4.64
4.73
4.81
2.98[7]
3.08
3.20
4.08
4.57
4.74[8]
4.82
4.91
V
V
V
V
V
V
V
V
V
VPUMP0
VPUMP1
VPUMP2
VPUMP3
VPUMP4
VPUMP5
VPUMP6
VPUMP7
Vdd Value for PUMP Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.96
3.03
3.18
4.11
4.55
4.63
4.72
4.90
3.02
3.10
3.25
4.19
4.64
4.73
4.82
5.00
3.08
3.16
3.32
4.28
4.74
4.82
4.91
5.10
V
V
V
V
V
V
V
V
Notes
Vdd must be greater than or equal to 2.5V
during startup, reset from the XRES pin, or
reset from Watchdog.
Notes
7. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
8. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
Document Number: 001-12981 Rev. *E
Page 24 of 44
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7.3.10 DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 7-16. DC Programming Specifications
Description
Min
Typ
Max
Units
IDDP
Symbol
Supply Current During Programming or Verify
–
5
25
mA
Notes
VILP
Input Low Voltage During Programming or
Verify
–
–
0.8
V
VIHP
Input High Voltage During Programming or
Verify
2.2
–
–
V
IILP
Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify
–
–
0.2
mA
Driving internal pull
down resistor.
IIHP
Input Current when Applying Vihp to P1[0] or
P1[1] During Programming or Verify
–
–
1.5
mA
Driving internal pull
down resistor.
VOLV
Output Low Voltage During Programming or
Verify
–
–
Vss + 0.75
V
VOHV
Output High Voltage During Programming or
Verify
Vdd - 1.0
–
Vdd
V
FlashENPB
Flash Endurance (per block)
50,000[9]
–
–
–
Erase/write cycles per
block.
FlashENT
Flash Endurance (total)[10]
1,800,000
–
–
–
Erase/write cycles.
FlashDR
Flash Data Retention
10
–
–
Years
Notes
9. The 50,000 cycle Flash endurance per block will only be guaranteed if the Flash is operating within one voltage range. Voltage ranges are 3.0V to 3.6V and 4.75V
to 5.25V.
10. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block
ever sees more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
Document Number: 001-12981 Rev. *E
Page 25 of 44
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7.4 AC Electrical Characteristics
7.4.1 AC Chip Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 7-17. AC Chip Level Specifications
Symbol
FIMO
Description
Internal Main Oscillator Frequency
Min
23.4
Typ
24
Max
24.6[11]
Units
MHz
FCPU1
CPU Frequency (5V Nominal)
0.093
24
24.6[11,12]
MHz
FCPU2
CPU Frequency (3.3V Nominal)
0.093
12
12.3[12,13]
MHz
F48M
Digital PSoC Block Frequency
0
48
49.2[11,12,14]
MHz
F24M
F32K1
F32K_U
Digital PSoC Block Frequency
Internal Low Speed Oscillator Frequency
Internal Low Speed Oscillator Untrimmed
Frequency
0
15
5
24
32
–
24.6[12, 14]
64
–
MHz
kHz
kHz
DCILO
F32K2
Internal Low Speed Oscillator Duty Cycle
External Crystal Oscillator
20
–
50
32.768
80
–
%
kHz
FPLL
PLL Frequency
–
23.986
–
MHz
–
0.5
0.5
–
–
–
600
10
50
ps
ms
ms
Jitter24M2 24 MHz Period Jitter (PLL)
TPLLSLEW
PLL Lock Time
TPLLSLEWSL PLL Lock Time for Low Gain Setting
Notes
Trimmed. Using factory trim
values.
Trimmed. Using factory trim
values.
Trimmed. Using factory trim
values.
Refer to the AC Digital Block
Specifications below.
After a reset and before the
m8c starts to run, the ILO is
not trimmed. See the System
Resets section of the PSoC
Technical Reference Manual
for details on timing this.
Accuracy is capacitor and
crystal dependent. 50% duty
cycle.
Multiple (x732) of crystal
frequency.
OW
TOS
TOSACC
External Crystal Oscillator Startup to 1%
External Crystal Oscillator Startup to 100 ppm
–
–
1700
2800
2620
3800
ms
ms
Jitter32k
TXRST
DC24M
Step24M
32 kHz Period Jitter
External Reset Pulse Width
24 MHz Duty Cycle
24 MHz Trim Step Size
–
10
40
–
100
–
50
50
–
60
–
ns
μs
%
kHz
The crystal oscillator
frequency is within 100 ppm
of its final value by the end of
the Tosacc period. Correct
operation assumes a
properly loaded 1 μW
maximum drive level 32.768
kHz crystal. 3.0V ≤ Vdd ≤
5.5V, -40 °C ≤ TA ≤ 85 °C.
Notes
11. 4.75V < Vdd < 5.25V.
12. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
13. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation
at 3.3V.
14. See the individual user module data sheets for information on maximum frequencies for user modules.
Document Number: 001-12981 Rev. *E
Page 26 of 44
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Table 7-17. AC Chip Level Specifications (continued)
Symbol
Fout48M
Description
48 MHz Output Frequency
Jitter24M1
FMAX
SRPOWER_
Min
46.8
Typ
48.0
Max
49.2[11,13]
Units
MHz
24 MHz Period Jitter (IMO)
Maximum frequency of signal on row input or
row output.
Power Supply Slew Rate
–
–
600
–
12.3
ps
MHz
–
–
250
V/ms
Time from End of POR to CPU Executing
Code
–
16
100
ms
UP
TPOWERUP
Notes
Trimmed. Utilizing factory
trim values.
Vdd slew rate during power
up.
Power up from 0V. See the
System Resets section of the
PSoC Technical Reference
Manual.
Figure 7-3. PLL Lock Timing Diagram
PLL
Enable
TPLLSLEW
24 MHz
FPLL
PLL
Gain
0
Figure 7-4. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
TPLLSLEWLOW
24 MHz
FPLL
PLL
Gain
1
Figure 7-5. External Crystal Oscillator Startup Timing Diagram
32K
Select
32 kHz
TOS
F32K2
Figure 7-6. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F 24M
Document Number: 001-12981 Rev. *E
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Figure 7-7. 32 kHz Period Jitter (ECO) Timing Diagram
Jitter32k
F 32K2
7.5 AC General Purpose I/O Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 7-18. AC GPIO Specifications
Symbol
FGPIO
TRiseF
TFallF
TRiseS
TFallS
Description
GPIO Operating Frequency
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
Min
0
3
2
10
10
Typ
–
–
–
27
22
Max
12
18
18
–
–
Units
MHz
ns
ns
ns
ns
Notes
Normal Strong Mode
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Figure 1. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
7.5.1 AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.
Table 7-19. 5V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
Description
Rising Settling Time from 80% of ΔV to 0.1% of ΔV
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10
pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Document Number: 001-12981 Rev. *E
Min
Typ
Max
Units
–
–
–
–
–
–
3.9
0.72
0.62
μs
μs
μs
–
–
–
–
–
–
5.9
0.92
0.72
μs
μs
μs
0.15
1.7
6.5
–
–
–
–
–
–
V/μs
V/μs
V/μs
Notes
Page 28 of 44
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Table 7-19. 5V AC Operational Amplifier Specifications (continued)
Symbol
SRFOA
BWOA
ENOA
Description
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
Min
Typ
Max
Units
0.01
0.5
4.0
–
–
–
–
–
–
V/μs
V/μs
V/μs
0.75
3.1
5.4
–
–
–
–
100
–
–
–
–
MHz
MHz
MHz
nV/rt-Hz
Notes
Table 7-20. 3.3V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Rising Settling Time from 80% of ΔV to 0.1% of ΔV
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Falling Settling Time from 20% of ΔV to 0.1% of ΔV
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
Min
Typ
Max
Units
Notes
–
–
–
–
3.92
0.72
μs
μs
–
–
–
–
5.41
0.72
μs
μs
0.31
2.7
–
–
–
–
V/μs
V/μs
0.24
1.8
–
–
–
–
V/μs
V/μs
0.67
2.8
–
–
–
100
–
–
–
MHz
MHz
nV/rt-Hz
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 7-8. Typical AGND Noise with P2[4] Bypass
dBV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
Document Number: 001-12981 Rev. *E
0.01
0.1 Freq (kHz)
1
10
100
Page 29 of 44
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At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 7-9. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
0.01
0.1
Freq (kHz)
1
10
100
7.4.4 AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.
Table 7-21. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Min
–
Typ
–
Max
50
Units
μs
Notes
≥ 50 mV overdrive comparator
reference set within VREFLPC.
7.4.5 AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 7-22. AC Digital Block Specifications
Function
Description
All
Functions
Maximum Block Clocking Frequency (> 4.75V)
Timer
Capture Pulse Width
Counter
Dead Band
Min
Typ
Max
Units
49.2
Maximum Block Clocking Frequency (< 4.75V)
24.6
3.0V < Vdd < 4.75V.
50[15]
–
–
ns
Maximum Frequency, No Capture
–
–
49.2
MHz
Maximum Frequency, With Capture
–
–
24.6
MHz
50[15]
–
–
ns
Maximum Frequency, No Enable Input
–
–
49.2
MHz
Maximum Frequency, Enable Input
–
–
24.6
MHz
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50[15]
–
–
ns
Disable Mode
50[15]
–
–
ns
–
–
49.2
MHz
Enable Pulse Width
Notes
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
Kill Pulse Width:
Maximum Frequency
Document Number: 001-12981 Rev. *E
4.75V < Vdd < 5.25V.
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Table 7-22. AC Digital Block Specifications (continued)
Function
Description
Min
Typ
Max
Units
Notes
4.75V < Vdd < 5.25V.
CRCPRS
(PRS Mode)
Maximum Input Clock Frequency
–
–
49.2
MHz
CRCPRS
(CRC Mode)
Maximum Input Clock Frequency
–
–
24.6
MHz
SPIM
Maximum Input Clock Frequency
–
–
8.2
MHz
SPIS
Maximum Input Clock Frequency
–
–
4.1
ns
50[15]
–
–
ns
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum Input Clock Frequency with Vdd ≥ 4.75V, 2 Stop Bits
–
–
49.2
MHz
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum Input Clock Frequency with Vdd ≥ 4.75V, 2 Stop Bits
–
–
49.2
MHz
Width of SS_ Negated Between Transmissions
Transmitter
Receiver
Maximum data rate at
4.1 MHz due to 2 x
over clocking.
Maximum data rate at
3.08 MHz due to 8 x
over clocking.
Maximum data rate at
6.15 MHz due to 8 x
over clocking.
Maximum data rate at
3.08 MHz due to 8 x
over clocking.
Maximum data rate at
6.15 MHz due to 8 x
over clocking.
7.4.6 AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 7-23. 5V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
BWOB
Description
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Power = Low
Power = High
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Power = Low
Power = High
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Power = Low
Power = High
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
Power = Low
Power = High
Min
Typ
Max
Units
–
–
–
–
2.5
2.5
μs
μs
–
–
–
–
2.2
2.2
μs
μs
0.65
0.65
–
–
–
–
V/μs
V/μs
0.65
0.65
–
–
–
–
V/μs
V/μs
0.8
0.8
–
–
–
–
MHz
MHz
300
300
–
–
–
–
kHz
kHz
Notes
Note
15. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-12981 Rev. *E
Page 31 of 44
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CY8CLED08
Table 7-24. 3.3V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
BWOB
Description
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Power = Low
Power = High
Falling Slew Rate (80% to 20%), 1V Step, 100pF
Load
Power = Low
Power = High
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF
Load
Power = Low
Power = High
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
Power = Low
Power = High
Min
Typ
Max
Units
–
–
–
–
3.8
3.8
μs
μs
–
–
–
–
2.6
2.6
μs
μs
0.5
0.5
–
–
–
–
V/μs
V/μs
0.5
0.5
–
–
–
–
V/μs
V/μs
0.7
0.7
–
–
–
–
MHz
MHz
200
200
–
–
–
–
kHz
kHz
Notes
7.4.7 AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 7-25. 5V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency
0.093
–
24.6
MHz
–
High Period
20.6
–
5300
ns
–
Low Period
20.6
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Notes
Table 7-26. 3.3V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency with CPU Clock divide by
1[16]
0.093
–
12.3
MHz
FOSCEXT
Frequency with CPU Clock divide by 2 or
greater[17]
0.186
–
24.6
MHz
–
High Period with CPU Clock divide by 1
41.7
–
5300
ns
–
Low Period with CPU Clock divide by 1
41.7
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Notes
Notes
16. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle
requirements.
17. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that
the fifty percent duty cycle requirement is met.
Document Number: 001-12981 Rev. *E
Page 32 of 44
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CY8CLED08
7.4.8 AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 7-27. AC Programming Specifications
Symbol
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
TERASEB
TWRITE
TDSCLK
TDSCLK3
TERASEALL
Description
Rise Time of SCLK
Fall Time of SCLK
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Flash Erase Time (Bulk)
TPROGRAM_HOT Flash Block Erase + Flash Block Write Time
TPROGRAM_COLD Flash Block Erase + Flash Block Write Time
Min
1
1
40
40
0
–
–
–
–
–
Typ
–
–
–
–
–
10
10
–
–
95
–
–
–
–
Max
20
20
–
–
8
–
–
45
50
–
Units
ns
ns
ns
ns
MHz
ms
ms
ns
ns
ms
80[18] ms
160[18] ms
Notes
Vdd > 3.6
3.0 ≤ Vdd ≤ 3.6
Erase all blocks and
protection fields at once.
0°C ≤ TJ ≤ 100°C
-40°C ≤ TJ ≤ 0°C
Note
18. For the full industrial range, the user must employ a Temperature Sensor User Module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
Document Number: 001-12981 Rev. *E
Page 33 of 44
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CY8CLED08
7.4.9 AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 7-28. AC Characteristics of the I2C SDA and SCL Pins
Symbol
Description
FSCLI2C
SCL Clock Frequency
THDSTAI2C Hold Time (repeated) START Condition. After
this period, the first clock pulse is generated.
TLOWI2C
LOW Period of the SCL Clock
THIGHI2C
HIGH Period of the SCL Clock
TSUSTAI2C Set-up Time for a Repeated START Condition
THDDATI2C Data Hold Time
TSUDATI2C Data Set Up Time
TSUSTOI2C Set-up Time for STOP Condition
TBUFI2C
Bus Free Time Between a STOP and START
Condition
TSPI2C
Pulse Width of spikes are suppressed by the
input filter.
Standard-Mode
Min
Max
0
100
4.0
–
Fast-Mode
Min
Max
0
400
0.6
–
Units
Notes
kHz
μs
4.7
4.0
4.7
0
250
4.0
4.7
–
–
–
–
–
–
–
1.3
0.6
0.6
0
100[19]
0.6
1.3
–
–
–
–
–
–
–
μs
μs
μs
μs
ns
μs
μs
–
–
0
50
ns
Figure 7-10. Definition for Timing for Fast-/Standard-Mode on the I2C Bus
SDA
TLOWI2C
TSPI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Note
19. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-12981 Rev. *E
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CY8CLED08
8. Packaging Information
This section illustrates the packaging specifications for the CY8CLED08 EZ-Color device, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
8.1 Packaging Dimensions
Figure 8-1. 28-Pin (210-Mil) SSOP
51-85079 *D
Document Number: 001-12981 Rev. *E
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CY8CLED08
Figure 8-2. 48-Pin (300-Mil) SSOP
51-85061 *C
Figure 8-3. 48-Pin (7x7 mm) QFN (Punched)
SIDE VIEW
TOP VIEW
0.08
BOTTOM VIEW
C
1.00 MAX.
6.90
7.10
0.05 MAX.
5.1
0.80 MAX.
6.70
6.80
0.23±0.05
0.20 REF.
N
N
PIN1 ID
0.20 R.
1
2 0.45
1
2
0.80 DIA.
6.70
6.80
6.90
7.10
5.1
SOLDERABLE
EXPOSED
PAD
5.45
5.55
0.30-0.45
0°-12°
0.50
C
NOTES:
1.
SEATING
PLANE
5.45
5.55
0.42±0.18
(4X)
HATCH AREA IS SOLDERABLE EXPOSED METAL.
2. REFERENCE JEDEC#: MO-220
3. PACKAGE WEIGHT: 0.13g
4. ALL DIMENSIONS ARE IN MM [MIN/MAX]
5. PACKAGE CODE
PART #
DESCRIPTION
LF48A
LY48A
STANDARD
LEAD FREE
Document Number: 001-12981 Rev. *E
001-12919 *B
Page 36 of 44
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CY8CLED08
Figure 8-4. 48-Pin (7x7x1.0 mm) QFN (Sawn)
TOP VIEW
SIDE VIEW
7.00±0.100
BOTTOM VIEW
0.900±0.100
48
0.25
36
1
5.100 REF
0.200 REF.
37
0.50 PITCH
+0.05
-0.07
PIN1 ID
R 0.20
37
PIN 1 DOT
1
36
LASER MARK
0.45
7.00±0.100
SOLDERABLE
EXPOSED
PAD
5.100 REF
12
25
13
24
25
C
HATCH AREA IS SOLDERABLE EXPOSED METAL.
0.08
NOTES:
12
0.40±0.10
13
24
SEATING PLANE
0.020 +0.025
-0.00
1.
5.500±0.100
5.500±0.100
2. REFERENCE JEDEC#: MO-220
3. PACKAGE WEIGHT: 0.13g
4. ALL DIMENSIONS ARE IN MILLIMETERS
001-13191 *E
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
Important Note Pinned vias for thermal conduction are not required for the low-power device.
Document Number: 001-12981 Rev. *E
Page 37 of 44
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CY8CLED08
8.1 Thermal Impedances
Table 8-1. Thermal Impedances per Package
Package
Typical θJA[20]
48 SSOP
69 °C/W
48
QFN[21]
28 SSOP
18 °C/W
95 °C/W
8.2 Capacitance on Crystal Pins
Table 8-2. Typical Package Capacitance on Crystal Pins
Package
48 SSOP
48 QFN
28 SSOP
Package Capacitance
3.3 pF
2.3 pF
2.8 pF
8.3 Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 8-3. Solder Reflow Peak Temperature
Package
Minimum Peak
Temperature[22]
Maximum Peak Temperature
48 SSOP
220°C
260°C
48 QFN
240°C
260°C
28 SSOP
240°C
260°C
Notes
20. TJ = TA + POWER x θJA
21. To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane.
22. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5°C with Sn-Pb or 245 ± 5°C with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
Document Number: 001-12981 Rev. *E
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CY8CLED08
9. Development Tool Selection
This section presents the development tools available for all
current PSoC based devices including the CY8CLED08
EZ-Color family.
9.1 Software Tools
9.1.1 PSoC Designer™
At the core of the PSoC development software suite is PSoC
Designer, used to generate PSoC firmware applications. PSoC
Designer is available free of charge at
http://www.cypress.com/psocdesigner and includes a free C
compiler.
9.1.2 PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube In-Circuit Emulator and
PSoC MiniProg. PSoC programmer is available free ofcharge at
http://www.cypress.com/psocprogrammer.
9.2 Hardware Tools
9.2.1 In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
9.3 Evaluation Tools
All evaluation tools can be purchased from the Cypress Online
Store.
9.3.1 CY3261A-RGB EZ-Color RGB Kit
The CY3261A-RGB board is a preprogrammed HB LED color
mix board with seven pre-set colors using the CY8CLED16
EZ-Color HB LED Controller. The board is accompanied by a
CD containing the color selector software application, PSoC
Designer, PSoC Programmer, and a suite of documents,
schematics, and firmware examples. The color selector software
application can be installed on a host PC and is used to control
the EZ-Color HB LED controller using the included USB cable.
The application enables you to select colors via a CIE 1931 chart
or by entering coordinates. The kit includes:
■
Training Board (CY8CLED16)
■
One mini-A to mini-B USB Cable
■
PSoC Designer CD-ROM
■
Design Files and Application Installation CD-ROM
To program and tune this kit via PSoC Designer you must use a
Mini Programmer Unit (CY3217 Kit) and a CY3240-I2CUSB kit.
9.3.2 CY3263-ColorLock Evaluation Board
■
Tools CD, which includes:
❐ PSoC Programmer
❐ .NET Framework 2.0 (for Windows 2000 and Windows XP)
❐ PSoC Designer
❐ ColorLock Express Pack
❐ CY3263-ColorLock EZ-Color Kit CD
❐ ColorLock Monitor Application
❐ Kit Documents (Quick Start, Kit Guide, Release Note, Application Note, Data Sheets, Schematics, and Layouts)
❐ Firmware
■
Retractable USB Cable (A to Mini-B)
■
PSoC MiniProg Programmer
■
Power Supply Adapter
The emulator consists of a base unit that connects to the PC by
way of the USB port. The base unit is universal and will operate
with all PSoC based devices. Emulation pods for each device
family are available separately. The emulation pod takes the
place of the PSoC device in the target board and performs full
speed (24 MHz) operation.
9.2.2 I2C to USB Bridge
The I2C to USB Bridge is a quick and easy link from any design
or application’s I2C bus to a PC via USB for design testing,
debugging and communication.
9.2.3 PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube In-Circuit Emulator and
PSoC MiniProg. PSoC programmer is available free ofcharge at
http://www.cypress.com/psocprogrammer.
Document Number: 001-12981 Rev. *E
Page 39 of 44
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CY8CLED08
9.3.3 CY3265-RGB EZ-Color Evaluation Kit
9.3.5 CY3210-PSoCEval1
The CY3265-RGB evaluation board demonstrates the ability of
the EZ-Color device to use real-time temperature feedback to
control three primary, high brightness LEDs and create accurate,
mixed-color output. There are three variations of the kit available,
depending on the LED manufacturer of the LEDs on the board:
CY3265C-RGB (Cree LEDs), CY3265N-RGB (Nichia LEDs), or
CY3265O-RGB (OSRAM LEDs). The kit includes:
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit
includes:
■
CY3265C-RGB Evaluation Board
■
Tools CD, which includes:
❐ PSoC Programmer
❐ PSoC Designer
❐ .NET Framework 2.0 (Windows XP 32 bit)
■
Evaluation Board with LCD Module
■
MiniProg Programming Unit
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
■
Kit Documents (Quick Start, Kit Guide, Release Note, Application Note, Data Sheets, Schematics, and Layouts) Firmware
■
Blue PCA Enclosure/Case
■
12V 1A Power Supply
All device programmers can be purchased from the Cypress
Online Store.
■
Retractable USB Cable (A to Mini-B)
9.4.1 CY3216 Modular Programmer
■
PSoC MiniProg Programmer
■
Quick Start Guide
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
9.3.4 CY3210-MiniProg1
The CY3210-MiniProg1 kit allows a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
9.4 Device Programmers
■
Modular Programmer Base
■
3 Programming Module Cards
■
MiniProg Programming Unit
■
MiniProg Programming Unit
■
PSoC Designer Software CD
■
MiniEval Socket Programming and Evaluation Board
■
Getting Started Guide
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■
USB 2.0 Cable
■
28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
9.4.2 CY3207ISSP In-System Serial Programmer (ISSP)
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
Note CY3207ISSP needs special software and is not compatible
with PSoC Programmer. The kit includes:
Document Number: 001-12981 Rev. *E
■
CY3207 Programmer Unit
■
PSoC ISSP Software CD
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
USB 2.0 Cable
Page 40 of 44
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CY8CLED08
9.5 Accessories (Emulation and Programming)
Table 1. Emulation and Programming Accessories
Part #
Pin
Package
CY8CLED08-48PVXI
48 SSOP
CY8CLED08-48LFXI/
CY8CLED08-48LTXI
48 QFN
CY8CLED08-28PVXI
28 SSOP
Flex-Pod Kit[23]
Foot Kit[24]
CY3250-LED08
CY3250-48SSOP-FK
CY3250-LED08QFN
CY3250-48QFN-FK
CY3250-LED08
CY3250-28SSOP-FK
Adapter[25]
Adapters can be found at
http://www.emulation.com.
9.6 Third Party Tools
9.7 Build a PSoC Emulator into Your Board
Several tools have been specially designed by the following
third-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools
can be found at http://www.cypress.com under Design Support
>> Development Kits/Boards.
For details on how to emulate your circuit before going to volume
production using an on-chip debug (OCD) non-production PSoC
device, see Application Note “Debugging - Build a PSoC
Emulator into Your Board - AN2323”.
Notes
23. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
24. Foot kit includes surface mount feet that can be soldered to the target PCB.
25. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com.
Document Number: 001-12981 Rev. *E
Page 41 of 44
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CY8CLED08
10. Ordering Information
10.1 Key Device Features
The following table lists the CY8CLED08 EZ-Color devices’ key package features and ordering codes.
16K
256
Yes
-40C to +85C
8
12
44
12
4
Yes
48 Pin (300 Mil) SSOP (Tape and Reel)
CY8CLED08-48PVXIT
16K
256
Yes
-40C to +85C
8
12
44
12
4
Yes
48 Pin (7x7) QFN (Punched)
CY8CLED08-48LFXI
16K
256
Yes
-40C to +85C
8
12
44
12
4
Yes
48 Pin (7x7) QFN (Tape and Reel)
(Punched)
CY8CLED08-48LFXIT
16K
256
Yes
-40C to +85C
8
12
44
12
4
Yes
28 Pin (210 Mil) SSOP
CY8CLED08-28PVXI
16K
256
Yes
-40C to +85C
8
12
24
12
4
Yes
28 Pin (210 Mil) SSOP (Tape and Reel)
CY8CLED08-28PVXIT
16K
256
Yes
-40C to +85C
8
12
24
12
4
Yes
48 Pin (7x7) QFN (Sawn)
CY8CLED08-48LTXI
16K
256
Yes
-40C to +85C
8
12
44
12
4
Yes
48 Pin (7x7) QFN (Tape and Reel) (Sawn)
CY8CLED08-48LTXIT
16K
256
Yes
-40C to +85C
8
12
44
12
4
Yes
Analog
Inputs
XRES Pin
Temperature
Range
CY8CLED08-48PVXI
Analog
Outputs
Switch Mode
Pump
48 Pin (300 Mil) SSOP
Ordering
Code
Package
Digital I/O
Pins
RAM
(Bytes)
Analog Blocks
(Columns of 3)
Flash
(Bytes)
Digital Blocks
(Rows of 4)
Table 2. Device Key Features and Ordering Information
10.2 Ordering Code Definitions
CY 8 C LED
xx - xx xxxx
Package Type:
Thermal Rating:
PX = PDIP Pb-Free
C = Commercial
SX = SOIC Pb-Free
I = Industrial
PVX = SSOP Pb-Free E = Extended
LFX/LKX = QFN Pb-Free
AX = TQFP Pb-Free
Pin Count
Part Number
LED Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number: 001-12981 Rev. *E
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CY8CLED08
11. Document History Page
Document Title: CY8CLED08 EZ-ColorTM HB LED Controller
Document Number: 001-12981
Revision
ECN
Orig. of
Change
Submission
Date
06/13/2007
Description of Change
**
1148504 SFVTMP3
*A
1391163
AESA
See ECN
*B
2763950
DPT
10/01/0209
Added 48QFN package diagram (Sawn)
Saw Marketing part number in ordering information.
*C
2794355
XBM
10/28/2009
Added “Contents” on page 3
Updated “Development Tools” on page 7.
Corrected FCPU1 and FCPU2 parameters in “AC Chip Level Specifications” on
page 26.
*D
2819954
CGX
12/02/2009
Corrected package diagram for 28-Pin (210-Mil) SSOP (Figure 8-1.)
*E
2850593
FRE
01/14/2010
Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as
follows:
Replaced TRAMP (time) with SRPOWER_UP (slew rate) specification.
Added note to Flash Endurance specification.
Added IOH, IOL, DCILO, F32K_U, TPOWERUP, TERASEALL,
TPROGRAM_HOT, and TPROGRAM_COLD specifications.
Corrected the Pod Kit part numbers.
Updated Development Tool Selection.
Updated copyright and Sales, Solutions, and Legal Information URLs.
Updated 28-Pin (210-Mil) SSOP package diagram.
Document Number: 001-12981 Rev. *E
New document (revision **).
Added 28 pin SSOP
Page 43 of 44
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CY8CLED08
Sales, Solutions, and Legal Information
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
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PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
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© Cypress Semiconductor Corporation, 2007-2009, 2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products
for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-12981 Rev. *E
Revised January 15, 2010
Page 44 of 44
PSoC Designer™ and EZ-Color™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corporation.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
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