CYPRESS CY8C24423A_09

CY8C24423A
®
Automotive PSoC
Programmable System-on-Chip
Features
■
AEC Qualified
■
Powerful Harvard Architecture Processor
❐ M8C Processor Speeds up to 24 MHz
❐ 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 3.0V to 5.25V Operating Voltage
❐ Automotive Temperature Range: -40°C to +85°C
■
■
■
■
■
Additional System Resources
2
❐ I C™ Slave, Master, or Multi-Master operation up to 400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
■
Complete Development Tools
❐ Free Development Software (PSoC Designer™)
❐ Full Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Bytes Trace Memory
Advanced Peripherals (PSoC® Blocks)
❐ Six Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ Four Digital PSoC Blocks Provide:
• 8- to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full- or Half-Duplex UART
• SPI Master or Slave
• Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
Logic Block Diagram
Port 2
Port 0
Analog
Drivers
PSoC CORE
System Bus
Global Digital Interconnect
Precision, Programmable Clocking
❐ Internal ±5% 24/48 MHz Oscillator
❐ High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Low Speed, Low Power Oscillator for Watchdog and
Sleep Functionality
SRAM
256 Bytes
SROM
Global Analog Interconnect
Flash 4K
Sleep and
Watchdog
CPU Core (M8C)
Interrupt
Controller
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
Flexible On-Chip Memory
❐ 4K Bytes Flash Program Storage, 1000 Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
Programmable Pin Configurations
❐ 25 mA Sink, 10 mA Drive on All GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
[1]
❐ Up to 12 Analog Inputs on GPIO
❐ Two 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on All GPIO
Port 1
DIGITAL SYSTEM
Digital
Clocks
ANALOG SYSTEM
Digital
Block
Array
Analog
Block
Array
(1 Row,
4 Blocks)
(2 Columns,
6 Blocks)
Multiply
Accum.
Analog
Ref
Analog
Input
Muxing
POR and LVD
Decimator
I2C
System Resets
Internal
Voltage
Ref.
SYSTEM RESOURCES
Note
1. There are eight standard analog inputs on the GPIO. The other four analog inputs connect from the GPIO directly to specific switched-capacitor block inputs. See
the PSoC Technical Reference Manual for more details.
Cypress Semiconductor Corporation
Document Number: 001-52469 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 22, 2009
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CY8C24423A
The PSoC family consists of many programmable
system-on-chips with on-chip Controller devices. These devices
are designed to replace multiple traditional MCU-based system
components with one, low cost single-chip programmable
device. PSoC devices include configurable blocks of analog and
digital logic, and programmable interconnects. This architecture
enables the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable I/O are included in a range of
convenient pinouts and packages.
Digital System
The Digital System is composed of four digital PSoC blocks.
Each block is an 8-bit resource that can be used alone or
combined with other blocks to form 8, 16, 24, and 32-bit
peripherals, which are called user modules.
Figure 1. Digital System Block Diagram
Port 1
Port 2
Port 0
To System Bus
Digital Clocks
From Core
The PSoC architecture, as shown in the Logic Block Diagram on
page 1, is comprised of four main areas: PSoC Core, Digital
System, Analog System, and System Resources. Configurable
global buses allow all the device resources to be combined into
a complete custom system. Each CY8C24x23A PSoC device
includes four digital blocks and six analog blocks. Depending on
the PSoC package, up to 24 general purpose I/O (GPIO) are also
included. The GPIO provide access to the global digital and
analog interconnects.
To Analog
System
DIGITAL SYSTEM
Digital PSoC Block Array
8
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
8
Row Output
Configuration
8
Row Input
Configuration
PSoC Functional Overview
8
PSoC Core
GIE[7:0]
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose I/O).
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture
microprocessor. The CPU uses an interrupt controller with
multiple vectors, to simplify programming of real time embedded
events. Program execution is timed and protected using the
included Sleep Timer and Watchdog Timer (WDT).
Memory includes 4 KB of Flash for program storage and 256
bytes of SRAM for data storage. Program Flash uses four
protection levels on blocks of 64 bytes, allowing customized
software IP protection.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to
±5% over temperature and voltage. A low power 32 kHz ILO
(internal low speed oscillator) is provided for the Sleep Timer and
WDT. If crystal accuracy is desired, the ECO (32.768 kHz
external crystal oscillator) is available for use as a Real Time
Clock (RTC) and can optionally generate a crystal-accurate 24
MHz system clock using a PLL. The clocks, together with
programmable clock dividers (as a System Resource), provide
the flexibility to integrate almost any timing requirement into the
PSoC device.
PSoC GPIOs provide connection to the CPU, digital, and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system
interrupt.
Document Number: 001-52469 Rev. *C
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Digital peripheral configurations include:
■
PWMs (8 to 32 bit)
■
PWMs with Dead Band (8 to 24 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
Full or Half-Duplex 8-bit UART with selectable parity
■
SPI master and slave
■
I2C master, slave, or multi-master
■
Cyclical Redundancy Checker/Generator (16 bit)
■
IrDA
■
Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in Table 1 on page 4.
Page 2 of 36
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CY8C24423A
Analog System
The Analog System is composed of six configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the common PSoC analog functions for this device
(most available as user modules) are:
Figure 2. Analog System Block Diagram
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
Analog-to-digital converters (up to two, with 6 to 14-bit
resolution, selectable as Incremental, Delta-Sigma, and SAR)
■
Filters (two and four pole band-pass, low-pass, and notch)
■
Amplifiers (up to two, with selectable gain up to 48x)
■
Instrumentation amplifiers (one with selectable gain up to 93x)
P2[3]
P2[2]
■
Comparators (up to two, with 16 selectable thresholds)
P2[1]
P2[0]
■
DACs (up to two, with 6 to 9-bit resolution)
■
Multiplying DACs (up to two, with 6 to 9-bit resolution)
■
High current output drivers (two with 30 mA drive)
■
1.3V reference (as a System Resource)
■
DTMF Dialer
■
Modulators
■
Correlators
■
Peak Detectors
■
Many other topologies possible
AGNDIn RefIn
■
P2[6]
P2[4]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
Block Array
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in Figure 2.
ACB00
ACB01
ASC10
ASD11
ASD20
ASC22
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
BandGap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-52469 Rev. *C
Page 3 of 36
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CY8C24423A
Additional System Resources
Getting Started
System Resources, some of which have been previously listed,
provide additional capability useful for complete systems.
Additional resources include a multiplier, decimator, low voltage
detection, and power on reset. Brief statements describing the
merits of each system resource follow:
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
For in depth information, along with detailed programming
details, see the PSoC® Programmable System-on-Chip
Technical Reference Manual for CY8C24x23A PSoC devices.
■
A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math as well
as digital filters.
■
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
■
The I2C module provides 0 to 400 kHz communication over two
wires. Slave, master, and multi-master modes are all
supported.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at www.cypress.com/psoc.
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
Development Kits
■
Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
■
An internal 1.3V voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
Training
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have a varying number of digital and analog
blocks. The following table lists the resources available for
specific PSoC device groups. The PSoC device covered by this
data sheet is highlighted in Table 1.
training covers a wide variety of topics and skill levels to assist
you in your designs.
CYPros Consultants
Analog
Columns
Analog
Blocks
4
16
12
4
4
12
2K
32K
CY8C27x43
up to
44
2
8
12
4
4
12
256
Bytes
16K
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various application designs that include firmware and hardware design files
that enable you to complete your designs quickly.
64
1
4
48
2
2
6
1K
16K
Technical Support
CY8C24x23A
up to
24
1
4
12
2
2
6
256
Bytes
4K
CY8C23x33
up to
1
4
12
2
2
4
256
Bytes
8K
CY8C21x34[2]
up to
28
1
4
28
0
2
4[3]
512
Bytes
8K
CY8C21x23
16
1
4
8
0
2
4[3]
256
Bytes
4K
CY8C20x34
up to
28
0
0
28
0
0
3[3, 4] 512
Bytes
8K
CY8C24x94
[2]
Flash
Size
Analog
Outputs
up to
64
PSoC Part
Number
SRAM
Size
Analog
Inputs
CY8C29x66[2]
Digital
I/O
Digital
Blocks
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
Digital
Rows
Table 1. PSoC Device Characteristics
Free PSoC technical training (on demand, webinars, and
workshops) is available online at www.cypress.com/training. The
Solutions Library
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.
Notes
2. Automotive qualified devices available in this group.
3. Limited analog functionality.
4. Two analog blocks and one CapSense™ block.
Document Number: 001-52469 Rev. *C
Page 4 of 36
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CY8C24423A
Development Tools
Code Generation Tools
PSoC Designer is a Microsoft® Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.
PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party
assemblers and C compilers.
Assemblers. The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
PSoC Designer Software Subsystems
System-Level View
A drag-and-drop visual embedded system design environment
based on PSoC Express. In the system level view you create a
model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state
based upon any or all other system devices. Based upon the
design, PSoC Designer automatically selects one or more PSoC
On-Chip Controllers that match your system requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.4. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
blocks. Examples of user modules are ADCs, DACs, Amplifiers,
and Filters. Configure the user modules for your chosen
application and connect them to each other and to the proper
pins. Then generate your project. This prepopulates your project
with APIs and libraries that you can use to program your
application.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder, and common debug, emulation, and programming
tools.
Document Number: 001-52469 Rev. *C
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
Debugger commands allow the designer to read and program
and read and write data memory, read and write I/O registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
Page 5 of 36
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CY8C24423A
Designing with PSoC Designer
Organize and Connect
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
You can build signal chains at the chip level by interconnecting
user modules to each other and the I/O pins, or connect system
level inputs, outputs, and communication interfaces to each
other with valuator functions.
The PSoC development process can be summarized in the
following four steps:
1. Select components
2. Configure components
3. Organize and Connect
4. Generate, Verify, and Debug
In the system-level view, selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog to
digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
In the chip-level view, perform the selection, configuration, and
routing so that you have complete control over the use of all
on-chip resources.
Select Components
Generate, Verify, and Debug
Both the system-level and chip-level views provide a library of
prebuilt, pretested hardware peripheral components. In the
system-level view, these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces
(I2C-bus, for example), and the logic to control how they interact
with one another (called valuators).
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Application” step. This causes PSoC Designer to generate
source code that automatically configures the device to your
specification and provides the software for the system.
In the chip-level view, the components are called “user modules”.
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and mixed signal
varieties.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in the PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
Document Number: 001-52469 Rev. *C
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
control and respond to hardware events at run-time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
Page 6 of 36
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Document Conventions
Units of Measure
Acronyms Used
A units of measure table is located in the Electrical Specifications
section. Table 7 on page 12 lists all the abbreviations used to
measure the PSoC devices.
The following table lists the acronyms that are used in this
document.
Table 2. Acronyms
Acronym
Description
AC
alternating current
ADC
analog-to-digital converter
API
application programming interface
CPU
central processing unit
CT
continuous time
DAC
digital-to-analog converter
DC
direct current
ECO
external crystal oscillator
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, ‘01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or ‘0x’ are
decimal.
EEPROM electrically erasable programmable read-only
memory
FSR
full scale range
GPIO
general purpose I/O
GUI
graphical user interface
HBM
human body model
ICE
in-circuit emulator
ILO
internal low speed oscillator
IMO
internal main oscillator
I/O
input/output
IPOR
imprecise power on reset
LSb
least-significant bit
LVD
low voltage detect
MSb
most-significant bit
PC
program counter
PLL
phase-locked loop
POR
power on reset
PPOR
precision power on reset
PSoC
Programmable System-on-Chip
PWM
pulse width modulator
SC
switched capacitor
SRAM
static random access memory
Document Number: 001-52469 Rev. *C
Page 7 of 36
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CY8C24423A
Pinouts
The automotive CY8C24x23A PSoC device is available in a variety of packages which are listed and illustrated in the following tables.
Every port pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O.
28-Pin Part Pinout
Table 3. 28-Pin Part Pinout (SSOP)
Type
Pin
Pin
Description
No. Digital Analog Name
1
I/O
I
P0[7] Analog column mux input
2
I/O
I/O
P0[5] Analog column mux input and column
output
3
I/O
I/O
P0[3] Analog column mux input and column
output
4
I/O
I
P0[1] Analog column mux input
5
I/O
P2[7]
6
I/O
P2[5]
7
I/O
I
P2[3] Direct switched capacitor block input
8
I/O
I
P2[1] Direct switched capacitor block input
9
Power
Vss
Ground connection
10
I/O
P1[7] I2C Serial Clock (SCL)
11
I/O
P1[5] I2C Serial Data (SDA)
12
I/O
P1[3]
13
I/O
P1[1] Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK[5]
14
Power
Vss
Ground connection
15
I/O
P1[0] Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA[5]
16
I/O
P1[2]
17
I/O
P1[4] Optional External Clock Input (EXTCLK)
18
I/O
P1[6]
19
Input
XRES Active high external reset with internal
pull down
20
I/O
I
P2[0] Direct switched capacitor block input
21
I/O
I
P2[2] Direct switched capacitor block input
22
I/O
P2[4] External Analog Ground (AGND)
23
I/O
P2[6] External Voltage Reference (VRef)
24
I/O
I
P0[0] Analog column mux input
25
I/O
I
P0[2] Analog column mux input
26
I/O
I
P0[4] Analog column mux input
27
I/O
I
P0[6] Analog column mux input
28
Power
Vdd
Supply voltage
Figure 3. CY8C24423A 28-Pin PSoC Device
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
P2[7]
P2[5]
AI, P2[3]
AI, P2[1]
Vss
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
P2[6], External VRef
P2[4], External AGND
P2[2], AI
P2[0], AI
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
LEGEND: A = Analog, I = Input, and O = Output.
Note
5. These are the ISSP pins, which are not High Z when coming out of POR (Power On Reset). See the PSoC Technical Reference Manual for details.
Document Number: 001-52469 Rev. *C
Page 8 of 36
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CY8C24423A
Registers
Register Conventions
Register Mapping Tables
This section lists the registers of the automotive CY8C24x23A
PSoC device. For detailed register information, reference the
PSoC Technical Reference Manual.
The register conventions specific to this section are listed in the
following table.
The PSoC device has a total register address space of 512
bytes. The register space is referred to as I/O space and is
divided into two banks. The XIO bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XIO bit
is set the user is in Bank 1.
Table 4. Abbreviations
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Convention
R
Description
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Document Number: 001-52469 Rev. *C
Page 9 of 36
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CY8C24423A
Table 5. Register Map Bank 0 Table: User Space
Name
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
Addr (0,Hex) Access
Name
Addr (0,Hex)
00
RW
40
01
RW
41
02
RW
42
03
RW
43
04
RW
44
05
RW
45
06
RW
46
07
RW
47
08
RW
48
09
RW
49
0A
RW
4A
0B
RW
4B
0C
4C
0D
4D
0E
4E
0F
4F
10
50
11
51
12
52
13
53
14
54
15
55
16
56
17
57
18
58
19
59
1A
5A
1B
5B
1C
5C
1D
5D
1E
5E
1F
5F
DBB00DR0
20
#
AMX_IN
60
DBB00DR1
21
W
61
DBB00DR2
22
RW
62
DBB00CR0
23
#
ARF_CR
63
DBB01DR0
24
#
CMP_CR0
64
DBB01DR1
25
W
ASY_CR
65
DBB01DR2
26
RW
CMP_CR1
66
DBB01CR0
27
#
67
DCB02DR0
28
#
68
DCB02DR1
29
W
69
DCB02DR2
2A
RW
6A
DCB02CR0
2B
#
6B
DCB03DR0
2C
#
6C
DCB03DR1
2D
W
6D
DCB03DR2
2E
RW
6E
DCB03CR0
2F
#
6F
30
ACB00CR3
70
31
ACB00CR0
71
32
ACB00CR1
72
33
ACB00CR2
73
34
ACB01CR3
74
35
ACB01CR0
75
36
ACB01CR1
76
37
ACB01CR2
77
38
78
39
79
3A
7A
3B
7B
3C
7C
3D
7D
3E
7E
3F
7F
Blank fields are Reserved and must not be accessed.
Document Number: 001-52469 Rev. *C
Access
RW
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
Addr (0,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
ASD20CR0
90
ASD20CR1
91
ASD20CR2
92
ASD20CR3
93
ASC21CR0
94
ASC21CR1
95
ASC21CR2
96
ASC21CR3
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
# Access is bit specific.
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR3
INT_MSK3
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL_X
MUL_Y
MUL_DH
MUL_DL
ACC_DR1
ACC_DR0
ACC_DR3
ACC_DR2
RW
RW
RW
RW
RW
RW
RW
CPU_F
CPU_SCR1
CPU_SCR0
Addr (0,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
#
#
Page 10 of 36
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CY8C24423A
Table 6. Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
Addr (1,Hex) Access
Name
Addr (1,Hex)
00
RW
40
01
RW
41
02
RW
42
03
RW
43
04
RW
44
05
RW
45
06
RW
46
07
RW
47
08
RW
48
09
RW
49
0A
RW
4A
0B
RW
4B
0C
4C
0D
4D
0E
4E
0F
4F
10
50
11
51
12
52
13
53
14
54
15
55
16
56
17
57
18
58
19
59
1A
5A
1B
5B
1C
5C
1D
5D
1E
5E
1F
5F
DBB00FN
20
RW
CLK_CR0
60
DBB00IN
21
RW
CLK_CR1
61
DBB00OU
22
RW
ABF_CR0
62
23
AMD_CR0
63
DBB01FN
24
RW
64
DBB01IN
25
RW
65
DBB01OU
26
RW
AMD_CR1
66
27
ALT_CR0
67
DCB02FN
28
RW
68
DCB02IN
29
RW
69
DCB02OU
2A
RW
6A
2B
6B
DCB03FN
2C
RW
6C
DCB03IN
2D
RW
6D
DCB03OU
2E
RW
6E
2F
6F
30
ACB00CR3
70
31
ACB00CR0
71
32
ACB00CR1
72
33
ACB00CR2
73
34
ACB01CR3
74
35
ACB01CR0
75
36
ACB01CR1
76
37
ACB01CR2
77
38
78
39
79
3A
7A
3B
7B
3C
7C
3D
7D
3E
7E
3F
7F
Blank fields are Reserved and must not be accessed.
Document Number: 001-52469 Rev. *C
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
Addr (1,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
ASD20CR0
90
ASD20CR1
91
ASD20CR2
92
ASD20CR3
93
ASC21CR0
94
ASC21CR1
95
ASC21CR2
96
ASC21CR3
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
# Access is bit specific.
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
VLT_CMP
IMO_TR
ILO_TR
BDG_TR
ECO_TR
RW
RW
RW
RW
RW
RW
RW
CPU_F
CPU_SCR1
CPU_SCR0
Addr (1,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
W
W
RW
W
RL
#
#
Page 11 of 36
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CY8C24423A
Electrical Specifications
This section presents the DC and AC electrical specifications of the automotive CY8C24x23A PSoC devices. For the latest electrical
specifications, visit http://www.cypress.com/psoc.
Specifications are valid for -40°C ≤ TA ≤ 85°C and TJ ≤ 100°C, except where noted.
Refer to Table 22 on page 22 for the electrical specifications on the IMO using SLIMO mode.
Figure 4. Voltage versus CPU Frequency
Figure 5. IMO Frequency Trim Options
5.25
5.25
lid ing
Va at
er ion
Op eg
R
4.75
SLIMO
Mode=0
SLIMO
Mode=1
SLIMO
Mode=0
4.75
Vdd Voltage (V)
Vdd Voltage (V)
SLIMO
Mode=1
3.0
0
3.6
3.0
0
12 MHz
93 kHz
24 MHz
6 MHz
CPU Frequency
(nominal setting)
12 MHz
24 MHz
IMO Frequency
The following table lists the units of measure that are used in this section.
Table 7. Units of Measure
Symbol
oC
dB
fF
Hz
KB
Kbit
kHz
kΩ
Mbaud
Mbps
MHz
MΩ
μA
μF
μH
μs
μV
Unit of Measure
degree Celsius
decibels
femto farad
hertz
1024 bytes
1024 bits
kilohertz
kilohm
megabaud
megabits per second
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microvolts
Document Number: 001-52469 Rev. *C
Symbol
μVrms
μW
mA
ms
mV
nA
ns
nV
Ω
pA
pF
pp
ppm
ps
sps
σ
V
Unit of Measure
microvolts root-mean-square
microwatts
milli-ampere
milli-second
milli-volts
nanoampere
nanosecond
nanovolts
ohm
picoampere
picofarad
peak-to-peak
parts per million
picosecond
samples per second
sigma: one standard deviation
volts
Page 12 of 36
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CY8C24423A
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 8. Absolute Maximum Ratings
Symbol
Description
TSTG
Storage Temperature
Min
-55
Typ
25
Max
+100
TA
Vdd
VIO
Ambient Temperature with Power Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
-40
-0.5
Vss - 0.5
–
–
–
VIOZ
DC Voltage Applied to Tri-state
Vss - 0.5
–
IMIO
ESD
LU
Maximum Current into any Port Pin
Electro Static Discharge Voltage
Latch Up Current
-25
2000
–
–
–
–
+85
+6.0
Vdd +
0.5
Vdd +
0.5
+50
–
200
Min
-40
-40
Typ
–
–
Max
+85
+100
Units
Notes
°C Higher storage temperatures
reduce data retention time.
Recommended storage
temperature is +25°C ± 25°C.
Extended duration storage
temperatures above 65°C
degrades reliability.
°C
V
V
V
mA
V
mA
Human Body Model ESD.
Operating Temperature
Table 9. Operating Temperature
Symbol
Description
TA
Ambient Temperature
TJ
Junction Temperature
Document Number: 001-52469 Rev. *C
Units
Notes
°C
°C The temperature rise from ambient
to junction is package specific. See
Table 34 on page 32. The user must
limit the power consumption to
comply with this requirement.
Page 13 of 36
[+] Feedback
CY8C24423A
DC Electrical Characteristics
DC Chip-Level Specifications
Table 10 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Table 10. DC Chip-Level Specifications
Symbol
Description
Vdd
Supply Voltage
Min
3.0
Typ
–
Max
5.25
IDD
Supply Current
–
5
8
IDD3
Supply Current
–
3.3
6.0
ISB
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT.[6]
–
3
6.5
ISBH
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT at High Temperature.[6]
–
4
25
ISBXTL
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and External Crystal.[6]
–
4
7.5
ISBXTLH Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and External Crystal at High
Temperature.[6]
–
5
26
1.28
1.30
1.32
VREF
Reference Voltage (Bandgap)
Units
Notes
V
See DC POR and LVD specifications,
Table 20 on page 20.
mA Conditions are Vdd = 5.0V, CPU = 3
MHz, 48 MHz disabled, VC1 = 1.5
MHz, VC2 = 93.75 kHz, VC3 = 93.75
kHz, Analog power = off. SLIMO mode
= 0. IMO = 24 MHz.
mA Conditions are Vdd = 3.3V, CPU = 3
MHz, 48 MHz disabled, VC1 = 1.5
MHz, VC2 = 93.75 kHz, VC3 = 93.75
kHz, Analog power = off. SLIMO mode
= 0. IMO = 24 MHz.
μA Conditions are with internal low speed
oscillator active, Vdd = 3.3V, -40°C ≤
TA ≤ 55°C, Analog power = off.
μA Conditions are with internal low speed
oscillator active, Vdd = 3.3V, 55°C < TA
≤ 85°C, Analog power = off.
μA Conditions are with properly loaded,
1 μW max, 32.768 kHz crystal.
Vdd = 3.3V, -40°C ≤ TA ≤ 55°C, Analog
power = off.
μA Conditions are with properly loaded,
1 μW max, 32.768 kHz crystal.
Vdd = 3.3 V, 55°C < TA ≤ 85°C, Analog
power = off.
V
Trimmed for appropriate Vdd.
Vdd ≥ 3.0V
Note
6. Standby current includes all functions (POR, LVD, WDT, Sleep Timer) needed for reliable system operation. This must be compared with devices that have similar
functions enabled.
Document Number: 001-52469 Rev. *C
Page 14 of 36
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CY8C24423A
DC General Purpose I/O Specifications
Table 11 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Table 11. 5V and 3.3V DC GPIO Specifications
Symbol
Description
RPU
Pull Up Resistor
Pull Down Resistor
RPD
High Output Level
VOH
VOL
Low Output Level
VIL
VIH
VH
IIL
CIN
Input Low Level
Input High Level
Input Hysterisis
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
COUT
Capacitive Load on Pins as Output
Document Number: 001-52469 Rev. *C
Min
4
4
Vdd - 1.0
Typ
5.6
5.6
–
Max
8
8
–
–
–
0.75
–
2.1
–
–
–
–
–
60
1
3.5
0.8
–
3.5
10
–
–
10
Units
Notes
kΩ
kΩ
V
IOH = 10 mA, Vdd = 4.75 to 5.25V
(maximum 40 mA on even port pins
(for example, P0[2], P1[4]),
maximum 40 mA on odd port pins
(for example, P0[3], P1[5])). 80 mA
maximum combined IOH budget.
V
IOL = 25 mA, Vdd = 4.75 to 5.25V
(maximum 100 mA on even port
pins (for example, P0[2], P1[4]),
maximum 100 mA on odd port pins
(for example, P0[3], P1[5])). 150
mA maximum combined IOL
budget.
V
V
mV
nA Gross tested to 1 μA
pF Package and pin dependent.
Temp = 25°C
pF Package and pin dependent.
Temp = 25°C
Page 15 of 36
[+] Feedback
CY8C24423A
DC Operational Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are
for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time (CT) PSoC blocks and the Analog Switched Capacitor
(SC) PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time (CT) PSoC block.
Table 12. 5V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
TCVOSOA Average Input Offset Voltage Drift
Input Leakage Current (Port 0 Analog Pins)
IEBOA
CINOA
Input Capacitance (Port 0 Analog Pins)
VCMOA
Common Mode Voltage Range
Common Mode Voltage Range (high power or
high opamp bias)
GOLOA
Open Loop Gain
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
VOHIGHOA High Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
VOLOWOA Low Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
ISOA
Supply Current (including associated AGND
buffer)
Power = Low, Opamp Bias = High
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Power = High, Opamp Bias = High
PSRROA Supply Voltage Rejection Ratio
Document Number: 001-52469 Rev. *C
Min
Typ
Max
Units
–
–
–
–
–
–
1.6
1.3
1.2
10
8
7.5
mV
mV
mV
7.0
20
4.5
0.0
0.5
–
–
60
60
80
–
–
–
Vdd - 0.2
Vdd - 0.2
Vdd - 0.5
–
–
–
–
–
–
V
V
V
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
–
–
–
–
–
–
64
150
300
600
1200
2400
4600
80
200
400
800
1600
3200
6400
–
μA
μA
μA
μA
μA
μA
dB
Notes
μV/°C
pA Gross tested to 1 μA
pF Package and pin dependent.
Temp = 25°C
Vdd
V
The common-mode input voltage
Vdd - 0.5
range is measured through an
analog output buffer. The
specification includes the
limitations imposed by the
characteristics of the analog
output buffer.
Specification is applicable at high
–
dB power. For all other bias modes
–
(except high power, high opamp
–
bias), minimum is 60 dB.
35.0
–
9.5
Vss ≤ VIN ≤ (Vdd - 2.25) or
(Vdd - 1.25V) ≤ VIN ≤ Vdd
Page 16 of 36
[+] Feedback
CY8C24423A
Table 13. 3.3V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
High Power is 5V Only
TCVOSOA Average Input Offset Voltage Drift
Min
Typ
Max
Units
–
–
1.65
1.32
10
8
mV
mV
–
7.0
35.0
μV/°C
Notes
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
20
–
pA
Gross tested to 1 μA
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25°C
VCMOA
Common Mode Voltage Range
0.2
–
Vdd - 0.2
V
The common-mode input voltage
range is measured through an
analog output buffer. The
specification includes the
limitations imposed by the
characteristics of the analog
output buffer.
GOLOA
Open Loop Gain
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High, Opamp Bias = Low
60
60
80
–
–
–
–
–
–
dB
VOHIGHOA High Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High is 5V only
Vdd - 0.2
Vdd - 0.2
Vdd - 0.2
–
–
–
–
–
–
V
V
V
VOLOWOA Low Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High, Opamp Bias = Low
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
–
–
–
–
–
150
300
600
1200
2400
200
400
800
1600
3200
μA
μA
μA
μA
μA
ISOA
PSRROA
Supply Current (including associated AGND
buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
Supply Voltage Rejection Ratio
Specification is applicable at high
power. For all other bias modes
(except high power, high opamp
bias), minimum is 60 dB.
Not allowed
64
80
–
dB
Vss ≤ VIN ≤ (Vdd - 2.25) or
(Vdd - 1.25V) ≤ VIN ≤ Vdd
DC Low Power Comparator Specifications
Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 14. DC Low Power Comparator Specifications
Symbol
VREFLPC
ISLPC
VOSLPC
Description
Low power comparator (LPC) reference
voltage range
LPC supply current
LPC voltage offset
Document Number: 001-52469 Rev. *C
Min
0.2
Typ
–
Max
Vdd - 1
Units
V
–
–
10
2.5
40
30
μA
mV
Notes
Page 17 of 36
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CY8C24423A
DC Analog Output Buffer Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are
for design guidance only.
Table 15. 5V DC Analog Output Buffer Specifications
Symbol
VOSOB
TCVOSOB
VCMOB
ROUTOB
Description
Min
Input Offset Voltage (Absolute Value)
–
Average Input Offset Voltage Drift
–
Common-Mode Input Voltage Range
0.5
Output Resistance
Power = Low
–
Power = High
–
VOHIGHOB High Output Voltage Swing (Load = 32Ω to
Vdd/2)
0.5 x Vdd + 1.1
Power = Low
0.5 x Vdd + 1.1
Power = High
VOLOWOB Low Output Voltage Swing (Load = 32Ω to
Vdd/2)
Power = Low
–
Power = High
–
ISOB
Supply Current Including Bias Cell (No Load)
–
Power = Low
–
Power = High
PSRROB Supply Voltage Rejection Ratio
52
Typ
3
+6
–
Max
12
–
Vdd - 1.0
Units
mV
μV/°C
V
1
1
–
–
Ω
Ω
–
–
–
–
V
V
–
–
0.5 x Vdd - 1.3
0.5 x Vdd - 1.3
V
V
1.1
2.6
64
5.1
8.8
–
mA
mA
dB
Typ
3
+6
-
Max
12
–
Vdd - 1.0
Units
mV
μV/°C
V
1
1
–
–
Ω
Ω
–
–
–
–
V
V
–
–
0.5 x Vdd - 1.0
0.5 x Vdd - 1.0
V
V
0.8
2.0
64
2.0
4.3
–
mA
mA
dB
Notes
VOUT > (Vdd - 1.25).
Table 16. 3.3V DC Analog Output Buffer Specifications
Symbol
VOSOB
TCVOSOB
VCMOB
ROUTOB
Description
Min
Input Offset Voltage (Absolute Value)
–
Average Input Offset Voltage Drift
–
Common-Mode Input Voltage Range
0.5
Output Resistance
Power = Low
–
Power = High
–
VOHIGHOB High Output Voltage Swing (Load = 1 kΩ to
Vdd/2)
Power = Low
0.5 x Vdd + 1.0
Power = High
0.5 x Vdd + 1.0
VOLOWOB Low Output Voltage Swing (Load = 1 kΩ to
Vdd/2)
Power = Low
–
Power = High
–
ISOB
Supply Current Including Bias Cell (No Load)
Power = Low
–
Power = High
PSRROB Supply Voltage Rejection Ratio
52
Document Number: 001-52469 Rev. *C
Notes
VOUT > (Vdd - 1.25)
Page 18 of 36
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CY8C24423A
DC Analog Reference Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are
for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling
of the digital signal may appear on the AGND.
Table 17. 5V DC Analog Reference Specifications
Symbol
Description
BG
Bandgap Voltage Reference
–
AGND = Vdd/2[7]
Min
1.28
Vdd/2 - 0.04
Typ
1.30
Vdd/2 - 0.01
Max
1.32
Vdd/2 + 0.007
Units
V
V
2 x BG - 0.048
P2[4] - 0.011
BG - 0.009
1.6 x BG - 0.022
-0.034
2 x BG - 0.030
P2[4]
BG + 0.008
1.6 x BG - 0.010
0.000
2 x BG + 0.024
P2[4] + 0.011
BG + 0.016
1.6 x BG + 0.018
0.034
V
V
V
V
V
–
–
–
–
–
AGND = 2 x BandGap[7]
AGND = P2[4] (P2[4] = Vdd/2)[7]
AGND = BandGap[7]
AGND = 1.6 x BandGap[7]
AGND Block to Block Variation
(AGND = Vdd/2)[7]
–
–
–
–
–
RefHi = Vdd/2 + BandGap[8]
Vdd/2 + BG - 0.10
Vdd/2 + BG
Vdd/2 + BG + 0.10
[8]
RefHi = 3 x BandGap
3 x BG - 0.06
3 x BG
3 x BG + 0.06
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)[8] 2 x BG + P2[6] - 0.113 2 x BG + P2[6] - 0.018 2 x BG + P2[6] + 0.077
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)[8]
P2[4] + BG - 0.130
P2[4] + BG - 0.016
P2[4] + BG + 0.098
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2
P2[4] + P2[6] - 0.133 P2[4] + P2[6] - 0.016 P2[4] + P2[6] + 0.100
P2[6] = 1.3V)[8]
V
V
V
V
V
–
–
–
–
–
–
RefHi = 3.2 x BandGap[8]
3.2 x BG - 0.112
3.2 x BG
3.2 x BG + 0.076
RefLo = Vdd/2 - BandGap[8]
Vdd/2 - BG - 0.04
Vdd/2 - BG + 0.024
Vdd/2 - BG + 0.04
RefLo = BandGap[8]
BG - 0.06
BG
BG + 0.06
[8]
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
2 x BG - P2[6] - 0.084 2 x BG - P2[6] + 0.025 2 x BG - P2[6] + 0.134
RefLo = P2[4] - BandGap (P2[4] = Vdd/2)[8]
P2[4] - BG - 0.056
P2[4] - BG + 0.026
P2[4] - BG + 0.107
RefLo = P2[4] - P2[6] (P2[4] = Vdd/2,
P2[4] - P2[6] - 0.057 P2[4] - P2[6] + 0.026 P2[4] - P2[6] + 0.110
P2[6] = 1.3V)[8]
V
V
V
V
V
V
Table 18. 3.3V DC Analog Reference Specifications
Symbol
BG
–
–
–
–
–
–
Description
Bandgap Voltage Reference
AGND = Vdd/2[7]
AGND = 2 x BandGap[7]
AGND = P2[4] (P2[4] = Vdd/2)[7]
AGND = BandGap[7]
AGND = 1.6 x BandGap[7]
AGND Column to Column Variation
(AGND = Vdd/2)[7]
–
RefHi = Vdd/2 + BandGap[8]
Min
1.28
Vdd/2 - 0.03
P2[4] - 0.008
BG - 0.009
1.6 x BG - 0.027
-0.034
Typ
1.30
Vdd/2 - 0.01
Not Allowed
P2[4] + 0.001
BG + 0.005
1.6 x BG - 0.010
0.000
Max
1.33
Vdd/2 + 0.005
Units
V
V
P2[4] + 0.009
BG + 0.015
1.6 x BG + 0.018
0.034
V
V
V
mV
Not Allowed
Notes
7. This specification is only valid when CT Block Power = High. AGND tolerance includes the offsets of the local buffer in the PSoC block.
8. This specification is only valid when Ref Control Power = High.
Document Number: 001-52469 Rev. *C
Page 19 of 36
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CY8C24423A
Table 18. 3.3V DC Analog Reference Specifications (continued)
Symbol
–
–
–
–
Description
Min
Typ
Max
Units
RefHi = 3 x BandGap[8]
Not Allowed
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)[8]
Not Allowed
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)[8]
Not Allowed
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2,
P2[4] + P2[6] - 0.075 P2[4] + P2[6] - 0.009 P2[4] + P2[6] + 0.057
V
P2[6] = 0.5V)[8]
–
–
–
–
–
–
RefHi = 3.2 x BandGap[8]
RefLo = Vdd/2 - BandGap[8]
RefLo = BandGap[8]
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)[8]
RefLo = P2[4] - BandGap (P2[4] = Vdd/2)[8]
RefLo = P2[4] - P2[6] (P2[4] = Vdd/2,
P2[4] - P2[6] - 0.048
P2[6] = 0.5V)[8]
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
P2[4]- P2[6] + 0.022
P2[4] - P2[6] + 0.092
V
DC Analog PSoC Block Specifications
Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Table 19. DC Analog PSoC Block Specifications
Symbol
Description
RCT
Resistor Unit Value (Continuous Time)
CSC
Capacitor Unit Value (Switched Capacitor)
Min
–
–
Typ
12.2
80
Max
–
–
Units
kΩ
fF
Notes
DC POR and LVD Specifications
Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Programmable
System-on-Chip Technical Reference Manual for more information on the VLT_CR register.
Table 20. DC POR and LVD Specifications
Symbol
Description
Vdd Value for PPOR Trip
VPPOR0 PORLEV[1:0] = 00b
VPPOR1 PORLEV[1:0] = 01b
VPPOR2 PORLEV[1:0] = 10b
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
Min
Typ
Max
Units
Notes
–
2.36
2.82
4.55
2.40
2.95
4.70
V
V
V
Vdd must be greater than or
equal to 2.5V during startup,
reset from the XRES pin, or
reset from Watchdog.
2.40
2.85
2.95
3.06
4.37
4.50
4.62
4.71
2.450
2.920
3.02
3.13
4.48
4.64
4.73
4.81
2.51[9]
2.99[10]
3.09
3.20
4.55
4.75
4.83
4.95
V
V
V
V
V
V
V
V
Notes
9. Always greater than 50 mV above VPPOR (PORLEV=00) for falling supply.
10. Always greater than 50 mV above VPPOR (PORLEV=01) for falling supply.
Document Number: 001-52469 Rev. *C
Page 20 of 36
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CY8C24423A
DC Programming Specifications
Table 21 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Table 21. DC Programming Specifications
Symbol
VddIWRITE
IDDP
VILP
VIHP
IILP
FlashENPB
Description
Supply Voltage for Flash Write Operations
Supply Current During Programming or Verify
Input Low Voltage During Programming or Verify
Input High Voltage During Programming or Verify
Input Current when Applying VILP to P1[0] or P1[1]
During Programming or Verify
Input Current when Applying VIHP to P1[0] or P1[1]
During Programming or Verify
Output Low Voltage During Programming or Verify
Output High Voltage During Programming or
Verify
Flash Endurance (per block)
FlashENT
FlashDR
Flash Endurance (total)[11]
Flash Data Retention
IIHP
VOLV
VOHV
Min
3.0
–
–
2.1
–
Typ
–
5
–
–
–
Max
–
25
0.8
–
0.2
Units
Notes
V
mA
V
V
mA Driving internal pull down
resistor.
mA Driving internal pull down
resistor.
V
V
–
–
1.5
–
Vdd - 1.0
–
–
0.75
Vdd
1,000
–
–
–
36,000
10
–
–
–
–
–
Years
Erase/write cycles per
block
Erase/write cycles
Note
11. A maximum of 36 x 1,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 1,000 maximum cycles each, 36x2 blocks
of 500 maximum cycles each, or 36x4 blocks of 250 maximum cycles each (to limit the total number of cycles to 36x1,000 and that no single block ever sees more
than 1,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
Document Number: 001-52469 Rev. *C
Page 21 of 36
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CY8C24423A
AC Electrical Characteristics
AC Chip-Level Specifications
Table 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Table 22. 5V and 3.3V AC Chip-Level Specifications
Symbol
FIMO24
Description
Internal Main Oscillator
Frequency for 24 MHz
FIMO6
Internal Main Oscillator
Frequency for 6 MHz
FCPU1
CPU Frequency (5V Vdd
Nominal)
CPU Frequency (3.3V Vdd
Nominal)
Digital PSoC Block Frequency
FCPU2
F48M
F24M
F32K1
Digital PSoC Block Frequency
Internal Low Speed Oscillator
Frequency
F32K2
External Crystal Oscillator
FPLL
Jitter24M2
TPLLSLEW
TPLLSLEWSLOW
PLL Frequency
24 MHz Period Jitter (PLL)
PLL Lock Time
PLL Lock Time for Low Gain
Setting
External Crystal Oscillator
Startup to 1%
External Crystal Oscillator
Startup to 100 ppm
TOS
TOSACC
Jitter32k
TXRST
DC24M
Step24M
Fout48M
Jitter24M1P
Jitter24M1R
FMAX
TRAMP
32 kHz Period Jitter
External Reset Pulse Width
24 MHz Duty Cycle
24 MHz Trim Step Size
48 MHz Output Frequency
24 MHz Period Jitter (IMO)
Peak-to-Peak
24 MHz Period Jitter (IMO) Root
Mean Squared
Maximum Frequency of signal
on row input or row output.
Supply Ramp Time
Min
22.8[13]
Typ
24
Max
25.2[12,13]
Units
Notes
MHz Trimmed for 5V or 3.3V operation using
factory trim values. See Figure 5 on
page 12. SLIMO mode = 0.
5.5[13]
6
6.5[12,13]
MHz Trimmed for 5V or 3.3V operation using
factory trim values. See Figure 5 on
page 12. SLIMO mode = 1.
0.089[13]
24
25.2[12,13]
MHz Minimum CPU frequency is 0.022 MHz
when SLIMO mode = 1
0.089[13]
12
12.6[13]
MHz Minimum CPU frequency is 0.022 MHz
when SLIMO mode = 1
0
48
50.4[12,13,14] MHz Refer to the AC Digital Block
Specifications.
0
24
25.2[13,14]
MHz
15
32
64
kHz This specification applies when the ILO
has been trimmed. During power up,
the ILO is untrimmed and has a
minimum frequency of 5 kHz.
–
32.768
–
kHz Accuracy is capacitor and crystal
dependent. 50% duty cycle.
–
23.986
–
MHz Is a multiple (x732) of crystal frequency.
–
–
600
ps Refer to Figure 9 on page 23.
0.5
–
10
ms Refer to Figure 6 on page 23.
0.5
–
50
ms Refer to Figure 7 on page 23.
–
1700
2620
ms
Refer to Figure 8 on page 23.
–
2800
3800
ms
–
10
40
–
45.6[13]
–
100
–
50
50
48.0
300
–
–
60
–
50.4[12, 13]
–
The crystal oscillator frequency is
within 100 ppm of its final value by the
end of the TOSACC period. Correct
operation assumes a properly loaded 1
µW maximum drive level 32.768 kHz
crystal. 3.0V ≤ Vdd ≤ 5.25V, -40 oC ≤ TA
≤ 85 oC.
Refer to Figure 10 on page 23.
–
–
600
ps
–
–
12.6[13]
MHz
20
–
–
μs
ns
μs
%
kHz
MHz Trimmed. Using factory trim values.
ps Refer to Figure 9 on page 23.
Notes
12. 4.75V ≤ Vdd ≤ 5.25V.
13. Accuracy derived from Internal Main Oscillator (IMO) with appropriate trim for Vdd range.
14. See the individual user module data sheets for information on maximum frequencies for user modules.
Document Number: 001-52469 Rev. *C
Page 22 of 36
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CY8C24423A
Figure 6. PLL Lock Timing Diagram
PLL
Enable
TPLLSLEW
24 MHz
FPLL
PLL
Gain
0
Figure 7. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
TPLLSLEWLOW
24 MHz
FPLL
PLL
Gain
1
Figure 8. External Crystal Oscillator Startup Timing Diagram
32K
Select
32 kHz
TOS
F32K2
Figure 9. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1P
Jitter24M2
F 24M
Figure 10. 32 kHz Period Jitter (ECO) Timing Diagram
Jitter32k
F 32K2
Document Number: 001-52469 Rev. *C
Page 23 of 36
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CY8C24423A
AC General Purpose I/O Specifications
Table 23 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Table 23. 5V and 3.3V AC GPIO Specifications
Symbol
FGPIO
TRiseF
TFallF
TRiseS
TFallS
Description
GPIO Operating Frequency
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
Min
0
3
2
10
10
Typ
–
–
–
27
22
Max
12.6[13]
18
18
–
–
Units
MHz
ns
ns
ns
ns
Notes
Normal Strong Mode
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Figure 11. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
Document Number: 001-52469 Rev. *C
TFallF
TFallS
Page 24 of 36
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CY8C24423A
AC Operational Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are
for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.
Table 24. 5V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Rising Settling Time from 80% of ΔV to 0.1% of ΔV
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Settling Time from 20% of ΔV to 0.1% of ΔV
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Slew Rate (80% to 20%) (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
Min
Typ
Max
Units
–
–
–
–
–
–
3.9
0.72
0.62
μs
μs
μs
–
–
–
–
–
–
5.9
0.92
0.72
μs
μs
μs
0.15
1.7
6.5
–
–
–
–
–
–
V/μs
V/μs
V/μs
0.01
0.5
4.0
–
–
–
–
–
–
V/μs
V/μs
V/μs
0.75
3.1
5.4
–
–
–
–
100
–
–
–
–
MHz
MHz
MHz
nV/rt-Hz
Min
Typ
Max
Units
–
–
–
–
3.92
0.72
μs
μs
–
–
–
–
5.41
0.72
μs
μs
0.31
2.7
–
–
–
–
V/μs
V/μs
0.24
1.8
–
–
–
–
V/μs
V/μs
0.67
2.8
–
–
–
100
–
–
–
MHz
MHz
nV/rt-Hz
Table 25. 3.3V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Rising Settling Time from 80% of ΔV to 0.1% of ΔV
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Falling Settling Time from 20% of ΔV to 0.1% of ΔV
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Falling Slew Rate (80% to 20%) (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
Document Number: 001-52469 Rev. *C
Page 25 of 36
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CY8C24423A
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1 kΩ resistance and the external capacitor.
Figure 12. Typical AGND Noise with P2[4] Bypass
dBV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 13. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
Document Number: 001-52469 Rev. *C
0.01
0.1
Freq (kHz)
1
10
100
Page 26 of 36
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CY8C24423A
AC Low Power Comparator Specifications
Table 26 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Table 26. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Min
–
Typ
–
Max
50
Units
μs
Notes
≥ 50 mV overdrive comparator
reference set within VREFLPC
AC Digital Block Specifications
Table 27 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Table 27. 5V and 3.3V AC Digital Block Specifications
Function
Timer
Counter
Description
Min
Typ
Max
Units
50[15]
–
–
ns
Maximum Frequency, No Capture
–
–
50.4[13]
MHz
Maximum Frequency, With Capture
–
–
25.2[13]
MHz
50[15]
–
–
ns
–
–
50.4[13]
MHz
–
–
25.2[13]
MHz
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50[15]
–
–
ns
Disable Mode
50[15]
–
–
ns
–
–
50.4[13]
MHz
4.75V ≤ Vdd ≤ 5.25V.
MHz
4.75V ≤ Vdd ≤ 5.25V.
Capture Pulse Width
Enable Pulse Width
Maximum Frequency, No Enable Input
Maximum Frequency, Enable Input
Dead Band
CRCPRS
(PRS Mode)
Maximum Input Clock Frequency
–
–
50.4[13]
CRCPRS
(CRC Mode)
Maximum Input Clock Frequency
–
–
25.2[13]
MHz
SPIM
Maximum Input Clock Frequency
–
–
8.4[13]
MHz
SPIS
Maximum Input Clock Frequency
–
–
4.2[13]
MHz
50[15]
–
–
ns
Width of SS_ Negated Between Transmissions
Receiver
4.75V ≤ Vdd ≤ 5.25V.
4.75V ≤ Vdd ≤ 5.25V.
Kill Pulse Width:
Maximum Frequency
Transmitter
Notes
[13]
Maximum data rate is 4.2 Mbps
due to 2 x over clocking.
Maximum Input Clock Frequency
–
–
25.2
MHz
Maximum baud rate is 3.15
Mbaud due to 8 x over clocking.
Maximum Input Clock Frequency with Vdd ≥
4.75V, 2 Stop Bits
–
–
50.4[13]
MHz
Maximum baud rate is 6.3
Mbaud due to 8 x over clocking.
Maximum Input Clock Frequency
–
–
25.2[13]
MHz
Maximum baud rate is 3.15
Mbaud due to 8 x over clocking.
Maximum Input Clock Frequency with Vdd ≥
4.75V, 2 Stop Bits
–
–
50.4[13]
MHz
Maximum baud rate is 6.3
Mbaud due to 8 x over clocking.
Note
15. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-52469 Rev. *C
Page 27 of 36
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CY8C24423A
AC Analog Output Buffer Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are
for design guidance only.
Table 28. 5V AC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
TROB
Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
–
–
–
–
2.5
2.5
μs
μs
TSOB
Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
–
–
–
–
2.2
2.2
μs
μs
SRROB
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low
Power = High
0.65
0.65
–
–
–
–
V/μs
V/μs
SRFOB
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low
Power = High
0.65
0.65
–
–
–
–
V/μs
V/μs
BWOB
Small Signal Bandwidth, 20 mVpp, 3dB BW, 100 pF Load
Power = Low
Power = High
0.8
0.8
–
–
–
–
MHz
MHz
BWOB
Large Signal Bandwidth, 1 Vpp, 3dB BW, 100 pF Load
Power = Low
Power = High
300
300
–
–
–
–
kHz
kHz
Min
Typ
Max
Units
Table 29. 3.3V AC Analog Output Buffer Specifications
Symbol
Description
TROB
Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
–
–
–
–
3.8
3.8
μs
μs
TSOB
Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
–
–
–
–
2.6
2.6
μs
μs
SRROB
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low
Power = High
0.5
0.5
–
–
–
–
V/μs
V/μs
SRFOB
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low
Power = High
0.5
0.5
–
–
–
–
V/μs
V/μs
BWOB
Small Signal Bandwidth, 20 mVpp, 3dB BW, 100 pF Load
Power = Low
Power = High
0.7
0.7
–
–
–
–
MHz
MHz
BWOB
Large Signal Bandwidth, 1 Vpp, 3dB BW, 100 pF Load
Power = Low
Power = High
200
200
–
–
–
–
kHz
kHz
Document Number: 001-52469 Rev. *C
Page 28 of 36
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CY8C24423A
AC External Clock Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are
for design guidance only.
Table 30. 5V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT Frequency
0.093
–
High Period
20.6
–
24.6
MHz
–
5300
ns
–
Low Period
–
Power Up IMO to Switch
20.6
–
–
ns
150
–
–
μs
Min
Typ
Max
Units
Table 31. 3.3V AC External Clock Specifications
Symbol
Description
FOSCEXT Frequency with CPU Clock divide by
1[16]
0.093
–
12.3
MHz
FOSCEXT Frequency with CPU Clock divide by 2 or greater[17]
0.186
–
24.6
MHz
–
High Period with CPU Clock divide by 1
41.7
–
5300
ns
–
Low Period with CPU Clock divide by 1
41.7
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
AC Programming Specifications
Table 32 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Table 32. AC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
1
–
20
ns
Fall Time of SCLK
1
–
20
ns
Data Setup Time to Falling Edge of SCLK
40
–
–
ns
THSCLK
Data Hold Time from Falling Edge of SCLK
40
–
–
ns
FSCLK
Frequency of SCLK
0
–
8
MHz
TERASEB Flash Erase Time (Block)
–
20
–
ms
TWRITE
Flash Block Write Time
–
20
–
ms
TDSCLK
Data Out Delay from Falling Edge of SCLK
–
–
45
ns
Vdd > 3.6
TDSCLK3
Data Out Delay from Falling Edge of SCLK
–
–
50
ns
3.0 ≤ Vdd ≤ 3.6
TRSCLK
Rise Time of SCLK
TFSCLK
TSSCLK
Notes
Notes
16. Maximum CPU frequency is 12 MHz nominal at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle
requirements.
17. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the
fifty percent duty cycle requirement is met.
Document Number: 001-52469 Rev. *C
Page 29 of 36
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CY8C24423A
AC I2C Specifications
Table 33 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Table 33. AC Characteristics of the I2C SDA and SCL Pins
Symbol
Standard Mode
Description
Fast Mode
Units
Min
Max
Min
Max
0
100[18]
0
400[18]
kHz
4.0
–
0.6
–
μs
FSCLI2C
SCL Clock Frequency
THDSTAI2C
Hold Time (repeated) START Condition. After
this period, the first clock pulse is generated.
TLOWI2C
LOW Period of the SCL Clock
4.7
–
1.3
–
μs
THIGHI2C
HIGH Period of the SCL Clock
4.0
–
0.6
–
μs
TSUSTAI2C
Setup Time for a Repeated START Condition
4.7
–
0.6
–
μs
THDDATI2C
Data Hold Time
0
–
0
–
μs
TSUDATI2C
Data Setup Time
250
–
100[19]
–
ns
TSUSTOI2C
Setup Time for STOP Condition
4.0
–
0.6
–
μs
TBUFI2C
Bus Free Time Between a STOP and START
Condition
4.7
–
1.3
–
μs
TSPI2C
Pulse Width of spikes are suppressed by the
input filter.
–
–
0
50
ns
Figure 14. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Notes
18. FSCLI2C is derived from SysClk of the PSoC. This specification assumes that SysClk is operating at 24 MHz, nominal. If SysClk is at a lower frequency, then the
FSCLI2C specification adjusts accordingly.
19. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement TSUDATI2C ≥ 250 ns must then be met. This is automatically the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax + TSUDATI2C = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-52469 Rev. *C
Page 30 of 36
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CY8C24423A
Packaging Information
This section illustrates the packaging specifications for the automotive CY8C24x23A PSoC device, along with the thermal impedances
for the package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the drawings at http://www.cypress.com/design/MR10161.
Packaging Dimensions
Figure 15. 28-Pin (210-Mil) SSOP
51-85079 *C
Document Number: 001-52469 Rev. *C
Page 31 of 36
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CY8C24423A
Thermal Impedances
Table 34. Thermal Impedances per Package
Typical θJA [20]
Package
28 SSOP
101°C/W
Capacitance on Crystal Pins
Table 35. Typical Package Capacitance on Crystal Pins
Package
28 SSOP
Package Capacitance
2.8 pF
Solder Reflow Peak Temperature
The following table lists the minimum solder reflow peak temperatures to achieve good solderability.
Table 36. Solder Reflow Peak Temperature
Package
28 SSOP
Minimum Peak Temperature[21]
240°C
Maximum Peak Temperature
260°C
Notes
20. TJ = TA + POWER x θJA
21. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
Document Number: 001-52469 Rev. *C
Page 32 of 36
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CY8C24423A
Development Tool Selection
This section presents the development tools available for the CY8C24x23A family.
Software
Evaluation Tools
PSoC Designer
All evaluation tools can be purchased from the Cypress Online
Store. The online store (www.cypress.com/shop) also has the
most up to date information on kit contents, descriptions, and
availability.
At the core of the PSoC development software suite is PSoC
Designer. Utilized by thousands of PSoC developers, this robust
software has been facilitating PSoC designs for years. PSoC
Designer is available free of charge at http://www.cypress.com.
PSoC Designer comes with a free C compiler.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube In-Circuit Emulator and
PSoC MiniProg. PSoC programmer is available free of charge at
http://www.cypress.com/psocprogrammer.
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, an RS-232 port, and
plenty of breadboarding space to meet all of your evaluation
needs. The kit includes:
■
Evaluation Board with LCD Module
■
MiniProg Programming Unit
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
Development Kits
■
PSoC Designer Software CD
All development kits can be purchased from the Cypress Online
Store. The online store (www.cypress.com/shop) also has the
most up to date information on kit contents, descriptions, and
availability.
■
Getting Started Guide
■
USB 2.0 Cable
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface allows users to run, halt, and single step the processor
and view the contents of specific memory locations. Advanced
emulation features are also supported through PSoC Designer.
The kit includes:
■
ICE-Cube Unit
■
28-Pin PDIP Emulation Pod for CY8C29466-24PXI
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Samples (two)
■
PSoC Designer Software CD
■
ISSP Cable
■
MiniEval Socket Programming and Evaluation board
■
Backward Compatibility Cable (for connecting to legacy Pods)
■
Universal 110/220 Power Supply (12V)
■
European Plug Adapter
■
USB 2.0 Cable
■
Getting Started Guide
■
Development Kit Registration form
Document Number: 001-52469 Rev. *C
CY3210-24X23 Evaluation Pod (EvalPod)
PSoC EvalPods are pods that connect to the ICE In-Circuit
Emulator (CY3215-DK kit) to allow debugging capability. They
can also function as a standalone device without debugging
capability. The EvalPod has a 28-pin DIP footprint on the bottom
for easy connection to development kits or other hardware. The
top of the EvalPod has prototyping headers for easy connection
to the device's pins. CY3210-24X23 provides evaluation of the
CY8C24x23A PSoC device family.
Page 33 of 36
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CY8C24423A
Device Programmers
CY3207ISSP In-System Serial Programmer (ISSP)
All device programmers can be purchased from the Cypress
Online Store.
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
CY3210-MiniProg1
The CY3210-MiniProg1 kit allows a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■
MiniProg Programming Unit
■
MiniEval Socket Programming and Evaluation Board
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
Note: CY3207ISSP needs special software and is not
compatible with PSoC Programmer. This software is free and
can be downloaded from http://www.cypress.com. The kit
includes:
■
CY3207 Programmer Unit
■
PSoC ISSP Software CD
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
USB 2.0 Cable
Accessories (Emulation and Programming)
Table 37. Emulation and Programming Accessories
Part Number
CY8C24423A-24PVXA
Pin Package
28 SSOP
Pod Kit[22]
CY3250-24X23A
Foot Kit[23]
CY3250-28SSOP-FK
Adapter[24]
Adapters can be found at
http://www.emulation.com.
Third Party Tools
Build a PSoC Emulator into Your Board
Several tools have been specially designed by the following
3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools
can be found at http://www.cypress.com under Design
Resources > Evaluation Boards.
For details on how to emulate your circuit before going to volume
production using an on-chip debug (OCD) non-production PSoC
device, see Application Note “Debugging - Build a PSoC
Emulator into Your Board - AN2323” at http://www.cypress.com.
Notes
22. Pod kit contains an emulation pod, a flex-cable (connects the pod to the ICE), two feet, and device samples.
23. Foot kit includes surface mount feet that can be soldered to the target PCB.
24. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com.
Document Number: 001-52469 Rev. *C
Page 34 of 36
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CY8C24423A
Ordering Information
The following table lists the automotive CY8C24x23A PSoC device group’s key package features and ordering codes.
XRES Pin
Analog Outputs
Analog Inputs[1]
Digital I/O Pins
Analog Blocks
Digital Blocks
SRAM
(Bytes)
Temperature
Range
Flash
(Bytes)
Package
Ordering
Code
Table 38. CY8C24423A Automotive PSoC Device Key Features and Ordering Information
28 Pin (210 Mil) SSOP
CY8C24423A-24PVXA
4K
256
-40°C to +85°C
4
6
24
12
2
Yes
28 Pin (210 Mil) SSOP
(Tape and Reel)
CY8C24423A-24PVXAT 4K
256
-40°C to +85°C
4
6
24
12
2
Yes
Ordering Code Definitions
CY 8 C 24 xxx-SPxx
Package Type:
Thermal Rating:
PX = PDIP Pb-Free
C = Commercial
SX = SOIC Pb-Free
I = Industrial
PVX = SSOP Pb-Free
E = Automotive Extended -40°C to +125°C
LFX/LKX = QFN Pb-Free
A = Automotive -40°C to +85°C
AX = TQFP Pb-Free
CPU Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = PSoC
Company ID: CY = Cypress
Document Number: 001-52469 Rev. *C
Page 35 of 36
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CY8C24423A
Document History Page
Document Title: CY8C24423A Automotive PSoC® Programmable System-on-Chip
Document Number: 001-52469
Rev.
ECN
Orig. of
Change
Submission
Date
Description of Change
**
2678061
VIVG/PYRS
03/24/09
New data sheet for Automotive A-Grade
*A
2685606
SHEA
04/08/09
Minor ECN to correct the spec number in Document History.
*B
2702925
BTK
*C
2742354
BTK/PYRS
05/06/2009 Post to external web
07/22/09
Changed title. Updated Features section. Updated text of PSoC Functional
Overview section. Updated Getting Started section. Made corrections and minor text
edits to Pinouts section. Changed the name of the Register Reference section to
"Registers". Added clarifying comments to some electrical specifications. Updated
some figures. Changed TRAMP specification per MASJ input. Fixed all AC specifications to conform to a ±5% IMO accuracy. Made other miscellaneous minor text
edits. Deleted some non-applicable or redundant information. Added a footnote to
clarify that 8 of the 12 analog inputs are regular and the other 4 are direct SC block
connections. Updated Development Tool Selection section.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at www.cypress.com/sales.
Products
PSoC
psoc.cypress.com
Clocks & Buffers
clocks.cypress.com
Wireless
wireless.cypress.com
Memories
memory.cypress.com
Image Sensors
image.cypress.com
© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-52469 Rev. *C
Revised July 22, 2009
Page 36 of 36
PSoC Designer™ is a trademark and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective
corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C
system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their
respective holders.
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