MAXIM MAX1333

19-3712; Rev 0; 5/05
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
The MAX1332/MAX1333 2-channel, serial-output,
12-bit, analog-to-digital converters (ADCs) feature two
true-differential analog inputs and offer outstanding noise
immunity and dynamic performance. Both devices easily
interface with SPI™/QSPI™/MICROWIRE™ and standard
digital signal processors (DSPs).
The MAX1332 operates from a single supply of +4.75V
to +5.25V with sampling rates up to 3Msps. The
MAX1333 operates from a single supply of +2.7V to
+3.6V with sampling rates up to 2Msps. These devices
feature a partial power-down mode and a full powerdown mode that reduce the supply current to 3.3mA
and 0.2µA, respectively. Also featured is a separate
power supply input (DVDD) that allows direct interfacing
to +2.7V to +3.6V digital logic. The fast conversion
speed, low power dissipation, excellent AC performance, and DC accuracy (±0.6 LSB INL) make the
MAX1332/MAX1333 ideal for industrial process control,
motor control, and base-station applications.
The MAX1332/MAX1333 are available in a space-saving (3mm x 3mm), 16-pin, TQFN package and operate
over the extended (-40°C to +85°C) temperature range.
Features
♦ 3Msps Sampling Rate (+5V, MAX1332)
♦ 2Msps Sampling Rate (+3V, MAX1333)
♦ Separate Logic Supply: +2.7V to +3.6V
♦ Two True-Differential Analog Input Channels
♦ Bipolar/Unipolar Selection Input
♦ Only 38mW (typ) Power Consumption
♦ Only 2µA (max) Shutdown Current
♦ High-Speed, SPI-Compatible, 3-Wire Serial
Interface
♦ 2MHz Full-Linear Bandwidth
♦ 71.4dB SINAD and -93dB THD at 525kHz Input
Frequency
♦ No Pipeline Delays
♦ Space-Saving (3mm x 3mm), 16-Pin, TQFN
Package
Ordering Information
Applications
Data Acquisition
Bill Validation
Motor Control
Base Stations
High-Speed Modems
Optical Sensors
Industrial Process Control
PART
TEMP RANGE PIN-PACKAGE
MAX1332ETE* -40°C to +85°C 16 TQFN-EP** (3mm x 3mm)
MAX1333ETE
-40°C to +85°C 16 TQFN-EP** (3mm x 3mm)
*Future product—contact factory for availability.
**EP = Exposed paddle.
Selector Guide and Pin Configuration appear at end of data
sheet.
Typical Operating Circuit
+2.7V TO +3.6V
+4.75V TO +5.25V
1µF
0.1µF
0.1µF
AVDD
DIFFERENTIAL
INPUTS
AIN1P
-
AIN1N
+
AIN0P
MAX1332 CHSEL
AIN0N
CNVST
REF
1µF
SHDN
+
REF INPUT
VOLTAGE
1µF
DVDD
BIP/UNI
µC/DSP
SCLK
DOUT
0.1µF
AGND
AGND DGND
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1332/MAX1333
General Description
MAX1332/MAX1333
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
Continuous Power Dissipation (TA = +70°C)
16-Pin TQFN (derate 17.5mW/°C above +70°C) ....1398.6mW
Operating Temperature Range
MAX133_ETE ...................................................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
AVDD to AGND (MAX1332) ......................................-0.3V to +6V
AVDD to AGND (MAX1333) ......................................-0.3V to +4V
DVDD to DGND.........................................................-0.3V to +4V
AGND to DGND.....................................................-0.3V to +0.3V
SCLK, CNVST, SHDN, CHSEL, BIP/UNI,
DOUT to DGND ...................................-0.3V to (DVDD + 0.3V)
AIN0P, AIN0N, AIN1P, AIN1N, REF to
AGND...................................................-0.3V to (AVDD + 0.3V)
Maximum Current into Any Pin .........................................±50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS (MAX1332)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to +3.6V, fSCLK = 48MHz, VREF = 4.096V, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (BIP/UNI = DGND) (Note 1)
Resolution
N
12
Bits
Integral Nonlinearity
INL
±0.6
±1.0
LSB
Differential Nonlinearity
DNL
±0.6
±1.0
LSB
Offset Error
±0.9
±3.0
LSB
Gain Error
±0.6
±6.0
LSB
Offset-Error Temperature
Coefficient
±0.2
ppm/°C
Gain-Error Temperature
Coefficient
±1.1
ppm/°C
DYNAMIC SPECIFICATIONS (AIN = -0.2dBFS, fIN = 525kHz, BIP/UNI = DVDD, unless otherwise noted) (Note 1)
Signal-to-Noise Ratio
Signal-to-Noise Plus Distortion
SNR
70
71.5
dB
SINAD
70
71.4
dB
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
-93
84
Channel-to-Channel Isolation
Full-Linear Bandwidth
SINAD > 68dB
-84
dBc
93
dBc
76
dB
2
MHz
Full-Power Bandwidth
6
MHz
Small-Signal Bandwidth
6
MHz
CONVERSION RATE
Minimum Conversion Time
tCONV
Figure 5
Maximum Throughput Rate
Minimum Track-and-Hold
Acquisition Time
2
271
3
tACQ
Figure 5
_______________________________________________________________________________________
ns
Msps
52
ns
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to +3.6V, fSCLK = 48MHz, VREF = 4.096V, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Aperture Delay
tAD
Figure 21
<10
ns
Aperture Jitter
tAJ
Figure 21
<10
ps
DIFFERENTIAL ANALOG INPUTS (AIN0P, AIN0N, AIN1P, AIN1N)
Differential Input Voltage Range
(VAIN_P - VAIN_N)
VIN
BIP/UNI = DGND
0
BIP/UNI = DVDD
-VREF / 2
VREF
AGND
- 50mV
Absolute Input Voltage Range
DC Leakage Current
ILKG
Input Capacitance
REFERENCE INPUT (REF)
CIN
REF Input Voltage Range
VREF
REF Input Capacitance
CREF
REF DC Leakage Current
IREF
V
+VREF / 2
AVDD
+
50mV
V
±1
µA
14
pF
AVDD
+
50mV
1.0
14
V
pF
±10
µA
0.3 x
DVDD
V
DIGITAL INPUTS (SCLK, CNVST, SHDN, CHSEL, BIP/UNI)
Input-Voltage Low
VIL
Input-Voltage High
VIH
0.7 x
DVDD
Input Hysteresis
V
100
Input Leakage Current
Input Capacitance
IILKG
±0.2
CIN
15
mV
±5
µA
pF
DIGITAL OUTPUT (DOUT)
Output-Voltage Low
VOL
Output-Voltage High
ISINK = 5mA
VOH
ISOURCE = 1mA
Tri-State Leakage Current
ILKGT
Between conversions, CNVST = DVDD
Tri-State Output Capacitance
COUT
Between conversions, CNVST = DVDD
0.4
DVDD 0.5
V
V
±1
15
µA
pF
POWER REQUIREMENTS
Analog Supply Voltage
AVDD
4.75
5.25
V
Digital Supply Voltage
DVDD
2.7
3.6
V
Analog Supply Current
IAVDD
Normal mode; average current (fSAMPLE =
3MHz, fSCLK = 48MHz)
11
12
Partial power-down mode
3.5
6
Full power-down mode
0.1
2
mA
µA
_______________________________________________________________________________________
3
MAX1332/MAX1333
ELECTRICAL CHARACTERISTICS (MAX1332) (continued)
MAX1332/MAX1333
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX1332) (continued)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to +3.6V, fSCLK = 48MHz, VREF = 4.096V, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at TA = +25°C.)
PARAMETER
Digital Supply Current
Power-Supply Rejection
SYMBOL
IDVDD
PSR
TYP
MAX
UNITS
Average current (fSAMPLE = 3MHz, fSCLK =
48MHz, zero-scale input)
CONDITIONS
MIN
4.5
7
mA
Power-down (fSCLK = 48MHz), CNVST =
DVDD
15
30
Static; all digital inputs are connected to
DVDD or DGND
0.2
2
µA
AVDD = 4.75V to 5.25V, full-scale input
±2
mV
TIMING CHARACTERISTICS (MAX1332) (Figure 4)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to +3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Clock Period
tCP
20.8
ns
SCLK Pulse Width
tSPW
6
ns
CNVST Rise to DOUT Disable
tCRDD
15
ns
CNVST Fall to DOUT Enable
tCFDE
15
ns
CHSEL to CNVST Fall Setup
tCHCF
40
ns
BIP/UNI to CNVST Fall Setup
tBUCF
40
ns
CNVST Fall to CHSEL Hold
tCFCH
0
ns
SCLK Fall to BIP/UNI Hold
tCFBU
0
ns
DOUT Remains Valid After SCLK
SCLK Rise to DOUT Transition
tDHOLD
tDOT
CLOAD = 0pF (Note 2)
1
2
CLOAD = 30pF
ns
6
ns
CNVST to SCLK Rise
tSETUP
6
ns
SCLK Rise to CNVST
tHOLD
0
ns
CNVST Pulse Width
tCSW
6
ns
Minimum Recovery Time (Full
Power-Down)
tFPD
From CNVST fall or SHDN rise
Minimum Recovery Time (Partial
Power-Down)
tPPD
From CNVST fall
Note 1: Tested with AVDD = 4.75V and DVDD = +2.7V.
Note 2: Guaranteed by design, not production tested.
4
_______________________________________________________________________________________
4
µs
500
ns
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
(AVDD = +2.7V to +3.6V, DVDD = +2.7V to AVDD, fSCLK = 32MHz, VREF = 2.5V, TA = TMIN to TMAX, unless otherwise noted. Typical
values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 3) (BIP/UNI = DGND)
Resolution
N
12
Bits
Relative Accuracy
INL
±0.6
±1.0
LSB
Differential Nonlinearity
DNL
±0.6
±1.0
LSB
Offset Error
±0.9
±3.0
LSB
Gain Error
±0.6
±6.0
LSB
Offset-Error Temperature
Coefficient
±1.1
ppm/°C
Gain-Error Temperature
Coefficient
±0.2
ppm/°C
DYNAMIC SPECIFICATIONS (AIN = -0.2dBFS, fIN = 525kHz, BIP/UNI = DVDD, unless otherwise noted) (Note 3)
Signal-to-Noise Ratio
Signal-to-Noise Plus Distortion
SNR
70
71.5
dB
SINAD
70
71.4
dB
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
-93
83.5
Channel-to-Channel Isolation
Full-Linear Bandwidth
SINAD > 68dB
Full-Power Bandwidth
Small-Signal Bandwidth
-86.5
93
dBc
dBc
76
dB
1.7
MHz
5.5
MHz
5
MHz
CONVERSION RATE
Minimum Conversion Time
tCONV
Figure 5
Maximum Throughput Rate
Minimum Track-and-Hold
Acquisition Time
406
2.0
ns
Msps
tACQ
Figure 5
Aperture Delay
tAD
Figure 21
<10
ns
Aperture Jitter
tAJ
Figure 21
<10
ps
78
ns
DIFFERENTIAL ANALOG INPUTS (AIN0P, AIN0N, AIN1P, AIN1N)
Differential Input Voltage Range
(VAIN_P - VAIN_N)
VIN
0
BIP/ UNI = DVDD
-VREF / 2
AGND
- 50mV
Absolute Input Voltage Range
DC Leakage Current
BIP/UNI = DGND
ILKG
VREF
+VREF / 2
V
AVDD
+
50mV
V
±1
µA
_______________________________________________________________________________________
5
MAX1332/MAX1333
ELECTRICAL CHARACTERISTICS (MAX1333)
MAX1332/MAX1333
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX1333) (continued)
(AVDD = +2.7V to +3.6V, DVDD = +2.7V to AVDD, fSCLK = 32MHz, VREF = 2.5V, TA = TMIN to TMAX, unless otherwise noted. Typical
values are at TA = +25°C.)
PARAMETER
Input Capacitance
REFERENCE INPUT (REF)
SYMBOL
CONDITIONS
MIN
CIN
REF Input Voltage
VREF
REF Input Capacitance
CREF
REF DC Leakage Current
IREF
TYP
MAX
14
pF
AVDD
+
50mV
1.0
UNITS
14
V
pF
±10
µA
0.3 x
DVDD
V
DIGITAL INPUTS (SCLK, CNVST, SHDN, CHSEL, BIP/UNI)
Input-Voltage Low
VIL
Input-Voltage High
VIH
0.7 x
DVDD
Input Hysteresis
Input Leakage Current
Input Capacitance
V
100
IILKG
±0.2
CIN
15
mV
±5
µA
pF
DIGITAL OUTPUT (DOUT)
Output-Voltage Low
VOL
ISINK = 5mA
Output-Voltage High
VOH
ISOURCE = 1mA
Tri-State Leakage Current
ILKGT
Between conversions, CNVST = DVDD
Tri-State Output Capacitance
COUT
Between conversions, CNVST = DVDD
0.4
DVDD 0.5
V
V
±1
15
µA
pF
POWER REQUIREMENTS
Analog Supply Voltage
AVDD
2.7
3.6
V
Digital Supply Voltage
DVDD
2.7
AVDD
V
Analog Supply Current
Digital Supply Current
Positive Supply Rejection
6
IAVDD
IDVDD
PSR
Normal mode; average current (fSAMPLE =
2MHz, fSCLK = 32MHz)
9.5
11.5
Partial power-down mode
3.3
4
Full power-down mode
mA
0.1
2
µA
Average current (fSAMPLE = 2MHz, fSCLK =
32MHz, zero-scale input)
3
5.4
mA
Power-down (fSCLK = 32MHz, CNVST =
DVDD)
10
20
Static; all digital inputs are connected to
DVDD or DGND
0.2
2
µA
AVDD = 2.7V to 3.6V, full-scale input
_______________________________________________________________________________________
±3
mV
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
(AVDD = +2.7V to +3.6V, DVDD = +2.7V to AVDD, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Clock Period
tCP
31.2
ns
SCLK Pulse Width
tCPW
10
ns
CNVST Rise to DOUT Disable
tCRDD
15
ns
CNVST Fall to DOUT Enable
tCFDE
15
ns
CHSEL to CNVST Fall Setup
tCHCF
50
ns
BIP/UNI to CNVST Fall Setup
tBUCF
50
ns
CNVST Fall to CHSEL Hold
tCFCH
0
ns
SCLK Fall to BIP/UNI Hold
tCFBU
0
ns
DOUT Remains Valid After SCLK
tDHOLD
SCLK Rise to DOUT Transition
tDOT
CLOAD = 0pF (Note 4)
1
CLOAD = 30pF
2
ns
6
ns
CNVST to SCLK Rise
tSETUP
6
ns
SCLK Rise to CNVST
tHOLD
0
ns
CNVST Pulse Width
tCSW
6
ns
Minimum Recovery Time (Full
Power-Down)
tFPD
From CNVST fall or SHDN rise
Minimum Recovery Time (Partial
Power-Down)
tPPD
From CNVST fall
4
µs
500
ns
Note 3: Tested with AVDD = DVDD = +2.7V.
Note 4: Guaranteed by design, not production tested.
DVDD
6kΩ
DOUT
DOUT
6kΩ
30pF
30pF
DGND
DGND
a) HIGH IMPEDANCE TO VOH, VOL TO VOH,
AND VOH TO HIGH IMPEDANCE
b) HIGH IMPEDANCE TO VOL, VOH TO VOL,
AND VOL TO HIGH IMPEDANCE
Figure 1. Load Circuits for Enable/Disable Times
_______________________________________________________________________________________
7
MAX1332/MAX1333
TIMING CHARACTERISTICS (MAX1333) (Figure 4)
Typical Operating Characteristics
(AVDD = +5V, DVDD = +3V, VREF = 4.096V, fSCLK = 64MHz. TA = +25°C, unless otherwise noted.)
MAX1332
OFFSET ERROR vs. AVDD
GAIN ERROR vs. AVDD
MAX1332 toc02
1.5
1.5
1.0
1.0
GAIN ERROR (LSB)
OFFSET ERROR (LSB)
2.0
MAX1332 toc01
2.0
0.5
0
-0.5
-1.0
0.5
0
-0.5
-1.0
DVDD = +3V
fSCLK = 64MHz
-1.5
DVDD = +3V
fSCLK = 64MHz
-1.5
-2.0
-2.0
4.75
4.85
4.95
5.05
5.25
5.15
4.75
4.85
AVDD (V)
GAIN ERROR vs. AVDD
5.15
5.25
MAX1332 toc04
MAX1332 toc03
12.0
11.8
11.6
1.0
11.4
0.5
IAVDD (mA)
GAIN ERROR (LSB)
5.05
AVDD SUPPLY CURRENT vs. TEMPERATURE
1.5
0
-0.5
11.2
11.0
10.8
10.6
-1.0
10.4
DVDD = +3V
fSCLK = 64MHz
-1.5
ZERO-SCALE INPUT
fSCLK = 64MHz
10.2
-2.0
10.0
4.75
4.85
4.95
5.05
5.25
5.15
-40
-15
AVDD (V)
10
35
60
85
TEMPERATURE (°C)
AVDD SUPPLY CURRENT vs. fSCLK
AVDD SUPPLY CURRENT vs. AVDD
11.5
MAX1332 toc06
13.0
MAX1332 toc05
12.0
12.5
12.0
11.0
11.5
IAVDD (mA)
10.5
10.0
9.5
11.0
10.5
10.0
9.5
9.0
DVDD = +3V
ZERO-SCALE INPUT
fSCLK = 64MHz
9.0
8.5
8.5
8.0
8.0
0
8
16
24
32
40
fSCLK (MHz)
8
4.95
AVDD (V)
2.0
IAVDD (mA)
MAX1332/MAX1333
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
48
56
64
4.75
4.85
4.95
5.05
5.15
5.25
AVDD (V)
_______________________________________________________________________________________
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
MAX1332
DVDD SUPPLY CURRENT vs. fSCLK
5.5
DVDD SUPPLY CURRENT vs. DVDD
8
MAX1332 toc08
MAX1332 toc07
6
5
MAX1332 toc09
DVDD SUPPLY CURRENT vs. TEMPERATURE
6.0
7
4
4.0
3.5
6
IDVDD (mA)
IDVDD (mA)
4.5
3
5
2
4
1
3
3.0
ZERO-SCALE INPUT
fSCLK = 64MHz
2.5
2.0
0
-15
10
35
60
85
AVDD = +5V
ZERO-SCALE INPUT
fSCLK = 64MHz
2
0
8
16
TEMPERATURE (°C)
24
32
40
48
56
64
fSCLK (MHz)
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
DVDD (V)
TOTAL SUPPLY CURRENT
vs. THROUGHPUT RATE
100
NO POWER-DOWN
10
MAX1332 toc10
-40
IAVDD + IDVDD (mA)
IDVDD (mA)
5.0
FULL POWER-DOWN
PARTIAL POWER-DOWN
1
0.1
0.001
0.01
0.1
1
10
fCNVST (MHz)
_______________________________________________________________________________________
9
MAX1332/MAX1333
Typical Operating Characteristics (continued)
(AVDD = +5V, DVDD = +3V, VREF = 4.096V, fSCLK = 64MHz. TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(AVDD = +3V, DVDD = +3V, VREF = 2.5V, fSCLK = 40MHz. TA = +25°C, unless otherwise noted.)
MAX1333
0.6
0.4
0.4
0.2
0.2
0
-0.2
1.5
0
-0.2
1.0
0.5
0
-0.5
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.5
-1.0
-1.0
-2.0
0
512 1024 1536 2048 2560 3072 3584 4096
-1.0
AVDD = +3V
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
OFFSET ERROR vs. AVDD
MAX1333 toc05
1.5
1.5
-1
0.5
0
-0.5
-2
-1.0
-3
-1.5
60
85
DVDD = AVDD
1.0
GAIN ERROR (LSB)
GAIN ERROR (LSB)
0
35
2.0
1.0
1
10
GAIN ERROR vs. AVDD
GAIN ERROR vs. TEMPERATURE
2
-15
TEMPERATURE (°C)
2.0
MAX1333 toc04
DVDD = AVDD
3
-40
OUTPUT CODE
4
OFFSET ERROR (LSB)
OFFSET ERROR vs. TEMPERATURE
2.0
MAX1333 toc03
0.8
DNL (LSB)
INL (LSB)
0.6
fSCLK = 32MHz
MAX1333 toc06
0.8
1.0
OFFSET ERROR (LSB)
fSCLK = 32MHz
MAX1333 toc01
1.0
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
MAX1333 toc02
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
0.5
0
-0.5
-1.0
-1.5
AVDD = +3V
-2.0
-2.0
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
-40
-15
35
60
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
85
AVDD (V)
TEMPERATURE (°C)
AVDD (V)
AVDD SUPPLY CURRENT vs. fSCLK
AVDD SUPPLY CURRENT vs. TEMPERATURE
11.5
AVDD SUPPLY CURRENT vs. AVDD
12.0
MAX1333 toc08
12.0
MAX1333 toc07
12.0
11.5
11.5
11.0
10.5
10.5
10.5
10.0
IAVDD (mA)
11.0
IAVDD (mA)
11.0
10.0
10.0
9.5
9.5
9.0
9.0
9.0
8.5
8.5
ZERO-SCALE INPUT
fSCLK = 40MHz
8.5
9.5
8.0
8.0
-40
-15
10
35
TEMPERATURE (°C)
10
10
60
85
MAX1333 toc09
-4
IAVDD (mA)
MAX1332/MAX1333
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
AVDD = DVDD
ZERO-SCALE INPUT
fSCLK = 40MHz
8.0
0
5
10
15
20
25
fSCLK (MHz)
30
35
40
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
AVDD (V)
______________________________________________________________________________________
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
MAX1332/MAX1333
Typical Operating Characteristics (continued)
(AVDD = +3V, DVDD = +3V, VREF = 2.5V, fSCLK = 40MHz. TA = +25°C, unless otherwise noted.)
MAX1333
DVDD SUPPLY CURRENT
vs. TEMPERATURE
2.5
2.5
1.5
1.5
1.0
1.0
0.5
0.5
10
35
85
60
0
5
10
TEMPERATURE (°C)
15
20
25
30
35
SINAD vs. INPUT FREQUENCY
88
64
76
-94
fSCLK = 32MHz
fSCLK = 32MHz
-100
1200
1600
2000
0
400
INPUT FREQUENCY (kHz)
800
1200
1600
NO POWER-DOWN
IAVDD + IDVDD (mA)
-2
-3
-4
fSCLK = 32MHz
AIN = -0.1dBFS
-6
1
2
3
4
5
6
INPUT FREQUENCY (MHz)
800
1200
1600
2000
INPUT FREQUENCY (kHz)
100
MAX1333 toc16
-1
0
400
TOTAL SUPPLY CURRENT
vs. THROUGHPUT RATE
0
-5
0
2000
INPUT FREQUENCY (kHz)
OUTPUT AMPLITUDE
vs. INPUT FREQUENCY
OUTPUT AMPLITUDE (dBFS)
-82
-88
70
800
3.00
-76
82
fSCLK = 32MHz
62
2.95
THD vs. INPUT FREQUENCY
THD (dBc)
SFDR (dBc)
94
66
2.90
-70
MAX1333 toc14
MAX1333 toc13
100
68
2.85
DVDD (V)
SFDR vs. INPUT FREQUENCY
70
400
2.80
fSCLK (MHz)
72
0
2.75
2.70
40
MAX1333 toc15
-15
AVDD = +3V
ZERO-SCALE INPUT
fSCLK = 40MHz
0
0
-40
SINAD (dB)
2.0
7
8
MAX1333 toc17
1.25
1.00
3.0
IDVDD (mA)
IDVDD (mA)
IDVDD (mA)
ZERO-SCALE INPUT
fSCLK = 40MHz
3.5
3.0
2.0
MAX1333 toc12
3.5
3.25
4.0
MAX1333 toc11
4.0
MAX1333 toc10
3.75
3.50
3.00
2.75
2.50
2.25
2.00
1.75
1.50
DVDD SUPPLY CURRENT vs. DVDD
DVDD SUPPLY CURRENT vs. fSCLK
4.00
10
FULL POWER-DOWN
PARTIAL POWER-DOWN
1
0.1
0.001
0.01
0.1
1
10
fCNVST (MHz)
______________________________________________________________________________________
11
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
MAX1332/MAX1333
Pin Description
PIN
FUNCTION
1
AIN0P
Positive Analog-Input Channel 0
2
AIN0N
Negative Analog-Input Channel 0
3
AIN1P
Positive Analog-Input Channel 1
4
AIN1N
Negative Analog-Input Channel 1
5
REF
External Reference Voltage Input. VREF = 1V to (AVDD + 50mV). Bypass REF to AGND with a 0.1µF
and a 1µF.
6
SHDN
Shutdown Input. Pull SHDN low to enter full power-down mode. Drive SHDN high to resume normal
operation regardless of previous software entered into power-down mode.
7
BIP/UNI
Analog-Input-Mode Select. Drive BIP/UNI high to select bipolar-input mode. Pull BIP/UNI low to select
unipolar-input mode.
8
AGND
Analog Ground. Connect all AGNDs and EP to the same potential.
9
CHSEL
Channel-Select Input. Drive CHSEL high to select channel 1. Pull CHSEL low to select channel 0.
10
CNVST
Conversion-Start Input. The first rising edge of CNVST powers up the MAX1332/MAX1333 and begins
acquiring the analog input. A falling edge samples the analog input and starts a conversion. CNVST
also controls the power-down mode of the device (see the Partial Power-Down (PPD) and Full PowerDown (FPD) Mode section).
11
SCLK
Serial-Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed.
DOUT
Serial-Data Output. Data is clocked out on the rising edge of SCLK (see the Starting a Conversion
section).
13
DVDD
Positive-Digital-Supply Input. DVDD is the positive supply input for the digital section of the
MAX1332/MAX1333. Connect DVDD to a 2.7V to 3.6V power supply. Bypass DVDD to DGND with a
0.1µF capacitor in parallel with a 1µF capacitor. Place the bypass capacitors as close to the device
as possible.
14
DGND
Digital Ground. Ensure that the potential difference between AGND and DGND is less than ±0.3V.
15
AVDD
Positive-Analog-Supply Input. AVDD is the positive supply input for the analog section of the
MAX1332/MAX1333. Connect AVDD to a 4.75V to 5.25V power supply for the MAX1332. Connect
AVDD to a 2.7V to 3.6V power supply for the MAX1333. Bypass AVDD to AGND with a 0.1µF capacitor
in parallel with a 1µF capacitor. Place the bypass capacitors as close to the device as possible.
16
AGND
—
EP
12
12
NAME
Analog Ground. Connect all AGNDs and EP to the same potential.
Exposed Paddle. Internally connected to AGND. Connect the exposed paddle to the analog ground plane.
______________________________________________________________________________________
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
The MAX1332/MAX1333 use an input track and hold
(T/H) circuit along with a successive-approximation
register (SAR) to convert a differential analog input signal to a digital 12-bit output. The serial interface
requires only three digital lines (SCLK, CNVST, and
DOUT) and provides easy interfacing to microcontrollers (µCs) and DSPs. Figure 2 shows the simplified
block diagram for the MAX1332/MAX1333.
Power Supplies
The MAX1332/MAX1333 accept two power supplies
that allow the digital noise to be isolated from sensitive
analog circuitry. For both the MAX1332 and MAX1333,
the digital power-supply input accepts a supply voltage
of +2.7V to +3.6V. However, the supply voltage range
for the analog power supply is different for each
device. The MAX1332 accepts a +4.75V to +5.25V
analog power supply, and the MAX1333 accepts
a +2.7V to +3.6V analog power supply. See the Layout,
Grounding, and Bypassing section for information on
how to isolate digital noise from the analog power input.
The MAX1332/MAX1333s’ analog power supply consists of one AVDD input, two AGND inputs, and the
exposed paddle (EP). The digital power input consists
of one DVDD input and one DGND input. Ensure that
the potential on both AGND inputs is the same.
Furthermore, ensure that the potential between AGND
and DGND is limited to ±0.3V. Ideally there should be
no potential difference between AGND and DGND.
There are no power sequencing issues between AVDD
and DVDD. The analog and digital power supplies are
insensitive to power-up sequencing.
True-Differential Analog Input T/H
The equivalent input circuit of Figure 3 shows the
MAX1332/MAX1333s’ input architecture, which is composed of a T/H, a comparator, and a switched-capacitor DAC. On power-up, the MAX1332/MAX1333 enter
full power-down mode. Drive CNVST high to exit full
power-down mode and to start acquiring the input. The
positive input capacitor is connected to AIN_P and the
negative input capacitor is connected to AIN_N. The
T/H enters its hold mode on the falling edge of CNVST
and the ADC starts converting the sampled difference
between the analog inputs. Once a conversion has
been initiated, the T/H enters acquisition mode for the
next conversion on the 13th falling edge of SCLK after
CNVST has been transitioned from high to low.
The time required for the T/H to acquire an input signal
is determined by how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
MAX1332/MAX1333
Detailed Description
DVDD
AVDD
CHSEL
BIP/UNI
AIN0P
AIN0N
AIN1P
INPUT
MUX
AND T/H
OUTPUT
BUFFER
12-BIT SAR
ADC
DOUT
AIN1N
REF
MAX1332
MAX1333
AGND
CONTROL
LOGIC AND
TIMING
CNVST
SCLK
SHDN
DGND
Figure 2. Simplified Functional Diagram
the acquisition time lengthens. The acquisition time,
tACQ, is the minimum time needed for the signal to be
acquired. It is calculated by the following equation:
tACQ ≥ k x (RSOURCE + RIN) x CIN
where:
k = 9 ≈ ln (2 × 2N )
The constant k is the number of RC time constants
required so that the voltage on the internal sampling
capacitor reaches N-bit accuracy, i.e., so that the difference between the input voltage and the sampling
capacitor voltage is equal to 0.5 LSB. N = 12 for the
MAX1332/MAX1333.
RIN = 250Ω is the equivalent differential analog input
resistance, CIN = 14pF is the equivalent differential analog input capacitance, and R SOURCE is the source
impedance of the input signal. Note that tACQ is never
less than 52µs for the MAX1332 and 78µs for the
MAX1333, and any source impedance below 160Ω does
not significantly affect the ADC’s AC performance.
Input Bandwidth
The ADC’s input-tracking circuitry has a 5MHz smallsignal bandwidth, making it possible to digitize highspeed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band
______________________________________________________________________________________
13
MAX1332/MAX1333
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
AVDD
CAPACITIVE
DAC
CIN+
RIN+
AIN_P
COMP
CIN-
CONTROL
LOGIC
RIN-
AIN_N
AGND
Figure 3a. Equivalent Input Circuit (Acquisition Mode)
AVDD
CAPACITIVE
DAC
CIN+
RIN+
AIN_P
COMP
CIN-
CONTROL
LOGIC
RIN-
AIN_N
AGND
Figure 3b. Equivalent Input Circuit (Hold/Conversion Mode)
of interest, lowpass or bandpass filtering is recommended to limit the bandwidth of the input signal.
wideband amplifier that settles quickly and is stable
with the ADC’s 14pF input capacitance.
Input Buffer
See the Maxim website (www.maxim-ic.com) for application notes on how to choose the optimum buffer
amplifier for an ADC application. The MAX4430 is one
of the devices that is ideal for this application.
To improve the input signal bandwidth under AC conditions, drive the input with a wideband buffer (>50MHz)
that can drive the ADC’s input capacitance (14pF) and
settle quickly. Most applications require an input buffer
to achieve 12-bit accuracy. Although slew rate and
bandwidth are important, the most critical input buffer
specification is settling time. The sampling requires an
acquisition time of 52µs for the MAX1332 and 78µs for
the MAX1333. At the beginning of the acquisition, the
ADC internal sampling capacitors connect to the analog inputs, causing some disturbance. Ensure the
amplifier is capable of settling to at least 12-bit accuracy during this interval. Use a low-noise, low-distortion,
14
Differential Analog Input Range and
Protection
The MAX1332/MAX1333 produce a digital output that
corresponds to the differential analog input voltage as
long as the differential analog inputs are within the
specified range. When operating in unipolar mode
(BIP/UNI = 0), the usable differential analog input range
is from 0 to V REF. When operating in bipolar mode
(BIP/UNI = 1), the differential analog input range is from
-V REF /2 to +V REF /2. In both unipolar and bipolar
______________________________________________________________________________________
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
MAX1332/MAX1333
CNVST
tHOLD
tSETUP
SCLK
tCSW
tCP
tDOT
tCRDD
tCFDE
DOUT
tDHOLD
Figure 4. Detailed Serial-Interface Timing
tCONV
CNVST
tSETUP
SCLK
1
POWER- MODE SELECTION WINDOW
2
3
4
5
6
7
8
9
10
tACQ
11
12
13
14
15
16
CONTINUOUS-CONVERSION
SELECTION WINDOW
DOUT
HIGH-Z
0
0
ANALOG
INPUT TRACK
AND HOLD STATE
0
D11
D10
D9
HOLD
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
TRACK
Figure 5. Interface Timing Sequence
modes, the input common-mode voltage can vary as
long as the voltage at any single analog input (VAIN_P,
VAIN_N) remains within 50mV of the analog power supply rails (AVDD, AGND).
As shown in Figure 3, internal protection diodes confine
the analog input voltage within the region of the analog
power-supply rails (AVDD, AGND) and allow the analog
input voltage to swing from AGND - 0.3V to AVDD + 0.3V
without damage. Input voltages beyond AGND - 0.3V
and AVDD + 0.3V forward bias the internal protection
diodes. In this situation, limit the forward diode current to
50mA to avoid damaging the MAX1332/MAX1333.
Serial Digital Interface
Timing and Control
Conversion-start and data-read operations are controlled by the CNVST and SCLK digital inputs. CNVST
controls the state of the T/H as well as when a conversion is initiated. CNVST also controls the power-down
mode of the device (see the Partial Power-Down (PPD)
and Full Power-Down (FPD) Mode section). SCLK
clocks data out of the serial interface and sets the conversion speed. Figures 4 and 5 show timing diagrams
that outline the serial-interface operation.
Starting a Conversion
On power-up, the MAX1332/MAX1333 enter full powerdown mode. The first rising edge of CNVST exits the full
power-down mode and the MAX1332/MAX1333 begin
acquiring the analog input. A CNVST falling edge initiates a conversion sequence. The T/H stage holds the
input voltage; DOUT changes from high impedance to
logic low; and the ADC begins to convert at the first
SCLK rising edge. SCLK is used to drive the conversion process, and it shifts data out of DOUT. SCLK
begins shifting out the data after the 4th rising edge of
SCLK. DOUT transitions tDOT after each SCLK’s rising
edge and remains valid for tDHOLD after the next rising
edge. The 4th rising clock edge produces the MSB of
the conversion result at DOUT, and the MSB remains
valid tDHOLD after the 5th rising edge of SCLK. Sixteen
______________________________________________________________________________________
15
MAX1332/MAX1333
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
CNVST
SCLK
DOUT
1
13
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
16
D2
D1
D0
1
0
0
Figure 6. Continuous Conversion with Burst or Continuous Clock
CONVST MUST GO HIGH AFTER 4TH BUT BEFORE 13TH SCLK RISING EDGE
CNVST
ONE 8-BIT TRANSFER
SCLK
1ST SCLK RISING EDGE
DOUT
0
0
0
D11
MODE
D10
D9
D8
NORMAL
D7
DOUT GOES HIGH IMPEDANCE ONCE CONVST GOES HIGH
PPD
Figure 7. SPI Interface—Partial Power-Down
rising SCLK edges are needed to clock out the three
leading zeros, 12 data bits, and a trailing zero. For continuous operation, pull CNVST high between the 14th
and the 15th rising edges of SCLK. The highest
throughput is achieved when performing continuous
conversions. If CNVST is low during the rising edge of
the 16th SCLK, the DOUT line goes to a high-impedance state on either CNVST’s rising edge or the next
SCLK’s rising edge, enabling the serial interface to be
shared by multiple devices. Figure 6 illustrates a conversion using a typical serial interface.
Partial Power-Down (PPD) and Full PowerDown (FPD) Mode
Power consumption is reduced significantly by placing
the MAX1332/MAX1333 in either partial power-down
mode or full power-down mode. Partial power-down
mode is ideal for infrequent data sampling and fast
wake-up time applications. Once CNVST is transitioned
from high to low, pull CNVST high any time after the 4th
rising edge of the SCLK but before the 13th rising edge
16
of the SCLK to enter partial power-down mode (see
Figure 7). Drive CNVST low and then drive high before
the 4th SCLK to remain in partial power-down mode. This
reduces the supply current to 3.3mA. Drive CNVST low
and allow at least 13 SCLK cycles to elapse before driving CNVST high to exit partial power-down mode.
Full power-down mode reduces the supply current to
0.2µA and is ideal for infrequent data sampling. To
enter full power-down mode, the MAX1332/MAX1333
must first be in partial power-down mode. While in partial power-down mode, repeat the sequence used to
enter partial power-down mode to enter full powerdown mode (see Figure 8). Drive CNVST low and allow
at least 13 SCLK cycles to elapse before driving
CNVST high to exit full power-down mode.
Maintain a logic low or a logic high on SCLK and all
digital inputs at DVDD or DGND while in either partial
power-down or full power-down mode to minimize
power consumption.
______________________________________________________________________________________
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
MAX1332/MAX1333
EXECUTE PARTIAL POWER-DOWN TWICE
CNVST
1ST 8-BIT TRANSFER
2ND 8-BIT TRANSFER
SCLK
1ST SCLK RISING EDGE
0
DOUT
0
0
1ST SCLK RISING EDGE
D11
MODE
D10
D9
D8
D7
0
0
0
0
PPD
NORMAL
0
0
0
0
RECOVERY
FPD
Figure 8. SPI Interface—Full Power-Down
7FF
ZS = 0
FFE
1 LSB =
FFD
VREF
4096
7FE
+FS = VREF
2
ZS = 0
FULL-SCALE
TRANSITION
-VREF
2
V
1 LSB = REF
4096
-FS =
FFC
OUTPUT CODE (hex)
OUTPUT CODE (hex)
FULL-SCALE
TRANSITION
FS = VREF
FFF
FFB
004
001
000
FFF
FFE
003
002
801
001
800
000
0
1
2
3
4
FS - 1.5 LSB
DIFFERENTIAL INPUT VOLTAGE (LSB)
FS
Figure 9. Unipolar Transfer Function
Another way of entering the full power-down mode is
using the SHDN input. Drive SHDN to a logic low to put
the device into the full power-down mode. Drive SHDN
high to exit full power-down mode and return to normal
operating mode. SHDN overrides any software-controlled
power-down mode and every time it is deasserted, it
places the MAX1332/MAX1333 in its normal mode of
operation regardless of its previous state.
-FS
0
-FS + 0.5 LSB
+FS - 1.5 LSB
DIFFERENTIAL INPUT VOLTAGE (LSB)
+FS
Figure 10. Bipolar Transfer Function
Transfer Function
The MAX1332/MAX1333 output is straight binary in
unipolar mode and is two’s complement in bipolar mode.
Figure 9 shows the unipolar transfer function for the
MAX1332/MAX1333. Table 1 shows the unipolar relationship between the differential analog input voltage and
the digital output code. Figure 10 shows the bipolar
transfer function for the MAX1332/MAX1333. Table 2
shows the bipolar relationship between the differential
analog input voltage and the digital output code.
______________________________________________________________________________________
17
MAX1332/MAX1333
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
Table 1. Unipolar Code Table (MAX1332)
BINARY DIGITAL OUTPUT
CODE D11–D0
HEXADECIMAL EQUIVALENT
OF D11–D0
DECIMAL EQUIVALENT OF
D11–D0 (CODE10)
DIFFERENTIAL INPUT
VOLTAGE (V) (VREF = 4.096V )
1111 1111 1111
0xFFF
4095
+4.095 ±0.5 LSB
1111 1111 1110
0xFFE
4094
+4.094 ±0.5 LSB
1000 0000 0001
0x801
2049
+2.049 ±0.5 LSB
1000 0000 0000
0x800
2048
+2.048 ±0.5 LSB
0111 1111 1111
0x7FF
2047
+2.047 ±0.5 LSB
0000 0000 0001
0x001
1
+0.001 ±0.5 LSB
0000 0000 0000
0x000
0
+0.000 ±0.5 LSB
HEXADECIMAL EQUIVALENT
OF D11–D0
DECIMAL EQUIVALENT OF
D11–D0 (CODE10)
DIFFERENTIAL INPUT
VOLTAGE (V) (VREF = 4.096V)
0111 1111 1111
0x7FF
+2047
+2.047 ±0.5 LSB
0111 1111 1110
0x7FE
+2046
+2.046 ±0.5 LSB
0000 0000 0001
0x001
+1
+0.001 ±0.5 LSB
0000 0000 0000
0x000
0
0.000 ±0.5 LSB
1111 1111 1111
0xFFF
-1
-0.001 ±0.5 LSB
1000 0000 0001
0x801
-2047
-2.047 ±0.5 LSB
1000 0000 0000
0x800
-2048
-2.048 ±0.5 LSB
Table 2. Bipolar Code Table (MAX1332)
TWO’s-COMPLEMENT
DIGITAL OUTPUT CODE
D11–D0
Determine the differential analog input voltage as a
function of VREF and the digital output code with the following equation:
∆VAIN = LSB × CODE10 ± 0.5 × LSB
where:
∆VAIN = VAIN _ P − VAIN _ N
V
V
LSB = REF = REF
212 4096
CODE10 = the decimal equivalent of the digital output
code (see Tables 1 and 2).
±0.5 x LSB represents the quantization error that is
inherent to any ADC.
When using a 4.096V reference, 1 LSB equals 1.0mV.
When using a 2.5V reference, 1 LSB equals 0.61mV.
18
Applications Information
External Reference
The MAX1332/MAX1333 use an external reference
between 1V and (AV DD + 50mV). Bypass REF with
a 1µF capacitor in parallel with a 0.1µF capacitor
to AGND for best performance (see the Typical
Operating Circuit).
Connection to Standard Interfaces
The MAX1332/MAX1333 serial interface is fully compatible with SPI, QSPI and MICROWIRE (see Figure 11). If
a serial interface is available, set the µC’s serial interface in master mode so the µC generates the serial
clock. Choose a clock frequency based on the AVDD
and DVDD amplitudes.
SPI and MICROWIRE
When using SPI or MICROWIRE, the MAX1332/
MAX1333 are compatible with all four modes programmed with the CPHA and CPOL bits in the SPI or
MICROWIRE control register. (This control register is in
______________________________________________________________________________________
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
DSP Interface to the TMS320C54_
The MAX1332/MAX1333 can be directly connected to
the TMS320C54_ family of DSPs from Texas
Instruments. Set the DSP to generate its own clocks or
use external clock signals. Use either the standard or
buffered serial port. Figure 15 shows the simplest interface between the MAX1332/MAX1333 and the
TMS320C54_, where the transmit serial clock (CLKX)
drives the receive serial clock (CLKR) and SCLK, and
the transmit frame sync (FSX) drives the receive frame
sync (FSR) and CNVST.
For continuous conversion, set the serial port to transmit a clock and pulse the frame sync signal for a clock
period before data transmission. Use the serial port
configuration (SPC) register to set up with internal
frame sync (TXM = 1), CLKX driven by an on-chip clock
source (MCM = 1), burst mode (FSM = 1), and 16-bit
word length (FO = 0).
This setup allows continuous conversions provided that
the data transmit register (DXR) and the data-receive
register (DRR) are serviced before the next conversion.
Alternately, autobuffering can be enabled when using
the buffered serial port to execute conversions and
read the data without µC intervention. Connect DVDD to
the TMS320C54_ supply voltage. The word length can
be set to 8 bits with FO = 1 to implement the power-
CNVST
SCLK
MISO
DOUT
+3V TO +5V
MAX1332
MAX1333
SS
a) SPI
CS
CNVST
SCK
SCLK
MISO
DOUT
+3V TO +5V
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
the 12 bits of data from the ADC, QSPI allows acquiring
the conversion data with a single 16-bit transfer. The
MAX1332/MAX1333 require 16 clock cycles from the
µC to clock out the 12 bits of data. Figure 14 shows a
transfer using CPOL = 1 and CPHA = 1. The conversion result contains three zeros, followed by the 12 data
bits and a trailing zero with the data in MSB-first format.
I/O
SCK
MAX1332/MAX1333
the bus master, not the MAX1332/MAX1333.)
Conversion begins with a CNVST falling edge. DOUT
goes low, indicating a conversion is in progress. Two
consecutive 1-byte reads are required to get the full 12
bits from the ADC. DOUT transitions on SCLK rising
edges and is guaranteed to be valid tDOT later and
remain valid until tDHOLD after the following SCLK rising
edge. When using CPOL = 0 and CPHA = 0 or CPOL =
1 and CPHA = 1, the data is clocked into the µC on the
following or next SCLK rising edge. When using CPOL
= 0 and CPHA = 1 or CPOL = 1 and CPHA = 0, the
data is clocked into the µC on the next falling edge.
See Figure 11 for connections and Figures 12 and 13
for timing. See the Timing Characteristics table to determine the best mode to use.
SS
MAX1332
MAX1333
b) QSPI
I/O
CNVST
SK
SCLK
SI
DOUT
MAX1332
MAX1333
c) MICROWIRE
Figure 11. Common Serial-Interface Connections to the
MAX1332/MAX1333
down modes. The CNVST pin must idle high to remain
in either power-down state.
Another method of connecting the MAX1332/MAX1333
to the TMS320C54_ is to generate the clock signals
external to either device. This connection is shown in
Figure 16 where serial clock (CLOCK) drives the
receive serial clock (CLKR) and SCLK, and the convert
signal (CONVERT) drives the receive frame sync (FSR)
and CNVST.
The serial port must be set up to accept an external
receive clock and external receive frame sync. Write
the serial port configuration (SPC) register as follows:
• TXM = 0, external frame sync
• MCM = 0, CLKX is taken from the CLKX pin
• FSM = 1, burst mode
• FO = 0, data transmitted/received as 16-bit words
This setup allows continuous conversion provided that
the data-receive register (DRR) is serviced before the
next conversion. Alternately, autobuffering can be
______________________________________________________________________________________
19
MAX1332/MAX1333
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
CNVST
1
SCLK
8
HIGH
IMPEDANCE
DOUT
D11
D10
D9
D8
9
D7
16
D6
D5
D4
1ST BYTE READ
D3
D2
D1
HIGH
IMPEDANCE
D0
2ND BYTE READ
Figure 12. SPI/MICROWIRE Serial-Interface Timing—Single Conversion
CNVST
1
SCLK
13
0
DOUT
0
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
14
D0
16
0
0
1
0
0
Figure 13. SPI/MICROWIRE Serial-Interface Timing—Continuous Conversion
CNVST
1
SCLK
DOUT
2
16
HIGH
IMPEDANCE
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
HIGH
IMPEDANCE
D0
Figure 14. QSPI Serial-Interface Timing
DVDD
DVDD
SCLK
CLKX
MAX1332
MAX1333 CNVST
CLKR
TMS320C54x
FSX
FSR
DOUT
DR
Figure 15. Interfacing to the TMS320C54_ Internal Clocks
20
DVDD
DVDD
SCLK
CLKR
TMS320C54x
FSR
MAX1332 CNVST
MAX1333 DOUT
DR
CLOCK
CONVERT
Figure 16. Interfacing to the TMS320C54_ External Clocks
______________________________________________________________________________________
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
MAX1332/MAX1333
CNVST
1
SCLK
DOUT
D0
0
8
0
0
0
D11
D10
D9
D8
16
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
Figure 17. DSP Interface—Continuous Conversion
CNVST
SCLK
DOUT
1
1
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
Figure 18. DSP Interface—Single Conversion—Continuous/Burst Clock
enabled when using the buffered serial port to read the
data without µC intervention. Connect DV DD to the
TMS320C54_ supply voltage.
The MAX1332/MAX1333 can also be connected to the
TMS320C54_ by using the data transmit (DX) pin to
drive CNVST and the transmit clock (CLKX) generated
internally to drive SCLK. A pullup resistor is required on
the CNVST signal to keep it high when DX goes high
impedance and write (0001)h to the data transmit register (DXR) continuously for continuous conversions. The
power-down modes can be entered by writing (00FF)h
to the DXR (see Figures 17 and 18).
DSP Interface to the ADSP21_ _ _
The MAX1332/MAX1333 can be directly connected to
the ADSP21_ _ _ family of DSPs from Analog Devices.
Figure 19 shows the direct connection of the
MAX1332/MAX1333 to the ADSP21_ _ _. There are two
modes of operation that can be programmed to interface with the MAX1332/MAX1333. For continuous conversions, idle CNVST low and pulse it high for one
clock cycle during the LSB of the previous transmitted
word. Configure the ADSP21_ _ _ STCTL and SRCTL
registers for early framing (LAFR = 0) and for an active-
high frame (LTFS = 0, LRFS = 0) signal. In this mode,
the data-independent frame-sync bit (DITFS = 1) can
be selected to eliminate the need for writing to the
transmit data register more than once. For single conversions, idle CNVST high and pulse it low for the entire
conversion. Configure the ADSP21_ _ _ STCTL and
SRCTL registers for late framing (LAFR = 1) and for an
active-low frame (LTFS = 1, LRFS = 1) signal. This is
also the best way to enter the power-down modes by
setting the word length to 8 bits (SLEN = 0111).
Connect the DVDD pin to the ADSP21_ _ _ supply voltage (see Figures 17 and 18).
Layout, Grounding, and Bypassing
For best performance, use PC boards. Wire-wrap
boards must not be used. Board layout must ensure
that digital and analog signal lines are separated from
each other. Do not run analog and digital (especially
clock) lines parallel to one another, or digital lines
underneath the ADC package.
Figure 20 shows the recommended system ground
connections. Establish an analog ground point at
AGND and a digital ground point at DGND. Connect all
other analog grounds to the analog ground point.
______________________________________________________________________________________
21
MAX1332/MAX1333
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
ANALOG SUPPLY
AVDD
DVDD
TCLK
MAX1332
MAX1333 CNVST
RCLK
DIGITAL SUPPLY
RETURN
DVDD
DGND
DVDD
ANALOG
GROUND
POINT
VDDINT
SCLK
RETURN
DIGITAL
GROUND
POINT
10Ω*
ADSP21_ _ _
TFS
RFS
DOUT
DR
AVDD
AGND
DGND
MAX1332
MAX1333
DVDD
DIGITAL
CIRCUITRY
DATA
*OPTIONAL
Figure 19. Interfacing to the ADSP21_ _ _
Figure 20. Power-Supply Grounding Condition
Connect all digital grounds to the digital ground point.
For lowest noise operation, make the power supply
returns as low impedance and as short as possible.
Connect the analog ground point to the digital ground
point together at the IC.
High-frequency noise in the power supplies degrades
the ADC’s performance. Bypass AVDD to AGND with
0.1µF and 1µF bypass capacitors. Likewise, bypass
DVDD to DGND with 0.1µF and 1µF bypass capacitors.
Minimize capacitor lead lengths for best supply noise
rejection. To reduce the effects of supply noise, a 10Ω
resistor can be connected as a lowpass filter to attenuate supply noise (see Figure 20).
the transfer function once offset and gain errors have
been nullified. INL deviations are measured at every
step and the worst-case deviation is reported in the
electrical characteristics table.
Exposed Paddle
The MAX1332/MAX1333 TQFN package has an exposed
paddle on the bottom of the package, providing a very
low thermal resistance path for heat removal from the IC,
as well as a low-inductance path to ground. The pad is
electrically connected to AGND on the MAX1332/
MAX1333 and must be soldered to the circuit board analog ground plane for proper thermal and electrical performance. Refer to the Maxim Application Note HFAN-08.1:
Thermal Considerations for QFN and Other Exposed Pad
Packages, for additional information.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer
function from a straight line. For the MAX1332/
MAX1333, this straight line is between the end points of
22
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and
the ideal value of 1 LSB. A DNL error specification of
less than 1 LSB guarantees no missing codes and a
monotonic transfer function. For the MAX1332/
MAX1333, DNL deviations are measured at every step
and the worst-case deviation is reported in the electrical characteristics table.
Offset Error
Offset error is a figure of merit that indicates how well
the actual transfer function matches the ideal transfer
function at a single point. Typically, the point at which
the offset error is specified is at or near the zero-scale
of the transfer function or at or near the midscale of the
transfer function.
For the MAX1332/MAX1333, operating with a unipolar
transfer function, the ideal zero-scale digital output
transition from 0x000 to 0x001 occurs at 0.5 LSB above
AGND. Unipolar offset error is the amount of deviation
between the measured zero-scale transition point and
the ideal zero-scale transition point.
For the MAX1332/MAX1333, operating with a bipolar
transfer function, the ideal midscale digital output transition from 0xFFF to 0x000 occurs at 0.5 LSB below
AGND. Bipolar offset error is the amount of deviation
______________________________________________________________________________________
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
CNVST
In reality, there are other noise sources such as thermal
noise, reference noise, and clock jitter that also
degrade SNR.
For the MAX1332/MAX1333, SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS
noise includes all spectral components to the Nyquist
frequency excluding the fundamental, the first five harmonics, and the DC offset.
ANALOG
INPUT
tAD
tAJ
SAMPLED
DATA (T/H)
T/H
TRACK
HOLD
TRACK
Signal-to-Noise Plus Distortion (SINAD)
Figure 21. T/H Aperture Timing
between the measured midscale transition point and
the ideal midscale transition point.
Gain Error
Gain error is a figure of merit that indicates how well the
slope of the actual transfer function matches the slope
of the ideal transfer function. For the MAX1332/
MAX1333, the gain error is the difference of the measured full-scale and zero-scale transition points minus
the difference of the ideal full-scale and zero-scale
transition points.
For the unipolar input, the full-scale transition point is
from 0xFFE to 0xFFF and the zero-scale transition point
if from 0x000 to 0x001.
For the bipolar input, the full-scale transition point is
from 0x7FE to 0x7FF and the zero-scale transition point
is from 0x800 to 0x801.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of the CNVST and the instant when an
actual sample is taken (Figure 21).
Signal-to-Noise Ratio (SNR)
SNR is a dynamic figure of merit that indicates the converter’s noise performance.
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
SINAD is a dynamic figure of merit that indicates the
converter’s noise and distortion performance.
SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus
distortion includes all spectral components to the
Nyquist frequency excluding the fundamental and the
DC offset:
⎡
⎤
SIGNALRMS
SINAD(dB) = 20 × log⎢
⎥
⎣ (NOISE + DISTORTION)RMS ⎦
Effective Number of Bits (ENOB)
ENOB specifies the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s
error consists of quantization noise only. ENOB for a fullscale sinusoidal input waveform is computed from:
ENOB =
SINAD −1.76
6.02
Total Harmonic Distortion (THD)
THD is a dynamic figure of merit that indicates how much
harmonic distortion the converter adds to the signal.
THD is the ratio of the RMS sum of the first five harmonics of the fundamental signal to the fundamental itself.
This is expressed as:
⎛
V22 + V32 + V42 + V52 + V62
THD = 20 × log⎜
V1
⎜
⎝
⎞
⎟
⎟
⎠
where V1 is the fundamental amplitude, and V2 through
V6 are the amplitudes of the 2nd- through 6th-order
harmonics.
______________________________________________________________________________________
23
MAX1332/MAX1333
tion error only and results directly from the ADC’s resolution (N bits):
SNRdB[max] = 6.02dB x N + 1.76dB
then swept up to the point where the amplitude of the
digitized conversion result has decreased by -3dB.
Power-Supply Rejection (PSR)
PSR is defined as the shift in offset error when the analog power supply is moved from 2.7V to 3.6V.
Pin Configuration
SCLK
CNVST
CHSEL
11
10
AGND
7
BIP/UNI
6
SHDN
5
REF
9
Selector Guide
PART
AVDD
(V)
MAX SAMPLING RATE
(Msps)
MAX1332ETE
+5
3
MAX1333ETE
+3
2
Chip Information
PROCESS: BiCMOS
Full-Linear Bandwidth
Full-linear bandwidth is the frequency at which the signal-to-noise plus distortion (SINAD) is equal to 68dB.
The amplitude of the analog input signal is -0.5dBFS.
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC in such a way that the signal’s slew rate does not
limit the ADC’s performance. The input frequency is
24
8
4
3
AIN1P
AGND 16
Full-Power Bandwidth
A large -0.5dB FS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as fullpower input bandwidth frequency.
MAX1332
MAX1333
AVDD 15
Channel-to-Channel Isolation
Channel-to-channel isolation is a figure of merit that
indicates how well each analog input is isolated from
the others. The channel-to-channel isolation for the
MAX1332/MAX1333 is measured by applying a low-frequency 500kHz -0.5dBFS sine wave to the on channel
while a high-frequency 900kHz -0.5dBFS sine wave is
applied to the off channel. An FFT is taken for the on
channel. From the FFT data, channel-to-channel
crosstalk is expressed in dB as the power ratio of the
500kHz low-frequency signal applied to the on channel
and the 900kHz high-frequency crosstalk signal from
the off channel.
DOUT
DGND 14
2
• 4th-order intermodulation products (IM4): 3f IN1 fIN2, 3fIN2 - fIN1, 3fIN1 + fIN2, 3fIN2 + fIN1
• 5th-order intermodulation products (IM5): 3f IN1 2fIN2, 3fIN2 - 2fIN1, 3fIN1 + 2fIN2, 3fIN2 + 2fIN1
DVDD 13
AIN0N
• 3rd-order intermodulation products (IM3): 2fIN1 fIN2, 2fIN2 - fIN1, 2fIN1 + fIN2, 2fIN2 + fIN1
TOP VIEW
1
IMD is the total power of the IM2 to IM5 intermodulation
products to the Nyquist frequency relative to the total
input power of the two input tones fIN1 and fIN2. The
individual input tone levels are at -7dBFS. The intermodulation products are as follows:
• 2nd-order intermodulation products (IM2): f IN1 +
fIN2, fIN2 - fIN1
12
Intermodulation Distortion (IMD)
AIN1N
Spurious-Free Dynamic Range (SFDR)
SFDR is a dynamic figure of merit that indicates the
lowest usable input signal amplitude. SFDR is the ratio
of the RMS amplitude of the fundamental (maximum
signal component) to the RMS value of the next-largest
spurious component, excluding DC offset. SFDR is
specified in decibels relative to the carrier (dBc).
AIN0P
MAX1332/MAX1333
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
______________________________________________________________________________________
3Msps/2Msps, 5V/3V, 2-Channel, TrueDifferential 12-Bit ADCs
12x16L QFN THIN.EPS
D2
0.10 M C A B
b
D
D2/2
D/2
E/2
E2/2
CL
(NE - 1) X e
E
E2
L
k
e
CL
(ND - 1) X e
CL
CL
0.10 C
0.08 C
A
A2
L
A1
L
e
e
PACKAGE OUTLINE
12, 16L, THIN QFN, 3x3x0.8mm
E
21-0136
PKG
12L 3x3
REF.
MIN.
A
0.70
b
0.20
D
2.90
E
e
2.90
L
0.45
NOM.
0.75
0.80
0.70
0.75
0.80
0.25
0.30
0.20
0.25
0.30
3.00
3.10
2.90
3.00
3.10
T1233-1
3.00
3.10
2.90
3.00
3.10
T1233-3
0.95
1.10
1.25
T1633-1
0.95
1.10
1.25
T1633-2
0.95
1.10
1.25
T1633F-3
0.65
0.80
0.95
T1633-4
0.95
1.10
1.25
0.50 BSC.
NOM.
0.65
0.30
0.40
12
16
3
4
NE
3
4
k
MAX.
0.50 BSC.
N
0.50
0
0.02
0.05
0
0.02
0.05
0.25
0.20 REF
-
-
0.25
0.20 REF
-
-
A2
EXPOSED PAD VARIATIONS
MIN.
ND
A1
2
16L 3x3
MAX.
0.55
1
PKG.
CODES
E2
D2
MIN.
NOM.
MAX.
MIN.
NOM. MAX.
0.95
1.10
1.25
0.95
1.10
1.25
0.95
1.10
0.95
1.10
0.95
0.65
0.95
PIN ID
JEDEC
DOWN
BONDS
ALLOWED
0.35 x 45∞
WEED-1
NO
1.25
0.35 x 45∞
WEED-1
YES
1.25
0.35 x 45∞
WEED-2
NO
1.10
1.25
0.35 x 45∞
WEED-2
YES
0.80
0.95
0.225 x 45∞ WEED-2
N/A
1.10
1.25
0.35 x 45∞
NO
WEED-2
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
PACKAGE OUTLINE
12, 16L, THIN QFN, 3x3x0.8mm
21-0136
E
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
MAX1332/MAX1333
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)