VISHAY SI9137DB

Si9137
Vishay Siliconix
Multi-Output, Sequence Selectable Power-Supply Controller
for Mobile Applications
FEATURES
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Up to 95% Efficiency
"3% Total Regulation (Line, Load and Temperature)
5.5-V to 30-V Input Voltage Range
3.3-V, 5-V, and Adjustable 5- to 12-V Outputs
300-kHz Low-Noise Fixed Frequency Operation
Precision 3.3-V Reference Output
5-V/30-mA Linear Regulator Output
High Efficiency Pulse Skipping Mode Operation at Light Load
Programmable Output Sequencing
Only Three Inductors RequiredNo Transformer
LITTLE FOOTR Optimized Output Drivers
Internal Soft-Start
Minimal External Control Components
28-Pin SSOP Package
Output Overvoltage Protection
Output Undervoltage Shutdown
Power-Good Output (RESET)
APPLICATIONS
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Notebook and Subnotebook Computers
PDAs and Mobile Communicators
Portable Display
Multimedia Set-Top Box
Telecommunications Infrastructure
Distributed Power Conversion
DESCRIPTION
The Si9137 is a current-mode PWM and PSM converter
controller, with two synchronous buck converters (3.3 V and
5 V) and an adjustable flyback (non-isolated buck-boost)
converter whose output can be set between 5 and 12 V with
an external resistor divider. Designed for portable devices, it
offers a total of five power outputs (three tightly regulated dc/dc
converter outputs, a precision 3.3-V reference and a 5-V LDO
output) and includes on-board pre-programmed power-up
sequencing, power-good signal with delay, internal frequency
compensation networks and automatic boot-strapping. It
requires minimum external components and is capable of
achieving conversion efficiencies approaching 95%.
The Si9137 is available in a 28-pin SSOP package and
specified to operate over the extended commercial (0_C to
90_C) temperature range.
FUNCTIONAL BLOCK DIAGRAM
VIN
(5.5 V to 30 V)
VL
(5.0 V)
+3.3 V/6 A
5-V
Linear
Regulator
3.3-V
SMPS
3.3-V
Voltage
Reference
5-V
SMPS
5- to 12-V SMPS
Programmable
SEQ
RUN/STOP
Document Number: 70874
S-20642—Rev. B, 13-May-02
Power-Up
Sequence
Power_Good
VREF
(+3.3 V)
+5 V/6 A
VFLYBACK
+5- to +12-V/500 mA
Adjustable
RESET
(Power_Good)
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Si9137
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +36 V
PGND to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 V
VL to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +6.5 V
BST3, BST5, BSTFY to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +36 V
VL Short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
LX3 to BST3; LX5 to BST5; LXFY to BSTFY . . . . . . . . . . . . . . –6.5 V to 0.3 V
Inputs/Outputs to GND
(CS3, CS5, CSP, CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VL +0.3 V)
RUN/STOP, SEQ, RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
DL3, DL5, DLFY to PGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VL +0.3 V)
DH3 to LX3, DH5 to LX5,
DHFY to LXFY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (BSTx +0.3 V)
Continuous Power Dissipation (TA = 70_C)a
28-Pin SSOPb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 mW
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . –40_C to 125_C
Lead Temperature (Soldering, 10 Sec.) . . . . . . . . . . . . . . . . . . . . . . . . . 300_C
Notes
a. Device mounted with all leads soldered or welded to PC board.
b. Derate 9.52 mW/_C above 70_C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS
Test Conditions
Parameter
Limits
VIN = 15 V , IVL = IREF = 0 mA
TA = 0_C to 90_C, All Controllers ON
Mina
Typb
VIN = 6 to 30 V, 0 < VCS3 – VFB3 < 90 mV
3.22
3.32
Maxa
Unit
3.42
V
3.3-V Buck Controller
Total Regulation (Line, Load, and Temperature)
Line Regulation
VIN = 6 to 30 V
"0.5
Load Regulation
0 < VCS3 – VFB3 < 90 mV
"0.5
Current Limit
Bandwidth
Phase Margin
VCS3 – VFB3
90
125
160
%
mV
L = 10 mH, C = 330 mF
50
kHz
RSENSE = 20 mW
65
_
5-V Buck Controller
Total Regulation (Line, Load, and Temperature)
VIN = 6 to 30 V, 0 < VCS5 – VFB5 < 90 mV
4.87
5.02
5.17
Line Regulation
VIN = 6 to 30 V
±0.5
Load Regulation
0 < VCS5 – VFB5 < 90 mV
±0.5
Current Limit
Bandwidth
Phase Margin
VCS5 – VFB5
90
125
160
V
%
mV
L = 10 mH, C = 330 mF
50
kHz
RSENSE = 20 mW
65
_
5- to 12-V Flyback Controller
Total Regulation (Line, Load, and Temperature)
Output Voltage Set to 12 V
VIN = 6 to 30 V, 0 < VCSP – VCSN < 300 mV
R5 = 26.4 kW, R6 = 10 kW (See Figure 1)
11.4
12.0
12.6
Line Regulation
VIN = 6 to 30 V
±0.5
Load Regulation
0 < VCSP – VFBN < 300 mV
±0.5
Current Limit
Bandwidth
Phase Margin
VCSP – VCSN
330
410
500
V
%
mV
L = 10 mH, C = 100 mF
10
kHz
RSENSE = 100 mW, Ccomp = 120 pF
65
_
Internal Regulator
VL Output
VL Fault Lockout Voltage
All Controllers OFF, VIN >5.5 V, 0 <IL <30 mA
4.7
5.5
VL Falling Edge
3.6
4.2
FB5 Rising Edge
4.2
VL Fault Lockout Hysteresis
VL /FB5 Switchover Voltage
VL /FB5 Switchover Hysteresis
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2
75
mV
4.7
75
V
V
mV
Document Number: 70874
S-20642—Rev. B, 13-May-02
Si9137
Vishay Siliconix
SPECIFICATIONS
Test Conditions
Parameter
Limits
VIN = 15 V , IVL = IREF = 0 mA
TA = 0_C to 90_C, All Controllers ON
Mina
Typb
Maxa
No External Load
3.24
3.30
3.36
V
30
75
mV
Unit
Reference
REF Output
REF Load Regulation
0 to 1 mA
Supply Current
Supply Current*Shutdown
RUN/STOP = GND, All Converters OFF, No Load
25
60
Supply Current*Operation
All Controllers ON, No Load, fOSC = 300 kHz
1100
1800
330
m
mA
Oscillator
Oscillator Frequency
270
300
Maximum Duty Cycle
92
95
6
10
kHz
%
Fault Detection 3.3-V and 5-V Outputs
Overvoltage Trip Threshold
Overvoltage-Fault Propagation Delay
Output Undervoltage Threshold
Output Undervoltage Lockout Time
With Respect To Unloaded Output Voltage
CS3 or CS5 Driven 2% Above Overvoltage Trip Threshold
%
14
ms
1.5
With Respect to Unloaded Output Voltage
–40
–30
–20
%
From each SMPS Enabled
16
20
24
ms
RESET
RESET Start Threshold
RESET Propagation Delay (Falling)
RESET Delay Time (Rising)
With Respect To Unloaded Output Voltage
Rising Edge
–5.5
%
Falling Edge, FB3 or FB5 Driven 2% Above Overvoltage
or 2% Below Undervoltage Lockout Thresholds
1.5
ms
With Respect to 2nd SMPS Lockout Time Done
92
107
122
ms
Inputs and Outputs
Feedback Input Leakage Current
Input Leakage Current
Gate Driver Sink/Source Current (Buck)
Gate Driver On-Resistance (Buck)
Gate Driver Sink/Source Current (Flyback)
Gate Driver On-Resistance (Flyback)
RESET Output Low Voltage
RESET High Voltage Leakage
FBFY = 3.3 V
1
RUN/STOP, SEQ, VIN = 0 V or VL
"1
DL3, DH3, DL5, DH5 Forced to 2 V
1
m
mA
A
7
W
High or Low
15
W
RESET, ISINK = 4 mA
0.4
V
RESET = 5 V
1
mA
High or Low
2
DHFY, DLFY Forced to 2 V
0.2
A
RUN/STOP
VIL
VIH
0.8
2.4
V
Notes
a. The algebraic convention is used whereby the most negative value is a minimum and the most positive a maximum.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing, and are measured at TA = 25_C.
Document Number: 70874
S-20642—Rev. B, 13-May-02
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Si9137
Vishay Siliconix
PIN CONFIGURATION
RESET
1
28
CS3
FBFY
2
27
FB3
BSTFY
3
26
DH3
DHFY
4
25
LX3
LXFY
5
24
BST3
DLFY
6
23
DL3
CSP
7
22
VIN
CSN
8
21
VL
COMP
9
20
FB5
GND
10
19
PGND
REF
11
18
DL5
RUN/STOP
12
17
BST5
SEQ
13
16
LX5
CS5
14
15
DH5
SSOP-28
Top View
ORDERING INFORMATION
Part Number
Temperature Range
VOUT
Si9137LG
0 to 90_C
3.3 V, 5 V, 5 to ADJ V
Evaluation Board
Temperature Range
Board Type
Si9137DB
0 to 90_C
Surface Mount
PIN DESCRIPTION
Pin
Symbol
1
RESET
Open drain NMOS output active-low timed reset output. RESET swings GND to VL. Goes high after a fixed 32,000 clock
cycle delay following proper power-up of all supply outputs indicating Power_Good.
2
FBFY
Feedback for flyback converter. Normally connected to an external resistor divider used to set the flyback output voltage.
3
BSTFY
Boost capacitor connection for flyback converter.
4
DHFY
Gate-drive output for flyback high-side MOSFET.
5
LXFY
Inductor connection for flyback converter.
6
DLFY
Gate-drive output for flyback low-side MOSFET.
7
CSP
Current sense positive input for flyback converter.
8
CSN
Current sense negative input for flyback converter.
9
COMP
10
GND
Analog ground.
11
REF
3.3-V internal reference.
12
RUN/STOP
13
SEQ
Pin Strap input that selects SMPS power-up sequence (pin should be fixed to GND, REF or VL):
SEQ = GND: 5-V then 3.3-V then adjustable 5- to 12-V output
SEQ = VL: 3.3-V then 5-V then adjustable 5- to 12-V output
SEQ = REF: 3.3-V then 5-V then adjustable 5- to 12-V output, high impedance error detect mode.
14
CS5
Current sense input for 5-V buck controller.
15
DH5
Gate-drive output for 5-V buck high-side MOSFET.
16
LX5
Inductor connection for buck 5-V.
17
BST5
Boost capacitor connection for 5-V buck converter.
18
DL5
Gate-drive output for 5-V buck low-side MOSFET.
19
PGND
20
FB5
21
VL
5-V logic supply voltage for internal circuitry.
22
VIN
Input voltage
23
DL3
Gate-drive output for 3.3-V buck low-side MOSFET.
24
BST3
Boost capacitor connection for 3.3-V buck converter.
25
LX3
Inductor connection for 3.3-V buck low-side MOSFET.
26
DH3
Gate-drive output for 3.3-V buck high-side MOSFET.
27
FB3
Feedback for 3.3-V buck.
28
CS3
Current sense input for 3.3-V buck.
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4
Description
Flyback compensation connection, if required.
Triple controller ON/OFF control. Logic threshold is 0.8 to 2.4 V. When RUN/STOP is low, all converters are off and supply
current is 25-mA typical, 60-mA maximum.
Power ground.
Feedback for 5-V buck.
Document Number: 70874
S-20642—Rev. B, 13-May-02
Si9137
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Efficiency vs. 3.3-V Output Current
Efficiency vs. 5.0-V Output Current
100
100
Frequency = 300 kHz
Frequency = 300 kHz
90
90
VIN = 6 V
15 V
Efficiency (%)
Efficiency (%)
VIN = 6 V
15 V
80
30 V
70
80
30 V
70
3.3 V, 12 V No Load
5 V, 12 V No Load
60
60
50
0.001
50
0.01
0.1
1
10
0.001
0.01
Current (A)
0.1
1
10
Current (A)
Efficiency vs. 5- to 12-V Adjustable Output
Current (Output Set to 12 V)
85
VIN = 15 V
Frequency = 300 kHz
80
6V
Efficiency (%)
75
30 V
70
65
5 V, 3.3 V No Load
60
55
0.001
0.01
0.1
1
Current (A)
Document Number: 70874
S-20642—Rev. B, 13-May-02
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Si9137
Vishay Siliconix
TYPICAL WAVEFORMS
PWM Loading 5-V Converter
PWM Unloading 5-V Converter
(VIN = 10 V)
(VIN = 10 V)
VOUT
(100 mV/div)
VOUT
(100 mV/div)
Load
(1 A/div)
Load
(1 A/div)
20.0 ms/div
20.0 ms/div
PWM to PSM 5-V Converter
PSM to PWM 5-V Converter
(VIN = 10 V)
(VIN = 10 V)
VOUT
(100 mV/div)
VOUT
(100 mV/div)
Load
(1 A/div)
Load
(1 A/div)
100 ms/div
100 ms/div
PSM Operation 5-V Converter
(VIN = 10 V)
10.0 ms/div
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PWM Operation 5-V Converter
VOUT
(100 mV/div)
(VIN = 10 V)
VOUT
(100 mV/div)
Inductor Node
(L X5)
Inductor Node
(L X5)
Inductor Current
(1A/div)
Inductor Current
(1A/div)
2.00 ms/div
Document Number: 70874
S-20642—Rev. B, 13-May-02
Si9137
Vishay Siliconix
TYPICAL WAVEFORMS
PWM Unloading 3-V Converter
PWM Loading 3-V Converter
(VIN = 10 V)
(VIN = 10 V)
VOUT
(100 mV/div)
VOUT
(100 mV/div)
Load
(1 A/div)
Load
(1 A/div)
20.0 ms/div
20.0 ms/div
PSM to PWM 3-V Converter
PWM to PSM 3-V Converter
(VIN = 10 V)
(VIN = 10 V)
VOUT
(100 mV/div)
VOUT
(100 mV/div)
Load
(1 A/div)
Load
(1 A/div)
50.0 ms/div
50.0 ms/div
250-mA Transient Adjustable Converter
(Output Set To 12 V)
(VIN = 10 V)
VOUT
(100 mV/div)
Load Current
(100 mA/div)
200 ms/div
Document Number: 70874
S-20642—Rev. B, 13-May-02
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Si9137
Vishay Siliconix
STANDARD APPLICATION CIRCUIT
VIN
+5 V up to 30 mA
C7
33 mF
D1A
CMPD2836
VIN
VL
D1B
C1
0.1 mF
BST3
C4
33 mF
C2
0.1 mF
BST5
Q2
Si4416DY
L1, 10 mH
DH5
Q1
Si4416DY
DH3
C5
4.7 mF
R2
0.02 W
C3
330 mF
LX3
+3.3 VOUT
R1
0.02 W
L2
10 mH
DL5
Q3
Si4812DY
+5 VOUT
LX5
DL3
Q4
Si4812DY
CS5
C6
330 mF
FB5
D3
CS3
BSTFY
CMPD2836
C8
0.1 mF
DHFY
VL
C9
4.7 mF
Q5
Si2304DS
L3, 10 mH
D4, BYS10-35
VFLYBACK
LXFY
20 kW
+5 to +12 V
C10
100 mF
D2, BYS10-35
FB3
Q6
Si2304DS
DLFY
RESET
CSP
PGND*
GND*
0.2 W
RUN/STOP
SEQ
R3
R5
CSN
FBFY
+3.3 V up
to 1 mA
C11
1 mF
REF
COMP
GND
PGND
*PGND and GND planes should be connected to a single point ground.
C12
120 pF
R6
where:
ǒR 5 ) R 6 Ǔ
V FLYBACK +
R6
V REF
FIGURE 1.
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Document Number: 70874
S-20642—Rev. B, 13-May-02
Si9137
Vishay Siliconix
TIMING DIAGRAMS
The converter is enabled
RUN/STOP
VIN is applied
VIN
LDO is activated after VIN is
applied
VL
REF circuit is activated after VL
becomes available
2.4 V
VREF
After VREF goes above 2.4 V,
the converter is turned on
OSC EN
(Sysmon EN)
Oscillator is activated
OSC
Slow soft-start gradually increases
the maximum inductor current
4 ms
fmax (SS)
High-side gate drive duty ratio
gradually increases to maximum
DH
tBBM
Low-side gate drive
DL
FIGURE 2. Converter is Enabled Before VIN is Applied
The converter is enabled
RUN/STOP
VIN is applied
VIN
LDO is activated after VIN is
applied
VL
REF circuit is activated after VL
becomes available
2.4 V
VREF
After VREF goes above 2.4 V,
the converter is turned on
OSC EN
(Sysmon EN)
Oscillator is activated
OSC
4 ms
Slow soft-start gradually increases
the maximum inductor current
fmax (SS)
DH
DL
FIGURE 3. Converter is Enabled After VIN is Applied
Document Number: 70874
S-20642—Rev. B, 13-May-02
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9
Si9137
Vishay Siliconix
TIMING DIAGRAMS
VIN
[ V (VL)
VL
4V
3.4 V
RESET
VREF
OSC EN
(Sysmon EN)
OSC
DH
DL
fmax (SS)
FIGURE 4. Power Off Sequence
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Document Number: 70874
S-20642—Rev. B, 13-May-02
Si9137
Vishay Siliconix
DETAILED FUNCTIONAL BLOCK DIAGRAMS
FB5
CS_
+
1X _
Error
Amplifier
–
REF
RX
FB_
RY
SEQ RUN/STOP
PWMCMP
+
BST_
–
DH
+
DH
Logic
Control
Pulse
Skipping
Control
SLC
Internal voltage divider is
only used on 5-V output.
LX_
BBM
20 mV
VL
Current
Limit
DL
DL
V
Soft-Start
SYNC
Rectifier Control
t
FIGURE 5. Buck Block Diagram (3.3-V and 5-Controllers)
FBFY
R2
SEQ
Error
Amplifier
–
REF
–
+
BSTFY
Logic
Control
+
R3
RUN/STOP
PWM
Comparator
DH
LXFY
COMP
DHFY
C/S
Amplifier
CSP
–
CSN
+
Pulse
Skipping
Control
DL
DLFY
–
100 mV
+
Current Limit
V
Soft-Start
t
FIGURE 6. Buck-Boost Block Diagram (5- to 12-V Adjustable Controller)
Document Number: 70874
S-20642—Rev. B, 13-May-02
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Si9137
Vishay Siliconix
DETAILED FUNCTIONAL BLOCK DIAGRAMS
VIN
5-V
Linear
Regulator
VL
5-V
Buck
Controller
FB5
CS5
BST5
DH5
LX5
DL5
3.3-V
Buck
Controller
FB3
CS3
BST3
DH3
LX3
DL3
5- to 12-V
Adjustable
Flyback
Controller
FBFY
CSP
CSN
BSTFY
DHFY
LXFY
DLFY
4.5 V
4V
Logic
Control
3.3-V
Reference
2.4 V
RUN/STOP
SEQ
RESET
FIGURE 7. Complete Si9137 Block Diagram
DESCRIPTION OF OPERATION
Shutdown Mode
The logic threshold for the RUN/STOP pin is 1.6 V. Input
voltage must be 0.8 V or less for logic low and 2.4 V or higher
for logic high.
Start-up Sequence
Start-up is controlled by RUN/STOP in conjunction with SEQ.
If SEQ is tied to GND, the 5-V SMPS output will come up first,
followed by the 3.3-V output and then the adjustable 5- to 12-V
output. If SEQ is tied to VL, then the 3.3-V SMPS output will
come up first, followed by the 5-V and then the adjustable 5- to
12-V output.
When the first SMPS output voltage is within tolerance, the
second SMPS will begin its soft-start cycle. When the second
SMPS output is within tolerance, the third SMPS will start its
soft-start cycle. When both the 3.3-V and 5-V SMPS outputs
are within tolerance and 32,000 clock cycles (typically equal to
107 ns) have elapsed since the second SMPS output went into
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12
regulation, the RESET pin will be pulled high, signifying that all
converters are operating correctly ( see RESET Power Good
Voltage Monitor).
The Si9137 converts a 5.5-V to 30-V input voltage to five
different output voltages; two buck (step-down) high current,
PWM, switch-mode supplies of 3.3 V and 5 V, one “flyback”
PWM switch-mode supply adjustable from 5 V to 12 V, one
precision 3.3-V reference and one 5-V between low drop out
(LDO) linear regulator output. Switch-mode supply output
current capabilities depend on external components (can be
selected to exceed 10 A). In the standard application circuit
illustrated in Figure 1, each buck converter is capable of
delivering 5 A, with the flyback converter delivering 250 mA.
The recommended load current for the precision 3.3-V
reference output is less than 1 mA, and for the 5-V LDO output
is less than 30 mA. In order to maximize power efficiency of the
converter, when the 5-V buck converter output (FB5) voltage is
above 4.5-V, the internal 5-V LDO is turned off and VL is
supplied by the 5-V converter output.
Document Number: 70874
S-20642—Rev. B, 13-May-02
Si9137
Vishay Siliconix
DESCRIPTION OF OPERATION (CONT’D)
Buck Converter Operation:
The 3.3-V and 5-V buck converters are both current-mode
PWM and PSM (during light load operation) regulators using
high-side bootstrap n-channel and low-side n-channel
MOSFETs. At light load conditions, the converters switch at a
lower frequency than the clock frequency. This operating
condition is defined as pulse-skipping. The operation of the
converter(s) switching at clock frequency is defined as normal
operation.
Normal Operation: Buck Converters
In normal operation, the buck converter high-side MOSFET is
turned on with a delay (known as break-before-make time tBBM), after the rising edge of the clock. After a certain on time,
the high-side MOSFET is turned off and then after a delay
(tBBM), the low-side MOSFET is turned on until the next rising
edge of the clock, or the inductor current reaches zero. The
tBBM (approximately 25 ns to 60 ns), has been optimized to
guarantee the efficiency is not adversely affected at the high
switching frequency and a specified minimum to account for
variations of possible MOSFET gate capacitances.
Current Limit: Buck Converters
When the buck converter inductor current is too high, the
voltage across pin CS3(5) and pin FB3(5) will exceed
approximately 125 mV causing the high-side MOSFET to be
turned off instantaneously regardless of the input, or output
condition. The Si9137 features clock cycle by clock cycle
current limiting capability.
Flyback Converter Operation:
The Si9137 has an adjustable 5-V to 12-V output non-isolated
buck-boost converter, called for brevity a flyback. The input
voltage range can span above or below the regulated output
voltage. It consists of two n-channel MOSFET switches that
are turned on and off in phase, and two diodes. Similar to the
buck converter, during the light load conditions, the flyback
converter will switch at a frequency lower than the internal
clock frequency, which can be defined as pulse skipping mode
(PSM); otherwise, it operates in normal PWM mode.
The output voltage of the flyback converter is set by two
resistors (R5 and R6, see Figure 1) where,
V FLYBACK +
During the normal operation, the high-side MOSFET switch
on-time is controlled internally to provide excellent line and
load regulation over temperature. Both buck converters
should have load, line, regulation to within 0.5% tolerance.
Pulse Skipping: Buck Converters
When the buck converter switching frequency is less than the
internal clock frequency, its operation mode is defined as pulse
skipping mode. During this mode, the high-side MOSFET is
turned on until VCS-VFB reaches 20 mV, or the on time reaches
its maximum duty ratio. After the high-side MOSFET is turned
off, the low-side MOSFET is turned on after the tBBM delay,
which will remain on until the inductor current reaches zero.
The output voltage will rise slightly above the regulation
voltage after this sequence, causing the controller to stay idle
for the next clock cycle, or several clock cycles. When the
output voltage falls slightly below the regulation level, the
high-side MOSFET will be turned on again at the next clock
cycle. With the converter remaining idle during some clock
cycles, the switching losses are reduced preserving
conversion efficiency during the light output current condition.
Document Number: 70874
S-20642—Rev. B, 13-May-02
ǒR 5 ) R 6 Ǔ
R6
V REF
Normal Operation: Flyback Converter
In normal operation mode, the two MOSFETs are turned on at
the rising edge of the clock, and then turned off. The on time is
controlled internally to provide excellent load, line, and
temperature regulation. The flyback converter has load, line
and temperature regulation well within 0.5%.
Pulse Skipping: Flyback Converter
Under the light load conditions, similar to the buck converter,
the flyback converter will enter pulse skipping mode. The
MOSFETs will be turned on until the inductor current increases
to such a level that the voltage across the pin CSP and pin CSN
reaches 410 mV, or the on time reaches the maximum duty
cycle. After the MOSFETs are turned off, the inductor current
will conduct through two diodes until it reaches zero. At this
point, the flyback converter output will rise slightly above the
regulation level, and the converter will stay idle for one or
several clock cycle(s) until the output falls back slightly below
the regulation level. The switching losses are reduced by
skipping pulses preserving the efficiency during light load.
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13
Si9137
Vishay Siliconix
DESCRIPTION OF OPERATION (CONT’D)
Current Limit: Flyback Converter
Similar to the buck converter; when the voltage across pin
CSP and pin CSN exceeds 410-mV typical, the two MOSFETs
will be turned off regardless of the input and output conditions.
Grounding:
There are two separate grounds on the Si9137, analog signal
ground (GND) and power ground (PGND). The purpose of two
separate grounds is to prevent the high currents on the power
devices (both external and internal) from interfering with the
analog signals. The internal components of Si9137 have their
grounds tied (internally) together. These two grounds are then
tied together (externally) at a single point, to ensure Si9137
noise immunity.
This separation of grounds should be maintained in the
external circuitry, with the power ground of all power devices
being returned directly to the input capacitors, and the small
signal ground being returned to the GND pin of Si9137.
Output Undervoltage Protection
Each of the Si9137 5-V and 3.3-V SMPS outputs has an
undervoltage protection circuit that is activated 6,144 clock
cycles (20.48 ms) after the SMPS is enabled. If either SMPS
output is typically under 70% of the nominal value, all SMPSs
are latched off and their outputs are clamped to ground by the
synchronous rectifier MOSFETs. The SMPS will not restart
until RUN/STOP is toggled.
Stability:
Buck Converters:
In order to simplify designs, the 5-V and 3.3-V supplies do not
require external frequency compensation. Meanwhile, it
achieves excellent regulation and efficiency. The converters
are current mode control, with a bandwidth substantially
higher than the LC tank dominant pole frequency of the output
filter. To ensure stability, the minimum capacitance and
maximum ESR values are:
C LOAD w
RESET Power-Good Voltage Monitor
The power-good monitor generates a system RESET signal.
At first power-up (RUN/STOP going high), RESET is held low
until the 3.3-V, 5-V outputs are in regulation and beyond the
UVLO timer. At this point, an internal timer begins counting
oscillator pulses and RESET continues to be held low until
32,000 cycles have elapsed. After this timeout period, 107 ms
@ 300 kHz, RESET is actively pulled up to VL, when the
recommended 20-kW resistor to VL is on the RESET pin.
V REF
2p xV OUT x R CS x BW
ESR v
V OUT x Rcs
V REF
where VREF = 3.3 V, VOUT is the output voltage (5 V or 3.3 V),
Rcs is the current sensing resistor in ohms and BW = 50 khz
With the components specified in the application circuit
(L = 10 mH,
RCS = 0.02 W,
COUT = 330 mF,
ESR
approximately 0.1 W), the converter should have a bandwidth
of approximately 50 kHz, with minimum phase margin of 65_,
and dc gain above 50 dB.
Other Outputs
Output Overvoltage Protection
The 5-V and 3.3-V SMPS outputs are monitored for
overvoltage. If either output is typically more than 10% above
the nominal regulation point, all low-side gate drivers are
latched high until RUN/STOP is toggled. This action turns on
the synchronous rectifier MOSFETs with a 100% duty cycle,
in turn rapidly discharging the output capacitors and forcing all
SMPS outputs to ground.
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14
The Si9137 also provides a 3.3-V reference which can be
externally loaded up to 1 mA, as well as, a 5-V LDO output
which can be loaded up to 30 mA, or even more depending on
the system application. When the 5-V buck converter is turned
on, the 5-V LDO output is shorted with the 5-V buck converter
output, so its loading capability is substantially increased. For
stability, the 3.3-V reference output requires a 1-mF capacitor,
and the 5-V LDO output requires a 4.7-mF capacitor.
Document Number: 70874
S-20642—Rev. B, 13-May-02