RENESAS 3850

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 38000 SERIES
3850/3851
Group
User’s Manual
keep safety first in your circuit designs !
● Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury,
fire or property damage. Remember to give due consideration to safety when
making your circuit designs, with appropriate measures such as (i) placement
of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.
Notes regarding these materials
● These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the customer’s
application; they do not convey any license under any intellectual property rights,
or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
● Mitsubishi Electric Corporation assumes no responsibility for any damage, or
infringement of any third-party’s rights, originating in the use of any product
data, diagrams, charts or circuit application examples contained in these materials.
● All information contained in these materials, including product data, diagrams
and charts, represent information on products at the time of publication of these
materials, and are subject to change by Mitsubishi Electric Corporation without
notice due to product improvements or other reasons. It is therefore recommended
that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for the latest product information before
purchasing a product listed herein.
● Mitsubishi Electric Corporation semiconductors are not designed or manufactured
for use in a device or system that is used under circumstances in which human
life is potentially at stake. Please contact Mitsubishi Electric Corporation or an
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● Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
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products contained therein.
REVISION DESCRIPTION LIST
Rev.
No.
1.0
3850/3851 GROUP USER’S MANUAL
Revision Description
First Edition
Rev.
date
981021
(1/1)
Preface
This user’s manual describes Mitsubishi’s CMOS 8bit microcomputers 3851 Group and 3850 Group.
After reading this manual, the user should have a
through knowledge of their functions and features,
and should be able to fully utilize the product. The
manual starts with specifications and ends with
application examples.
The difference between the 3851 Group and 3850
Group is the I2C-BUS built-in or not. The 3850 Group
does not have the built-in I 2C-BUS. Accordingly, use
this user’s manual with care, considering the difference
between the 3851 Group and 3850 Group. This user’s
manual mainly explains the 3851 Group. The difference
is explained in the section “FUNCTIONAL
DESCRIPTION SUPPLEMENT of Chapter 1”.
For details of software, refer to the “740 SERIES
SOFTWARE MANUAL.”
For details of development support tools, refer to the
data book or the data sheet of “DEVELOPMENT
SUPPORT TOOLS FOR 740 FAMILY”.
BEFORE USING THIS MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development. Chapter 3 also includes necessary information for
systems development. You must refer to that chapter.
1. Organization
● CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
● CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on
setting examples of relevant registers.
● CHAPTER 3 APPENDIX
This chapter includes necessary information for systems development using the microcomputer, such
as the electrical characteristics, the list of registers, the Mask ROM confirmation form (for mask ROM
version), the ROM programming confirmation form (for One Time PROM version), and the Mark
specification form which are to be submitted when ordering.
2. Structure of register
The figure of each register structure describes its functions, contents at reset, and attributes as follows :
(Note 2)
Bit attributes
Bits
(Note 1)
Contents immediately after reset release
b7 b6 b5 b4 b3 b2 b1 b0
0
CPU mode register (CPUM) [Address : 3B 16]
B
Name
0
Processor mode bits
1
Function
At reset
R W
b1 b0
0 0 : Single-chip mode
01:
10:
Not available
11:
0 : 0 page
1 : 1 page
0
0
2
Stack page selection bit
3
0
✕
4
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
0
✕
5
Fix this bit to “0.”
1
6
Main clock (X IN-XOUT) stop bit
7
Internal system clock selection bit
: Bit in which nothing is arranged
0 : Operating
1 : Stopped
0 : XIN -XOUT selected
1 : XCIN -XCOUT selected
0
✽
✽
: Bit that is not used for control of the corresponding function
Note 1:. Contents immediately after reset release
0....... “0” at reset release
1....... “1” at reset release
?....... Undefined at reset release
✽.......Contents determined by option at reset release
Note 2: Bit attributes......... The attributes of control register bits are classified into 3 bytes : read-only, writeonly and read and write. In the figure, these attributes are represented as follows :
R....... Read
...... Read enabled
✕.......Read disabled
W......Write
..... Write enabled
✕...... Write disabled
✽.......“0” write
Table of contents
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................ 1-2
FEATURES ...................................................................................................................................... 1-2
APPLICATION ................................................................................................................................ 1-2
PIN CONFIGURATION (TOP VIEW) ........................................................................................... 1-2
FUNCTIONAL BLOCK .................................................................................................................. 1-3
PIN DESCRIPTION ........................................................................................................................ 1-4
PART NUMBERING ....................................................................................................................... 1-5
GROUP EXPANSION .................................................................................................................... 1-6
Memory Type ............................................................................................................................ 1-6
Memory Size ............................................................................................................................. 1-6
Packages ................................................................................................................................... 1-6
FUNCTIONAL DESCRIPTION ...................................................................................................... 1-7
Central Processing Unit (CPU) .............................................................................................. 1-7
MEMORY ................................................................................................................................. 1-11
I/O PORTS .............................................................................................................................. 1-13
INTERRUPTS .......................................................................................................................... 1-16
TIMERS ................................................................................................................................... 1-19
SERIAL I/O.............................................................................................................................. 1-21
MULTI-MASTER I2C-BUS INTERFACE ............................................................................... 1-25
PULSE WIDTH MODULATION (PWM) ................................................................................ 1-36
A-D CONVERTER .................................................................................................................. 1-38
WATCHDOG TIMER .............................................................................................................. 1-39
RESET CIRCUIT .................................................................................................................... 1-40
CLOCK GENERATING CIRCUIT ......................................................................................... 1-42
NOTES ON PROGRAMMING ..................................................................................................... 1-45
Processor Status Register .................................................................................................... 1-45
Interrupts ................................................................................................................................. 1-45
Decimal Calculations .............................................................................................................. 1-45
Timers ...................................................................................................................................... 1-45
Multiplication and Division Instructions ............................................................................... 1-45
Ports ......................................................................................................................................... 1-45
Serial I/O ................................................................................................................................. 1-45
A-D Converter ......................................................................................................................... 1-45
Instruction Excution Time ...................................................................................................... 1-45
DATA REQUIRED FOR MASK ORDERS ................................................................................ 1-46
DATA REQUIRED FOR ROM WRITING ORDERS ................................................................. 1-46
ROM PROGRAMMING METHOD .............................................................................................. 1-46
FUNCTIONAL DESCRIPTION SUPPLEMENT ......................................................................... 1-47
Interrupt ................................................................................................................................... 1-47
Timing After Interrupt............................................................................................................. 1-48
A-D Converter ......................................................................................................................... 1-49
MISRG ..................................................................................................................................... 1-51
3850 Group ............................................................................................................................. 1-53
3850/3851 Group User’s Manual
i
Table of contents
CHAPTER 2 APPLICATION
2.1 I/O port ..................................................................................................................................... 2-2
2.1.1 Memory map ................................................................................................................... 2-2
2.1.2 Relevant registers .......................................................................................................... 2-2
2.1.3 Handling of unused pins ............................................................................................... 2-3
2.1.4 Notes on input and output pins ................................................................................... 2-4
2.1.5 Termination of unused pins .......................................................................................... 2-5
2.2 Timer......................................................................................................................................... 2-6
2.2.1 Memory map ................................................................................................................... 2-6
2.2.2 Relevant registers .......................................................................................................... 2-6
2.2.3 Timer application examples ........................................................................................ 2-12
2.2.4 Notes on timer .............................................................................................................. 2-25
2.3 Serial I/O ................................................................................................................................ 2-26
2.3.1 Memory map ................................................................................................................. 2-26
2.3.2 Relevant registers ........................................................................................................ 2-27
2.3.3 Serial I/O connection examples ................................................................................. 2-31
2.3.4 Setting of serial I/O transfer data format ................................................................. 2-33
2.3.5 Serial I/O application examples ................................................................................. 2-34
2.3.6 Notes on serial I/O ...................................................................................................... 2-52
2.4 Muti-master I2C-BUS Interface .......................................................................................... 2-55
2.4.1 Memory map ................................................................................................................. 2-55
2.4.2 Relevant registers ........................................................................................................ 2-55
2.4.3 I2C-BUS overview ......................................................................................................... 2-61
2.4.4 Communication format ................................................................................................. 2-62
2.4.5 Synchronization and Arbitration lost .......................................................................... 2-63
2.4.6 SMBUS communication usage example ................................................................... 2-65
2.4.7 Notes on muti-master I2C-BUS Interface .................................................................. 2-81
2.4.8 Notes on programming for SMBUS interface ........................................................... 2-84
2.5 PWM ........................................................................................................................................ 2-85
2.5.1 Memory map ................................................................................................................. 2-85
2.5.2 Relevant registers ........................................................................................................ 2-85
2.5.3 PWM output circuit application example ................................................................... 2-87
2.5.4 Notes on PWM ............................................................................................................. 2-89
2.6 A-D converter ....................................................................................................................... 2-90
2.6.1 Memory map ................................................................................................................. 2-90
2.6.2 Relevant registers ........................................................................................................ 2-90
2.6.3 A-D converter application examples .......................................................................... 2-93
2.6.4 Notes on A-D converter .............................................................................................. 2-95
2.7 Reset....................................................................................................................................... 2-96
2.7.1 Connection example of reset IC ................................................................................ 2-96
2.7.2 Notes on RESET pin ................................................................................................... 2-97
ii
3850/3851 Group User’s Manual
Table of contents
CHAPTER 3 APPENDIX
3.1 Electrical characteristics ..................................................................................................... 3-2
3.1.1 Absolute maximum ratings ............................................................................................ 3-2
3.1.2 Recommended operating conditions ............................................................................ 3-3
3.1.3 Electrical characteristics ................................................................................................ 3-5
3.1.4 A-D converter characteristics ....................................................................................... 3-6
3.1.5 Timing requirements ...................................................................................................... 3-7
3.1.6 Switching characteristics ............................................................................................... 3-8
3.1.7 Multi-master I2C-BUS bus line characteristics .......................................................... 3-11
3.2 Standard characteristics .................................................................................................... 3-12
3.2.1 Power source current characteristic examples ........................................................ 3-12
3.2.2 Port standard characteristic examples ...................................................................... 3-15
3.2.3 A-D conversion standard characteristics ................................................................... 3-17
3.3 Notes on use ........................................................................................................................ 3-18
3.3.1 Notes on interrupts ...................................................................................................... 3-18
3.3.2 Notes on timer .............................................................................................................. 3-19
3.3.3 Notes on serial I/O ...................................................................................................... 3-19
3.3.4 Notes on multi-master I2C-BUS interface ................................................................. 3-21
3.3.5 Notes on A-D converter .............................................................................................. 3-24
3.3.6 Notes on watchdog timer ............................................................................................ 3-24
3.3.7 Notes on RESET pin ................................................................................................... 3-24
3.3.8 Notes on input and output pins ................................................................................. 3-25
3.3.9 Notes on low-speed operation mode ........................................................................ 3-26
3.3.10 Notes on restarting oscillation .................................................................................. 3-26
3.3.11 Notes on programming .............................................................................................. 3-27
3.3.12 Programming and test of built-in PROM version................................................... 3-29
3.3.13 Notes on built-in PROM version .............................................................................. 3-29
3.3.14 Termination of unused pins ...................................................................................... 3-31
3.4 Countermeasures against noise ...................................................................................... 3-32
3.4.1 Shortest wiring length .................................................................................................. 3-32
3.4.2 Connection of bypass capacitor across VSS line and VCC line ............................... 3-34
3.4.3 Wiring to analog input pins ........................................................................................ 3-35
3.4.4 Oscillator concerns....................................................................................................... 3-35
3.4.5 Setup for I/O ports ....................................................................................................... 3-37
3.4.6 Providing of watchdog timer function by software .................................................. 3-38
3.5 List of registers ................................................................................................................... 3-39
3.6 Mask ROM confirmation form........................................................................................... 3-56
3.7 ROM programming confirmation form ............................................................................ 3-66
3.8 Mark specification form ..................................................................................................... 3-74
3.9 Package outline ................................................................................................................... 3-76
3.10 Machine instructions ........................................................................................................ 3-78
3.11 List of instruction codes ................................................................................................. 3-89
3.12 SFR memory map .............................................................................................................. 3-90
3.13 Pin configurations ............................................................................................................. 3-91
3850/3851 Group User’s Manual
iii
List of figures
List of figures
CHAPTER 1 HARDWARE
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1 M38513M4-XXXFP/SP pin configuration ......................................................................... 1-2
2 Functional block diagram ................................................................................................... 1-3
3 Part numbering .................................................................................................................... 1-5
4 Memory expansion plan ..................................................................................................... 1-6
5 740 Family CPU register structure ................................................................................... 1-7
6 Register push and pop at interrupt generation and subroutine call ........................... 1-8
7 Structure of CPU mode register ..................................................................................... 1-10
8 Memory map diagram ...................................................................................................... 1-11
9 Memory map of special function register (SFR) .......................................................... 1-12
10 Port block diagram (1) ................................................................................................... 1-14
11 Port block diagram (2) ................................................................................................... 1-15
12 Interrupt control............................................................................................................... 1-18
13 Structure of Interrupt-related registers (1) .................................................................. 1-18
14 Structure of timer XY mode register ............................................................................ 1-19
15 Structure of timer count source selection register..................................................... 1-19
16 Block diagram of timer X, timer 1 and timer 2 .......................................................... 1-20
17 Block diagram of clock synchronous serial I/O .......................................................... 1-21
18 Operation of clock synchronous serial I/O function................................................... 1-21
19 Block diagram of UART serial I/O ............................................................................... 1-22
20 Operation of UART serial I/O function ........................................................................ 1-23
21 Structure of serial I/O control registers ....................................................................... 1-24
22 Block diagram of multi-master I 2C-BUS interface ...................................................... 1-25
23 Structure of I 2C address register .................................................................................. 1-26
24 Structure of I 2C clock control register ......................................................................... 1-27
25 SDA/SCL pin selection bit ............................................................................................. 1-28
26 Structure of I 2C control register .................................................................................... 1-28
27 Structure of I 2C status register ..................................................................................... 1-30
28 Interrupt request signal generating timing .................................................................. 1-30
29 START condition generating timing diagram .............................................................. 1-31
30 STOP condition generating timing diagram ................................................................ 1-31
31 START/STOP condition detecting timing diagram ..................................................... 1-31
32 STOP condition detecting timing diagram ................................................................... 1-31
33 Structure of I2C START/STOP condition control register ............................................ 1-33
34 Address data communication format............................................................................ 1-33
35 Timing of PWM period ................................................................................................... 1-36
36 Block diagram of PWM function ................................................................................... 1-36
37 Structure of PWM control register ............................................................................... 1-37
38 PWM output timing when PWM register or PWM prescaler is changed ................ 1-37
39 Structure of AD control register ................................................................................... 1-38
40 Structure of A-D conversion registers ......................................................................... 1-38
41 Block diagram of A-D converter ................................................................................... 1-38
42 Block diagram of Watchdog timer ................................................................................ 1-39
43 Structure of Watchdog timer control register ............................................................. 1-39
44 Reset circuit example .................................................................................................... 1-40
45 Reset sequence .............................................................................................................. 1-40
46 Internal status at reset .................................................................................................. 1-41
47 Ceramic resonator circuit .............................................................................................. 1-42
3850/3851 Group User’s Manual
i
List of figures
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49
50
51
52
53
54
55
56
57
58
59
60
61
External clock input circuit ............................................................................................ 1-42
Structure of MISRG ........................................................................................................ 1-43
System clock generating circuit block diagram (Single-chip mode) ........................ 1-43
State transitions of system clock ................................................................................. 1-44
Programming and testing of One Time PROM version ............................................ 1-46
Timing chart after an interrupt occurs ......................................................................... 1-48
Time up to execution of the interrupt processing routine ........................................ 1-48
A-D conversion equivalent circuit ................................................................................. 1-50
A-D conversion timing chart.......................................................................................... 1-50
Structure of MISRG ........................................................................................................ 1-52
Structure of I2C START/STOP condition control register ......................................... 1-52
Memory expansion plan of 3850 group ....................................................................... 1-53
Structure of Interrupt request register 1 of 3850 group ........................................... 1-54
Structure of Interrupt control register 1 of 3850 group ............................................ 1-54
CHAPTER 2 APPLICATION
Fig. 2.1.1 Memory map of registers relevant to I/O port ......................................................... 2-2
Fig. 2.1.2 Structure of Port Pi (i = 0, 1, 2, 3, 4) ...................................................................... 2-2
Fig. 2.1.3 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4) ....................................... 2-3
Fig. 2.2.1 Memory map of registers relevant to timers ............................................................ 2-6
Fig. 2.2.2 Structure of Prescaler 12, Prescaler X, Prescaler Y .............................................. 2-6
Fig. 2.2.3 Structure of Timer 1 .................................................................................................... 2-7
Fig. 2.2.4 Structure of Timer 2, Timer X, Timer Y ................................................................... 2-7
Fig. 2.2.5 Structure of Timer XY mode register ........................................................................ 2-8
Fig. 2.2.6 Structure of Timer count source set register ........................................................... 2-9
Fig. 2.2.7 Structure of Interrupt request register 1 ................................................................. 2-10
Fig. 2.2.8 Structure of Interrupt request register 2 ................................................................. 2-10
Fig. 2.2.9 Structure of Interrupt control register 1 .................................................................. 2-11
Fig. 2.2.10 Structure of Interrupt control register 2 ................................................................ 2-11
Fig. 2.2.11 Timers connection and setting of division ratios ................................................. 2-13
Fig. 2.2.12 Relevant registers setting ....................................................................................... 2-14
Fig. 2.2.13 Control procedure..................................................................................................... 2-15
Fig. 2.2.14 Peripheral circuit example ....................................................................................... 2-16
Fig. 2.2.15 Timers connection and setting of division ratios ................................................. 2-16
Fig. 2.2.16 Relevant registers setting ....................................................................................... 2-17
Fig. 2.2.17 Control procedure..................................................................................................... 2-18
Fig 2.2.18 Judgment method of valid/invalid of input pulses ................................................ 2-19
Fig. 2.2.19 Relevant registers setting ....................................................................................... 2-20
Fig. 2.2.20 Control procedure..................................................................................................... 2-21
Fig. 2.2.21 Timers connection and setting of division ratios ................................................. 2-22
Fig. 2.2.22 Relevant registers setting ....................................................................................... 2-23
Fig. 2.2.23 Control procedure..................................................................................................... 2-24
Fig. 2.3.1 Memory map of registers relevant to serial I/O..................................................... 2-26
Fig. 2.3.2 Structure of Transmit/Receive buffer register ........................................................ 2-27
Fig. 2.3.3 Structure of Serial I/O status register ..................................................................... 2-27
Fig. 2.3.4 Structure of Serial I/O control register .................................................................... 2-28
Fig. 2.3.5 Structure of UART control register .......................................................................... 2-28
Fig. 2.3.6 Structure of Baud rate generator ............................................................................. 2-29
Fig. 2.3.7 Structure of Interrupt edge selection register ........................................................ 2-29
Fig. 2.3.8 Structure of Interrupt request register 2 ................................................................. 2-29
Fig. 2.3.9 Structure of Interrupt control register 2 .................................................................. 2-30
ii
3850/3851 Group User’s Manual
List of figures
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2.3.10 Serial I/O connection examples (1) ....................................................................... 2-31
2.3.11 Serial I/O connection examples (2) ....................................................................... 2-32
2.3.12 Serial I/O transfer data format ............................................................................... 2-33
2.3.13 Connection diagram ................................................................................................. 2-34
2.3.14 Timing chart (using clock synchronous serial I/O) .............................................. 2-34
2.3.15 Registers setting relevant to transmitting side..................................................... 2-35
2.3.16 Registers setting relevant to receiving side ......................................................... 2-36
2.3.17 Control procedure of transmitting side .................................................................. 2-37
2.3.18 Control procedure of receiving side ...................................................................... 2-38
2.3.19 Connection diagram ................................................................................................. 2-39
2.3.20 Timing chart .............................................................................................................. 2-39
2.3.21 Registers setting relevant to serial I/O ................................................................. 2-40
2.3.22 Setting of serial I/O transmission data ................................................................. 2-40
2.3.23 Control procedure of serial I/O .............................................................................. 2-41
2.3.24 Connection diagram ................................................................................................. 2-42
2.3.25 Timing chart .............................................................................................................. 2-43
2.3.26 Relevant registers setting ....................................................................................... 2-43
2.3.27 Control procedure of master unit ........................................................................... 2-44
2.3.28 Control procedure of slave unit ............................................................................. 2-45
2.3.29 Connection diagram (Communication using UART) ............................................ 2-46
2.3.30 Timing chart (using UART) ..................................................................................... 2-46
2.3.31 Registers setting relevant to transmitting side..................................................... 2-48
2.3.32 Registers setting relevant to receiving side ......................................................... 2-49
2.3.33 Control procedure of transmitting side .................................................................. 2-50
2.3.34 Control procedure of receiving side ...................................................................... 2-51
2.3.35 Sequence of setting serial I/O control register again ......................................... 2-53
2.4.1 Memory map of registers relevant to I2C-BUS interface ...................................... 2-55
2.4.2 Structure of I2C data shift register ........................................................................... 2-55
2.4.3 Structure of I2C address register ............................................................................. 2-56
2.4.4 Structure of I2C status register................................................................................. 2-56
2.4.5 Structure of I2C control register ............................................................................... 2-57
2.4.6 Structure of I2C clock control register ..................................................................... 2-58
2.4.7 Structure of I2C START/STOP condition control register ..................................... 2-59
2.4.8 Structure of Interrupt request register 1 ................................................................. 2-59
2.4.9 Structure of Interrupt control register 1 .................................................................. 2-60
2.4.10 I2C-BUS connection structure ................................................................................. 2-61
2.4.11 I2C-BUS communication format example .............................................................. 2-62
2.4.12 RESTART condition of master reception .............................................................. 2-63
2.4.13 SCL waveforms when synchronizing clocks......................................................... 2-64
2.4.14 Initial setting example using SMBUS communication ......................................... 2-66
2.4.15 Read Word protocol communication as SMBUS master device ....................... 2-67
2.4.16 Transmission process of START condition and slave address ......................... 2-68
2.4.17 Transmission process of command ....................................................................... 2-69
2.4.18 Transmission process of RESTART condition and slave address + read bit . 2-70
2.4.19 Reception process of lower data ........................................................................... 2-71
2.4.20 Reception process of upper data .......................................................................... 2-72
2.4.21 Generating of STOP condition ............................................................................... 2-73
2.4.22 Communication example as SMBUS slave device .............................................. 2-74
2.4.23 Reception process of START condition and slave address .............................. 2-75
2.4.24 Reception process of command ............................................................................. 2-76
2.4.25 Reception process of RESTART condition and slave address + read bit....... 2-77
2.4.26 Transmission process of lower data...................................................................... 2-78
3850/3851 Group User’s Manual
iii
List of figures
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2.4.27 Transmission process of upper data ..................................................................... 2-79
2.4.28 Reception of STOP condition ................................................................................. 2-80
2.5.1 Memory map of registers relavant to PWM ........................................................... 2-85
2.5.2 Structure of PWM control register ........................................................................... 2-85
2.5.3 Structure of PWM prescaler ..................................................................................... 2-86
2.5.4 Structure of PWM register ........................................................................................ 2-86
2.5.5 Connection diagram ................................................................................................... 2-87
2.5.6 PWM output timing..................................................................................................... 2-87
2.5.7 Setting of related registers ....................................................................................... 2-88
2.5.8 PWM output ................................................................................................................ 2-88
2.5.9 Control procedure ....................................................................................................... 2-89
2.6.1 Memory map of registers relevant to A-D converter ............................................ 2-90
2.6.2 Structure of A-D control register .............................................................................. 2-90
2.6.3 Structure of A-D conversion register (high-order) ................................................. 2-91
2.6.4 Structure of A-D conversion register (low-order) ................................................... 2-91
2.6.5 Structure of Interrupt request register 2 ................................................................. 2-92
2.6.6 Structure of Interrupt control register 2 .................................................................. 2-92
2.6.7 Connection diagram ................................................................................................... 2-93
2.6.8 Relevant registers setting ......................................................................................... 2-93
2.6.9 Control procedure for 8-bit read .............................................................................. 2-94
2.6.10 Control procedure for 10-bit read .......................................................................... 2-94
2.7.1 Example of poweron reset circuit ............................................................................ 2-96
2.7.2 RAM backup system .................................................................................................. 2-96
CHAPTER 3 APPENDIX
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
iv
3.1.1
3.1.2
3.1.3
3.1.4
3.2.1
Circuit for measuring output switching characteristics (1) ..................................... 3-9
Circuit for measuring output switching characteristics (2) ..................................... 3-9
Timing chart ................................................................................................................ 3-10
Timing diagram of multi-master I 2C-BUS ................................................................ 3-11
Power source current characteristic examples (f(X IN) = 8MHz, in high-speed mode)
..................................................................................................................................... 3-12
3.2.2 Power source current characteristic examples (f(X IN) = 8MHz, in middle-speed mode)
..................................................................................................................................... 3-12
3.2.3 Power source current characteristic examples (f(X IN) = 4MHz, in high-speed mode)
..................................................................................................................................... 3-13
3.2.4 Power source current characteristic examples (f(X IN) = 4MHz, in middle-speed mode)
..................................................................................................................................... 3-13
3.2.5 Power source current characteristic examples (f(XCIN) = 32KHz, in low-speed mode)
..................................................................................................................................... 3-14
3.2.6 Standard characteristic examples of CMOS output port at P-channel drive ..... 3-15
3.2.7 Standard characteristic examples of CMOS output port at N-channel drive ..... 3-15
3.2.8 Standard characteristic examples of N-channel open-drain output port at N-channel
drive ............................................................................................................................. 3-16
3.2.9 Standard characteristic examples of CMOS large current output port at N-channel
drive ............................................................................................................................. 3-16
3.2.10 A-D conversion standard characteristics............................................................... 3-17
3.3.1 Sequence of switch the detection edge.................................................................. 3-18
3.3.2 Sequence of check of interrupt request bit ............................................................ 3-18
3.3.3 Sequence of setting serial I/O control register again ........................................... 3-20
3.3.4 Ceramic resonator circuit .......................................................................................... 3-26
3.3.5 Initialization of processor status register ................................................................ 3-27
3.3.6 Sequence of PLP instruction execution .................................................................. 3-27
3850/3851 Group User’s Manual
List of figures
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
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Fig.
Fig.
Fig.
Fig.
Fig.
3.3.7 Stack memory contents after PHP instruction execution ..................................... 3-27
3.3.8 Interrupt routine .......................................................................................................... 3-28
3.3.9 Status flag at decimal calculations .......................................................................... 3-28
3.3.10 Programming and testing of One Time PROM version ...................................... 3-29
3.4.1 Selection of packages ............................................................................................... 3-32
3.4.2 Wiring for the RESET pin ......................................................................................... 3-32
3.4.3 Wiring for clock I/O pins ........................................................................................... 3-33
3.4.4 Wiring for CNVss pin ............................................................................................... 3-33
3.4.5 Wiring for the V PP pin of the One Time PROM and the EPROM version ......... 3-34
3.4.6 Bypass capacitor across the Vss line and the Vcc line ....................................... 3-34
3.4.7 Analog signal line and a resistor and a capacitor ................................................ 3-35
3.4.8 Wiring for a large current signal line ...................................................................... 3-35
3.4.9 Wiring of RESET pin ................................................................................................. 3-36
3.4.10 Vss pattern on the underside of an oscillator ..................................................... 3-36
3.4.11 Setup for I/O ports ................................................................................................... 3-37
3.4.12 Watchdog timer by software ................................................................................... 3-38
3.5.1 Structure of Port Pi (i=0, 1, 2, 3, 4) ....................................................................... 3-39
3.5.2 Structure of Port Pi direction register(i=0, 1, 2, 3, 4) .......................................... 3-39
3.5.3 Structure of Transmit/Receive buffer register ........................................................ 3-40
3.5.4 Structure of Serial I/O status register ..................................................................... 3-40
3.5.5 Structure of Serial I/O control register .................................................................... 3-41
3.5.6 Structure of UART control register .......................................................................... 3-41
3.5.7 Structure of Baud rate generator ............................................................................. 3-42
3.5.8 Structure of PWM control register ........................................................................... 3-42
3.5.9 Structure of PWM prescaler ..................................................................................... 3-43
3.5.10 Structure of PWM register ...................................................................................... 3-43
3.5.11 Structure of Prescaler 12, Prescaler X, Prescaler Y .......................................... 3-44
3.5.12 Structure of Timer 1 ................................................................................................ 3-44
3.5.13 Structure of Timer 2, Timer X, Timer Y ............................................................... 3-45
3.5.14 Structure of timer count source selection register .............................................. 3-45
3.5.15 Structure of Timer XY mode register .................................................................... 3-46
3.5.16 Structure of I 2C data shift register ......................................................................... 3-47
3.5.17 Structure of I2C address register ........................................................................... 3-47
3.5.18 Structure of I2C status register .............................................................................. 3-48
3.5.19 Structure of I2C control register ............................................................................. 3-48
3.5.20 Structure of I2C clock control register ................................................................... 3-49
3.5.21 Structure of I2C START/STOP condition control register ................................... 3-50
3.5.22 Structure of A-D control register ............................................................................ 3-50
3.5.23 Structure of A-D conversion register(low-order) .................................................. 3-51
3.5.24 Structure of A-D conversion register (high-order) ............................................... 3-51
3.5.25 Structure of MISRG ................................................................................................. 3-52
3.5.26 Structure of Watchdog timer control register ....................................................... 3-52
3.5.27 Structure of Interrupt edge selection register ...................................................... 3-53
3.5.28 Structure of CPU mode register ............................................................................ 3-53
3.5.29 Structure of Interrupt request register 1 ............................................................... 3-54
3.5.30 Structure of Interrupt request register 2 ............................................................... 3-54
3.5.31 Structure of Interrupt control register 1 ................................................................ 3-55
3.5.32 Structure of Interrupt control register 2 ................................................................ 3-55
3.13.1 M38513M4-XXXFP/SP pin configuration ............................................................... 3-91
3850/3851 Group User’s Manual
v
List of tables
List of tables
CHAPTER 1 HARDWARE
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
1 Pin description ................................................................................................................. 1-4
2 Push and pop instructions of accumulator or processor status register ................. 1-8
3 Set and clear instructions of each bit of processor status register ......................... 1-9
4 I/O port function table ................................................................................................... 1-13
5 Interrupt vector address and priority .......................................................................... 1-17
6 Multi-master I2C-BUS interface functions ................................................................... 1-25
7 Set values of I2C clock control register and SCL frequency .................................. 1-27
8 START condition generating timing table .................................................................. 1-31
9 STOP condition generating timing table ..................................................................... 1-31
10 START condition/STOP condition detecting conditions ............................................ 1-31
11 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each
oscillation frequency .................................................................................................... 1-33
Table 12 Programming adapter .................................................................................................. 1-46
Table 13 Interrupt sources, vector addresses and interrupt priority ..................................... 1-47
Table 14 Change of A-D conversion register during A-D conversion .................................. 1-49
CHAPTER 2 APPLICATION
Table
Table
Table
Table
2.1.1
2.2.1
2.3.1
2.4.1
Handling of unused pins .......................................................................................... 2-3
CNTR0 / CNTR 1 active edge switch bit function ................................................... 2-8
Setting example of Baud rate generator values and transfer bit rate values 2-47
Set value of I2C clock control register and SCL frequency .............................. 2-58
CHAPTER 3 APPENDIX
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
3.1.1 Absolute maximum ratings ....................................................................................... 3-2
3.1.2 Recommended operating conditions (1) ................................................................ 3-3
3.1.3 Recommended operating conditions (2) ................................................................ 3-4
3.1.4 Electrical characteristics (1)..................................................................................... 3-5
3.1.5 Electrical characteristics (2) ................................................................................... 3-6
3.1.6 A-D converter characteristics .................................................................................. 3-6
3.1.7 Timing requirements (1) ........................................................................................... 3-7
3.1.8 Timing requirements (2) ........................................................................................... 3-7
3.1.9 Switching requirements (1) ...................................................................................... 3-8
3.1.10 Switching requirements (2) .................................................................................... 3-8
3.1.11 Multi-master I2C-BUS bus line characteristics .................................................. 3-11
3.3.1 Programming adapters ........................................................................................... 3-29
3.3.2 PROM programmer address setting ..................................................................... 3-30
3.5.1 CNTR0 / CNTR 1 active edge switch bit function ................................................. 3-46
3.5.2 Set value of I2C clock control register and SCL frequency .............................. 3-49
3850/3851 Group User’s Manual
i
CHAPTER 1
HARDWARE
DESCRIPION
FEATURES
APPLICATION
PIN CONFIGURATION
FUNCTIONAL BLOCK
PIN DESCRIPTION
PART NUMBERING
GROUP EXPANSION
FUNCTIONAL DESCRIPTION
NOTES ON PROGRAMMING
DATA REQUIRED FOR MASK ORDERS
DATA REQUIRED FOR ROM WRITING ORDERS
ROM PROGRAMMING METHOD
FUNCTIONAL DESCRIPION SUPPLEMENT
HARDWARE
DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION
DESCRIPTION
The 3851 group is the 8-bit microcomputer based on the 740 family core technology.
The 3851 group is designed for the household products and office
automation equipment and includes serial I/O functions, 8-bit
timer, A-D converter, and I 2C-bus interface.
FEATURES
●Basic machine-language instructions ...................................... 71
●Minimum instruction execution time .................................. 0.5 µs
(at 8 MHz oscillation frequency)
●Memory size
ROM ................................................................ 16 K to 24 Kbytes
RAM ................................................................... 512 to 640 bytes
●Programmable input/output ports ............................................ 34
●Interrupts ................................................. 16 sources, 16 vectors
●Timers ............................................................................. 8-bit ✕ 4
●Serial I/O ....................... 8-bit ✕ 1(UART or Clock-synchronized)
●Multi-master I2C-bus interface (option) ....................... 1 channel
●PWM ............................................................................... 8-bit ✕ 1
●A-D converter ............................................... 10-bit ✕ 5 channels
●Watchdog timer ............................................................ 16-bit ✕ 1
●Clock generating circuit ..................................... Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
● Power source voltage
In high-speed mode .................................................. 4.0 to 5.5 V
(at 8 MHz oscillation frequency)
In high-speed mode .................................................. 2.7 to 5.5 V
(at 4 MHz oscillation frequency)
In middle-speed mode............................................... 2.7 to 5.5 V
(at 8 MHz oscillation frequency)
In low-speed mode .................................................... 2.7 to 5.5 V
(at 32 kHz oscillation frequency)
● Power dissipation
In high-speed mode .......................................................... 34 mW
(at 8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode ............................................................ 60 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
● Operating temperature range.................................... –20 to 85°C
APPLICATION
Office automation equipment, FA equipment, Household products,
Consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
1
42
2
41
3
40
4
39
5
38
6
37
7
8
9
10
11
12
13
14
15
16
M38513M4-XXXFP
M38513M4-XXXSP
VCC
VREF
AVSS
P44/INT3/PWM
P43/INT2
P42/INT1
P41/INT0
P40/CNTR1
P27/CNTR0/SRDY
P26/SCLK
P25/SCL2/TxD
P24/SDA2/RxD
P23/SCL1
P22/SDA1
CNVSS
P21/XCIN
P20/XCOUT
RESET
XIN
XOUT
VSS
36
35
34
33
32
31
30
29
28
27
17
26
18
25
19
24
20
23
21
22
P30/AN0
P31/AN1
P32/AN2
P33/AN3
P34/AN4
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13/(LED0)
P14/(LED1)
P15/(LED2)
P16/(LED3)
P17/(LED4)
Package type : FP ........................... 42P2R-A (42-pin plastic-molded SSOP)
Package type : SP ........................... 42P4B (42-pin shrink plastic-molded DIP)
Fig. 1 M38513M4-XXXFP/SP pin configuration
1-2
3850/3851 Group User’s Manual
Sub-clock Sub-clock
input
output
XCIN XCOUT
3850/3851 Group User’s Manual
3
AVSS
VREF
2
A-D
converter
(10)
PWM
(8)
Reset
Clock generating circuit
20
Main-clock
output
XOUT
Watchdog
timer
19
Main-clock
input
XIN
I/O port P4
4 5 6 7 8
P4(5)
RAM
FUNCTIONAL BLOCK DIAGRAM
INT0–
INT3
ROM
I/O port P3
38 39 40 41 42
P3(5)
21
VSS
PC H
A
SI/O(8)
PS
2
I C
PC L
S
Y
X
18
C P U
RESET
1
CNTR0
Reset input
VCC
P2(8)
CNTR1
I/O port P2
XCOUT
XCIN
Prescaler Y(8)
Prescaler X(8)
Prescaler 12(8)
9 10 11 12 13 14 16 17
15
CNVSS
I/O port P1
22 23 24 25 26 27 28 29
P1(8)
P0(8)
I/O port P0
30 31 32 3334 35 36 37
Timer Y( 8 )
Timer X( 8 )
Timer 2( 8 )
Timer 1( 8 )
HARDWARE
FUNCTIONAL BLOCK
FUNCTIONAL BLOCK
Fig. 2 Functional block diagram
1-3
HARDWARE
PIN DESCRIPTION
PIN DESCRIPTION
Table 1 Pin description
Pin
Name
VCC, VSS
Power source
CNVSS
CNVSS input
RESET
Reset input
XIN
Clock input
XOUT
Clock output
P00–P07
I/O port P0
P10–P17
I/O port P1
P20/X COUT
P21/X CIN
P22/SDA1
P23/SCL 1
P24/SDA2 /RxD
P25/SCL 2/TxD
P26/S CLK
P27/CNTR0/
SRDY
P30/AN0 –
P34/AN4
P40/CNTR1
P41/INT0–
P43/INT2
I/O port P2
Functions
•This pin controls the operation mode of the chip.
•Normally connected to VSS.
•Reset input pin for active “L.”
•Input and output pins for the clock generating circuit.
•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and X OUT pins to set
the oscillation frequency.
•When an external clock is used, connect the clock source to the XIN pin and leave the X OUT
pin open.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level.
•CMOS 3-state output structure.
•P1 3 to P17 (5 bits) are enabled to output large current for LED drive (M38513E4/M4).
•P1 0 to P17 (8 bits) are enabled to output large current for LED drive (M38514E6/M6).
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•CMOS compatible input level.
•P2 2 to P2 5 can be switched between CMOS compatible input level or SMBUS input level in the I 2C-BUS
interface function.
•P20, P2 1, P24 to P27: CMOS3-state output structure.
•P2 4, P2 5: N-channel open-drain structure in the I 2CBUS interface function.
•P22, P2 3: N-channel open-drain structure.
•8-bit CMOS I/O port with the same function as port P0.
I/O port P3
I/O port P4
•CMOS compatible input level.
•CMOS 3-state output structure.
•8-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
•CMOS 3-state output structure.
• Sub-clock generating circuit I/O
pins (connect a resonator)
• I2C-BUS interface function pins
• I2C-BUS interface function pin/
Serial I/O function pins
• Serial I/O function pin
• Serial I/O function pin/
Timer X function pin
• A-D conver ter input pin
• Timer Y function pin
• Interrupt input pins
• Interrupt input pin
• PWM output pin
P44/INT3/PWM
1-4
Function except a port function
•Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.
3850/3851 Group User’s Manual
HARDWARE
PART NUMBERING
PART NUMBERING
Product name
M3851
3
M
4
-
XXX
FP
Package type
FP : 42P2R-A
SP : 42P4B
ROM number
Omitted in the one time PROM version shipped in blank.
– : standard
– is omitted in the One Time PROM version shipped in blank.
ROM/PROM size
1 : 4096 bytes
9: 36864 bytes
2 : 8192 bytes
A : 40960 bytes
3 : 12288 bytes
B : 45056 bytes
4 : 16384 bytes
C: 49152 bytes
5 : 20480 bytes
D: 53248 bytes
6 : 24576 bytes
E : 57344 bytes
7 : 28672 bytes
F : 61440 bytes
8 : 32768 bytes
The first 128 bytes and the last 2 bytes of ROM are reserved
areas ; they cannot be used.
Memory type
M : Mask ROM version
E : One Time PROM version
RAM size
0 : 192 bytes
5 : 768 bytes
1 : 256 bytes
6 : 896 bytes
2 : 384 bytes
7 : 1024 bytes
3 : 512 bytes
8 : 1536 bytes
4 : 640 bytes
9 : 2048 bytes
Fig. 3 Part numbering
3850/3851 Group User’s Manual
1-5
HARDWARE
GROUP EXPANSION
GROUP EXPANSION
Packages
Mitsubishi plans to expand the 3851 group as follows:
42P2R-A ............................................ 42-pin plastic molded SSOP
42P4B ......................................... 42-pin shrink plastic-molded DIP
Memory Type
Support for mask ROM and One Time PROM versions.
Memory Size
ROM size ............................................................ 16 K to 24 Kbytes
RAM size .............................................................. 512 to 640 bytes
Memory Expansion Plan
ROM size (bytes)
48K
32K
28K
New production
M38514E6FP/SP
M38514M6-XXXFP/SP
24K
20K
Mass production
M38513E4FP/SP
M38513M4-XXXFP/SP
16K
12K
8K
128
192
256
384
512
640
RAM size (bytes)
Fig. 4 Memory expansion plan
1-6
3850/3851 Group User’s Manual
768
896
1024
HARDWARE
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
Stack pointer (S)
The stack pointer is an 8-bit register used during sub-routine calls
and interrupts. The stack is used to store the current address data
and processor status when branching to subroutines or interrupt routines.
The lower eight bits of the stack address are determined by the contents of the stack pointer. The upper eight bits of the stack address
are determined by the Stack Page Selection Bit. If the Stack Page
Selection Bit is “0”, then the RAM in the zero page is used as the
stack area. If the Stack Page Selection Bit is “1”, then RAM in page 1
is used as the stack area.
The Stack Page Selection Bit is located in the SFR area in the zero
page. Note that the initial value of the Stack Page Selection Bit varies with each microcomputer type. Also some microcomputer types
have no Stack Page Selection Bit and the upper eight bits of the
stack address are fixed. The operations of pushing register contents
onto the stack and popping them from the stack are shown in Figure 8.
The 3851 group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine
instructions or the 740 Series Software Manual for details on the
instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
The central processing unit (CPU) has the six registers.
Accumulator (A)
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
Index register X (X), Index register Y (Y)
Both index register X and index register Y are 8-bit registers. In the
index addressing modes, the value of the OPERAND is added to the
contents of register X or register Y and specifies the real address.
When the T flag in the processor status register is set to “1”, the
value contained in index register X becomes the address for the second OPERAND.
b7
Program counter (PC)
The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed.
b0
Accumulator
A
b7
b0
Index Register X
X
b7
b0
Index Register Y
Y
b7
b0
Stack Pointer
S
b15
b7
PCH
b0
Program Counter
PCL
b7
b0
N V T B D I Z C Processor Status Register (PS)
Carry Flag
Zero Flag
Interrupt Disable Flag
Decimal Mode Flag
Break Flag
Index X Mode Flag
Overflow Flag
Negative Flag
Fig. 5 740 Family CPU register structure
3850/3851 Group User’s Manual
1-7
HARDWARE
FUNCTIONAL DESCRIPTION
On-going Routine
Interrupt request
(Note)
M (S)
(PCH)
(S)
(S – 1)
M (S)
(PCL)
(S)
(S – 1)
M (S)
(PS)
(S)
(S – 1)
Execute JSR
M (S)
Store Return Address
on Stack
(S)
M (S)
(S)
(PCH)
(S – 1)
(PCL)
(S – 1)
Subroutine
(S)
(PCL)
(S)
(S + 1)
(PS)
M (S)
(S)
(S + 1)
(PCL)
M (S)
(S)
(S + 1)
(PCH)
M (S)
M (S)
(S + 1)
(PCH)
M (S)
I Flag “0” to “1”
Fetch the Jump Vector
Execute RTI
(S + 1)
(S)
Store Contents of Processor
Status Register on Stack
Interrupt
Service Routine
Execute RTS
Restore Return
Address
Store Return Address
on Stack
Note : The condition to enable the interrupt
Restore Contents of
Processor Status Register
Restore Return
Address
Interrupt enable bit is “1”
Interrupt disable flag is “0”
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 2 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
1-8
Push instruction to stack
Pop instruction from stack
PHA
PHP
PLA
PLP
3850/3851 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Processor status register (PS)
The processor status register is an 8-bit register consisting of flags
which indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C)
flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid.
After reset, the Interrupt disable (I) flag is set to “1”, but all other flags
are undefined. Since the Index X mode (T) and Decimal mode (D)
flags directly affect arithmetic operations, they should be initialized in
the beginning of a program.
(1) Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
(2) Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
(3) Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
When an interrupt occurs, this flag is automatically set to “1” to
prevent other interrupts from interfering until the current interrupt
is serviced.
(4) Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
(5) Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”. The saved processor
status is the only place where the break flag is ever set.
(6) Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory, e.g. the results of an
operation between two memory locations is stored in the
accumulator. When the T flag is “1”, direct arithmetic operations
and direct data transfers are enabled between memory locations,
i.e. between memory and memory, memory and I/O, and I/O and
I/O. In this case, the result of an arithmetic operation performed
on data in memory location 1 and memory location 2 is stored in
memory location 1. The address of memory location 1 is
specified by index register X, and the address of memory
location 2 is specified by normal addressing modes.
(7) Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
(8) Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 3 Set and clear instructions of each bit of processor status register
C flag
Set instruction
Clear instruction
SEC
CLC
Z flag
_
_
I flag
SEI
CLI
D flag
SED
CLD
3850/3851 Group User’s Manual
B flag
_
_
T flag
V flag
SET
CLT
_
CLV
N flag
_
_
1-9
HARDWARE
FUNCTIONAL DESCRIPTION
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc.
The CPU mode register is allocated at address 003B16 .
b7
b0
CPU mode register
(CPUM : address 003B16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 : Not available
1 1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (return “1” when read)
(Do not write “0” to this bit.)
Port X C switch bit
0 : I/O port function (stop oscillating)
1 : X CIN–XCOUT oscillating function
Main clock (X IN–XOUT ) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0 0 : φ = f(X IN)/2 (high-speed mode)
0 1 : φ = f(X IN)/8 (middle-speed mode)
1 0 : φ = f(X CIN)/2 (low-speed mode)
1 1 : Not available
Fig. 7 Structure of CPU mode register
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3850/3851 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
MEMORY
Special Function Register (SFR) Area
Zero Page
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
Special Page
RAM
Access to this area with only 2 bytes is possible in the special
page addressing mode.
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM size
(bytes)
Address
XXXX16
192
256
384
512
640
768
896
1024
1536
2048
3072
4032
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
0C3F16
0FFF16
000016
SFR area
Zero page
004016
RAM
010016
XXXX16
Reserved area
044016
Not used
YYYY16
ROM area
Reserved ROM area
ROM size
(bytes)
Address
YYYY16
Address
ZZZZ16
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
(128 bytes)
ZZZZ16
ROM
FF0016
FFDC16
Interrupt vector area
FFFE16
FFFF16
Special page
Reserved ROM area
Fig. 8 Memory map diagram
3850/3851 Group User’s Manual
1-11
HARDWARE
FUNCTIONAL DESCRIPTION
000016
Port P0 (P0)
002016
Prescaler 12 (PRE12)
000116
Port P0 direction register (P0D)
002116
Timer 1 (T1)
000216
Port P1 (P1)
002216
Timer 2 (T2)
000316
Port P1 direction register (P1D)
002316
Timer XY mode register (TM)
000416
Port P2 (P2)
002416
Prescaler X (PREX)
000516
Port P2 direction register (P2D)
002516
Timer X (TX)
000616
Port P3 (P3)
002616
Prescaler Y (PREY)
000716
Port P3 direction register (P3D)
002716
Timer Y (TY)
000816
Port P4 (P4)
002816
Timer count source selection register (TCSS)
000916
Port P4 direction register (P4D)
002916
000A16
002A16
000B16
002B16
I2C data shift register (S0)
000C16
002C16
I2C address register (S0D)
000D16
002D16
I2C status register (S1)
000E16
002E16
I2C control register (S1D)
000F16
002F16
I2C clock control register (S2)
001016
003016
I2C start/stop condition control register (S2D)
001116
003116
Reserved ✽
001216
003216
001316
003316
003416
A-D control register (ADCON)
001516
Reserved ✽
003516
A-D conversion low-order register (ADL)
001616
Reserved ✽
003616
A-D conversion high-order register (ADH)
001716
Reserved ✽
003716
001816
Transmit/Receive buffer register (TB/RB)
003816
001916
Serial I/O status register (SIOSTS)
003916
Watchdog timer control register (WDTCON)
001A16
Serial I/O control register (SIOCON)
003A16
Interrupt edge selection register (INTEDGE)
001B16
UART control register (UARTCON)
003B16
CPU mode register (CPUM)
001C16
Baud rate generator (BRG)
003C16
Interrupt request register 1 (IREQ1)
001D16
PWM control register (PWMCON)
003D16
Interrupt request register 2 (IREQ2)
001E16
PWM prescaler (PREPWM)
003E16
Interrupt control register 1 (ICON1)
001F16
PWM register (PWM)
003F16
Interrupt control register 2 (ICON2)
001416
MISRG
✽ Reserved : Do not write “1” to this address.
Fig. 9 Memory map of special function register (SFR)
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3850/3851 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input
port or output port.
When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Table 4 I/O port function
Pin
Name
P00–P07
Port P0
P10–P17
Port P1
Input/Output
CMOS compatible
input level
CMOS 3-state output
P20/XCOUT
P21/XCIN
P22/SDA1
P23/SCL1
Port P2
P24/SDA2/RxD
P25/SCL2/TxD
I/O Structure
Input/output,
individual
bits
CMOS compatible
input level
CMOS/SMBUS input
level (when selecting
I 2C-BUS interface
function)
N-channel open-drain
output
CMOS compatible
input level
CMOS/SMBUS input
level (when selecting
I 2C-BUS interface
function)
CMOS 3-state output
N-channel open-drain
output (when
selecting I 2C-BUS
interface function)
P26/SCLK
Non-Port Function
P30/AN0—
P34/AN4
Port P3
P40 /CNTR1
P41/INT0—
P43/INT2
P44/INT3/PWM
CMOS compatible
input level
CMOS 3-state output
Ref.No.
(1)
Sub-clock generating
circuit
CPU mode register
(2)
(3)
I2C-BUS interface function I/O
I 2C control register
(4)
(5)
(6)
(7)
Serial I/O function I/O
I 2C control register
Serial I/O control
register
Serial I/O function I/O
Serial I/O control
register
(8)
Timer X function I/O
Serial I/O control
register
Timer XY mode register
(9)
A-D conversion input
A-D control register
(10)
Timer Y function I/O
Timer XY mode register
(11)
External interrupt input
Interrupt edge selection
register
(12)
External interrupt input
PWM output
Interrupt edge selection
register
PWM control register
(13)
I2C-BUS interface function I/O
Serial I/O function I/O
P27/CNTR 0/SRDY
Related SFRs
Port P4
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1-13
HARDWARE
FUNCTIONAL DESCRIPTION
(2) Port P20
(1) Port P0, P1
Port XC switch bit
Direction
register
Data bus
Direction
register
Port latch
Data bus
Port latch
Oscillator
Port P21
(3) Port P21
Port XC switch bit
Port XC switch bit
Direction
register
(4) Port P22
I2 C-BUS interface enable bit
SDA/SCL pin selection bit
Data bus
Port latch
Direction
register
Data bus
Port latch
Sub-clock generating circuit input
SDA output
(5) Port P23
SDA input
I 2 C-BUS interface enable bit
SDA/SCL pin selection bit
(6) Port P24
Direction
register
Data bus
I 2 C-BUS interface enable bit
SDA/SCL pin selection bit
Serial I/O enable bit
Receive enable bit
Port latch
Direction
register
Data bus
Port latch
SCL output
SCL input
(7) Port P25
SDA output
P-channel output disable bit
SDA input
Serial I/O input
Serial I/O enable bit
Transmit enable bit
I C bus interface enable bit
SDA/SCL pin selection bit
2
(8) Port P26
Serial I/O enable bit
Serial I/O clock selection bit
Direction
register
Serial I/O mode selection bit
Data bus
Port latch
Serial I/O enable bit
Direction
register
Data bus
Port latch
SCL input
Serial I/O output
SCL output
Serial clock output
External clock input
Fig. 10 Port block diagram (1)
1-14
3850/3851 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
(9) Port P27
(10) Port P30–P34
Pulse output mode
Serial I/O mode selection bit
Serial I/O enable bit
SRDY output enable bit
Direction
register
Data bus
Direction
register
Data bus
Port latch
Port latch
A-D converter input
Analog input pin selection bit
Pulse output mode
Serial ready output
CNTR0 interrupt
input
(12) Port P41–P43
Direction
register
Timer output
Data bus
Port latch
(11) Port P40
Direction
register
Interrupt input
Data bus
Port latch
Pulse output mode
Timer output
CNTR1 interrupt input
(13) Port P44
PWM output enable bit
Direction
register
Data bus
Port latch
PWM output
Fig. 11 Port block diagram (2)
3850/3851 Group User’s Manual
1-15
HARDWARE
FUNCTIONAL DESCRIPTION
INTERRUPTS
■Notes
Interrupts occur by 16 sources among 16 sources: seven external,
eight internal, and one software.
When the active edge of an external interrupt (INT 0–INT3, SCL/
SDA, CNTR 0, CNTR1) is set, the corresponding interrupt request
bit may also be set. Therefore, take the following sequence:
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
1. Disable the interrupt
2. Change the interrupt edge selection register
(SCL/SDA interrupt pin polarity selection bit for SCL/SDA; the
timer XY mode register for CNTR 0 and CNTR1 )
3. Clear the interrupt request bit to “0”
4. Accept the interrupt.
Interrupt Operation
By acceptance of an interrupt, the following operations are automatically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
1-16
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HARDWARE
FUNCTIONAL DESCRIPTION
Table 5 Interrupt vector addresses and priority
Interrupt Source
Reset (Note 2)
Priority
1
Vector Addresses (Note 1)
High
Low
FFFD16
FFFC 16
Interrupt Request
Generating Conditions
Remarks
At reset
Non-maskable
External interrupt
(active edge selectable)
INT 0
2
FFFB 16
FFFA16
At detection of either rising or
falling edge of INT0 input
SCL, SDA
3
FFF916
FFF816
At detection of either rising or
falling edge of SCL or SDA input
External interrupt
(active edge selectable)
INT 1
4
FFF716
FFF616
At detection of either rising or
falling edge of INT1 input
External interrupt
(active edge selectable)
INT 2
5
FFF516
FFF416
At detection of either rising or
falling edge of INT2 input
External interrupt
(active edge selectable)
INT3
6
FFF316
FFF216
At detection of either rising or
falling edge of INT3 input
External interrupt
(active edge selectable)
I2 C
Timer X
Timer Y
Timer 1
Timer 2
7
8
9
FFF116
FFEF 16
FFED16
10
11
FFEB16
FFE916
FFF016
FFEE16
FFEC16
FFEA16
FFE816
Serial I/O
reception
12
FFE716
FFE616
At completion of serial I/O data
reception
Valid when serial I/O is selected
Serial I/O
Transmission
13
FFE516
FFE416
At completion of serial I/O transfer shift or when transmission
buffer is empty
Valid when serial I/O is selected
CNTR0
14
FFE316
FFE216
At detection of either rising or
falling edge of CNTR0 input
External interrupt
(active edge selectable)
CNTR1
15
FFE116
FFE016
At detection of either rising or
falling edge of CNTR1 input
External interrupt
(active edge selectable)
A-D converter
BRK instruction
16
FFDF16
FFDE16
At completion of A-D conversion
17
FFDD16
FFDC16
At BRK instruction execution
At completion of data transfer
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
STP release timer underflow
Non-maskable software interrupt
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
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1-17
HARDWARE
FUNCTIONAL DESCRIPTION
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
Fig. 12 Interrupt control
b7
b0 Interrupt edge selection register
(INTEDGE : address 003A16)
INT0 active edge selection bit
INT1 active edge selection bit
INT2 active edge selection bit
INT3 active edge selection bit
Reserved(Do not write “1” to this bit)
Not used (returns “0” when read)
b7
b0 Interrupt request register 1
(IREQ1 : address 003C16)
0 : Falling edge active
1 : Rising edge active
b7
b0 Interrupt request register 2
(IREQ2 : address 003D16)
INT0 interrupt request bit
SCL/SDA interrupt request bit
INT1 interrupt request bit
INT2 interrupt request bit
INT3 interrupt request bit
I2C interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Serial I/O reception interrupt request bit
Serial I/O transmit interrupt request bit
CNTR0 interrupt request bit
CNTR1 interrupt request bit
AD converter interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
Interrupt control register 1
(ICON1 : address 003E16)
b7
INT0 interrupt enable bit
SCL/SDA interrupt enable bit
INT1 interrupt enable bit
INT2 interrupt enable bit
INT3 interrupt enable bit
I2C interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
0 : Interrupts disabled
1 : Interrupts enabled
Interrupt control register 2
(ICON2 : address 003F16)
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Serial I/O reception interrupt enable bit
Serial I/O transmit interrupt enable bit
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 13 Structure of interrupt-related registers (1)
1-18
b0
3850/3851 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
TIMERS
Timer 1 and Timer 2
The 3851 group has four timers: timer X, timer Y, timer 1, and
timer 2.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are count down. When the timer reaches “0016 ”, an underflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
The count source of prescaler 12 is the oscillation frequency
which is selected by timer 12 count source selection bit. The output of prescaler 12 is counted by timer 1 and timer 2, and a timer
underflow sets the interrupt request bit.
Timer X and Timer Y
Timer X and Timer Y can each select in one of four operating
modes by setting the timer XY mode register.
(1) Timer Mode
The timer counts the count source selected by Timer count source
selection bit.
b0
b7
Timer XY mode register
(TM : address 002316)
Timer X operating mode bit
b1b0
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR0 active edge selection bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Timer X count stop bit
0: Count start
1: Count stop
Timer Y operating mode bit
b5b4
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR1 active edge selection bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Timer Y count stop bit
0: Count start
1: Count stop
Fig. 14 Structure of timer XY mode register
b7
b0
Timer count source selection register
(TCSS : address 002816)
Timer X count source selection bit
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Timer Y count source selection bit
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Timer 12 count source selection bit
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XCIN)
Not used (returns “0” when read)
Fig. 15 Structure of timer count source selection register
(2) Pulse Output Mode
The timer counts the count source selected by Timer count source
selection bit. Whenever the contents of the timer reach “0016 ”, the
signal output from the CNTR 0 (or CNTR1 ) pin is inverted. If the
CNTR0 (or CNTR 1) active edge selection bit is “0”, output begins
at “ H”.
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P2 7 ( or port P40) direction register to output mode.
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the CNTR 0 or
CNTR1 pin.
When the CNTR 0 (or CNTR1) active edge selection bit is “0”, the
rising edge of the CNTR0 (or CNTR1) pin is counted.
When the CNTR 0 (or CNTR1) active edge selection bit is “1”, the
falling edge of the CNTR 0 (or CNTR1) pin is counted.
(4) Pulse Width Measurement Mode
If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer
counts the selected signals by the count source selection bit while
the CNTR0 (or CNTR1 ) pin is at “H”. If the CNTR0 (or CNTR1) active edge selection bit is “1”, the timer counts it while the CNTR 0
(or CNTR1) pin is at “L”.
The count can be stopped by setting “1” to the timer X (or timer Y)
count stop bit in any mode. The corresponding interrupt request
bit is set each time a timer underflows.
■Note
When switching the count source by the timer 12, X and Y count
source selection bit, the value of timer count is altered in
unconsiderable amount owing to generating of a thin pulses in
the count input signals.
Therefore, select the timer count source before set the value to
the prescaler and the timer.
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1-19
HARDWARE
FUNCTIONAL DESCRIPTION
Data bus
f(XIN)/16
f(XIN)/2
Prescaler X latch (8)
Timer X latch (8)
Pulse width
Timer X count source selection bit measurement Timer mode
Pulse output mode
mode
Prescaler X (8)
CNTR0 active
edge selection
bit
“0”
P27/CNTR0
Event
counter
mode
“1”
Timer X (8)
Timer X count stop bit
To CNTR0 interrupt
request bit
CNTR0 active
edge selection “1”
bit
“0”
Q
Toggle flip-flop T
Q
R
Timer X latch write pulse
Pulse output mode
Port P27
latch
Port P27
direction register
To timer X interrupt
request bit
Pulse output mode
Data bus
Prescaler Y latch (8)
f(XIN)/16
f(XIN)/2
Timer Y count source selection bit
Pulse width
measurement mode
Timer mode
Pulse output mode
Prescaler Y (8)
CNTR1 active
edge selection
bit
“0”
P40/CNTR1
Event
counter
mode
“1”
Port P40
direction register
Timer Y (8)
To timer Y interrupt
request bit
Timer Y count stop bit
To CNTR1 interrupt
request bit
CNTR1 active
edge selection “1”
bit
Q
Toggle flip-flop T
Q
Port P40
latch
Timer Y latch (8)
“0”
R
Timer Y latch write pulse
Pulse output mode
Pulse output mode
Data bus
Prescaler 12 latch (8)
f(XIN)/16
f(XCIN)
Prescaler 12 (8)
Timer 1 latch (8)
Timer 2 latch (8)
Timer 1 (8)
Timer 2 (8)
To timer 2 interrupt
request bit
Timer 12 count source selection bit
To timer 1 interrupt
request bit
Fig. 16 Block diagram of timer X, timer Y, timer 1, and timer 2
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3850/3851 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
SERIAL I/O
(1) Clock Synchronous Serial I/O Mode
Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud
rate generation.
Clock synchronous serial I/O mode can be selected by setting the
serial I/O mode selection bit of the serial I/O control register (bit 6
of address 001A16) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Data bus
Serial I/O control register
Address 001816
Receive buffer register
Receive interrupt request (RI)
Receive shift register
P24/RXD
Address 001A16
Receive buffer full flag (RBF)
Shift clock
Clock control circuit
P26/SCLK
XIN
Serial I/O synchronous
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
Baud rate generator
Address 001C16
1/4
P27/SRDY
F/F
1/4
Clock control circuit
Falling-edge detector
Shift clock
P25/TXD
Transmit shift register
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit buffer register
Transmit buffer empty flag (TBE)
Serial I/O status register
Address 001916
Address 001816
Data bus
Fig. 17 Block diagram of clock synchronous serial I/O
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
D0
D1
D2
D3
D4
D5
D6
D7
Serial input RxD
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY
Write pulse to receive/transmit
buffer register (address 001816)
TBE = 0
TBE = 1
TSC = 0
RBF = 1
TSC = 1
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has
ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 18 Operation of clock synchronous serial I/O function
3850/3851 Group User’s Manual
1-21
HARDWARE
FUNCTIONAL DESCRIPTION
(2) Asynchronous Serial I/O (UART) Mode
two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read from
the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit (b6) of the serial I/O control register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
Data bus
Address 0018 16
P24/RXD
Serial I/O control register
Address 001A16
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive buffer register
OE
Character length selection bit
ST detector
7 bits
Receive shift register
1/16
8 bits
PE FE
SP detector
Clock control circuit
UART control register
Address 001B16
Serial I/O synchronous clock selection bit
P26/SCLK1
XIN
BRG count source selection bit Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C 16
1/4
ST/SP/PA generator
Transmit shift completion flag (TSC)
1/16
Transmit shift register
P25/TXD
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer register
Address 001816
Transmit buffer empty flag (TBE)
Serial I/O status register Address 001916
Data bus
Fig.19 Block diagram of UART serial I/O
1-22
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HARDWARE
FUNCTIONAL DESCRIPTION
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TSC=0
TBE=1
Serial output TXD
TBE=0
TBE=1
ST
D0
D1
SP
TSC=1
ST
D0
D1
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read
signal
SP
Generated at 2nd bit in 2-stop-bit mode
RBF=0
RBF=1
Serial input RXD
ST
D0
D1
SP
RBF=1
ST
D0
D1
SP
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 20 Operation of UART serial I/O function
[Transmit Buffer Register/Receive Buffer
Register (TB/RB)] 001816
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
[Serial I/O Status Register (SIOSTS)] 001916
The read-only serial I/O status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE
(bit 7 of the serial I/O control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O control
register has been set to “1”, the transmit shift completion flag (bit
2) and the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O Control Register (SIOCON)] 001A16
The serial I/O control register consists of eight control bits for the
serial I/O function.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P25/T XD pin.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
■Note
When using the serial I/O, clear the I 2C-BUS interface enable bit
to “0” or the SDA/SCL pin selection bit to “0”.
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HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
b7
Serial I/O status register
(SIOSTS : address 0019 16)
b0
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Serial I/O synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
SRDY output enable bit (SRDY)
0: P2 7 pin operates as ordinary I/O pin
1: P2 7 pin operates as S RDY output pin
Overrun error flag (OE)
0: No error
1: Overrun error
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Serial I/O mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Not used (returns “1” when read)
b7
b0
UART control register
(UARTCON : address 001B 16)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P25/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
Fig. 21 Structure of serial I/O control registers
1-24
Serial I/O control register
(SIOCON : address 001A 16)
BRG count source selection bit (CSS)
0: f(X IN)
1: f(X IN)/4
3850/3851 Group User’s Manual
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
(pins P2 4 to P2 7 operate as ordinary I/O pins)
1: Serial I/O enabled
(pins P2 4 to P2 7 operate as serial I/O pins)
HARDWARE
FUNCTIONAL DESCRIPTION
MULTI-MASTER I2C-BUS INTERFACE
Table 6 Multi-master I2C-BUS interface functions
The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I 2C-BUS data transfer format. This
interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial
communications.
Figure 19 shows a block diagram of the multi-master I2 C-BUS interface and Table 4 lists the multi-master I2 C-BUS interface
functions.
This multi-master I 2C-BUS interface consists of the I 2C address
register, the I 2C data shift register, the I2C clock control register,
the I 2C control register, the I2C status register, the I2C start/stop
condition control register and other control circuits.
When using the multi-master I 2 C-BUS interface, set 1 MHz or
more to φ.
Item
Function
In conformity with Philips I 2C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I2C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at φ= 4 MHz)
Format
Communication mode
SCL clock frequency
System clock φ = f(XIN)/2 (high-speed mode)
φ = f(XIN)/8 (middle-speed mode)
Note: Mitsubishi Electric Corporation assumes no responsibility for infringement of any third-party’s rights or originating in the use of the
connection control function between the I2 C-BUS interface and the
ports SCL1 , SCL2, SDA1 and SDA2 with the bit 6 of I2C control register (002E16).
I2C address register
b7
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0
b0
Interrupt
generating
circuit
RBW
S0D
Interrupt request signal
(IICIRQ)
Address comparator
Serial data
(SDA)
Noise
elimination
circuit
Data
control
circuit
b7
b0
I2C data shift register
b7
b0
S0
AL AAS AD0 LRB
MST TRX BB PIN
SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0
S2D
AL
circuit
S1
I2 C status register
I2 C start/stop condition
control register
Internal data bus
BB
circuit
Serial
clock
(SCL)
Noise
elimination
circuit
Clock
control
circuit
b7
ACK
b0
ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0
BIT MODE
S2
I2C clock control register
Clock division
I2C clock control register
S1D
b0
b7
TISS
TSEL
S1D
I2C
System clock (φ)
10BIT
SAD
ALS
ES0 BC2 BC1 BC0
control register
Bit counter
Fig. 22 Block diagram of multi-master I 2C-BUS interface
✽ : Purchase of MITSUBISHI ELECTRIC CORPORATIONS I 2C components conveys a license under the Philips I 2C Patent Rights to use these components
an I 2C system, provided that the system conforms to the I2 C Standard Specification as defined by Philips.
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HARDWARE
FUNCTIONAL DESCRIPTION
[I2C Data Shift Register (S0)] 002B16
The I2 C data shift register (S0 : address 002B16 ) is an 8-bit shift
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to
the outside from bit 7 in synchronization with the SCL clock, and
each time one-bit data is output, the data of this register are
shifted by one bit to the left. When data is received, it is input to
this register from bit 0 in synchronization with the SCL clock, and
each time one-bit data is input, the data of this register are shifted
by one bit to the left. The minimum 2 machine cycles are required
from the rising of the SCL clock until input to this register.
The I2C data shift register is in a write enable status only when the
I2 C-BUS interface enable bit (ES0 bit : bit 3 of address 002E16) of
the I2C control register is “1”. The bit counter is reset by a write instruction to the I 2C data shift register. When both the ES0 bit and
the MST bit of the I2 C status register (address 002D16 ) are “1,” the
SCL is output by a write instruction to the I2C data shift register.
Reading data from the I2C data shift register is always enabled regardless of the ES0 bit value.
b7
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB
I2C address register
(S0D: address 002C 16)
Read/write bit
Slave address
Fig. 23 Structure of I2C address register
[I2C Address Register (S0D)] 002C16
The I2 C address register (address 002C 16) consists of a 7-bit
slave address and a read/write bit. In the addressing mode, the
slave address written in this register is compared with the address
data to be received immediately after the START condition is detected.
•Bit 0: Read/write bit (RWB)
This is not used in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared
with the contents (SAD6 to SAD0 + RBW) of the I2C address register.
The RWB bit is cleared to “0” automatically when the stop condition is detected.
•Bits 1 to 7: Slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit address
1-26
b0
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HARDWARE
FUNCTIONAL DESCRIPTION
Note: Do not write data into the I2C clock control register during transfer. If
data is written during transfer, the I 2C clock generator is reset, so
that data cannot be transferred normally.
I2C clock control register
(S2 : address 002F 16)
SCL frequency control bits
Refer to Table 5.
SCL mode specification bit
0 : Standard clock mode
1 : High-speed clock mode
ACK bit
0 : ACK is returned.
1 : ACK is not returned.
ACK clock bit
0 : No ACK clock
1 : ACK clock
Fig. 24 Structure of I2C clock control register
Table 7 Set values of I 2 C clock control register and SCL
frequency
SCL frequency
Setting value of
(at φ = 4 MHz, unit : kHz)
CCR4–CCR0
Standard clock High-speed clock
CCR4 CCR3 CCR2 CCR1 CCR0
mode
mode
0
0
0
0
Setting disabled
Setting disabled
0
0
0
0
1
Setting disabled
Setting disabled
0
0
0
1
0
Setting disabled
Setting disabled
0
0
0
1
1
– (Note 2)
333
0
0
1
0
0
– (Note 2)
250
0
0
1
0
1
100
400 (Note 3)
0
0
1
1
0
83.3
166
…
0
…
•Bit 7: ACK clock bit (ACK)
This bit specifies the mode of acknowledgment which is an acknowledgment response of data transfer. When this bit is set to
“0,” the no ACK clock mode is selected. In this case, no ACK clock
occurs after data transmission. When the bit is set to “1,” the ACK
clock mode is selected and the master generates an ACK clock
each completion of each 1-byte data transfer. The device for
transmitting address data and control data releases the SDA at
the occurrence of an ACK clock (makes SDA “H”) and receives the
ACK bit generated by the data receiving device.
b0
ACK FAST
CCR4 CCR3 CCR2 CCR1 CCR0
BIT MODE
…
✽ACK clock: Clock for acknowledgment
b7
ACK
…
The I2 C clock control register (address 002F16 ) is used to set ACK
control, SCL mode and SCL frequency.
•Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
These bits control the SCL frequency. Refer to Table 5.
•Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0,” the
standard clock mode is selected. When the bit is set to “1,” the
high-speed clock mode is selected.
When connecting the bus of the high-speed mode I 2C bus standard (maximum 400 kbits/s), use 8 MHz or more oscillation
frequency f(X IN) and 2 division clock.
•Bit 6: ACK bit (ACK BIT)
This bit sets the SDA status when an ACK clock✽ is generated.
When this bit is set to “0,” the ACK return mode is selected and
SDA goes to “L” at the occurrence of an ACK clock. When the bit
is set to “1,” the ACK non-return mode is selected. The SDA is
held in the “H” status at the occurrence of an ACK clock.
However, when the slave address agree with the address data in
the reception of address data at ACK BIT = “0,” the SDA is automatically made “L” (ACK is returned). If there is a disagreement
between the slave address and the address data, the SDA is automatically made “H” (ACK is not returned).
…
[I2C Clock Control Register (S2)] 002F16
500/CCR value
(Note 3)
1
1
1
0
1
17.2
1000/CCR value
(Note 3)
34.5
1
1
1
1
0
16.6
33.3
1
1
1
1
1
16.1
32.3
Notes 1: Duty of SCL clock output is 50 %. The duty becomes 35 to 45 %
only when the high-speed clock mode is selected and CCR value
= 5 (400 kHz, at φ = 4 MHz). “H” duration of the clock fluctuates
from –4 to +2 machine cycles in the standard clock mode, and
fluctuates from –2 to +2 machine cycles in the high-speed clock
mode. In the case of negative fluctuation, the frequency does not
increase because “L” duration is extended instead of “H” duration
reduction.
These are value when S CL clock synchronization by the synchronous function is not performed. CCR value is the decimal
notation value of the S CL frequency control bits CCR4 to CCR0.
2: Each value of S CL frequency exceeds the limit at φ = 4 MHz or
more. When using these setting value, use φ of 4 MHz or less.
3: The data formula of S CL frequency is described below:
φ/(8 ✕ CCR value) Standard clock mode
φ/(4 ✕ CCR value) High-speed clock mode (CCR value ≠ 5)
φ/(2 ✕ CCR value) High-speed clock mode (CCR value = 5)
Do not set 0 to 2 as CCR value regardless of φ frequency.
Set 100 kHz (max.) in the standard clock mode and 400 kHz
(max.) in the high-speed clock mode to the SCL frequency by setting the SCL frequency control bits CCR4 to CCR0.
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HARDWARE
FUNCTIONAL DESCRIPTION
[I2C Control Register (S1D)] 002E16
The I2C control register (address 002E 16) controls data communication format.
•Bits 0 to 2: Bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be
transmitted. The I 2C interrupt request signal occurs immediately
after the number of count specified with these bits (ACK clock is
added to the number of count when ACK clock is selected by ACK
clock bit (bit 7 of address 002F16)) have been transferred, and
BC0 to BC2 are returned to “0002”.
Also when a START condition is received, these bits become
“0002 ” and the address data is always transmitted and received in
8 bits.
•Bit 3: I2C interface enable bit (ES0)
This bit enables to use the multi-master I2C-BUS interface. When
this bit is set to “0,” the use disable status is provided, so that the
SDA and the SCL become high-impedance. When the bit is set to
“1,” use of the interface is enabled.
When ES0 = “0,” the following is performed.
• PIN = “1,” BB = “0” and AL = “0” are set (which are bits of the I2C
status register at address 002D 16 ).
• Writing data to the I2C data shift register (address 002B16) is disabled.
•Bit 4: Data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses.
When this bit is set to “0,” the addressing format is selected, so
that address data is recognized. When a match is found between a
slave address and address data as a result of comparison or when
a general call (refer to “I 2C Status Register,” bit 1) is received,
transfer processing can be performed. When this bit is set to “1,”
the free data format is selected, so that slave addresses are not
recognized.
•Bit 5: Addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit
is set to “0,” the 7-bit addressing format is selected. In this case,
only the high-order 7 bits (slave address) of the I2 C address register (address 002C16 ) are compared with address data. When this
bit is set to “1,” the 10-bit addressing format is selected, and all
the bits of the I2C address register are compared with address
data.
•Bit 6: SDA/SCL pin selection bit
This bit selects the input/output pins of SCL and SDA of the multimaster I2C-BUS interface.
•Bit 7: I2C-BUS interface pin input level selection bit
This bit selects the input level of the SCL and SDA pins of the
multi-master I2C-BUS interface.
TSEL
SCL1/P23
SCL
SCL2/TxD/P25
Multi-master
I2C-BUS interface
TSEL
TSEL
SDA1/P22
SDA
SDA2/RxD/P24
TSEL
Fig. 25 SDA/SCL pin selection bit
b7
TISS TSEL
b0
10 BIT
SAD
I2C control register
ALS ES0 BC2 BC1 BC0
(S1D : address 002E 16)
Bit counter (Number of
transmit/receive bits)
b2 b1 b0
0 0 0 : 8
0 0 1 : 7
0 1 0 : 6
0 1 1 : 5
1 0 0 : 4
1 0 1 : 3
1 1 0 : 2
1 1 1 : 1
I2C-BUS interface
enable bit
0 : Disabled
1 : Enabled
Data format selection bit
0 : Addressing format
1 : Free data format
Addressing format
selection bit
0 : 7-bit addressing
format
1 : 10-bit addressing
format
SDA/SCL pin selection bit
0 : Connect to ports P2 2, P23
1 : Connect to ports P2 4, P25
I2C-BUS interface pin input
level selection bit
0 : CMOS input
1 : SMBUS input
Fig. 26 Structure of I2C control register
1-28
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HARDWARE
FUNCTIONAL DESCRIPTION
[I2C Status Register (S1)] 002D16
The I 2C status register (address 002D 16) controls the I 2C-BUS interface status. The low-order 4 bits are read-only bits and the
high-order 4 bits can be read out and written to.
Set “0000 2” to the low-order 4 bits, because these bits become the
reserved bits at writing.
•Bit 0: Last receive bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an
ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned,
this bit is set to “1.” Except in the ACK mode, the last bit value of
received data is input. The state of this bit is changed from “1” to
“0” by executing a write instruction to the I 2C data shift register
(address 002B 16).
•Bit 1: General call detecting flag (AD0)
When the ALS bit is “0”, this bit is set to “1” when a general call✽
whose address data is all “0” is received in the slave mode. By a
general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to “0” by
detecting the STOP condition or START condition, or reset.
✽General call: The master transmits the general call address “0016” to all
slaves.
•Bit 2: Slave address comparison flag (AAS)
This flag indicates a comparison result of address data when the
ALS bit is “0”.
➀ In the slave receive mode, when the 7-bit addressing format is
selected, this bit is set to “1” in one of the following conditions:
• The address data immediately after occurrence of a START
condition agrees with the slave address stored in the high-order 7 bits of the I2C address register (address 002C16 ).
• A general call is received.
➁ In the slave receive mode, when the 10-bit addressing format is
selected, this bit is set to “1” with the following condition:
• When the address data is compared with the I2 C address register (8 bits consisting of slave address and RBW bit), the first
bytes agree.
➂ This bit is set to “0” by executing a write instruction to the I 2C
data shift register (address 002B16 ) when ES0 is set to “1” or
reset.
•Bit 3: Arbitration lost✽ detecting flag (AL)
In the master transmission mode, when the SDA is made “L” by
any other device, arbitration is judged to have been lost, so that
this bit is set to “1.” At the same time, the TRX bit is set to “0,” so
that immediately after transmission of the byte whose arbitration
was lost is completed, the MST bit is set to “0.” The arbitration lost
can be detected only in the master transmission mode. When arbitration is lost during slave address transmission, the TRX bit is
set to “0” and the reception mode is set. Consequently, it becomes
possible to detect the agreement of its own slave address and address data transmitted by another master device.
•Bit 4: SCL pin low hold bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte
data is transmitted, the PIN bit changes from “1” to “0.” At the
same time, an interrupt request signal occurs to the CPU. The PIN
bit is set to “0” in synchronization with a falling of the last clock (including the ACK clock) of an internal clock and an interrupt
request signal occurs in synchronization with a falling of the PIN
bit. When the PIN bit is “0,” the SCL is kept in the “0” state and
clock generation is disabled. Figure 25 shows an interrupt request
signal generating timing chart.
The PIN bit is set to “1” in one of the following conditions:
• Executing a write instruction to the I2C data shift register (address 002B16 ). (This is the only condition which the prohibition of
the internal clock is released and data can be communicated except for the start condition detection.)
• When the ES0 bit is “0”
• At reset
• When writing “1” to the PIN bit by software
The conditions in which the PIN bit is set to “0” are shown below:
• Immediately after completion of 1-byte data transmission (including when arbitration lost is detected)
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately after completion of slave address agreement or general call
address reception
• In the slave reception mode, with ALS = “1” and immediately after completion of address data reception
•Bit 5: Bus busy flag (BB)
This bit indicates the status of use of the bus system. When this bit
is set to “0,” this bus system is not busy and a START condition
can be generated. The BB flag is set/reset by the SCL, SDA pins
input signal regardless of master/slave. This flag is set to “1” by
detecting the start condition, and is set to “0” by detecting the stop
condition. The condition of these detecting is set by the start/stop
condition setting bits (SSC4–SSC0) of the I 2C start/stop condition
control register (address 003016). When the ES0 bit of the I2 C
control register (address 002E16) is “0” or reset, the BB flag is set
to “0.”
For the writing function to the BB flag, refer to the sections
“START Condition Generating Method” and “STOP Condition Generating Method” described later.
✽Arbitration lost :The status in which communication as a master is disabled.
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HARDWARE
FUNCTIONAL DESCRIPTION
•Bit 6: Communication mode specification bit (transfer direction specification bit: TRX)
This bit decides a direction of transfer for data communication.
When this bit is “0,” the reception mode is selected and the data of
a transmitting device is received. When the bit is “1,” the transmission mode is selected and address data and control data are
output onto the SDA in synchronization with the clock generated
on the SCL.
This bit is set/reset by software and hardware. About set/reset by
hardware is described below. This bit is set to “1” by hardware
when all the following conditions are satisfied:
• When ALS is “0”
• In the slave reception mode or the slave transmission mode
• When the R/W bit reception is “1”
This bit is set to “0” in one of the following conditions:
• When arbitration lost is detected.
• When a STOP condition is detected.
• When writing “1” to this bit by software is invalid by the START
condition duplication preventing function (Note).
• With MST = “0” and when a START condition is detected.
• With MST = “0” and when ACK non-return is detected.
• At reset
•Bit 7: Communication mode specification bit (master/slave
specification bit: MST)
This bit is used for master/slave specification for data communication. When this bit is “0,” the slave is specified, so that a START
condition and a STOP condition generated by the master are received, and data communication is performed in synchronization
with the clock generated by the master. When this bit is “1,” the
master is specified and a START condition and a STOP condition
are generated. Additionally, the clocks required for data communication are generated on the SCL.
This bit is set to “0” in one of the following conditions.
• Immediately after completion of 1-byte data transfer when arbitration lost is detected
• When a STOP condition is detected.
• Writing “1” to this bit by software is invalid by the START condition duplication preventing function (Note).
• At reset
Note: START condition duplication preventing function
The MST, TRX, and BB bits is set to “1” at the same time after confirming that the BB flag is “0” in the procedure of a START condition
occurrence. However, when a START condition by another master
device occurs and the BB flag is set to “1” immediately after the contents of the BB flag is confirmed, the START condition duplication
preventing function makes the writing to the MST and TRX bits invalid. The duplication preventing function becomes valid from the
rising of the BB flag to reception completion of slave address.
b7
b0
MST TRX BB PIN AL AAS AD0 LRB
I2C status register
(S1 : address 002D 16)
Last receive bit (Note)
0 : Last bit = “0”
1 : Last bit = “1”
General call detecting flag
(Note)
0 : No general call detected
1 : General call detected
Slave address comparison flag
(Note)
0 : Address disagreement
1 : Address agreement
Arbitration lost detecting flag
(Note)
0 : Not detected
1 : Detected
SCL pin low hold bit
0 : SCL pin low hold
1 : SCL pin low release
Bus busy flag
0 : Bus free
1 : Bus busy
Communication mode
specification bits
00 : Slave receive mode
01 : Slave transmit mode
10 : Master receive mode
11 : Master transmit mode
Note: These bits and flags can be read out, but cannot
be written.
Write “0” to these bits at writing.
Fig. 27 Structure of I2C status register
SCL
PIN
IICIRQ
Fig. 28 Interrupt request signal generating timing
1-30
3850/3851 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
START Condition Generating Method
START/STOP Condition Detecting Operation
When writing “1” to the MST, TRX, and BB bits of the I2 C status
register (address 002D16 ) at the same time after writing the slave
address to the I2 C data shift register (address 002B16) with the
condition in which the ES0 bit of the I 2C control register (address
002E 16) is “1” and the BB flag is “0”, a START condition occurs.
After that, the bit counter becomes “000 2” and an S CL for 1 byte is
output. The START condition generating timing is different in the
standard clock mode and the high-speed clock mode. Refer to
Figure 26, the START condition generating timing diagram, and
Table 6, the START condition generating timing table.
The START/STOP condition detection operations are shown in
Figures 28, 29, and Table 8. The START/STOP condition is set by
the START/STOP condition set bit.
The START/STOP condition can be detected only when the input
signal of the S CL and SDA pins satisfy three conditions: S CL release time, setup time, and hold time (see Table 8).
The BB flag is set to “1” by detecting the START condition and is
reset to “0” by detecting the STOP condition.
The BB flag set/reset timing is different in the standard clock mode
and the high-speed clock mode. Refer to Table 8, the BB flag set/
reset time.
Note: When a STOP condition is detected in the slave mode (MST = 0), an
interrupt request signal “IICIRQ” occurs to the CPU.
I2C status register
write signal
SCL
SDA
Setup
time
SCL release time
Hold time
SCL
SDA
Fig. 29 START condition generating timing diagram
Table 8 START condition generating timing table
Item
Standard clock mode High-speed clock mode
Setup time
5.0 µs (20 cycles)
2.5 µs (10 cycles)
Hold time
5.0 µs (20 cycles)
2.5 µs (10 cycles)
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the
number of φ cycles.
STOP Condition Generating Method
When the ES0 bit of the I 2C control register (address 002E 16 ) is
“1,” write “1” to the MST and TRX bits, and write “0” to the BB bit
of the I2 C status register (address 002D16) simultaneously. Then a
STOP condition occurs. The STOP condition generating timing is
different in the standard clock mode and the high-speed clock
mode. Refer to Figure 27, the STOP condition generating timing
diagram, and Table 7, the STOP condition generating timing table.
SCL
Fig. 31 START/STOP condition detecting timing diagram
SCL release time
SCL
SDA
BB flag
SDA
Setup
time
Hold time
BB flag
reset
time
Fig. 32 STOP condition detecting timing diagram
Table 10 START condition/STOP condition detecting conditions
Standard clock mode
High-speed clock mode
S CL release time SCC value + 1 cycle (6.25 µs)
4 cycles (1.0 µs)
Setup time
BB flag set/
reset time
Setup
time
Hold time
BB flag
reset
time
BB flag
Hold time
I2C status register
write signal
Setup
time
SCC value + 1 cycle < 4.0 µs (3.125 µs)
2 cycles (1.0 µs)
2
SCC value + 1 cycle < 4.0 µs (3.125 µs) 2 cycles (0.5 µs)
2
SCC value –1 + 2 cycles (3.375 µs) 3.5 cycles (0.875 µs)
2
Note: Unit : Cycle number of system clock φ
SSC value is the decimal notation value of the START/STOP condition set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC
value. The value in parentheses is an example when the I2C START/
STOP condition control register is set to “1816” at φ = 4 MHz.
Hold time
Fig. 30 STOP condition generating timing diagram
Table 9 STOP condition generating timing table
Standard clock mode
High-speed clock mode
Item
5.0 µs (20 cycles)
3.0 µs (12 cycles)
Setup time
4.5 µs (18 cycles)
2.5 µs (10 cycles)
Hold time
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the
number of φ cycles.
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1-31
HARDWARE
FUNCTIONAL DESCRIPTION
[I2C START/STOP Condition Control Register
(S2D)] 003016
The I2 C START/STOP condition control register (address 003016 )
controls START/STOP condition detection.
•Bits 0 to 4: START/STOP condition set bit (SSC4–SSC0)
SCL release time, setup time, and hold time change the detection
condition by value of the main clock divide ratio selection bit and
the oscillation frequency f(XIN) because these time are measured
by the internal system clock. Accordingly, set the proper value to
the START/STOP condition set bits (SSC4 to SSC0) in considered
of the system clock frequency. Refer to Table 8.
Do not set “000002” or an odd number to the START/STOP condition set bit (SSC4 to SSC0).
Refer to Table 9, the recommended set value to START/STOP
condition set bits (SSC4–SSC0) for each oscillation frequency.
•Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP)
An interrupt can occur when detecting the falling or rising edge of
the SCL or SDA pin. This bit selects the polarity of the SCL or
SDA pin interrupt pin.
•Bit 6: SCL/SDA interrupt pin selection bit (SIS)
This bit selects the pin of which interrupt becomes valid between
the SCL pin and the SDA pin.
Note: When changing the setting of the SCL /SDA interrupt pin polarity selection bit, the S CL/SDA interrupt pin selection bit, or the I 2 C-BUS
interface enable bit ES0, the SCL/SDA interrupt request bit may be
set. When selecting the SCL /S DA interrupt source, disable the interrupt before the S CL /S DA interrupt pin polarity selection bit, the SCL /
S DA interrupt pin selection bit, or the I2 C-BUS interface enable bit
ES0 is set. Reset the request bit to “0” after setting these bits, and
enable the interrupt.
1-32
Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective
address communication formats are described below.
➀ 7-bit addressing format
To adapt the 7-bit addressing format, set the 10BIT SAD bit of
the I 2C control register (address 002E 16) to “0.” The first 7-bit
address data transmitted from the master is compared with the
high-order 7-bit slave address stored in the I2 C address register
(address 002C16 ). At the time of this comparison, address comparison of the RWB bit of the I2 C address register (address
002C 16) is not performed. For the data transmission format
when the 7-bit addressing format is selected, refer to Figure 31,
(1) and (2).
➁ 10-bit addressing format
To adapt the 10-bit addressing format, set the 10BIT SAD bit of
the I2 C control register (address 002E16) to “1.” An address
comparison is performed between the first-byte address data
transmitted from the master and the 8-bit slave address stored
in the I2C address register (address 002C16). At the time of this
comparison, an address comparison between the RWB bit of
the I 2 C address register (address 002C16) and the R/W bit
which is the last bit of the address data transmitted from the
master is made. In the 10-bit addressing mode, the RWB bit
which is the last bit of the address data not only specifies the
direction of communication for control data, but also is processed as an address data bit.
When the first-byte address data agree with the slave address,
the AAS bit of the I2C status register (address 002D16) is set to
“1.” After the second-byte address data is stored into the I 2C
data shift register (address 002B 16), perform an address comparison between the second-byte data and the slave address
by software. When the address data of the 2 bytes agree with
the slave address, set the RBW bit of the I2C address register
(address 002C16 ) to “1” by software. This processing can make
the 7-bit slave address and R/W data agree, which are received after a RESTART condition is detected, with the value of
the I2 C address register (address 002C16). For the data transmission format when the 10-bit addressing format is selected,
refer to Figure 31, (3) and (4).
3850/3851 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
I2C START/STOP condition
control register
(S2D : address 0030 16)
SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0
START/STOP condition set bit
SCL/SDA interrupt pin polarity
selection bit
0 : Falling edge active
1 : Rising edge active
SCL/SDA interrupt pin selection bit
0 : SDA valid
1 : SCL valid
Reserved
Do not write “1” to this bit.
Fig. 33 Structure of I2C START/STOP condition control register
Table 11 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency
Oscillation
frequency
f(XIN) (MHz)
Main clock
divide ratio
System
clock φ
(MHz)
8
2
4
8
8
1
4
2
2
2
2
1
START/STOP
condition
control register
SCL release time
(µs)
Setup time
(µs)
Hold time
(µs)
XXX11010
XXX11000
XXX00100
XXX01100
XXX01010
XXX00100
6.75 µs (27 cycles)
6.25 µs (25 cycles)
5.0 µs (5 cycles)
6.5 µs (13 cycles)
5.5 µs (11 cycles)
5.0 µs (5 cycles)
3.375 µs (13.5 cycles)
3.125 µs (12.5 cycles)
2.5 µs (2.5 cycles)
3.25 µs (6.5 cycles)
2.75 µs (5.5 cycles)
2.5 µs (2.5 cycles)
3.375 µs (13.5 cycles)
3.125 µs (12.5 cycles)
2.5 µs (2.5 cycles)
3.25 µs (6.5 cycles)
2.75 µs (5.5 cycles)
2.5 µs (2.5 cycles)
Note: Do not set an odd number to the START/STOP condition set bit (SSC4 to SSC0).
S
Slave address R/W
7 bits
A
“0”
Data
A
1 to 8 bits
Data
A/A
P
A
P
1 to 8 bits
(1) A master-transmitter transnmits data to a slave-receiver
S
Slave address R/W
7 bits
A
“1”
Data
A
1 to 8 bits
Data
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
S
Slave address
R/W
1st 7 bits
7 bits
A
“0”
Slave address
2nd bytes
A
Data
1 to 8 bits
8 bits
A
Data
A/A
P
1 to 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
S
Slave address
R/W
1st 7 bits
A
Slave address
2nd bytes
A
Sr
Slave address
R/W
1st 7 bits
“1”
7 bits
“0”
8 bits
7 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W : Read/Write bit
A
Data
1 to 8 bits
A
Data
A
P
1 to 8 bits
: Master to slave
: Slave to master
Fig. 34 Address data communication format
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1-33
HARDWARE
FUNCTIONAL DESCRIPTION
Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is
shown below.
➀ Set a slave address in the high-order 7 bits of the I2 C address
register (address 002C16) and “0” into the RWB bit.
➁ Set the ACK return mode and SCL = 100 kHz by setting “85 16 ”
in the I2C clock control register (address 002F 16).
➂ Set “0016” in the I2C status register (address 002D16) so that
transmission/reception mode can become initializing condition.
➃ Set a communication enable status by setting “0816” in the I2 C
control register (address 002E16).
➄ Confirm the bus free condition by the BB flag of the I2C status
register (address 002D16 ).
➅ Set the address data of the destination of transmission in the
high-order 7 bits of the I2 C data shift register (address 002B16 )
and set “0” in the least significant bit.
➆ Set “F016 ” in the I2C status register (address 002D16) to generate a START condition. At this time, an SCL for 1 byte and an
ACK clock automatically occur.
➇ Set transmit data in the I 2C data shift register (address 002B16).
At this time, an SCL and an ACK clock automatically occur.
➈ When transmitting control data of more than 1 byte, repeat step
➇.
➉ Set “D016” in the I 2C status register (address 002D16 ) to generate a STOP condition if ACK is not retur ned from slave
reception side or transmission ends.
Example of Slave Reception
An example of slave reception in the high-speed clock mode, at
the SCL frequency of 400 kHz, in the ACK non-return mode and
using the addressing format is shown below.
➀ Set a slave address in the high-order 7 bits of the I2 C address
register (address 002C16 ) and “0” in the RWB bit.
➁ Set the no ACK clock mode and SCL = 400 kHz by setting
“6516 ” in the I2C clock control register (address 002F 16).
➂ Set “0016” in the I2C status register (address 002D16) so that
transmission/reception mode can become initializing condition.
➃ Set a communication enable status by setting “0816” in the I2 C
control register (address 002E16).
➄ When a START condition is received, an address comparison is
performed.
➅ •When all transmitted addresses are “0” (general call):
AD0 of the I 2C status register (address 002D 16) is set to “1”
and an interrupt request signal occurs.
• When the transmitted addresses agree with the address set
in ➀:
ASS of the I 2C status register (address 002D16) is set to “1”
and an interrupt request signal occurs.
• In the cases other than the above AD0 and AAS of the I2C status register (address 002D 16) are set to “0” and no interrupt
request signal occurs.
➆ Set dummy data in the I2C data shift register (address 002B16).
➇ When receiving control data of more than 1 byte, repeat step ➆.
➈ When a STOP condition is detected, the communication ends.
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3850/3851 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
■Precautions when using multi-master I2C-BUS
interface
(1) Read-modify-write instruction
The precautions when the read-modify-write instruction such as
SEB, CLB etc. is executed for each register of the multi-master
I 2C-BUS interface are described below.
• I2 C data shift register (S0: address 002B16 )
When executing the read-modify-write instruction for this register during transfer, data may become a value not intended.
• I2 C address register (S0D: address 002C16)
When the read-modify-write instruction is executed for this register at detecting the STOP condition, data may become a value
not intended. It is because H/W changes the read/write bit
(RBW) at the above timing.
• I2 C status register (S1: address 002D16 )
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by H/W.
• I2 C control register (S1D: address 002E16)
When the read-modify-write instruction is executed for this register at detecting the START condition or at completing the byte
transfer, data may become a value not intended. Because H/W
changes the bit counter (BC0-BC2) at the above timing.
• I2 C clock control register (S2: address 002F16 )
The read-modify-write instruction can be executed for this register.
• I 2 C START/STOP condition control register (S2D: address
003016)
The read-modify-write instruction can be executed for this register.
(2) START condition generating procedure using multi-master
1. Procedure example (The necessary conditions of the generating procedure are described as the following 2 to 5.
::
LDA —
(Taking out of slave address value)
SEI
(Interrupt disabled)
BBS 5, S1, BUSBUSY (BB flag confirming and branch process)
BUSFREE:
STA S0
(Writing of slave address value)
LDM #$F0, S1
(Trigger of START condition generating)
CLI
(Interrupt enabled)
::
BUSBUSY:
CLI
(Interrupt enabled)
::
5. Disable interrupts during the following three process steps:
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts
immediately.
(3) RESTART condition generating procedure
1. Procedure example (The necessary conditions of the generating procedure are described as the following 2 to 4.)
Execute the following procedure when the PIN bit is “0.”
::
LDM #$00, S1
(Select slave receive mode)
LDA —
(Taking out of slave address value)
SEI
(Interrupt disabled)
STA S0
(Writing of slave address value)
LDM #$F0, S1
(Trigger of RESTART condition generating)
CLI
(Interrupt enabled)
::
2. Select the slave receive mode when the PIN bit is “0.” Do not
write “1” to the PIN bit. Neither “0” nor “1” is specified for the
writing to the BB bit.
The TRX bit becomes “0” and the SDA pin is released.
3. The SCL pin is released by writing the slave address value to
the I2C data shift register.
4. Disable interrupts during the following two process steps:
• Writing of slave address value
• Trigger of RESTART condition generating
(4) Writing to I 2C status register
Do not execute an instruction to set the PIN bit to “1” from “0” and
an instruction to set the MST and TRX bits to “0” from “1” simultaneously. It is because it may enter the state that the S CL pin is
released and the SDA pin is released after about one machine
cycle. Do not execute an instruction to set the MST and TRX bits
to “0” from “1” simultaneously when the PIN bit is “1.” It is because
it may become the same as above.
(5) Process of after STOP condition generating
Do not write data in the I2C data shift register S0 and the I2C status register S1 until the bus busy flag BB becomes “0” after
generating the STOP condition in the master mode. It is because
the STOP condition waveform might not be normally generated.
Reading to the above registers do not have the problem.
2. Use “Branch on Bit Set” of “BBS 5, $002D, –” for the BB flag
confirming and branch process.
3. Use “STA $2B, STX $2B” or “STY $2B” of the zero page addressing instruction for writing the slave address value to the
I 2C data shift register.
4. Execute the branch instruction of above 2 and the store instruction of above 3 continuously shown the above procedure
example.
3850/3851 Group User’s Manual
1-35
HARDWARE
FUNCTIONAL DESCRIPTION
PULSE WIDTH MODULATION (PWM)
The 3851 group has a PWM function with an 8-bit resolution,
based on a signal that is the clock input XIN or that clock input divided by 2.
Data Setting
The PWM output pin also functions as port P44 . Set the PWM period by the PWM prescaler, and set the “H” term of output pulse by
the PWM register.
If the value in the PWM prescaler is n and the value in the PWM
register is m (where n = 0 to 255 and m = 0 to 255) :
PWM period = 255 ✕ (n+1) / f(XIN)
= 31.875 ✕ (n+1) µs
(when f(XIN) = 8 MHz, count source is f(XIN))
Output pulse “H” term = PWM period ✕ m / 255
= 0.125 ✕ (n+1) ✕ m µs
(when f(XIN) = 8 MHz, count source is f(XIN))
PWM Operation
When bit 0 (PWM enable bit) of the PWM control register is set to
“1”, operation starts by initializing the PWM output circuit, and
pulses are output starting at an “H”.
If the PWM register or PWM prescaler is updated during PWM
output, the pulses will change in the cycle after the one in which
the change was made.
31.875 ✕ m ✕ (n+1)
µs
255
PWM output
T = [31.875 ✕ (n+1)] µs
m: Contents of PWM register
n : Contents of PWM prescaler
T : PWM period (when f(X IN) = 8 MHz, count source
is f(XIN))
Fig. 35 Timing of PWM period
Data bus
PWM
prescaler pre-latch
PWM
register pre-latch
Transfer control circuit
PWM
prescaler latch
PWM
register latch
PWM prescaler
PWM register
Count source
selection bit
“0”
XIN
1/2
Port P44
“1”
Port P44 latch
PWM enable bit
Fig. 36 Block diagram of PWM function
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3850/3851 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
PWM control register
(PWMCON : address 001D 16)
PWM function enable bit
0: PWM disabled
1: PWM enabled
Count source selection bit
0: f(XIN)
1: f(XIN)/2
Not used (return “0” when read)
Fig. 37 Structure of PWM control register
A
B
B = C
T2
T
C
PWM output
T
PWM register
write signal
PWM prescaler
write signal
T
T2
(Changes “H” term from “A” to “B”.)
(Changes PWM period from “T” to “T2”.)
When the contents of the PWM register or PWM prescaler have changed, the PWM
output will change from the next period after the change.
Fig. 38 PWM output timing when PWM register or PWM prescaler is changed
■Note
The PWM starts after the PWM enable bit is set to enable and “L” level is output from the PWM pin.
The length of this “L“ level output is as follows:
n+1
2 • f(XIN)
sec
(Count source selection bit = 0, where n is the value set in the prescaler)
n+1
f(XIN)
sec
(Count source selection bit = 1, where n is the value set in the prescaler)
3850/3851 Group User’s Manual
1-37
HARDWARE
FUNCTIONAL DESCRIPTION
A-D CONVERTER
[A-D Conversion Registers (ADL, ADH)]
003516, 003616
b7
b0
AD control register
(ADCON : address 0034 16)
The A-D conversion registers are read-only registers that store the
result of an A-D conversion. Do not read these registers during an
A-D conversion
Analog input pin selection bits
b2 b1 b0
0
0
0
0
1
[AD Control Register (ADCON)] 003416
The AD control register controls the A-D conversion process. Bits
0 to 2 select a specific analog input pin. Bit 4 indicates the
completion of an A-D conversion. The value of this bit remains at
“0” during an A-D conversion and changes to “1” when an A-D
conversion ends. Writing “0” to this bit starts the A-D conversion.
0
0
1
1
0
0: P30/AN0
1: P31/AN1
0: P32/AN2
1: P33/AN3
0: P34/AN4
Not used (returns “0” when read)
A-D conversion completion bit
0: Conversion in progress
1: Conversion completed
Not used (returns “0” when read)
Comparison Voltage Generator
Fig. 39 Structure of AD control register
The comparison voltage generator divides the voltage between
AVSS and VREF into 1024 and outputs the divided voltages.
Channel Selector
10-bit reading
(Read address 003616 before 003516)
The channel selector selects one of ports P30/AN0 to P34/AN4 and
inputs the voltage to the comparator.
b7
b0
b9 b8
b7
b0
(Address 003616)
Comparator and Control Circuit
The comparator and control circuit compare an analog input voltage with the comparison voltage, and the result is stored in the
A-D conversion registers. When an A-D conversion is completed,
the control circuit sets the A-D conversion completion bit and the
A-D interrupt request bit to “1”.
Note that because the comparator consists of a capacitor coupling, set f(XIN) to 500 kHz or more during an A-D conversion.
The M38514E6/M6 can operate at even low-speed mode, because of the A-D converter of the M38514E6/M6 has a built-in
self-oscillation circuit.
(Address 003516) b7 b6 b5 b4 b3 b2 b1 b0
Note : The high-order 6 bits of address 0036 16 become “0”
at reading.
8-bit reading (Read only address 003516)
b7
b0
(Address 003516) b9 b8 b7 b6 b5 b4 b3 b2
Fig. 40 Structure of A-D conversion registers
Data bus
AD control register
(Address 0034 16)
b7
b0
3
A-D conversion interrupt request
A-D control circuit
Channel selector
P30/AN0
P31/AN 1
P32/AN 2
P33/AN 3
P34/AN 4
Comparator
A-D conversion high-order register (Address 0036 16)
A-D conversion low-order register (Address 0035 16)
10
Resistor ladder
VREF AV SS
Fig. 41 Block diagram of A-D converter
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3850/3851 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
WATCHDOG TIMER
●Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 003916 ) permits selecting a watchdog timer H count source. When this bit is
set to “0”, the count source becomes the underflow signal of
watchdog timer L. The detection time is set to 131.072 ms at f(XIN)
= 8 MHz frequency and 32.768 s at f(X CIN) = 32 kHz frequency.
When this bit is set to “1”, the count source becomes the signal
divided by 16 for f(XIN) (or f(XCIN)). The detection time in this case
is set to 512 µs at f(XIN) = 8 MHz frequency and 128 ms at f(X CIN)
= 32 kHz frequency. This bit is cleared to “0” after resetting.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control register (address 003916 ) after resetting, the watchdog timer is in the
stop state. The watchdog timer starts to count down by writing an
optional value into the watchdog timer control register (address
0039 16) and an internal reset occurs at an underflow of the watchdog timer H.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 0039 16) may be
started before an underflow. When the watchdog timer control register (address 003916 ) is read, the values of the high-order 6 bits
of the watchdog timer H, STP instruction disable bit, and watchdog timer H count source selection bit are read.
●Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 003916 ) permits disabling the STP instruction when the watchdog timer is in
operation.
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled, once the STP
instruction is executed, an internal reset occurs. When this bit is
set to “1”, it cannot be rewritten to “0” by program. This bit is
cleared to “0” after resetting.
●Initial value of watchdog timer
At reset or writing to the watchdog timer control register (address
0039 16), each watchdog timer H and L is set to “FF16.”
“FF16” is set when
watchdog timer
control register is
written to.
XCIN
XIN
“FF16” is set when
watchdog timer
control register is
written to.
“0”
“10”
Main clock division
ratio selection bits
(Note)
Data bus
Watchdog timer L (8)
1/16
“1”
“00”
“01”
Watchdog timer H (8)
Watchdog timer H count
source selection bit
STP instruction disable bit
STP instruction
Reset
circuit
RESET
Internal reset
Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
Fig. 42 Block diagram of Watchdog timer
b0
b7
Watchdog timer control register
(WDTCON : address 0039 16)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/16 or f(XCIN)/16
Fig. 43 Structure of Watchdog timer control register
3850/3851 Group User’s Manual
1-39
HARDWARE
FUNCTIONAL DESCRIPTION
RESET CIRCUIT
Poweron
To reset the microcomputer, RESET pin must be held at an "L"
level for 2 µs or more. Then the RESET pin is returned to an "H"
level (the power source voltage must be between 2.7 V and 5.5 V,
and the oscillation must be stable), reset is released. After the reset is completed, the program starts from the address contained in
address FFFD16 (high-order byte) and address FFFC 16 (low-order
byte). Make sure that the reset input voltage is less than 0.54 V for
VCC of 2.7 V.
RESET
Power source
voltage
0V
VCC
Reset input
voltage
0V
(Note)
0.2VCC
Note : Reset release voltage ; Vcc=2.7 V
RESET
VCC
Power source
voltage detection
circuit
Fig. 44 Reset circuit example
XIN
φ
RESET
RESETOUT
?
?
Address
?
?
FFFC
FFFD
ADH,L
Reset address from the vector table.
?
Data
?
?
?
ADL
ADH
SYNC
XIN: 8 to 13 clock cycles
Notes 1: The frequency relation of f(X IN) and f(φ) is f(XIN) = 2 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
3: All signals except X IN and RESET are internals.
Fig. 45 Reset sequence
1-40
3850/3851 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Address Register contents
(1)
Port P0 direction register (P0D)
000116
0016
(2)
Port P1 direction register (P1D)
000316
0016
(3)
Port P2 direction register (P2D)
000516
0016
(4)
Port P3 direction register (P3D)
000716
0016
(5)
Port P4 direction register (P4D)
000916
0016
(6)
Serial I/O status register (SIOSTS)
001916 1 0 0 0 0 0 0 0
(7)
Serial I/O control register (SIOCON)
001A16
(8)
UART control register (UARTCON)
001B16 1 1 1 0 0 0 0 0
(9)
PWM control register (PWMCON)
001D16
0016
(10) Prescaler 12 (PRE12)
002016
FF16
(11) Timer 1 (T1)
002116
0116
(12) Timer 2 (T2)
002216
0016
(13) Timer XY mode register (TM)
002316
0016
(14) Prescaler X (PREX)
002416
FF16
(15) Timer X (TX)
002516
FF16
(16) Prescaler Y (PREY)
002616
FF16
(17) Timer Y (TY)
002716
FF16
(18) Timer count source select register
002816
0016
(19) I2C address register (S0D)
002C16
0016
(20) I2C status register (S1)
002D16 0 0 0 1 0 0 0 X
(21) I2C control register (S1D)
002E16
0016
(22) I2C clock control register (S2)
002F16
0016
(23) I2C start/stop condition control register (S2D)
003016 0 0 0 X X X X X
(24) AD control register (ADCON)
003416 0 0 0 1 0 0 0 0
(25) MISRG
003816
(26) Watchdog timer control register (WDTCON)
003916 0 0 1 1 1 1 1 1
(27) Interrupt edge selection register (INTEDGE)
003A16
(28) CPU mode register (CPUM)
003B16 0 1 0 0 1 0 0 0
(29) Interrupt request register 1 (IREQ1)
003C16
0016
(30) Interrupt request register 2 (IREQ2)
003D16
0016
(31) Interrupt control register 1 (ICON1)
003E16
0016
(32) Interrupt control register 2 (ICON2)
003F16
0016
(33) Processor status register
(34) Program counter
Note : X indicates Not fixed .
0016
0016
0016
(PS) X X X X X 1 X X
(PCH)
FFFD16 contents
(PCL)
FFFC16 contents
Fig. 46 Internal status at reset
3850/3851 Group User’s Manual
1-41
HARDWARE
FUNCTIONAL DESCRIPTION
CLOCK GENERATING CIRCUIT
be generated.
The 3851 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (X CIN and X COUT). Use the circuit constants in accordance
with the resonator manufacturer’s recommended values. No external resistor is needed between XIN and X OUT since a feed-back
resistor exists on-chip. However, an external feed-back resistor is
needed between X CIN and XCOUT.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
Frequency Control
(1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8. After reset, this mode is selected.
(2) High-speed mode
(2) Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ restarts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after
the clock is restarted.
To ensure that the interrupts will be received to release the STP or
WIT state, their interrupt enable bits must be set to “1” before executing of the STP or WIT instruction.
When releasing the STP state, the prescaler 12 and timer 1 will
start counting the clock XIN divided by 16. Accordingly, set the
timer 1 interrupt enable bit to “0” before executing the STP instruction.
The internal clock φ is half the frequency of XIN.
■Note
(3) Low-speed mode
When using the oscillation stabilizing time set after STP instruction
released bit set to “1”, evaluate time to stabilize oscillation of the
used oscillator and set the value to the timer 1 and prescaler 12.
The internal clock φ is half the frequency of XCIN .
■Note
If you switch the mode between middle/high-speed and lowspeed, stabilize both X IN and XCIN oscillations. The sufficient time
is required for the sub-clock to stabilize, especially immediately after power on and at returning from the stop mode. When switching
the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3•f(XCIN).
XCIN
XCOUT
Rf
XIN
XOUT
Rd
(4) Low power dissipation mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set
bit 5 of the CPU mode register to “1.” When the main clock X IN is
restarted (by setting the main clock stop bit to “0”), set sufficient
time for oscillation to stabilize.
The sub-clock XCIN -XCOUT oscillating circuit can not directly input
clocks that are generated externally. Accordingly, make sure to
cause an external resonator to oscillate.
CCIN
1-42
CIN
COUT
Fig. 47 Ceramic resonator circuit
Oscillation Control
(1) Stop mode
XCIN
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillation stops. When the oscillation
stabilizing time set after STP instruction released bit is “0,” the
prescaler 12 is set to “FF16 ” and timer 1 is set to “01 16 .” When the
oscillation stabilizing time set after STP instruction released bit is
“1,” set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1.
Either XIN or XCIN divided by 16 is input to the prescaler 12 as
count source. Oscillator restarts when an external interrupt is received, but the internal clock φ is not supplied to the CPU (remains
at “H”) until timer 1 underflows. The internal clock φ is supplied for
the first time, when timer 1 underflows. This ensures time for the
clock oscillation using the ceramic resonators to be stabilized.
When the oscillator is restarted by reset, apply “L” level to the
RESET pin until the oscillation is stable since a wait time will not
CCOUT
XCOUT
Rf
XIN
XOUT
Open
Rd
External oscillation
circuit
CCIN
CCOUT
Vcc
Vss
Fig. 48 External clock input circuit
3850/3851 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
b7
Middle-speed mode automatic switch set bit
b0
By setting the middle-speed mode automatic switch set bit to “1”
while operating in the low-speed mode, XIN oscillation automatically starts and the mode is automatically switched to the
middle-speed mode when defecting a rising/falling edge of the
SCL or SDA pin. The middle-speed automatic switch wait time set
bit can select the switch timing from the low-speed to the middlespeed mode; either 4.5 to 5.5 machine cycles or 6.5 to 7.5
machine cycles in the low-speed mode. Select it according to oscillation start characteristics of used X IN oscillator.
The middle-speed mode automatic switch start bit is used to automatically make to X IN oscillation start and switch to the
middle-speed mode by setting this bit to “1” while operating in the
low-speed mode.
MISRG
(MISRG : address 0038 16)
Oscillation stabilizing time set after STP instruction
released bit
0: Automatically set “01 16 ” to Timer 1,
“FF 16 ” to Prescaler 12
1: Automatically set nothing
Middle-speed mode automatic switch set bit
0: Not set automatically
1: Automatic switching enable
Middle-speed mode automatic switch wait time set bit
0: 4.5 to 5.5 machine cycles
1: 6.5 to 7.5 machine cycles
Middle-speed mode automatic switch start bit
(Depending on program)
0: Invalid
1: Automatic switch start
Not used (return “0” when read)
Fig. 49 Structure of MISRG
XCOUT
XCIN
“0”
“1”
Port XC
switch bit
XOUT
XIN
Main clock division ratio
selection bits (Note 1)
Low-speed mode
1/2
1/4
Prescaler 12
1/2
High-speed or
middle-speed
mode
FF16
Timer 1
0116
Reset or
STP instruction
(Note 2)
Main clock division ratio
selection bits (Note 1)
Middle-speed mode
Timing φ (internal clock)
High-speed or
low-speed mode
Main clock stop bit
Q
S
R
S Q
STP instruction
WIT instruction
R
Q S
R
STP instruction
Reset
Interrupt disable flag l
Interrupt request
Notes 1: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mode is selected, set port Xc switch bit (b1) to “1”.
2: When the oscillation stabilizing time set after STP instruction released bit is “0”.
Fig. 50 System clock generating circuit block diagram (Single-chip mode)
3850/3851 Group User’s Manual
1-43
HARDWARE
FUNCTIONAL DESCRIPTION
Reset
4
CM7=0
CM6=0
CM5=0(8 MHz oscillating)
CM4=0(32 kHz stopped)
C
“0 M4
CM ”←
“1 6 →“
1”
”←
→
“0
”
”
“0
→
CM ”←
0”
“1 M6 →“
C ”←
“1
CM 6
“1”←→“0”
C
“0 M7
”
C ←
“1 M6 →“1
”←
”
→
“0
”
High-speed mode
(f(φ)=4 MHz)
CM7=0
CM6=0
CM5=0(8 MHz oscillating)
CM4=1(32 kHz oscillating)
CM 7
“1”←→“0”
CM 4
“1”←→“0”
CM7=0
CM6=1
CM5=0(8 MHz oscillating)
CM4=0(32 kHz stopped)
Middle-speed mode
(f(φ)=1 MHz)
CM7=0
CM6=1
CM5=0(8 MHz oscillating)
CM4=1(32 kHz oscillating)
High-speed mode
(f(φ)=4 MHz)
CM 6
“1”←→“0”
CM 4
“1”←→“0”
Middle-speed mode
(f(φ)=1 MHz)
Low-speed mode
(f(φ)=16 kHz)
b7
CM 5
“1”←→“0”
CM7=1
CM6=0
CM5=0(8 MHz oscillating)
CM4=1(32 kHz oscillating)
Low-speed mode
(f(φ)=16 kHz)
CM7=1
CM6=0
CM5=1(8 MHz stopped)
CM4=1(32 kHz oscillating)
b4
CPU mode register
(CPUM : address 003B 16)
CM4 : Port Xc switch bit
0 : I/O port function (stop oscillating)
1 : X CIN-XCOUT oscillating function
CM5 : Main clock (X IN- XOUT) stop bit
0 : Oscillating
1 : Stopped
CM7, CM6: Main clock division ratio selection bit
b7 b6
0 0 : φ = f(XIN)/2 ( High-speed mode)
0 1 : φ = f(XIN)/8 (Middle-speed mode)
1 0 : φ = f(XCIN)/2 (Low-speed mode)
1 1 : Not available
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is
ended.
3 : Timer operates in the wait mode.
4 : When the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 in middle/high-speed mode.
5 : When the stop mode is ended, a delay of approximately 16 ms occurs by Timer 1 and Timer 2 in low-speed mode.
6 : Wait until oscillation stabilizes after oscillating the main clock X IN before the switching from the low-speed mode to middle/high-speed
mode.
7 : The example assumes that 8 MHz is being applied to the X IN pin and 32 kHz to the X CIN pin. φ indicates the internal clock.
Fig. 51 State transitions of system clock
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3850/3851 Group User’s Manual
HARDWARE
NOTES ON PROGRAMMING
NOTES ON PROGRAMMING
Processor Status Register
A-D Converter
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” After
a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal
mode (D) flags because of their effect on calculations.
The comparator uses internal capacitors whose charge will be lost
if the clock frequency is too low.
Therefore, make sure that f(XIN) is at least on 500 kHz during an
A-D conversion.
Do not execute the STP or WIT instruction during an A-D conversion.
Interrupts
Instruction Execution Time
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt
request register, execute at least one instruction before performing
a BBC or BBS instruction.
The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The frequency of the internal clock φ is half of the XIN frequency in
high-speed mode.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.
• The execution of these instructions does not change the contents of the processor status register.
Ports
The contents of the por t direction registers cannot be read. The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a
direction register.
Use instructions such as LDM and STA, etc., to set the port direction registers.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the S RDY signal, set the transmit
enable bit, the receive enable bit, and the SRDY output enable bit
to “1.”
Serial I/O continues to output the final bit from the T XD pin after
transmission is completed.
When an external clock is used as synchronous clock in serial I/O,
write transmission data to the transmit buffer register while the
transfer clock is “H.”
3850/3851 Group User’s Manual
1-45
HARDWARE
DATA REQUIRED FOR MASK ORDERS/ROM PROGRAMMING METHOD
DATA REQUIRED FOR MASK ORDERS
ROM PROGRAMMING METHOD
The following are necessary when ordering a mask ROM production:
1.Mask ROM Order Confirmation Form
2.Mark Specification Form
3.Data to be written to ROM, in EPROM form (three identical copies)
The built-in PROM of the blank One Time PROM version and builtin EPROM version can be read or programmed with a
general-purpose PROM programmer using a special programming
adapter. Set the address of PROM programmer in the user ROM
area.
Table 12 Programming adapter
DATA R E QU I R E D F O R RO M W R I T I N G
ORDERS
The following are necessary when ordering a ROM writing:
1.ROM Writing Confirmation Form
2.Mark Specification Form
3.Data to be written to ROM, in EPROM form (three identical copies)
Package
Name of Programming Adapter
42P2R-A
PCA4738F-42A
42P4B
PCA4738S-42A
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in
Figure 52 is recommended to verify programming.
Programming with PROM
programmer
Screening (Caution)
(150 °C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
Caution : The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Fig. 52 Programming and testing of One Time PROM version
1-46
3850/3851 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
FUNCTIONAL DESCRIPTION SUPPLEMENT
Interrupt
3851 group permits interrupts on the basis of 15 sources. It is vector interrupts with a fixed priority system. Accordingly, when two or
more interrupt requests occur during the same sampling, the
higher-priority interrupt is accepted first. This priority is determined
by hardware, but variety of priority processing can be performed
by software, using an interrupt enable bit and an interrupt disable
flag.
For interrupt sources, vector addresses and interrupt priority, refer
to “Table 13”.
Table 13 Interrupt sources, vector addresses and interrupt priority
Vector addresses
Priority
Interrupt sources
Remarks
High-order Low-order
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Note
Reset (Note 1)
FFFD 16
FFFC16
INT 0 interrupt
FFFB16
FFFA16
SCL, SDA
FFF9 16
FFF8 16
INT1 interrupt
FFF7 16
FFF6 16
INT2 interrupt
FFF5 16
FFF4 16
INT3 interrupt
FFF3 16
FFF2 16
2
I C interrupt
FFF1 16
FFF0 16
Timer X interrupt
FFEF16
FFEE16
Timer Y interrupt
FFED16
FFEC16
Timer 1 interrupt
FFEB 16
FFEA16
Timer 2 interrupt
FFE916
FFE816
Serial I/O receive interrupt
FFE716
FFE616
Serial I/O transmit interrupt
FFE516
FFE416
CNTR 0 interrupt
FFE316
FFE216
CNTR 1 interrupt
FFE116
FFE016
A-D conversion interrupt
FFDF 16
FFDE16
BRK instruction interrupt
FFDD 16
FFDC 16
: Reset functions in the same way as an interrupt with
Non-maskable
External interrupt
External interrupt
External interrupt
External interrupt
External interrupt
(active
(active
(active
(active
(active
edge
edge
edge
edge
edge
selectable)
selectable)
selectable)
selectable)
selectable)
STP instruction release timer underflow
Valid when serial I/O is selected
Valid when serial I/O is selected
External interrupt (active edge selectable)
External interrupt (active edge selectable)
Non-maskable software interrupt
the highest priority.
3850/3851 Group User’s Manual
1-47
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Timing After Interrupt
The interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently in
execution.
Figure 53 shows a timing chart after an interrupt occurs, and Figure 54 shows the time up to execution of the interrupt processing
routine.
φ
SYNC
RD
WR
Address bus
Data bus
PC
S, SPS
Not used
S-1, SPS S-2, SPS
PCH PCL
BL
PS
BH
AL
AL, A H
AH
SYNC : CPU operation code fetch cycle
BL, BH : Vector address of each interrupt
AL, AH : Jump destination address of each interrupt
SPS : “0016” or “01 16”
(All signals are internals.)
Fig. 53 Timing chart after an interrupt occurs
Generation of interrupt request
Main routine
✽
0 to 16 cycles
Start of interrupt processing
Waiting time for Stack push and
post-processing Vector fetch
of pipeline
2 cycles
5 cycles
7 to 23 cycles
(At performing 8.0 MHz, in high-speed mode,
1.75 µs to 5.75 µs)
✽ : When executing the DIV instruction
Fig. 54 Time up to execution of the interrupt processing routine
1-48
3850/3851 Group User’s Manual
Interrupt processing routine
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
A-D Converter
By repeating the above operations up to the lowest-order bit of the
A-D conversion register, an analog value converts into a digital
value.
A-D conversion completes at 61 clock cycles (15.25µs at f(XIN) =
8.0 MHz) after it is started, and the result of the conversion is
stored into the A-D conversion register.
Concurrently with the completion of A-D conversion, the A-D conversion completion bit is set to “1” and an A-D conversion interrupt
request occurs, so that the AD conversion interrupt request bit is
set to “1”.
A-D conversion is started by setting AD conversion completion bit
to “0”. During A-D conversion, internal operations are performed
as follows.
1. After the start of A-D conversion, A-D conversion register
goes to “0016”.
2. The highest-order bit of A-D conversion register is set to
“1”. and the comparison voltage Vref is input to the
comparator. Then, Vref is compared with analog input voltage
VIN.
3. As a result of comparison, when Vref < VIN, the highestorder bit of A-D conversion register be- comes “1.” When
Vref > VIN, the highest-order bit becomes “0.”
Relative formula for a reference voltage VREF of A-D converter and Vref
When n = 0
Vref = 0
Vref = V REF ✕ n
1024
n : the value of A-D converter (decimal numeral)
When n = 1 to 1023
Table 14 Change of A-D conversion register during A-D conversion
Change of A-D conversion register
Value of comparison voltage (Vref)
At start of conversion
0
0
0
0
0
0
0
0
0
0
First comparison
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Second comparison
Third comparison
✽
✽
1
1
✽
2
••
•
After completion of
tenth comparison
0
VREF
2
V REF
2
V REF
2
±
±
V REF
4
V REF
4
••
•
1
✽
2
✽
3
✽
4
✽
5
V REF
8
••
•
A result of A-D conversion
✽
±
✽
6
✽
7
✽
8
✽
9
✽
10
V REF
2
±
V REF
4
± •••
±
V REF
1024
✽1–✽10: A result of the first to tenth comparison
3850/3851 Group User’s Manual
1-49
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Figure 55 shows A-D conversion equivalent circuit, and Figure 56
shows A-D conversion timing chart.
VCC
VSS
VCC AVSS
Approximately 2 K Ω
VIN
AN0
AN1
AN2
AN3
AN4
Sampling
clock
C
Chopper amplifier
A-D conversion high-order register
b4
b2 b1 b0
A-D control register
A-D conversion low-order register
Vref
VREF
Built-in
D-A converter
Reference
clock
AV SS
A-D converter interrupt
request
Fig. 55 A-D conversion equivalent circuit
φ
Write signal for A-D control register
61 cycles
AD conversion completion bit
Sampling clock
Fig. 56 A-D conversion timing chart
1-50
3850/3851 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
MISRG
(1) Oscillation stabilizing time set after STP
instruction released bit (bit 0 of address
0038 16)
Usually, when the MCU stops the clock oscillation by the STP instruction and the STP instruction has been released by an
external interrupt source, the fixed values of Timer 1 and
Prescaler 12 (Timer 1 = 01 16, Prescaler 12 = FF16 ) are automatically reloaded in order for the oscillation to stabilize. The user can
inhibit the automatic setting by writing “1” to bit 0 of MISRG (address 003816 ).
However, by setting this bit to “1”, the previous values, set just before the STP instruction was executed, will remain in Timer 1 and
Prescaler 12. Therefore, you will need to set an appropriate value
to each register, in accordance with the oscillation stabilizing time,
before executing the STP instruction.
Figure 57 shows the structure of MISRG.
(2) Middle-speed mode automatic switch
function
In order to switch the clock mode of an MCU which has a
subclock, the following procedure is necessary:
set CPU mode register (003B 16) --> start main clock oscillation -->
wait for oscillation stabilization --> switch to middle-speed mode
(or high-speed mode).
However, the 3851 group has the built-in function which automatically switches from low to middle-speed mode either by the SCL/
SDA interrupt or by program.
Figure 58 shows the structure of the I 2C start/stop condition control register.
• Middle-speed mode automatic switch by SCL/SDA Interrupt
The SCL/SDA interrupt source enables an automatic switch
when the middle-speed mode automatic switch set bit (bit 1) of
MISRG (address 003816) is set to “1”. The conditions for an automatic switch execution depend on the settings of bits 5 and 6
of the I2C start/stop condition control register (address 003016 ).
Bit 5 is the SCL/SDA interrupt pin polarity selection bit and bit 6
is the SCL/SDA interrupt pin selection bit. The main clock oscillation stabilizing time can also be selected by middle-speed
mode automatic switch wait time set bit (bit 2) of the MISRG.
• Middle-speed mode automatic switch by program
The middle-speed mode can also be automatically switched by
program while operating in low-speed mode. By setting the
middle-speed automatic switch start bit (bit 3) of MISRG (address 003816) to “1” while operating in low-speed mode, the
MCU will automatically switch to middle-speed mode. In this
case, the oscillation stabilizing time of the main clock can be selected by the middle-speed automatic switch wait set bit (bit 2)
of MISRG (address 003816 ).
3850/3851 Group User’s Manual
1-51
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
MISRG
b7 b6 b5 b4 b3 b2 b1 b0
MISRG [Address : 38 16 ]
B
Function
At reset
0 : Set automatically
(Note 1)
1 : Not set automatically
0
Name
0 Oscillation stabilization time
set bit after release of the
STP instruction
1 Middle-speed mode automatic 0 : Not set automatically
switch set bit
Middle-speed mode automatic
2 switch wait time set bit
Middle-speed mode automatic
switch start bit
(Depending on program)
3
R W
0
1 : Automatic switching enable
(Notes 2, 3)
0 : 4.5 to 5.5 machine cycles
1 : 6.5 to 7.5 machine cycles
0
0
0 : Invalid
1 : Automatic switch start
(Note 3)
4 Nothing is allocated for these bits. These are write disabled bits.
0
✕
5
0
✕
6
0
✕
7
0
✕
When these bits are read out, the values are “0”.
Notes 1: Automatically set “01 16” to timer 1, and “FF 16” to priscaler 12.
2: During operation in low-speed mode, it is possible automatically to switch to
middle-speed mode owing to S CL/SDA interrupt.
3: When automatic switch to middle-speed mode from low-speed mode
occurs, the values of CPU mode register (3B 16) change.
Fig. 57 Structure of MISRG
I2C START/STOP condition control register
b7 b6 b5 b4 b3 b2 b1 b0
I2C START/STOP condition control register (S2D) [Address : 30
B
Function
Name
0 START/STOP condition set bit
(SSC0, SSC1, SSC2, SSC3,
SSC4)
(Note)
SCL release time
= φ(µs) ✕ (SSC+1)
1
Set up time
= φ(µs) ✕ (SSC+1)/2
2
16]
At reset
?
Hold time
= φ(µs) ✕ (SSC+1)/2
3
4
0 : Falling edge active
1 : Rising edge active
selection bit (SIP)
6 SCL/SDA interrupt pin select on 0 : SDA valid
1 : SCL valid
bit (SIS)
5 SCL/SDA interrupt pin polarity
7 Fix this bit to “0”.
Note : Fix SSC0 bit to “0”.
Fig. 58 Structure of I 2C START/STOP condition control register
1-52
3850/3851 Group User’s Manual
0
0
0
R W
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
3850 group
Differences between 3850 and 3851 groups
3850 group MCUs do not have the built-in I 2C-bus as in the 3851
group. Accordingly, the 3850 group does not have registers
relevent to I2C-bus interface for the SFR area. The structure of the
interrupt control registers also differs. The following is a list of registers which are not included in the 3850 Group.
(1) I2C data shift register (address 002B16 )
(2) I2C address register (address 002C 16)
(3) I2C status register (address 002D16 )
(4) I2C control register (address 002E 16)
Fix ES0 bit (bit3) to “0”.
(5) I2C clock control register (address 002F16 )
(6) I2C START/STOP condition control register
(address 003016 )
(7) SCL/SDA interrupt request bit (bit1) of Interrupt
request register 1 (address 003C16 )
(8) I2C interrupt request bit (bit5) of Interrupt request
register 1 (address 003C16)
(9) SCL/SDA interrupt enable bit (bit1) of Interrupt control
register 1 (address 003E16 )
Fix this bit to “0”.
(10) I2C interrupt enable bit (bit5) of Interrupt control
register 1 (address 003E16 )
Fix this bit to “0”.
ROM size (bytes)
48K
32K
28K
Under development
M38504M6/E6
24K
20K
Mass production
16K
M38503M4/E4
12K
Mass production
M38503M2
8K
128
192
256
384
512
640
768
896
1024
RAM size (bytes)
Fig. 59 Memory expansion plan of 3850 group
3850/3851 Group User’s Manual
1-53
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address : 3C
B
Function
Name
0 INT 0 interrupt request bit
16]
At reset
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
1 Fix this bit to “0”.
2 INT 1 interrupt request bit
3 INT 2 interrupt request bit
4 INT 3 interrupt request bit
5 Fix this bit to “0”.
6 Timer X interrupt request bit
7 Timer Y interrupt request bit
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 60 Structure of Interrupt request register 1 of 3850 group
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E 16]
B
Function
Name
0 INT 0 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
1 Fix this bit to “0”.
2 INT 1 interrupt enable bit
3 INT 2 interrupt enable bit
4 INT 3 interrupt enable bit
7 Timer Y interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 61 Structure of Interrupt control register 1 of 3850 group
1-54
0
0
5 Fix this bit to “0”.
6 Timer X interrupt enable bit
At reset
3850/3851 Group User’s Manual
0
0
R W
CHAPTER 2
APPLICATION
2.1
2.2
2.3
2.4
2.5
2.6
2.7
I/O port
Timer
Serial I/O
Multi-master I2C-BUS interface
PWM
A-D converter
Reset
APPLICATION
2.1 I/O port
2.1 I/O port
This paragraph explains the registers setting method and the notes relevant to the I/O ports.
2.1.1 Memory map
000016
Port P0 (P0)
000116
Port P0 direction register (P0D)
000216
Port P1 (P1)
000316
Port P1 direction register (P1D)
000416
Port P2 (P2)
000516
Port P2 direction register (P2D)
000616
Port P3 (P3)
000716
000816
Port P3 direction register (P3D)
Port P4 (P4)
000916
Port P4 direction register (P4D)
Fig. 2.1.1 Memory map of registers relevant to I/O port
2.1.2 Relevant registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (Pi) (i = 0, 1, 2, 3, 4) [Address : 00 16, 0216, 04 16, 0616, 0816]
B
Name
0 Port Pi 0
Function
●
In output mode
Write
Port latch
Read
●
In input mode
Write : Port latch
Read : Value of pins
1 Port Pi1
2 Port Pi2
?
?
?
3 Port Pi3
?
4 Port Pi4
?
5 Port Pi5
?
6 Port Pi6
?
7 Port Pi7
?
Fig. 2.1.2 Structure of Port Pi (i = 0, 1, 2, 3, 4)
2-2
At reset
3850/3851 Group User’s Manual
R W
APPLICATION
2.1 I/O port
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4) [Address : 01
B
0 Port Pi direction register
1
2
3
4
5
6
7
Function
Name
0 : Port Pi 0 input mode
1 : Port Pi 0 output mode
0 : Port Pi 1 input mode
1 : Port Pi 1 output mode
0 : Port Pi 2 input mode
1 : Port Pi 2 output mode
0 : Port Pi 3 input mode
1 : Port Pi 3 output mode
0 : Port Pi 4 input mode
1 : Port Pi 4 output mode
0 : Port Pi 5 input mode
1 : Port Pi 5 output mode
0 : Port Pi 6 input mode
1 : Port Pi 6 output mode
0 : Port Pi 7 input mode
1 : Port Pi 7 output mode
16,
0316, 05 16, 07 16, 0916]
At reset
R W
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
Fig. 2.1.3 Structure of Port Pi direction register (i=0, 1, 2, 3, 4)
2.1.3 Handling of unused pins
Table 2.1.1 Handling of unused pins
Pins/Ports name
Handling
P0, P1, P2, P3, P4 •Set to the input mode and connect each to Vcc or Vss through a resistor of 1 kΩ to
10 kΩ.
V REF
AvSS
X OUT
•Set to the output mode and open at “L” or “H” level.
•Connect to Vss (GND).
•Connect to Vss (GND).
•Open, only when using an external clock
3850/3851 Group User’s Manual
2-3
APPLICATION
2.1 I/O port
2.1.4 Notes on input and output pins
(1) Notes in stand-by state
In stand-by state*1 for low-power dissipation, do not make input levels of an input port and an I/O
port “undefined”, especially for I/O ports of the P-channel and the N-channel open-drain.
Pull-up (connect the port to VCC ) or pull-down (connect the port to VSS ) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
● Reason
Even when setting as an output port with its direction register, in the following state :
• P-channel ...... when the content of the port latch is “0”
• N-channel ...... when the content of the port latch is “1”
the transistor becomes the OFF state, which causes the ports to be the high-impedance state.
Note that the level becomes “undefined” depending on external circuits.
Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the
state that input levels of a input port and an I/O port are “undefined”. This may cause power
source current.
* 1 stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
(2) Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction*2, the value of the
unspecified bit may be changed.
● Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
• As for a bit which is set for an input port :
The pin state is read in the CPU, and is written to this bit after bit managing.
• As for a bit which is set for an output port :
The bit value of the port latch is read in the CPU, and is written to this bit after bit managing.
Note the following :
• Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
• As for a bit of the port latch which is set for an input port, its value may be changed even when
not specified with a bit managing instruction in case where the pin state differs from its port latch
contents.
* 2 bit managing instructions : SEB, and CLB instructions
2-4
3850/3851 Group User’s Manual
APPLICATION
2.1 I/O port
2.1.5 Termination of unused pins
(1) Terminate unused pins
➀ Output ports : Open
➁ Input ports :
Connect each pin to VCC or V SS through each resistor of 1 kΩ to 10 kΩ.
As for pins whose potential affects to operation modes such as pins CNV SS, INT or others, select
the VCC pin or the V SS pin according to their operation mode.
➂ I/O ports :
• Set the I/O ports for the input mode and connect them to V CC or V SS through each resistor of
1 kΩ to 10 kΩ.
Set the I/O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the mode
of the ports is switched over to the output mode by the program after reset. Thus, the potential
at these pins is undefined and the power source current may increase in the input mode. With
regard to an effects on the system, thoroughly perform system evaluation on the user side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
➃ The AVss pin when not using the A-D converter :
• When not using the A-D converter, handle a power source pin for the A-D converter, AVss pin
as follows:
• AVss:Connect to the Vss pin
(2) Termination remarks
➀ Input ports and I/O ports :
Do not open in the input mode.
● Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➁ and
➂ shown on the above.
➁ I/O ports :
When setting for the input mode, do not connect to V CC or V SS directly.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and V CC (or VSS ).
➂ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to VCC or V SS through
a resistor.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
3850/3851 Group User’s Manual
2-5
APPLICATION
2.2 Timer
2.2 Timer
This paragraph explains the registers setting method and the notes relevant to the timers.
2.2.1 Memory map
002016
Prescaler 12 (PRE12)
002116
Timer 1 (T1)
002216
Timer 2 (T2)
002316
Timer XY mode register (TM)
002416
Prescaler X (PREX)
002516
Timer X (TX)
002616
Prescaler Y (PREY)
002716
Timer Y (TY)
002816
Timer count source set register (TCSS)
003C16
Interrupt request register 1 (IREQ1)
003D16
Interrupt request register 2 (IREQ2)
003E16
Interrupt control register 1 (ICON1)
003F16
Interrupt control register 2 (ICON2)
Fig. 2.2.1 Memory map of registers relevant to timers
2.2.2 Relevant registers
Prescaler 12, Prescaler X, Prescaler Y
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 12 (PRE12) [Address : 20 16]
Prescaler X (PREX) [Address : 24 16]
Prescaler Y (PREY) [Address : 26 16]
B
Name
Function
0 •Set a count value of each prescaler.
•The value set in this register is written to both each prescaler
and the corresponding prescaler latch at the same time.
•When this register is read out, the count value of the corres2 ponding prescaler is read out.
1
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 2.2.2 Structure of Prescaler 12, Prescaler X, Prescaler Y
2-6
At reset
3850/3851 Group User’s Manual
R W
APPLICATION
2.2 Timer
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1 (T1) [Address : 21 16]
B
Name
Function
0 •Set a count value of timer 1.
At reset
R W
1
•The value set in this register is written to both timer 1 and timer 1
1 latch at the same time.
•When this register is read out, the timer 1’s count value is read
2 out.
0
0
3
0
4
0
5
0
6
0
7
0
Fig. 2.2.3 Structure of Timer 1
Timer 2, Timer X, Timer Y
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2 (T2) [Address : 22 16]
Timer X (TX) [Address : 25 16]
Timer Y (TY) [Address : 27 16]
B
Name
Function
0 •Set a count value of each timer.
•The value set in this register is written to both each timer and
1 each timer latch at the same time.
•When this register is read out, each timer’s count value is read
2 out.
At reset
R W
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 2.2.4 Structure of Timer 2, Timer X, Timer Y
3850/3851 Group User’s Manual
2-7
APPLICATION
2.2 Timer
Timer XY mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer XY mode register (TM) [Address : 23 16 ]
B
Function
Name
0 Timer X operating mode bits
1
b1 b0
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement
mode
At reset
0
0
2 CNTR 0 active edge switch bit
The function depends on the
operating mode of Timer X.
(Refer to Table 2.2.1)
0
3 Timer X count stop bit
0 : Count start
1 : Count stop
0
4 Timer Y operating mode bits
b5 b4
0
5
6 CNTR 1 active edge switch bit
7 Timer Y count stop bit
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement
mode
The function depends on the
operating mode of Timer Y.
(Refer to Table 2.2.1)
0 : Count start
1 : Count stop
R W
0
0
0
Fig. 2.2.5 Structure of Timer XY mode register
Table 2.2.1 CNTR 0 /CNTR1 active edge switch bit function
Timer X /Timer Y operation
modes
Timer mode
Pulse output mode
Event counter mode
Pulse width measurement mode
CNTR0 / CNTR 1 active edge switch bit
(bits 2, 6 of address 23 16 ) contents
“0” CNTR0 / CNTR 1 interrupt request occurrence: Falling edge
; No influence to timer count
“1” CNTR0 / CNTR 1 interrupt request occurrence: Rising edge
; No influence to timer count
“0” Pulse output start: Beginning at “H” level
CNTR0 / CNTR 1 interrupt request occurrence: Falling edge
“1” Pulse output start: Beginning at “L” level
CNTR0 / CNTR 1 interrupt request occurrence: Rising edge
“0” Timer X
CNTR0 /
“1” Timer X
CNTR0 /
“0” Timer X
/ Timer Y: Rising edge count
CNTR 1 interrupt request occurrence: Falling edge
/ Timer Y: Falling edge count
CNTR 1 interrupt request occurrence: Rising edge
/ Timer Y: “H” level width measurement
CNTR0 / CNTR 1 interrupt request occurrence: Falling edge
“1” Timer X / Timer Y: “L” level width measurement
CNTR0 / CNTR 1 interrupt request occurrence: Rising edge
2-8
3850/3851 Group User’s Manual
APPLICATION
2.2 Timer
Timer count source selection register
b7 b6 b5 b4 b3 b2 b1 b0
Timer count source selection register (TCSS) [Address : 28
B
0
1
2
Name
16]
Function
Timer X count source selection 0 : f(X IN)/16 (f(X CIN)/16 at low-speed mode)
bit
1 : f(X IN)/2 (f(XCIN)/2 at low-speed mode)
Timer Y count source selection 0 : f(X IN)/16 (f(X CIN)/16 at low-speed mode)
bit
1 : f(X IN)/2 (f(XCIN)/2 at low-speed mode)
Timer 12 count source
0 : f(X IN)/16 (f(X CIN)/16 at low-speed mode)
1 : f(X CIN)
selection bit
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
At reset
R W
0
0
0
0
✕
4
0
✕
5
0
✕
6
0
✕
7
0
✕
3
Fig. 2.2.6 Structure of Timer count source set register
3850/3851 Group User’s Manual
2-9
APPLICATION
2.2 Timer
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address : 3C
B
Function
Name
0 INT 0 interrupt request bit
1 SCL/SDA interrupt request bit
2 INT 1 interrupt request bit
3 INT 2 interrupt request bit
4 INT 3 interrupt request bit
5 I2C interrupt request bit
6 Timer X interrupt request bit
7 Timer Y interrupt request bit
16]
At reset
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.2.7 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2) [Address : 3D
B
16]
Function
Name
At reset
0
✽
0
✽
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
1
interrupt
request
bit
CNTR
0 : No interrupt request issued
5
1 : Interrupt request issued
AD
converter
interrupt
request
0 : No interrupt request issued
6
1 : Interrupt request issued
bit
Nothing
is
allocated
for
this
bit.
This
is a write disabled bit.
7
When this bit is read out, the value is “0”.
0
✽
0
✽
0
✽
0
✕
1 Timer 2 interrupt request bit
2 Serial I/O receive interrupt
request bit
3 Serial I/O transmit interrupt
request bit
4 CNTR 0 interrupt request bit
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.2.8 Structure of Interrupt request register 2
2-10
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 Timer 1 interrupt request bit
3850/3851 Group User’s Manual
APPLICATION
2.2 Timer
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E
B
Function
Name
0 INT 0 interrupt enable bit
1 SCL/SDA interrupt enable bit
2 INT 1 interrupt enable bit
3 INT 2 interrupt enable bit
4 INT 3 interrupt enable bit
5 I2C interrupt enable bit
6 Timer X interrupt enable bit
7 Timer Y interrupt enable bit
16]
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset
R W
0
0
0
0
0
0
0
0
Fig. 2.2.9 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2 (ICON2) [Address : 3F 16]
B
Function
Name
0 Timer 1 interrupt enable bit
1 Timer 2 interrupt enable bit
2 Serial I/O receive interrupt
enable bit
3 Serial I/O transmit interrupt
enable bit
4 CNTR 0 interrupt enable bit
5 CNTR 1 interrupt enable bit
6 AD converter interrupt enable
bit
7 Fix this bit to “0”.
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset
R W
0
0
0
0
0
0
0
0
Fig. 2.2.10 Structure of Interrupt control register 2
3850/3851 Group User’s Manual
2-11
APPLICATION
2.2 Timer
2.2.3 Timer application examples
(1) Basic functions and uses
[Function 1] Control of Event interval (Timer X, Timer Y, Timer 1, Timer 2)
When a certain time, by setting a count value to each timer, has passed, the timer interrupt request
occurs.
<Use>
•Generation of an output signal timing
•Generation of a wait time
[Function 2] Control of Cyclic operation (Timer X, Timer Y, Timer 1, Timer 2)
The value of the timer latch is automatically written to the corresponding timer each time the timer
underflows, and each timer interrupt request occurs in cycles.
<Use>
•Generation of cyclic interrupts
•Clock function (measurement of 250 ms); see Application example 1
•Control of a main routine cycle
[Function 3] Output of Rectangular waveform (Timer X, Timer Y)
The output level of the CNTR0 pin or CNTR1 pin is inverted each time the timer underflows (in the
pulse output mode).
<Use>
•Piezoelectric buzzer output; see Application example 2
•Generation of the remote control carrier waveforms
[Function 4] Count of External pulses (Timer X, Timer Y)
External pulses input to the CNTR 0 pin or CNTR 1 pin are counted as the timer count source (in
the event counter mode).
<Use>
•Frequency measurement; see Application example 3
•Division of external pulses
•Generation of interrupts due to a cycle using external pulses as the count source; count of a
reel pulse
[Function 5] Measurement of External pulse width (Timer X, Timer Y)
The “H” or “L” level width of external pulses input to CNTR 0 pin or CNTR1 pin is measured (in the
pulse width measurement mode).
<Use>
•Measurement of external pulse frequency (measurement of pulse width of FG pulse✽ for a
motor); see Application example 4
•Measurement of external pulse duty (when the frequency is fixed)
FG pulse✽ : Pulse used for detecting the motor speed to control the motor speed.
2-12
3850/3851 Group User’s Manual
APPLICATION
2.2 Timer
(2) Timer application example 1: Clock function (measurement of 250 ms)
Outline: The input clock is divided by the timer so that the clock can count up at 250 ms intervals.
Specifications: •The clock f(X IN) = 4.19 MHz (2 22 Hz) is divided by the timer.
•The clock is counted up in the process routine of the timer X interrupt which occurs
at 250 ms intervals.
Figure 2.2.11 shows the timers connection and setting of division ratios; Figure 2.2.12 shows the
relevant registers setting; Figure 2.2.13 shows the control procedure.
f(XIN) = 4.19 MHz
Timer X count source
selection bit
Prescaler X
Timer X
Timer X interrupt
request bit
1/16
1/256
1/256
0 or 1
Dividing by 4 with software
1/4
250 ms
1 second
0 : No interrupt request issued
1 : Interrupt request issued
Fig. 2.2.11 Timers connection and setting of division ratios
3850/3851 Group User’s Manual
2-13
APPLICATION
2.2 Timer
Timer count source selection register (address 28 16)
b7
b0
TCSS
0
Timer X count source : f(X IN)/16
Timer XY mode register (address 23 16)
b7
b0
1
TM
0 0
Timer X operating mode: Timer mode
Timer X count: Stop
Clear to “0” when starting count.
Prescaler X (address 24 16)
b7
b0
PREX
255
Timer X (address 25 16)
b7
Set “division ratio – 1”
b0
255
TX
Interrupt control register 1 (address 3E 16)
b7
b0
1
ICON1
Timer X interrupt: Enabled
Interrupt request register 1 (address 3C 16)
b7
IREQ1
b0
0
Timer X interrupt request
(becomes “1” at 250 ms intervals)
Fig. 2.2.12 Relevant registers setting
2-14
3850/3851 Group User’s Manual
APPLICATION
2.2 Timer
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SEI
•All interrupts disabled
.....
TM
IREQ1
ICON1
•Timer X operating mode : Timer mode
•Clear Timer X interrupt request bit
•Timer X interrupt enabled
(address 28 16), bit0
(address 24 16)
(address 25 16)
0
256 – 1
256 – 1
•Timer X count source : f(X IN/16)
•Set “division ratio – 1” to Prescaler X and Timer X
(address 23 16), bit3
0
•Timer X count start
.....
xxxx10002
(address 23 16)
0
(address 3C 16), bit6
1
(address 3E 16), bit6
TCSS
PREX
TX
.....
TM
.....
CLI
•Interrupts enabled
Main processing
.....
<Procedure for completion of clock set>
(Note 1)
TM
PREX
TX
IREQ1
TM
(address 23 16), bit3
(address 24 16)
(address 25 16)
(address 3C 16), bit6
(address 23 16), bit3
•Reset Timer to restart count from 0 second after completion
of clock set
1
256 – 1
256 – 1
0
0
Note 1: Perform procedure for completion of clock set only
when completing clock set.
Timer X interrupt process routine
CLT (Note 2)
CLD (Note 3)
Push registers to stack
Note 2: When using Index X mode flag (T)
Note 3: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
Y
Clock stop ?
•Judge whether clock stops
N
Clock count up (1/4 second to year)
Pop registers
•Clock count up
•Pop registers pushed to stack
RTI
Fig. 2.2.13 Control procedure
3850/3851 Group User’s Manual
2-15
APPLICATION
2.2 Timer
(3) Timer application example 2: Piezoelectric buzzer output
Outline: The rectangular waveform output function of the timer is applied for a piezoelectric buzzer
output.
Specifications: •The rectangular waveform, dividing the clock f(X IN) = 4.19 MHz (222 Hz) into about
2 kHz (2048 Hz), is output from the P2 7/CNTR 0 pin.
•The level of the P27/CNTR 0 pin is fixed to “H” while a piezoelectric buzzer output
stops.
Figure 2.2.14 shows a peripheral circuit example, and Figure 2.2.15 shows the timers connection and
setting of division ratios. Figures 2.2.16 shows the relevant registers setting, and Figure 2.2.17
shows the control procedure.
The “H” level is output while a piezoelectric buzzer output stops.
CNTR 0 output
P27/CNTR 0
PiPiPi.....
244 µs 244 µs
Set a division ratio so that the
underflow output period of the timer X
can be 244 µs.
3851 Group
Fig. 2.2.14 Peripheral circuit example
Timer X count source
selection bit
Prescaler X
f(XIN) = 4.19 MHz
1/16
1
Timer X
Fixed
1/64
1/2
Fig. 2.2.15 Timers connection and setting of division ratios
2-16
3850/3851 Group User’s Manual
CNTR 0
APPLICATION
2.2 Timer
Timer count source selection register (address 28 16)
b0
b7
0
TCSS
Timer X count source : f(X IN)/16
Timer XY mode register (address 23 16)
b7
b0
TM
1 0 0 1
Timer X operating mode: Pulse output mode
CNTR0 active edge switch: Output starting at “H” level
Timer X count: Stop
Clear to “0” when starting count.
Timer X (address 25 16)
b7
b0
63
TX
Set “division ratio – 1”
Prescaler X (address 24 16)
b7
b0
0
PREX
Interrupt control register 1 (address 3E 16)
b7
ICON1
b0
0
Timer X interrupt: Disabled
Fig. 2.2.16 Relevant registers setting
3850/3851 Group User’s Manual
2-17
APPLICATION
2.2 Timer
RESET
Initialization
.....
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
(address 04 16), bit7
(address 05 16)
P2
P2D
1
1XXXXXXX2
.....
TCSS
ICON1
TM
TX
PREX
(address 28 16), bit0
(address 3E 16), bit6
(address 23 16)
(address 25 16)
(address 24 16)
•Timer X count source : f(X IN)/16
•Timer X interrupt disabled
•Stop CNTR 0 output; Stop piezoelectric buzzer output
•Set “division ratio – 1” to Timer X and Prescaler X
0
0
XXXX1X012
64 – 1
1–1
.....
Main processing
.....
Output unit
Yes
•Process piezoelectric buzzer request, generated during
main processing, in output unit
Piezoelectric buzzer request ?
No
TM (address 23 16), bit3
TX (address 25 16)
1
64 – 1
TM (address 23 16), bit3
0
Start piezoelectric buzzer output
Stop piezoelectric buzzer output
Fig. 2.2.17 Control procedure
2-18
3850/3851 Group User’s Manual
APPLICATION
2.2 Timer
(4) Timer application example 3: Frequency measurement
Outline: The following two values are compared to judge whether the frequency is within a valid
range.
•A value by counting pulses input to P4 0/CNTR1 pin with the timer.
•A reference value
Specifications: •The pulse is input to the P40/CNTR1 pin and counted by the timer Y.
•A count value is read out at about 2 ms intervals, the timer 1 interrupt interval.
When the count value is 28 to 40, it is judged that the input pulse is valid.
•Because the timer is a down-counter, the count value is compared with 227 to 215
(Note).
Note: 227 to 215 = {255 (initial value of counter) – 28} to {255 – 40}; 28 to 40 means the number
of valid value.
Figure 2.2.18 shows the judgment method of valid/invalid of input pulses; Figure 2.2.19 shows the
relevant registers setting; Figure 2.2.20 shows the control procedure.
Input pulse
••••
71.4 µs or more
(14 kHz µs or less)
••••
71.4 µs
(14 kHz µs)
••••
50 µs
(20 kHz µs)
Valid
Invalid
2 ms = 28 counts
71.4 µs
50 µs or less
(20 kHz µs or more)
Invalid
2 ms
50 µs
= 40 counts
Fig 2.2.18 Judgment method of valid/invalid of input pulses
3850/3851 Group User’s Manual
2-19
APPLICATION
2.2 Timer
Timer XY mode register (address 23 16)
b7
TM
1
b0
1 1 0
Timer Y operating mode: Event counter mode
CNTR1 active edge switch: Falling edge count
Timer Y count: Stop
Clear to “0” when starting count
Prescaler 12 (address 20 16)
b7
PRE12
b0
63
Timer 1 (address 21 16)
b7
T1
b0
7
Set “division ratio – 1”
Prescaler Y (address 26 16)
b7
PREY
b0
0
Timer Y (address 27 16)
b7
TY
b0
Set 255 just before counting pulses
(After a certain time has passed, the number of input
pulses is decreased from this value.)
255
Interrupt control register 1 (address 3E 16)
b7
ICON1
b0
0
Timer Y interrupt: Disabled
Interrupt control register 2 (address 3F 16)
b7
b0
1
ICON2
Timer 1 interrupt: Enabled
Interrupt request register 1 (address 3C 16)
b7
IREQ1
b0
0
Judgment of Timer Y interrupt request bit
( “1” of this bit when reading the count value indicates the 256 or more
pulses input in the condition of Timer Y = 255)
Fig. 2.2.19 Relevant registers setting
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3850/3851 Group User’s Manual
APPLICATION
2.2 Timer
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrary.
Initialization
SEI
•All interrupts disabled
.....
TM
PRE12
T1
PREY
TY
ICON1
ICON2
1110 XXXX2
(address 23 16)
64 – 1
(address 20 16)
8–1
(address 21 16)
1–1
(address 26 16)
(address 27 16)
256 – 1
0
(address 3E 16), bit7
1
(address 3F 16), bit0
•Timer Y interrupt disabled
•Timer 1 interrupt enabled
(address 23 16), bit7
•Timer Y count start
•Timer Y operating mode : Event counter mode
(Count a falling edge of pulses input from CNTR 1 pin.)
•Set division ratio so that Timer 1 interrupt will occur at
2 ms intervals.
.....
TM
0
.....
•Interrupts enabled
CLI
Timer 1 interrupt process routine
CLT (Note 1)
CLD (Note 2)
Push registers to stack
Note 1: When using Index X mode flag (T)
Note 2: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
1
IREQ1(address 3C 16), bit7 ?
•Process as out of range when the count value is 256 or more
0
(A)
TY (address 27 16)
•Read the count value
•Store the count value into Accumulator (A)
In range
•Compare the read value with
reference value
•Store the comparison result to
flag Fpulse
214 < (A) < 228
Out of range
Fpulse
TY
IREQ1
0
(address 27 16)
(address 3C 16), bit7
Fpulse
256 – 1
0
1
•Initialize the counter value
•Clear Timer Y interrupt request bit
Process judgment result
Pop registers
•Pop registers pushed to stack
RTI
Fig. 2.2.20 Control procedure
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2-21
APPLICATION
2.2 Timer
(5) Timer application example 4: Measurement of FG pulse width for motor
Outline: The timer X counts the “H” level width of the pulses input to the P27 /CNTR 0 pin. An
underflow is detected by the timer X interrupt and an end of the input pulse “H” level is
detected by the CNTR 0 interrupt.
Specifications: •The timer X counts the “H” level width of the FG pulse input to the P27/CNTR 0 pin.
<Example>
When the clock frequency is 4.19 MHz, the count source is 3.8 µs, which is obtained by dividing
the clock frequency by 16. Measurement can be made up to 250 ms in the range of FFFF 16 to
0000 16.
Figure 2.2.21 shows the timers connection and setting of division ratio; Figure 2.2.22 shows the
relevant registers setting; Figure 2.2.23 shows the control procedure.
Timer X count source
selection bit
f(XIN) = 4.19 MHz
1/16
Prescaler X
Timer X
Timer X interrupt
request bit
1/256
1/256
0 or 1
250 ms
0 : No interrupt request issued
1 : Interrupt request issued
Fig. 2.2.21 Timers connection and setting of division ratios
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3850/3851 Group User’s Manual
APPLICATION
2.2 Timer
Timer XY mode register (address 23 16)
b7
b0
1 0 1 1
TM
Timer X operating mode: Pulse width measurement mode
CNTR 0 active edge switch: “H” level width measurement
Timer X count: Stop
Clear to “0” when starting count
Prescaler X (address 24 16)
b7
b0
PREX
255
Timer X (address 25 16)
b7
Set “division ratio – 1”
b0
255
TX
Interrupt control register 1 (address 3E 16)
b7
ICON1
b0
1
Timer X interrupt: Enabled
Interrupt request register 1 (address 3C 16)
b7
IREQ1
b0
0
Timer X interrupt request
(Set to “1” automatically when Timer X underflows)
Interrupt control register 2 (address 3F 16)
b7
ICON2
b0
1
CNTR0 interrupt: Enabled
Interrupt request register 2 (address 3D 16)
b7
IREQ2
b0
0
CNTR 0 interrupt request
(Set to “1” automatically when “H” level input came to the end)
Fig. 2.2.22 Relevant registers setting
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2-23
APPLICATION
2.2 Timer
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SEI
•All interrupts disabled
.....
TM
PREX
TX
ICON1
IREQ1
ICON2
IREQ2
(address 23 16)
(address 24 16)
(address 25 16)
(address 3E 16), bit6
(address 3C 16), bit6
(address 3F16), bit4
(address 3D 16), bit4
256 – 1
256 – 1
1
0
1
0
•Timer X operating mode : Pulse width measurement mode
(Measure “H” level of pulses input from CNTR 0 pin.)
•Set division ratio so that Timer X interrupt will occur at
250 ms intervals.
•Timer X interrupt enabled
•Clear Timer X interrupt request bit
•CNTR0 interrupt enabled
•Clear CNTR 0 interrupt request bit
0
•Timer X count start
XXXX10112
.....
TM
(address 23 16), bit3
.....
•Interrupts enabled
CLI
Timer X interrupt process routine
•Error occurs
Process errors
RTI
CNTR0 interrupt process routine
CLT (Note 1)
CLD (Note 2)
Push registers to stack
(A)
Low-order 8-bit result of
pulse width measurement
(A)
High-order 8-bit result of
pulse width measurement
PREX (address 24 16)
TX
(address 25 16)
Pop registers
PREX
Inverted (A)
Note 1: When using Index X mode flag (T)
Note 2: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
•Read the count value and store it to RAM
TX
Inverted (A)
256 – 1
256 – 1
•Set division ratio so that Timer X interrupt will occur at
250 ms intervals.
•Pop registers pushed to stack
RTI
Fig. 2.2.23 Control procedure
2-24
3850/3851 Group User’s Manual
APPLICATION
2.2 Timer
2.2.4 Notes on the timer
● If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
● When switching the count source by the timer 12, X and Y count source selection bit, the value
of timer count is altered in unconsiderable amount owing to generating of a thin pulses in the count
input signals.
Therefore, select the timer count source before set the value to the prescaler and the timer.
3850/3851 Group User’s Manual
2-25
APPLICATION
2.3 Serial I/O
2.3 Serial I/O
This paragraph explains the registers setting method and the notes relevant to the Serial I/O.
2.3.1 Memory map
~
~
~
~
001816
Transmit/Receive buffer register (TB/RB)
001916
Serial I/O status register (SIOSTS)
001A16
Serial I/O control register (SIOCON)
001B16
UART control register (UARTCON)
001C16
Baud rate generator (BRG)
003A16
Interrupt edge selection register (INTEDGE)
~
~
~
~
~
~
~
~
003D16
Interrupt request register 2 (IREQ2)
003F16
Interrupt control register 2 (ICON2)
Fig. 2.3.1 Memory map of registers relevant to Serial I/O
2-26
3850/3851 Group User’s Manual
APPLICATION
2.3 Serial I/O
2.3.2 Relevant registers
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB) [Address : 18 16]
B
Name
Function
0 The transmission data is written to or the receive data is read out
from this buffer register.
1 • At writing: A data is written to the transmit buffer register.
• At reading: The contents of the receive buffer register are read
out.
2
At reset
R W
?
?
?
3
?
4
?
5
?
6
?
7
?
Note: The contents of transmit buffer register cannot be read out.
The data cannot be written to the receive buffer register.
Fig. 2.3.2 Structure of Transmit/Receive buffer register
Serial I/O status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O status register (SIOSTS) [Address : 19 16]
B
Function
Name
0 Transmit buffer empty flag
0 : Buffer full
1 : Buffer empty
0 : Buffer empty
1 : Buffer full
0 : Transmit shift in progress
1 : Transmit shift completed
At reset
R W
0
✕
0
✕
0
✕
3 Overrun error flag (OE)
0
✕
4
0
✕
0
✕
0
✕
1
✕
(TBE)
1 Receive buffer full flag (RBF)
2 Transmit shift register shift
completion flag (TSC)
5
6
7
0 : No error
1 : Overrun error
0 : No error
Parity error flag (PE)
1 : Parity error
0 : No error
Framing error flag (FE)
1 : Framing error
0 : (OE) ∪ (PE) ∪ (FE) = 0
Summing error flag (SE)
1 : (OE) ∪ (PE) ∪ (FE) = 1
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “1”.
Fig. 2.3.3 Structure of Serial I/O status register
3850/3851 Group User’s Manual
2-27
APPLICATION
2.3 Serial I/O
Serial I/O control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O control register (SIOCON) [Address : 1A
B
16]
Function
Name
At reset
0 : f(X IN)
1 : f(X IN)/4
0
• In clock synchronous serial I/O
0 : BRG output devided by 4
1 : External clock input
• In UART
0 : BRG output devided by 16
1 : External clock input devided by 16
0
2 SRDY output enable bit (SRDY) 0 : P2 7 pin operates as ordinary I/O pin
0
0 BRG count source
selection bit (CSS)
1 Serial I/O synchronous
clock selection bit (SCS )
R W
1 : P2 7 pin operates as S RDY output pin
3 Transmit interrupt
source selection bit (TIC)
4 Transmit enable bit (TE)
5 Receive enable bit (RE)
6 Serial I/O mode selection bit
(SIOM)
7 Serial I/O enable bit
(SIOE)
0 : Interrupt when transmit buffer has emptied
1 : Interrupt when transmit shift operation is
completed
0 : Transmit disabled
1 : Transmit enabled
0 : Receive disabled
1 : Receive enabled
0
0 : Clock asynchronous(UART) serial I/O
1 : Clock synchronous serial I/O
0
0 : Serial I/O disabled
(pins P2 4 to P2 7 operate as ordinary I/O pins)
1 : Serial I/O enabled
(pins P2 4 to P2 7 operate as serial I/O pins)
0
0
0
Fig. 2.3.4 Structure of Serial I/O control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register (UARTCON) [Address : 1B 16]
B
0
1
2
3
4
Name
Character length selection bit
(CHAS)
Parity enable bit
(PARE)
Parity selection bit
(PARS)
Stop bit length selection bit
(STPS)
P25/TxD P-channel output
disable bit (POFF)
At reset
R W
0
0
0
0
0
1
✕
6
1
✕
7
1
✕
5
Fig. 2.3.5 Structure of UART control register
2-28
Function
0 : 8 bits
1 : 7 bits
0 : Parity checking disabled
1 : Parity checking enabled
0 : Even parity
1 : Odd parity
0 : 1 stop bit
1 : 2 stop bits
In output mode
0 : CMOS output
1 : N-channel open-drain output
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “1”.
3850/3851 Group User’s Manual
APPLICATION
2.3 Serial I/O
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator (BRG) [Address : 1C 16]
Function
B
At reset
0 Set a count value of baud rate generator.
?
1
?
2
?
3
?
4
?
5
?
6
?
7
?
R W
Fig. 2.3.6 Structure of Baud rate generator
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A
B
Name
16]
Function
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
This is the reserved bit. Do not write “1” to this bit.
0 INT 0 interrupt edge
selection bit
1 INT 1 interrupt edge
selection bit
INT
2 interrupt edge
2
selection bit
3 INT 3 interrupt edge
selection bit
At reset
R W
0
0
0
0
0
✕
0
✕
6
0
✕
7
0
✕
4
5 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
Fig. 2.3.7 Structure of Interrupt edge selection register
3850/3851 Group User’s Manual
2-29
APPLICATION
2.3 Serial I/O
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2) [Address : 3D
B
16]
Function
Name
At reset
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
CNTR
1
interrupt
request
bit
5
1 : Interrupt request issued
6 AD converter interrupt request 0 : No interrupt request issued
1 : Interrupt request issued
bit
7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
0
✽
0
✽
0
✽
0
✕
0 Timer 1 interrupt request bit
1 Timer 2 interrupt request bit
2 Serial I/O receive interrupt
request bit
3 Serial I/O transmit interrupt
request bit
4 CNTR 0 interrupt request bit
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.3.8 Structure of Interrupt request register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2 (ICON2) [Address : 3F 16]
B
Function
Name
0 Timer 1 interrupt enable bit
1 Timer 2 interrupt enable bit
2 Serial I/O receive interrupt
enable bit
3 Serial I/O transmit interrupt
enable bit
4 CNTR 0 interrupt enable bit
5 CNTR 1 interrupt enable bit
6 AD converter interrupt enable
bit
7 Fix this bit to “0”.
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 2.3.9 Structure of Interrupt control register 2
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3850/3851 Group User’s Manual
At reset
0
0
0
0
0
0
0
0
R W
APPLICATION
2.3 Serial I/O
2.3.3 Serial I/O connection examples
(1) Control of peripheral IC equipped with CS pin
There are connection examples using a clock synchronous serial I/O mode.
Figure 2.3.10 shows connection examples of a peripheral IC equipped with the CS pin.
(1) Only transmission
(Using the RXD pin as an I/O port)
CS
Port
SCLK
CLK
TXD
DATA
3851 group
Peripheral IC
(OSD controller etc.)
(3) Transmission and reception
(When connecting RXD with TXD)
(When connecting IN with OUT in
peripheral IC)
3851
(2) Transmission and reception
Port
CS
SCLK
CLK
TXD
R XD
IN
3851 group
OUT
Peripheral IC
(E2 PROM etc.)
(4) Connection of plural IC
Port
CS
Port
CS
SCLK
CLK
SCLK
CLK
TXD
IN
TXD
IN
RXD
OUT
R XD
Port
OUT
group ✽1
IC ✽2
Peripheral
2
(E PROM etc.)
Peripheral IC 1
3851 group
✽1:
Select an N-channel open-drain output for TXD pin output control.
✽2: Use the OUT pin of peripheral IC which is an N-channel opendrain output and becomes high impedance during receiving data.
Note: “Port” means an output port controlled by software.
CS
CLK
IN
OUT
Peripheral IC 2
Fig. 2.3.10 Serial I/O connection examples (1)
3850/3851 Group User’s Manual
2-31
APPLICATION
2.3 Serial I/O
(2)
Connection with microcomputer
Figure 2.3.11 shows connection examples with another microcomputer.
(1) Selecting internal clock
SCLK
(2) Selecting external clock
CLK
SCLK
CLK
TXD
IN
TX D
IN
RX D
OUT
RX D
OUT
3851 group
Microcomputer
(3) Using SRDY signal output function
(Selecting an external clock)
SRDY
RDY
SCLK
3851 group
(4) In UART
CLK
TX D
RXD
TXD
IN
RX D
TXD
R XD
OUT
3851 group
Microcomputer
3851 group
Fig. 2.3.11 Serial I/O connection examples (2)
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Microcomputer
3850/3851 Group User’s Manual
Microcomputer
APPLICATION
2.3 Serial I/O
2.3.4 Setting of serial I/O transfer data format
A clock synchronous or clock asynchronous (UART) can be selected as a data format of the serial I/O.
Figure 2.3.12 shows the serial I/O transfer data format.
1ST-8DATA-1SP
ST
LSB
MSB
SP
1ST-7DATA-1SP
ST
LSB
MSB
SP
1ST-8DATA-1PAR-1SP
ST
LSB
MSB
PAR
PAR
SP
MSB
2SP
SP
1ST-7DATA-1PAR-1SP
ST
UART
LSB
MSB
1ST-8DATA-2SP
ST
LSB
1ST-7DATA-2SP
ST
Serial I/O
LSB
MSB
2SP
1ST-8DATA-1PAR-2SP
ST
LSB
MSB
PAR
PAR
2SP
2SP
1ST-7DATA-1PAR-2SP
ST
Clock synchronous
Serial I/O
LSB
MSB
LSB first
ST : Start bit
SP : Stop bit
PAR : Parity bit
Fig. 2.3.12 Serial I/O transfer data format
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APPLICATION
2.3 Serial I/O
2.3.5 Serial I/O application examples
(1) Communication using clock synchronous serial I/O (transmit/receive)
Outline : 2-byte data is transmitted and received, using the clock synchronous serial I/O.
The S RDY signal is used for communication control.
Figure 2.3.13 shows a connection diagram, and Figure 2.3.14 shows a timing chart.
Figure 2.3.15 shows a registers setting relevant to the transmitting side, and Figure 2.3.16 shows
registers setting relevant to the receiving side.
Transmitting side
Receiving side
P41/INT0
SRDY
SCLK
SCLK
TXD
RXD
3851 group
3851 group
Fig. 2.3.13 Connection diagram
Specifications : •
•
•
•
The Serial I/O is used (clock synchronous serial I/O is selected.)
Synchronous clock frequency : 125 kHz (f(X IN) = 4 MHz is divided by 32)
The S RDY (receivable signal) is used.
The receiving side outputs the SRDY signal at intervals of 2 ms (generated by timer),
and 2-byte data is transferred from the transmitting side to the receiving side.
••••
S RDY
SCLK
TXD
••••
D0 D1 D 2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
2 ms
Fig. 2.3.14 Timing chart (using clock synchronous serial I/O)
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3850/3851 Group User’s Manual
D0 D1
••••
APPLICATION
2.3 Serial I/O
Transmitting side
Serial I/O status register (Address : 19 16)
b7
b0
SIOSTS
Transmit buffer empty flag
• Confirm that the data has been transferred from Transmit buffer
register to Transmit shift register.
• When this flag is “1”, it is possible to write the next transmission
data in to Transmit buffer register.
Transmit shift register shift completion flag
Confirm completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Serial I/O control register (Address : 1A 16)
b7
SIOCON
b0
1 1 0 1
0 0
BRG counter source selection bit : f(X IN)
Serial I/O synchronous clock selection bit : BRG/4
Transmit enable bit : Transmit enabled
Receive enable bit : Receive disabled
Serial I/O mode selection bit : Clock synchronous serial I/O
Serial I/O enable bit : Serial I/O enabled
Baud rate generator (Address : 1C 16)
b7
BRG
b0
Set “division ratio – 1”
7
Interrupt edge selection register (Address : 3A
b7
INTEDGE
16)
b0
0
INT 0 interrupt edge selection bit : Falling edge active
Fig. 2.3.15 Registers setting relevant to transmitting side
3850/3851 Group User’s Manual
2-35
APPLICATION
2.3 Serial I/O
Receiving side
Serial I/O status register (Address : 19 16)
b7
b0
SIOSTS
Receive buffer full flag
Confirm completion of receiving 1-byte data with this flag.
“1” : at completing reception
“0” : at reading out contents of Receive buffer register
Overrun error flag
“1” : When data is ready in Receive shift register while Receive buffer
register contains the data.
Parity error flag
“1” : When a parity error occurs in enabled parity.
Framing error flag
“1” : When stop bits cannot be detected at the specified timing
Summing error flag
“1” : when any one of the following errors occurs.
• Overrun error
• Parity error
• Framing error
Serial I/O control register (Address : 1A 16)
b7
SIOCON 1 1 1 1
b0
1 1
Serial I/O synchronous clock selection bit : External clock
SRDY output enable bit : S RDY output enabled
Transmit enable bit : Transmit enabled
Set this bit to “1”, using SRDY output.
Receive enable bit : Receive enabled
Serial I/O mode selection bit : Clock synchronous serial I/O
Serial I/O enable bit : Serial I/O enabled
Fig. 2.3.16 Registers setting relevant to receiving side
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3850/3851 Group User’s Manual
APPLICATION
2.3 Serial I/O
Figure 2.3.17 shows a control procedure of the transmitting side, and Figure 2.3.18 shows a control
procedure of the receiving side.
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
.....
SIOCON (Address : 1A 16)
1101xx00 2
(Address : 1C 16)
8–1
BRG
0
INTEDGE (Address : 3A 16), bit0
0
IREQ1 (Address:3C 16), bit0?
• Detection of INT 0 falling edge
1
IREQ1 (Address : 3C 16), bit0
TB/RB (Address : 18 16)
0
The first byte of a
transmission data
SIOSTS (Address : 19 16), bit0?
0
1
TB/RB (Address : 18 16)
The second byte of a
transmission data
SIOSTS (Address : 19 16), bit0?
0
1
SIOSTS (Address : 19 16), bit2?
0
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
• Judgment of transferring from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
• Judgment of transferring from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
• Judgment of shift completion of Transmit shift register
(Transmit shift register shift completion flag)
1
Fig. 2.3.17 Control procedure of transmitting side
3850/3851 Group User’s Manual
2-37
APPLICATION
2.3 Serial I/O
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
.....
SIOCON (Address : 1A 16)
1111x11x 2
N
Pass 2 ms?
• An interval of 2 ms generated by Timer.
Y
TB/RB (Address : 18 16)
Dummy data
SIOSTS (Address : 19 16), bit1?
• SRDY output
SRDY signal is output by writing data to
the TB/RB.
Using the SRDY, set Transmit enable bit
(bit4) of the SIOCON to “1.”
0
• Judgement of completion of receiving
(Receive buffer full flag)
1
• Reception of the first byte data.
Receive buffer full flag is set to “0” by reading data.
Read out reception data from
TB/RB (Address : 18 16)
0
SIOSTS (Address : 19 16), bit1?
• Judgement of completion of receiving
(Receive buffer full flag)
1
Read out reception data from
TB/RB (Address : 18 16)
• Reception of the second byte data.
Receive buffer full flag is set to “0” by reading data.
Fig. 2.3.18 Control procedure of receiving side
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3850/3851 Group User’s Manual
APPLICATION
2.3 Serial I/O
(2)
Output of serial data (control of peripheral IC)
Outline : 4-byte data is transmitted and received, using the clock synchronous serial I/O.
The CS signal is output to a peripheral IC through port P4 3.
Figure 2.3.19 shows a connection diagram, and Figure 2.3.20 shows a timing chart.
P43
CS
SCLK
CLK
TXD
DATA
3851 group
CS
CLK
DATA
Peripheral IC
Example for using Serial I/O
Fig. 2.3.19 Connection diagram
Specifications : • The Serial I/O is used (clock synchronous serial I/O is selected.)
• Synchronous clock frequency : 125 kHz (f(X IN) = 4 MHz is divided by 32)
• Transfer direction : LSB first
• The Serial I/O interrupt is not used.
• Port P43 is connected to the CS pin (“L” active) of the peripheral IC for transmission
control; the output level of port P4 3 is controlled by software.
CS
CLK
DATA
DO0
DO1
DO2
DO3
Fig. 2.3.20 Timing chart
3850/3851 Group User’s Manual
2-39
APPLICATION
2.3 Serial I/O
Figure 2.3.21 shows registers setting relevant to serial I/O, and Figure 2.3.22 shows a setting of
serial I/O transmission data.
Serial I/O control register (Address : 1A 16)
b7
SIOCON
b0
1 1 0 1 1 0 0 0
BRG count source selection bit : f(X IN)
Serial I/O synchronous clock selection bit : BRG/4
SRDY output enable bit : SRDY output disabled
Transmit interrupt source selection bit : Transmit shift operating
completion
Transmit enable bit : Transmit enabled
Receive enable bit : Receive disabled
Serial I/O mode selection bit : Clock synchronous serial I/O
Serial I/O enable bit : Serial I/O enabled
UART control register (Address : 1B 16)
b7
b0
0
UARTCON
P25/TXD P-channel output disable bit : CMOS output
Baud rate generator (Address : 1C 16)
b7
b0
7
BRG
Set “division ratio – 1”
Interrupt control register 2 (Address : 3F 16)
b7
b0
ICON2
0
Serial I/O transmit interrupt enable bit : Interrupt disabled
Interrupt request register 2 (Address : 3D
b7
16)
b0
IREQ2
0
Serial I/O transmit interrupt request bit
Confirm completion of transmitting
1-byte data by one unit.
“1” : Transmit shift completion
Fig. 2.3.21 Registers setting relevant to serial I/O
Transmit/Receive buffer register (Address : 18
b7
b0
TB/RB
Set a transmission data.
Confirm that transmission of the previous data is
completed (bit 3 of the Interrupt request register 2
is “1”) before writing data.
Fig. 2.3.22 Setting of serial I/O transmission data
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3850/3851 Group User’s Manual
APPLICATION
2.3 Serial I/O
When the registers are set as shown in Fig. 2.3.21, the Serial I/O can transmit 1-byte data by writing
data to the transmit buffer register.
Thus, after setting the CS signal to “L”, write the transmission data to the transmit buffer register by
each 1 byte, and return the CS signal to “H” when the target number of bytes has been transmitted.
Figure 2.3.23 shows a control procedure of serial I/O.
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
....
Initialization
SIOCON (Address : 1A 16) 11011000 2
0
UARTCON (Address : 1B 16), bit4
(Address : 1C 16)
8–1
BRG
(Address : 3F 16), bit3
0
ICON2
(Address : 08 16), bit3
1
P4
xxxx1xxx 2
(Address : 09 16)
P4D
●
Set the Serial I/O.
●
Serial I/O transmit interrupt : Disabled
●
....
P4 (Address : 08 16), bit3
0
IREQ2 (Address : 3D 16), bit3
TB/RB (Address : 18 16)
●
●
0
a transmission
data
IREQ2 (Address : 3D 16), bit3?
●
0
●
Set the CS signal output port.
(“H” level output)
Set the CS signal output level to “L”.
Set the Serial I/O transmit interrupt
request bit to “0”.
Write a transmission data.
(Start of transmit 1-byte data)
Judgment of completion of transmitting 1byte data
1
N
Complete to transmit data?
●
●
Y
P4 (Address : 08 16), bit3
1
●
Use any of RAM area as a counter for
counting the number of transmitted bytes.
Judgment of completion of transmitting
the target number of bytes.
Return the CS signal output level to “H”
when transmission of the target number of
bytes is completed.
Fig. 2.3.23 Control procedure of serial I/O
3850/3851 Group User’s Manual
2-41
APPLICATION
2.3 Serial I/O
(3)
Cyclic transmission or reception of block data (data of specified number of bytes) between
two microcomputers
Outline : When the clock synchronous serial I/O is used for communication, synchronization of the
clock and the data between the transmitting and receiving sides may be lost because of
noise included in the synchronous clock. It is necessary to correct that constantly, using
“heading adjustment”.
This “heading adjustment” is carried out by using the interval between blocks in this
example.
Figure 2.3.24 shows a connection diagram.
SCLK
SCLK
RXD
TXD
TXD
RXD
Master unit
Slave unit
Fig. 2.3.24 Connection diagram
Specifications :
•
•
•
•
•
•
•
•
The serial I/O is used (clock synchronous serial I/O is selected).
Synchronous clock frequency : 131 kHz (f(X IN ) = 4.19 MHz is divided by 32)
Byte cycle: 488 µs
Number of bytes for transmission or reception : 8 byte/block
Block transfer cycle : 16 ms
Block transfer term : 3.5 ms
Interval between blocks : 12.5 ms
Heading adjustment time : 8 ms
Limitations of the specifications :
• Reading of the reception data and setting of the next transmission data must be
completed within the time obtained from “byte cycle – time for transferring 1-byte
data” (in this example, the time taken from generating of the serial I/O receive
interrupt request to input of the next synchronous clock is 431 µs).
• “Heading adjustment time < interval between blocks” must be satisfied.
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3850/3851 Group User’s Manual
APPLICATION
2.3 Serial I/O
The communication is performed according to the timing shown in Figure 2.3.25. In the slave unit,
when a synchronous clock is not input within a certain time (heading adjusment time), the next clock
input is processed as the beginning (heading) of a block.
When a clock is input again after one block (8 byte) is received, the clock is ignored.
Figure 2.3.26 shows relevant registers setting.
D0
D1
D2
D7
D0
Byte cycle
Interval between blocks
Block transfer term
Block transfer cycle
Heading adjustment time
Processing for heading adjustment
Fig. 2.3.25 Timing chart
Master unit
Slave unit
Serial I/O control register (Address : 1A 16)
b7
b0
SIOCON
Serial I/O control register (Address : 1A 16)
b7
b0
1 1 1 1 1 0 0 0
SIOCON
1 1 1 1
0 1
BRG count source : f(X IN)
Synchronous
clock : BRG/4
SRDY output disabled
Transmit interrupt source :
Transmit shift operating completion
Transmit enabled
Receive enabled
Not be effected by
external clock
Synchronous clock : External clock
SRDY output disabled
Clock synchronous serial I/O
Clock synchronous serial I/O
Serial I/O enabled
Serial I/O enabled
Not use the serial I/O transmit interrupt
Transmit enabled
Receive enabled
Both of units
UART control register (Address : 1B 16)
b7
b0
0
UARTCON
P25/TXD pin : CMOS output
Baud rate generator (Address : 1C 16)
b7
b0
BRG
7
Set “division ratio – 1”
Fig. 2.3.26 Relevant registers setting
3850/3851 Group User’s Manual
2-43
APPLICATION
2.3 Serial I/O
Control procedure :
● Control in the master unit
After setting the relevant registers shown in Figure 2.3.26, the master unit starts transmission or
reception of 1-byte data by writing transmission data to the transmit buffer register.
To perform the communication in the timing shown in Figure 2.3.25, take the timing into account
and write transmission data. Additionally, read out the reception data when the Serial I/O transmit
interrupt request bit is set to “1,” or before the next transmission data is written to the transmit
buffer register.
Figure 2.3.27 shows a control procedure of the master unit using timer interrupts.
Interrupt processing routine
executed every 488 µs
CLT (Note 1)
CLD (Note 2)
Push register to stack
Within a block transfer
period?
●
Note 1: When using the Index X mode flag (T).
Note 2: When using the Decimal mode flag (D).
Push the register used in the interrupt
processing routine into the stack.
N
●
Y
Generate a certain block interval by
using a timer or other functions.
●
Count a block interval counter
Read a reception data
Complete to transfer
a block?
Y
Start a block transfer?
Y
N
Write the first transmission data
(first byte) in a block
Write a transmission data
Pop registers
●
Pop registers which is pushed to stack.
RTI
Fig. 2.3.27 Control procedure of master unit
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3850/3851 Group User’s Manual
N
Check the block interval counter and
determine to start a block transfer.
APPLICATION
2.3 Serial I/O
● Control in the slave unit
After setting the relevant registers as shown in Figure 2.3.26, the slave unit becomes the state
where a synchronous clock can be received at any time, and the serial I/O receive interrupt
request bit is set to “1” each time an 8-bit synchronous clock is received.
In the serial I/O receive interrupt processing routine, the data to be transmitted next is written to
the transmit buffer register after the received data is read out.
However, if no serial I/O receive interrupt occurs for a certain time (heading adjustment time or
more), the following processing will be performed.
1. The first 1-byte data of the transmission data in the block is written into the transmit buffer register.
2. The data to be received next is processed as the first 1 byte of the received data in the block.
Figure 2.3.28 shows a control procedure of the slave unit using the serial I/O receive interrupt and
any timer interrupt (for heading adjustment).
Serial I/O receive interrupt
processing routine
Timer interrupt processing
routine
CLT (Note 1)
CLD (Note 2)
Push register to stack
●
●
Within a block transfer
term?
N
Push the register used in
the interrupt processing
routine into the stack.
Confirm the received byte
counter to judge the block
transfer term.
CLT (Note 1)
CLD (Note 2)
Push register to stack
●
Heading adjustment
counter – 1
Y
N
Heading adjustment
counter = 0?
Read a reception data
Push the register used in
the interrupt processing
routine into the stack.
Y
Write the first transmission
data (first byte) in a block
A received byte counter +1
A received byte
counter ≥ 8?
A received byte counter
Y
0
N
Pop registers
Write a transmission data
Write dummy data (FF 16)
●
Pop registers which is
pushed to stack.
RTI
Initial
value
(Note 3)
Heading
adjustment
counter
Pop registers
RTI
●
Pop registers which is
pushed to stack.
Notes 1: When using the Index X mode flag (T).
2: When using the Decimal mode flag (D).
3: In this example, set the value which is equal to the
heading adjustment time divided by the timer interrupt
cycle as the initial value of the heading adjustment
counter.
For example: When the heading adjustment time is 8 ms
and the timer interrupt cycle is 1 ms, set
8 as the initial value.
Fig. 2.3.28 Control procedure of slave unit
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2-45
APPLICATION
2.3 Serial I/O
(4)
Communication (transmit/receive) using asynchronous serial I/O (UART)
Outline : 2-byte data is transmitted and received, using the asynchronous serial I/O.
Port P40 is used for communication control.
Figure 2.3.29 shows a connection diagram, and Figure 2.3.30 shows a timing chart.
Transmitting side
Receiving side
P40
P40
TXD
R XD
3851 group
3851 group
Fig. 2.3.29 Connection diagram (Communication using UART)
Specifications : • The Serial I/O is used (UART is selected).
• Transfer bit rate : 9600 bps (f(X IN) = 4.9152 MHz is divided by 512)
• Communication control using port P4 0
(The output level of port P4 0 is controlled by softoware.)
• 2-byte data is transferred from the transmitting side to the receiving side at intervals
of 10 ms generated by the timer.
P40
TXD
••••
ST D0
D1 D2 D3 D4 D5 D6
D7 SP(2) ST D0 D1 D2 D3
D4 D5 D6 D7 SP(2)
10 ms
Fig. 2.3.30 Timing chart (using UART)
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3850/3851 Group User’s Manual
ST D0
••••
APPLICATION
2.3 Serial I/O
Table 2.3.1 shows setting examples of the baud rate generator (BRG) values and transfer bit rate
values; Figure 2.3.31 shows registers setting relevant to the transmitting side; Figure 2.3.32 shows
registers setting relevant to the receiving side.
Table 2.3.1 Setting examples of Baud rate generator values and transfer bit rate values
BRG count source
(Note 1)
BRG setting value
Transfer bit rate (bps) (Note 2)
at f(X IN) = 4.9152 MHZ
at f(XIN) = 8 MHZ
f(XIN)/4
255(FF 16)
300
488.28125
f(XIN)/4
127(7F 16)
600
976.5625
f(XIN)/4
63(3F16)
1200
1953.125
f(XIN)/4
31(1F16)
2400
3906.25
f(XIN)/4
15(0F16)
4800
7812.5
f(XIN)/4
7(0716)
9600
15625
f(XIN)/4
3(0316)
19200
31250
f(XIN)/4
1(0116)
38400
62500
f(XIN)
3(0316)
76800
125000
f(XIN)
1(0116)
153600
250000
f(XIN)
0(0016)
307200
500000
Notes 1: Select the BRG count source with bit 0 of the serial I/O control register (Address : 1A 16 ).
2: Equation of transfer bit rate:
Transfer bit rate (bps) =
f(XIN)
(BRG setting value + 1) ✕ 16 ✕ m✽
✽m: When bit 0 of the Serial I/O control register (Address : 1A16 ) is set to “0,” a value of m
is 1.
When bit 0 of the Serial I/O control register (Address : 1A16 ) is set to “1,” a value of m
is 4.
3850/3851 Group User’s Manual
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APPLICATION
2.3 Serial I/O
Transmitting side
Serial I/O status register (Address : 19 16)
b7
b0
SIOSTS
Transmit buffer empty flag
• Confirm that the data has been transferred from Transmit buffer
register to Transmit shift register.
• When this flag is “1”, it is possible to write the next transmission
data in to Transmit buffer register.
Transmit shift register shift completion flag
Confirm completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Serial I/O control register (Address : 1A 16)
b7
SIOCON
b0
1 0 0 1
0 0 1
BRG count source selection bit : f(XIN)/4
Serial I/O synchronous clock selection bit : BRG/16
SRDY output enable bit : SRDY out disabled
Transmit enable bit : Transmit enabled
Receive enable bit : Receive disabled
Serial I/O mode selection bit : Asynchronous serial I/O(UART)
Serial I/O enable bit : Serial I/O enabled
UART control register (Address : 1B 16)
b7
UARTCON
b0
0 1
0 0
Character length selection bit : 8 bits
Parity enable bit : Parity checking disabled
Stop bit length selection bit : 2 stop bits
P25/TXD P-channel output disable bit : CMOS output
Baud rate generator (Address : 1C 16)
b7
BRG
b0
7
Set
f(XIN)
Transfer bit rate ✕ 16 ✕ m ✽
–1
✽ When bit 0 of the Serial I/O control register (Address : 1A
a value of m is 1.
When bit 0 of the Serial I/O control register (Address : 1A
a value of m is 4.
Fig. 2.3.31 Registers setting relevant to transmitting side
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3850/3851 Group User’s Manual
16)
is set to “0,”
16)
is set to “1,”
APPLICATION
2.3 Serial I/O
Receiving side
Serial I/O status register (Address : 19 16)
b7
b0
SIOSTS
Receive buffer full flag
Confirm completion of receiving 1-byte data with this flag.
“1” : at completing reception
“0” : at reading out contents of Receive buffer register
Overrun error flag
“1” : When data is ready in Receive shift register while Receive buffer
register contains the data.
Parity error flag
“1” : When a parity error occurs in enabled parity.
Framing error flag
“1” : When stop bits cannot be detected at the specified timing
Summing error flag
“1” : when any one of the following errors occurs.
• Overrun error
• Parity error
• Framing error
Serial I/O control register (Address : 1A 16)
b7
SIOCON
b0
1 0 1 0
0 0 1
BRG count source selection bit : f(X IN)/4
Serial I/O synchronous clock selection bit : BRG/16
SRDY output enable bit : SRDY out disabled
Transmit enable bit : Transmit disabled
Receive enable bit : Receive enabled
Serial I/O mode selection bit : Asynchronous serial I/O(UART)
Serial I/O enable bit : Serial I/O enabled
UART control register (Address : 1B 16)
b7
b0
UARTCON
1
0 0
Character length selection bit : 8 bits
Parity enable bit : Parity checking disabled
Stop bit length selection bit : 2 stop bits
Baud rate generator (Address : 1C 16)
b7
BRG
b0
7
Set
f(XIN)
Transfer bit rate ✕ 16 ✕ m ✽
–1
✽ When bit 0 of the Serial I/O control register (Address : 1A
a value of m is 1.
When bit 0 of the Serial I/O control register (Address : 1A
a value of m is 4.
16)
is set to “0,”
16)
is set to “1,”
Fig. 2.3.32 Registers setting relevant to receiving side
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APPLICATION
2.3 Serial I/O
Figure 2.3.33 shows a control procedure of the transmitting side, and Figure 2.3.34 shows a control
procedure of the receiving side.
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
.....
1001x001 2
SIOCON (Address : 1A 16)
xxx01x00 2
UARTCON (Address : 1B 16)
8–1
(Address : 1C 16)
BRG
(Address : 08 16), bit0
0
P4
(Address : 09 16)
P4D
xxxxxxx1 2
• Port P4 0 set for communication control
N
Pass 10 ms?
• An interval of 10 ms generated by Timer
Y
P4 (Address : 08 16), bit0
TB/RB (Address : 18 16)
1
• Communication start
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
The first byte of a
transmission data
0
SIOSTS (Address : 19 16), bit0?
• Judgment of transferring data from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
1
TB/RB (Address : 18 16)
The second byte of
a transmission data
SIOSTS (Address : 19 16), bit0?
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
0
• Judgment of transferring data from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
0
• Judgment of shift completion of Transmit shift register
(Transmit shift register shift completion flag)
1
SIOSTS (Address : 19 16), bit2?
1
P4 (Address : 08 16), bit0
0
• Communication completion
Fig. 2.3.33 Control procedure of transmitting side
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APPLICATION
2.3 Serial I/O
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
.....
SIOCON (Address : 1A 16)
UARTCON (Address : 1B 16)
BRG
(Address : 1C 16)
(Address : 09 16)
P4D
1010x001 2
xxxx1x00 2
8–1
xxxxxxx0 2
0
SIOSTS (Address : 19 16), bit1?
• Judgment of completion of receiving
(Receive buffer full flag)
1
• Reception of the first byte data
Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from RB (Address : 18 16)
SIOSTS (Address : 19 16), bit6?
1
• Judgment of an error flag
0
• Judgment of completion of
receiving
(Receive buffer full flag)
0
SIOSTS (Address : 19 16), bit1?
1
• Reception of the second byte data
Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from RB (Address : 18 16)
SIOSTS (Address : 19 16), bit6?
1
• Judgment of an error flag
Processing for error
0
1
P4 (Address : 08 16), bit0?
0
SIOCON (Address : 1A 16)
SIOCON (Address : 1A 16)
0000X000 2
1010X001 2
• Countermeasure for a bit slippage
Fig. 2.3.34 Control procedure of receiving side
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APPLICATION
2.3 Serial I/O
2.3.6 Notes on serial I/O
(1)
Notes when selecting clock synchronous serial I/O
➀ Stop of transmission operation
Clear the serial I/O enable bit and the transmit enable bit to “0” (serial I/O and transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in
this case, since pins TxD, RxD, S CLK, and S RDY function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in this state, data starts to be shifted
to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during
internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O enable bit to “0” (serial
I/O disabled).
➂ Stop of transmit/receive operation
Clear both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled).
(when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
● Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.
If any one of transmission and reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,
the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clearing the serial I/O enable bit to “0”
(serial I/O disabled) (refer to (1) ➀).
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APPLICATION
2.3 Serial I/O
(2)
Notes when selecting clock asynchronous serial I/O
➀ Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in
this case, since pins TxD, RxD, S CLK, and S RDY function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in this state, data starts to be shifted
to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during
internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
➂ Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in
this case, since pins TxD, RxD, S CLK, and S RDY function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in this state, data starts to be shifted
to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during
internally shifting is output to the TxD pin and an operation failure occurs.
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
(3)
S RDY output of reception side
When signals are output from the SRDY pin on the reception side by using an external clock in the
clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY output enable bit, and
the transmit enable bit to “1” (transmit enabled).
(4)
Setting serial I/O control register again
Set the serial I/O control register again after the transmission and the reception circuits are reset by
clearing both the transmit enable bit and the receive enable bit to “0.”
Clear both the transmit enable
bit (TE) and the receive enable
bit (RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O control register
↓
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to “1”
Can be set with the
LDM instruction at
the same time
Fig. 2.3.35 Sequence of setting serial I/O control register again
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APPLICATION
2.3 Serial I/O
(5)
Data transmission control with referring to transmit shift register completion flag
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(6)
Transmission control when external clock is selected
When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the SCLK input level. Also, write the transmit data to the transmit buffer
register (serial I/O shift register) at “H” of the S CLK input level.
(7)
Transmit interrupt request when transmit enable bit is set
The transmission interrupt request bit is set and the interruption request is generated even when
selecting timing that either of the following flags is set to “1” as timing where the transmission
interruption is generated.
• Transmit buffer empty flag is set to “1”
• Transmit shift register completion flag is set to “1”
Therefore, when the transmit interrupt is used, set the transmit interrupt enable bit to transmit
enabled as the following sequence.
➀ Transmit enable bit is set to “1”
➁ Transmit interrupt request bit is set to “0”
● Reason
When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift
register completion flag are set to “1”.
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APPLICATION
2.4 Multi-master I2 C-BUS interface
2.4 Multi-master I2 C-BUS interface
The multi-master I2C-BUS interface is a serial communication circuit, conforming to the Philips I 2C-BUS data
transfer format.
2.4.1 Memory map
002B16 I2C data shift register (S0)
002C16 I2C address register (S0D)
002D16 I2C status register (S1)
002E16 I2C control register (S1D)
002F16 I2C clock control register (S2)
003016 I2C START/STOP condition control register (S2D)
003C16 Interrupt request register 1 (IREQ1)
003E16 Interrupt control register 1 (ICON1)
Fig. 2.4.1 Memory map of registers relevant to I 2C-BUS interface
2.4.2 Relevant registers
I2C data shift register
b7 b6 b5 b4 b3 b2 b1 b0
I2C data shift register (S0) [Address : 2B 16]
Function
B
0 This register is an 8-bit shift register to store receive data or write
At reset
R W
?
transmit data.
1
?
2
?
3
?
4
?
5
?
6
?
7
?
Note: Secure 8 machine cycles from clearing MST bit to “0” (slave mode) until writing
data to I 2C data shift register.
If executing the read-modify-write instruction(SEB, CLB etc.) for this register
during transfer, data may become a value not intended.
Fig. 2.4.2 Structure of I2C data shift register
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APPLICATION
2.4 Multi-master I2 C-BUS interface
I2C address register
b7 b6 b5 b4 b3 b2 b1 b0
I2C address register (S0D) [Address : 2C 16 ]
B
0 Read / write bit (RWB)
1 Slave address
2
Function
At reset
0 : Write bit
1 : Read bit
These bits are compared with the
address data transmitted from the
master.
0
Name
(SAD0, SAD1, SAD2, SAD3,
SAD4, SAD5, SAD6)
R W
0
0
3
0
4
0
5
0
6
0
7
0
Note: If the read-modify-write instruction(SEB, CLB, etc.) is executed for this register
at detectiong the stop condition, data may become a value not to intend.
Fig. 2.4.3 Structure of I2C address register
I2C status register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address : 2D 16]
B
0
Function
At reset
0 : Last bit = “0”
1 : Last bit = “1”
( Note1)
0 : No general call detected
1 : General call detected( Note1, 2)
0 : Address disagreement
1 : Address agreement ( Note1, 2)
0 : Not detected
1 : Detected
( Note1)
0 : SCL pin low hold
1 : SCL pin low release ( Note3)
0 : Bus free
1 : Bus busy
?
✕
0
✕
0
✕
0
✕
00 : Slave receive mode
01 : Slave transmit mode
10 : Master receive mode
11 : Master transmit mode
0
Name
Last receive bit (LRB)
1 General call detecting flag
(AD0)
2 Slave address comparison
flag (AAS)
3 Arbitration lost detecting flag
(AL)
4 SCL pin low hold bit (PIN)
5 Bus busy flag (BB)
6 Communication mode
specification bits (TRX, MST)
7
R W
1
0
0
Notes 1: These bits and flags can be read out, but cannot be written.
2
2: These bits can be detected when data format select bit (ALS) of I C control
register is “0” .
3: “1” can be written to this bit, but “0” cannot be written by program.
4: Do not execute the read-modify-write instruction (SEB, CLB) for this refgister,
because all bits of this register are changed by hardware.
Fig. 2.4.4 Structure of I2C status register
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APPLICATION
2.4 Multi-master I2 C-BUS interface
I2C control register
b7 b6 b5 b4 b3 b2 b1 b0
I2C control register (S1D) [Address : 2E 16]
B
Name
0 Bit counter (Number of
transmit/receive bits)
(BC0, BC1, BC2)
1
2
3 I2C-BUS interface enable bit
(ES0)
4 Data format selection bit
(ALS)
5 Addressing format selection
bit (10 BIT SAD)
Function
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0:8
1:7
0:6
1:5
0:4
1:3
0:2
1:1
0
0 : Addressing format
1 : Free data format
0
0 : 7-bit addressing format
1 : 10-bit addressing format
0
0 : Connect to ports P2 2, P2 3
1 : Connect to ports P2 4, P2 5
(Note 1)
7 I2C-BUS interface pin input
0 : CMOS input
1 : SMBUS input
level selection bit (TISS)
R W
0
0 : Disabled
1 : Enabled
6 SDA/SCL pin selection bit
(TSEL)
At reset
0
0
Notes 1: When using P2 4 and P2 5 as I2C-BUS interface, they are automatically
switched from CMOS output to P-channel output disabled.
2: When the read-modify-write instruction is executed for this register at
detectiong the START condition or at completing the byte transfer, data
may become a value not intended.
Fig. 2.4.5 Structure of I2C control register
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APPLICATION
2.4 Multi-master I2 C-BUS interface
I2C clock control register
b7 b6 b5 b4 b3 b2 b1 b0
I2C clock control register (S2) [Address : 2F 16]
B
Function
Name
0 SCL frequency control bits
At reset
Refer to Table 2.4.1
0
0 : Standard clock mode
1 : High-speed clock mode
0 : ACK is returned
1 : ACK is not returned
0 : No ACK clock
1 : ACK clock
0
(CCR0, CCR1, CCR2, CCR3,
CCR4)
1
2
3
4
5 SCL mode specification bit
(FAST MODE)
6 ACK bit (ACK BIT)
7 ACK clock bit (ACK)
Fig. 2.4.6 Structure of I2C clock control register
Table 2.4.1 Set value of I2C clock control register and SCL frequency
Setting value of
CCR4–CCR0
CCR4 CCR3 CCR2 CCR1 CCR0
1
1
1
1
1
1
1
1
1
0
1
1
0
1
0
1
0
1
0
…
…
0
0
1
1
0
0
1
…
0
0
0
0
1
1
1
…
0
0
0
0
0
0
0
…
0
0
0
0
0
0
0
1
0
1
SCL frequency (Note)
(at φ = 4 MHz, unit : kHz)
Standard clock
mode
Setting disabled
Setting disabled
Setting disabled
– (Note 2)
– (Note 2)
100
83.3
500/CCR value
(Note 3)
17.2
16.6
16.1
High-speed
clock mode
Setting disabled
Setting disabled
Setting disabled
333
250
400 (Note 3)
166
1000/CCR value
(Note 3)
34.5
33.3
32.3
Notes 1: Duty of SCL clock output is 50 %. The duty becomes 35 to 45 % only when the high-speed clock mode is selected
and CCR value = 5 (400 kHz, at φ = 4 MHz). “H” duration of the clock fluctuates from –4 to +2 machine cycles in
the standard clock mode, and fluctuates from –2 to +2 machine cycles in the high-speed clock mode. In the case of
negative fluctuation, the frequency does not increase because “L” duration is extended instead of “H” duration
reduction.
These are value when SCL clock synchronization by the synchronous function is not performed. CCR value is the
decimal notation value of the SCL frequency control bits CCR4 to CCR0.
2: Each value of SCL frequency exceeds the limit at φ = 4 MHz or more. When using these setting value, use φ of
4 MHz or less.
3: The data formula of SCL frequency is described below:
φ/(8 ✕ CCR value) Standard clock mode
φ/(4 ✕ CCR value) High-speed clock mode (CCR value ≠ 5)
φ/(2 ✕ CCR value) High-speed clock mode (CCR value = 5)
Do not set 0 to 2 as CCR value regardless of φ frequency.
Set 100 kHz (max.) in the standard clock mode and 400 kHz (max.) in the high-speed clock mode to the S CL
frequency by setting the SCL frequency control bits CCR4 to CCR0.
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0
0
R W
APPLICATION
2.4 Multi-master I2 C-BUS interface
I2C START/STOP condition control register
b7 b6 b5 b4 b3 b2 b1 b0
0
I2C START/STOP condition control register (S2D) [Address : 30
B
Function
Name
0 START/STOP condition set bit
(SSC0, SSC1, SSC2, SSC3,
SSC4)
(Note)
SCL release time
= φ(µs) ✕ (SSC+1)
1
Set up time
= φ(µs) ✕ (SSC+1)/2
2
16]
At reset
R W
?
Hold time
= φ(µs) ✕ (SSC+1)/2
3
4
0 : Falling edge active
1 : Rising edge active
selection bit (SIP)
0 : SDA valid
S
CL
/S
DA
interrupt
pin
selection
6
1 : SCL valid
bit (SIS)
7 Fix this bit to “0”.
5 SCL/SDA interrupt pin polarity
0
0
0
Note : Fix SSC0 bit to “0”.
Fig. 2.4.7 Structure of I2C START/STOP condition control register
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address : 3C
B
Function
Name
0 INT 0 interrupt request bit
1 SCL/SDA interrupt request bit
2 INT 1 interrupt request bit
3 INT 2 interrupt request bit
4 INT 3 interrupt request bit
5 I2C interrupt request bit
6 Timer X interrupt request bit
7 Timer Y interrupt request bit
16]
At reset
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.4.8 Structure of Interrupt request register 1
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APPLICATION
2.4 Multi-master I2 C-BUS interface
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E
B
Function
Name
0 INT 0 interrupt enable bit
1 SCL/SDA interrupt enable bit
2 INT 1 interrupt enable bit
3 INT 2 interrupt enable bit
4 INT 3 interrupt enable bit
5 I2C interrupt enable bit
6 Timer X interrupt enable bit
7 Timer Y interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 2.4.9 Structure of Interrupt control register 1
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At reset
0
0
0
0
0
0
0
0
R W
APPLICATION
2.4 Multi-master I2 C-BUS interface
2.4.3 I2C-BUS overview
The I2C-BUS is a both directions serial bus connected with two signal lines; the SCL which transmits a
clock and the SDA which transmits a data.
Each port of the 3851 group has an N-channel open-drain structure for output and a CMOS structure for
input. The devices connected with the I 2C-BUS interface use an open drain, so that external pull-up
resistors are required. Accordingly, while any one of devices always outputs “L”, other devices cannot
output “H”.
Figure 2.4.10 shows the I2C-BUS connection structure.
SCL output
SCL output
SCL input
SCL input
SDA output
SDA output
SDA input
SDA input
SCL output
SCL input
SDA output
SDA input
Fig. 2.4.10 I2C-BUS connection structure
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APPLICATION
2.4 Multi-master I2 C-BUS interface
2.4.4 Communication format
Figure 2.4.11 shows an I 2C-BUS communication format example.
The I 2C-BUS consists of the following:
•START condition to indicate communication start
•Slave address and data to specify each device
•ACK to indicate acknowledgment of address and data
•STOP condition to indicate communication completion.
Bus busy term
S
Slave address
7 bits
R/W A
Data
8 bits
A
Data
8 bits
Data 0 to 7
ACK
Data 0 to 7
A P
SCL
SDA
Start Addresses 0 to 6 W ACK
ACK
Stop
Fig. 2.4.11 I2C-BUS communication format example
(1)
START condition
When communication starts, the master device outputs the START condition to the slave device. The
I2C-BUS defines that a data can be changed when a clock line is “L”. Accordingly, data change when
a clock line is “H” is treated as STOP or START condition.
The data line change from “H” to “L” when a clock line is “H” is START condition.
(2)
STOP condition
Just as in START condition, the data line change from “L” to “H” when a clock line is “H” is STOP
condition.
The term from START condition to STOP condition is called “Bus busy”. The master device is
inhibited from starting data transfer during that term.
The Bus busy status can be judged by using the BB flag of I2C status register (bit 5 of address
002D16).
(3)
Slave address
The slave address is transmitted after START condition. This address consists of 7 bits and the 7th bit functions as the read/write (R/W) bit which indicates a data transmission method. The slave
devices connected with the same I2C-BUS must have their addresses, individually. It is because that
address is defined for the master to specify the transmitted/received slave device.
The read/write (R/W) bit indicates a data transmission direction; “L” means write from the master to
the slave, and “H” means read in.
(4)
Data
The data has an 8-bit length. There are two cases depending on the read/write (R/W) bit of a slave
address; one is from the master to the slave and the other is from the slave to the master.
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2.4 Multi-master I2 C-BUS interface
(5)
ACK bit
The ACK bit clock is generated by the master. This is used for indication of acknowledgment on the
SDA line, the slave’s busy and the data end.
For example, the slave device makes the SDA line “L” for acknowledgment when confirming the slave
address following the START condition. The built-in I2C-BUS interface has the slave address automatic
judgment function and the ACK acknowledgment function. “L” is automatically output when the ACK
bit of I2C clock control register (bit 6 of address 002F16) is “0” and an address data is received. When
the slave address and the address data do not correspond, “H” (NACK) is automatically output.
In case the slave device cannot receive owing to an interrupt process, performing operation or
others, the master can output STOP condition and complete data transfer by making the ACK data
of the slave address “H” for acknowledgment. Even in case the slave device cannot receive a data
during data transferring, the communication can be interrupted by performing NACK acknowledgment
to the following data.
When the master is receiving the data from the slave, the master can notify the slave of completion
of data reception by performing NACK acknowledgment to the last data received from the slave.
(5)
RESTART condition
The master can receive or transmit data without transmission of STOP condition while the master is
transmitting or receiving a data.
For example, after the master transmitted a data to the slave, transmitting a slave address + R
(Read) following RESTART condition can make the following data treat as a reception data.
Additionally, transmitting a slave address + W (Write) following RESTART condition can make the
following data treat as a transmission data.
S
Slave address R/W A
7 bits
Master reception
1st-byte
RESTART condition
START condition
“0”
Write
Data
A Sr Slave address R/W A
8 bits
7 bits
Lower data
“1”
Read
8 bits
A
Master reception
2nd-byte
Upper data
A P
8 bits
NACK expresses end of
master reception data
S: START condition
P: STOP condition
Master to slave
A: ACK bit
R/W: Read/Write bit
Slave to master
Sr: RESTART condition
Fig. 2.4.12 RESTART condition of master reception
2.4.5 Synchronization and Arbitration lost
(1) Synchronization
When a plural master exists on the I 2C-BUS and the masters, which have different speed, are going
to simultaneously communicate; there is a rule to unify clocks so that a clock of each bit can be
output correctly.
Figure 2.4.13 shows a synchronized SCL line example. The SCL (A) and the SCL (B) are the master
devices having a different speed. The SCL is synchronized waveforms.
As shown by Figure 2.4.13, the SCL lines can be synchronized by the following method; the device
which first finishes “H” term makes the SCL line “L” and the device which last remains “L” makes the
SCL line “H”.
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➀
SCL(A)
➁
➂
➅
➄
SCL(B)
➃
➆
SCL
Fig. 2.4.13 SCL waveforms when synchronizing clocks
➀ After START condition, the masters, which have different speed, simultaneously start clock transmission.
➁ The SCL outputs “L” because (A) finished counting “H” output; then (B)’s “H” output counting is
interrupted and (B) starts counting “L” output.
➂ The (A) outputs “H” because (A) finished counting “L” term; the SCL level does not become “H”
because (B) outputs “L”, and counting “H” term does not start but stop.
➃ (B) outputs “L” term.
➄ The SCL outputs “H” because (B) finished counting “L” term; then (B)’s “H” output counting is
started at the same time as (A).
➅ The SCL outputs “L” because (A) first finished counting “H” output; then (B)’s “H” output counting
is interrupted and (B) starts counting “L” output.
➆ The above are repeatedly performed.
(2)
Clock synchronization during communication
In the I2C-BUS, the slave device is permitted to retain the SCL line “L” and become waiting status
for transmission from the master. By byte unit, for the reception preparation of the slave device, the
master can become waiting status by making the SCL line “L”, which is after completion of byte
reception or the ACK.
By bit unit, it is possible to slow down a clock speed by retaining the SCL line “L” for slave devices
having limited hardware.
The 3851 group can transmit data correctly without reduction of data bits toward waiting status
request from the slave device. It is because the synchronization circuit is included for the case when
retaining the SCL line “L” as an internal hardware.
After the last bit, including the ACK bit, of a transmission/reception data byte, the SCL line automatically
remains “L” and waiting status is generated until completion of an interrupt process or reception
preparation.
(3) Arbitration lost
A plural master exists on the same bus in the I2C-BUS and there are possibility to start communication
simultaneously. Even when the master devices having the same transmission frequency start
communication simultaneously, which device must transmit data correctly. Accordingly, there is the
definition to detect a communication confliction on the SDA line in the I 2C-BUS.
The SDA line is output at the timing synchronized by the SCL, however, the synchronization among
the SDA signals is not performed.
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2.4 Multi-master I2 C-BUS interface
2.4.6 SMBUS communication usage example
This clause explains a SMBUS communication control example using the I2C-BUS. This is a control example
as the master device and the slave device in the Read Word protocol of SMBUS protocol.
The following is a communication example of the “Voltage () command” of the Smart battery data.
Communication specifications:
•Communication frequency = 100 kHz
•Slave address of itself, battery, = “0001011X 2” (X means the read/write bit)
•Slave address of communication destination, host, = “0001000X2” (X means the read/write bit)
•Voltage () command = “09 16 ”
•Voltage value of acknowledgment = “2EE0 16 ”; 12000 mV)
•The communication process is performed in the interrupt process. However, the main process performs
an occurrence of the first START condition and a slave address set.
•A communication buffer is established. Data transfer between the main process and the interrupt process
is performed through the communication buffer.
(1)
Initial setting
Figure 2.4.14 shows an initial setting example using SMBUS communication.
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I2C address register (address 2C 16)
b7
S0D
b0
0 0 0 1 0 1 1 0
Set slave address value 16 16
I2C clock control register (address 2F 16)
b0
b7
S2
1 0 0 0 0 1 0 1
Set clock 100 kHz (X IN = 8MHz)
Standard clock mode
ACK is returned
ACK clock
I2C status register (address 2D 16)
b7
S1
0 0
b0
1
SCL pin low hold bit: fix to “1”
Slave receive mode
I2C START/STOP condition control register (address 30 16)
b7
S2D
b0
0 0 0 1 1 0 1 0
Set setup time hold time to 27 cycles (6.75 µs: X IN = 8 MHz)
SCL/SDA interrupt: Falling edge active
SCL/SDA interrupt: SDA valid
Fix to “0”
I2C control register (address 2E 16)
b7
S1D
b0
1 0 0 0 1 0 0 0
Set number of transmit/receive bits to “8”
I2C-BUS interface: enabled
Addressing format
7-bit addressing format
SCL/SDA:connect to ports P2 2, P23
Set SMBUS input level
Fig. 2.4.14 Initial setting example using SMBUS communication
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2.4 Multi-master I2 C-BUS interface
(2)
Communication example in master device
The master device follows the procedures ➀ to ➅ shown by Figure 2.4.15.
Additionally, the shaded area in the figure is a transmission data from the master device and the
white area is a transmission data from the slave device.
➀
➁
➂
➃
➄
➅
Generating of START condition; Transmission of slave address + write bit
Transmission of command
Generating of RESTART condition; Transmission of slave address + read bit
Reception of lower data
Reception of upper data
Generating of STOP condition
Figures 2.4.16 to 2.4.21 show the procedures ➀ to ➅.
➀
S
➁
➂
Slave address R/W A Command A Sr
7 bits
“0”
Write
8 bits
Interrupt request
➄
➃
Slave address R/W A
7 bits
Interrupt request
Lower data
“1”
Read
A
➅
Upper data
8 bits
8 bits
Interrupt request Interrupt request
S: START condition
P: STOP condition
Master to slave
A: ACK bit
R/W: Read/Write bit
Slave to master
A P
Interrupt request
Sr: RESTART condition
Fig. 2.4.15 Read Word protocol communication as SMBUS master device
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➀ Generating of START condition; Transmission of slave address + write bit
After confirming that other master devices do not use the bus, generate the START condition,
because the SMBUS is a multi-master.
Write “slave address + write bit” to the I2C data shift register (address 002B16 ) before performing
to make the START condition generate. It is because the SCL of 1-byte unit is output, following
occurrence of the START condition.
If other master devices start communication until an occurrence of the START condition after
confirming the bus use, it cannot communicate correctly. However in this case, that situation does
not affect other master devices owing to detection of an arbitration lost or the START condition
duplication preventing function.
1
(A)←00010000 2
SEI(Note 1)
• Interrupts disabled
1 (used)
BB (address 2D 16), bit5 ? (Note 2)
• Bus use confirmation
0 (not used)
S0(address 2B16) ← (A)
S1(address 2D 16) ←11110000 2
CLI(Note 1)
• Slave address value write
• Start condition occurrence
• Interrupt enabled
End
Notes 1: In this example, the SEI instruction to disable interrupts need not be executed
because this processing is going to be performed in the interrupt processing.
When the start condition is generated out of the interrupt processing, execute
the SEI instruction to disable interrupts.
2: Use the branch bit instruction to confirm bus busy.
Fig. 2.4.16 Transmission process of START condition and slave address
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2.4 Multi-master I2 C-BUS interface
➁ Transmission of command
Confirm correct completion of communication at ➀ before command transmission. When receiving
the STOP condition, a process not to transmit a command is required, because the internal I 2CBUS generates an interrupt request also owing to the STOP condition transmitted to other devices.
After confirming correct completion of communication, write a command to the I 2C data shift
register (address 002B16 ).
In case the AL bit (bit 3 of address 002D16 ) is “1”, check the slave address comparison flag (ASS
bit; bit 2 of address 002D 16) to judge whether the device given a right of master transmission owing
to an arbitration specifies itself as a slave address. When it is “1”, perform the slave reception;
when “0”, wait for a STOP condition occurrence caused by other devices and the communication
completion.
In case the AL bit is “0”, check the last received bit (LRB bit; bit 0 of address 002D 16). When it
is “1”, make the STOP condition generate and release the bus use, because the specified slave
device does not exist on the SMBUS.
2
1(error)
PIN (address 2D 16), bit 4 ?
• Judgment of bus hold
0(slave address transmitted)
1(detected)
AL (address 2D 16), bit 3 ?
• Judgment of arbitration lost detection
0(not detected)
1(NACK)
LRB (address 2D 16), bit 0 ?
• ACK confirmation
0(ACK)
S0(address 2B 16) ← 00001001 2
• Command data write to I 2C data shift register
End
Stop condition output
AAS (address 2D 16), bit 2 ?
0(address not corresponded)
Re-transmission preparation
• Judgment of slave address comparison
1(address corresponded)
Slave reception
Fig. 2.4.17 Transmission process of command
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➂ Generating of RESTART condition; Transmission of slave address + read bit
Confirm correct completion of communication at ➁ before generating the RESTART condition.
After confirming correct completion, generate the RESTART condition and perform the transmission
process of “slave address + read bit”. Note that procedure because that is different from ➀’s
process.
As the same reason as ➀, write “slave address + read bit” to the I2C data shift register (address
002B 16 ) before performing to make the START condition generate. However, when writing a slave
address to the I 2C data shift register in this condition, a slave address is output at that time.
Consequently, the RESTART condition cannot be generated. Therefore, follow the slave reception
procedure before those processes.
In case the arbitration lost detecting flag (AL bit, bit 3 of address 002D 16 ) is “1”, return to the
process ➀, because other master devices will have priority to communicate.
When the last received bit (LRB bit; bit 0 of address 002D 16) is “1”, generate the STOP condition
and make the bus release, because acknowledgment cannot be done owing to BUSY status of the
slave device specified on the SMBUS or other reasons.
3
1 (stop condition)
PIN (address 2D 16), bit 4 ?
• Bus judgment during hold
0(command transmission)
1 (detected)
AL (address 2D 16), bit 3 ?
• Judgment of arbitration lost detection
0(not detected)
1(NACK)
LRB (address 2D 16), bit 0 ?
• ACK confirmation
0(ACK)
S1(address 2D 16) ← 00000000 2 (Note 1)
• Slave receive mode set
(A) ← 00010001 2
• Slave address read out
SEI(Note 2)
S0(address 002B 16) ← (A)
S1(address 002D 16) ← 11110000 2
CLI(Note 2)
• Interrupt disabled
• Slave address value write
• RESTART condition occurrence
• Interrupt enabled
End
Re-transmission preparation
Stop condition output
Notes 1: Set to the receive mode while the PIN bit is “0”. Do not write “1” to the PIN bit.
2: In this example, the SEI instruction to disable interrupts need not be executed
because this processing is going to be performed in the interrupt processing.
When the start condition is generated out of the interrupt processing, execute
the SEI instruction to disable interrupts.
Fig. 2.4.18 Transmission process of RESTART condition and slave address + read bit
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2.4 Multi-master I2 C-BUS interface
➃ Reception of lower data
Confirm correct completion of communication at ➂ before receiving the lower data. After confirming
correct completion, clear the ACK bit (bit 6 of address 002F 16 ) to “0”, in which ACK is returned and
set to the master receive mode. After that, write a dummy data to the I 2C data shift register
(address 002B 16 ).
When the MST bit (bit 7 of address 002D16) is “0”, perform the error process explained as follows
and return to the process ➀.
When the last received bit (LRB bit; bit 0 of address 002D 16) is “1”, generate the STOP condition
and make the bus release, because the slave device specified on the SMBUS does not exist.
4
1(STOP condition)
PIN (address 2D 16), bit 4 ?
• Judgment of bus hold
0(transmission of RESTART
condition)
0(slave)
MST (address 2D 16), bit 7 ?
• Judgment of slave mode detection
1(master)
1(NACK)
LRB (address 2D 16), bit0 ?
• ACK confirmation
0(ACK)
S2(address 2F 16) ← 10000101 2
• “ACK clock is used” select and
“ACK is returned” set
S1(address 2D 16) ←10100000 2
• Master receive mode set
S0(address 2B 16) ← 11111111 2
• Dummy data to I 2C data shift register write
End
Stop condition output
1(detected)
AL (address 2D 16), bit 3 ?
• Judgment of arbitration lost detection
0(not detected)
Re-transmission preparation
Error processing
Fig. 2.4.19 Reception process of lower data
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➄ Transmission of upper data
Confirm correct completion of communication at ➃ before receiving the upper data. After confirming
correct completion, store the received data (lower data).
Set the ACK bit (bit 6 of address 002F16) to “1”, in which ACK is not returned, write a dummy data
to the I 2C data shift register (address 002B 16).
When the MST bit (bit 7 of address 002D16) is “0”, return to the process ➀, because other devices
have priority to communicate.
5
1(stop condition)
PIN (address 2D 16), bit 4 ?
• Judgment of bus hold
0(lower data transmitted)
0(slave)
MST (address 2D 16), bit 7 ?
• Judgment of slave mode detection
1(Master)
Receive data buffer ← S0(address 2B 16)
• Receive data read and save
S2(address 2F 16) ←11000101 2
• “NACK is returned” set
S0(address 2B 16) ← 11111111 2
• Dummy data to I 2C data shift register write
End
1(detected)
AL (address 2D 16), bit 3 ?
0(not detected)
Re-transmission preparation
Error processing
Fig. 2.4.20 Reception process of upper data
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• Judgment of arbitration lost detection
APPLICATION
2.4 Multi-master I2 C-BUS interface
➅ Generating of STOP condition
Confirm correct completion of communication at ➄ before generating the STOP condition. After
confirming correct completion, store the received data (upper data).
Clear the ACK bit (bit 6 of address 002F16 ) to “0”, in which ACK is returned, generate the STOP
condition. The communication mode is set to the slave receive mode by the occurrence of STOP
condition.
When the MST bit (bit 7 of address 002D16) is “0”, return to the process ➀, because other devices
have priority to communicate.
6
1(stop condition)
PIN (address 2D 16), bit 4 ?
• Judgment of bus hold
0(upper data transmitted)
1(detected)
AL (address 2D 16), bit 3 ?
• Judgment of arbitration lost detection
0(not detected)
Receive data buffer ← S0(address 2B 16)
S2(address 2F 16) ← 10000101 2
• Receive data read and save
• Set “ACK is returned”
S1(address 2D 16) ← 11010000 2
• Stop condition occurrence
BB (address 2D 16), bit5 ? (Note)
• Judgment of bus busy
1(bus busy)
0(bus free)
Re-transmission preparation
End
Note: Use the branch bit instruction to check bus busy.
Also, execute the time out processing separately, if neccessary.
Fig. 2.4.21 Generating of STOP condition
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(3)
Communication example in slave device
The slave device follows the procedures ➀ to ➅ shown by Figure 2.4.22.
The only difference from the master device’s communication is an occurrence of interrupt request
after detection of STOP condition.
➀
➁
➂
➃
➄
➅
Reception of START condition; Transmission of ACK bit due to slave address correspondence
Reception of command
Reception of RESTART condition; Reception of slave address + read bit
Transmission of lower data
Transmission of upper data
Reception of STOP condition
Figures 2.4.23 to 2.4.28 show the procedures ➀ to ➅.
➀
S
➁
➂
Slave address R/W A Command A Sr Slave address R/W A
7 bits
“0”
Write
8 bits
Interrupt request
7 bits
Interrupt request
➃
Lower data
“1”
Read
8 bits
Interrupt request
S: START condition
P: STOP condition
Master to slave
A: ACK bit
R/W: Read/Write bit
Slave to master
Sr: RESTART condition
Fig. 2.4.22 Communication example as SMBUS slave device
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A
➄➅
Upper data
A P
8 bits
Interrupt request
Interrupt Interrupt request
request
APPLICATION
2.4 Multi-master I2 C-BUS interface
➀ Reception of START condition; Transmission of ACK bit due to slave address correspondence
In the case of operation as the slave, all processes are performed in the interrupt after setting of
the slave reception in the main process, because an interrupt request does not occur until
correspondence of a slave address.
In the first interrupt, after confirming correspondence of the slave address, write a dummy data to
receive a command into the I2C data shift register.
1
1(stop condition)
PIN (address 2D 16), bit 4 ?
• Judgment of bus hold
0(slave address received)
0(not corresponded)
AAS (address 2D 16), bit 2 ?
• Judgment of slave address correspondence
1(corresponded)
S0(address 2B 16) ← 11111111 2
• Dummy data write to I 2C data shift register
End
S1(address 2D 16) ← 00010000 2
• Slave receive mode set
Error processing
Fig. 2.4.23 Reception process of START condition and slave address
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➁ Reception of command
Confirm correct completion of the command reception in the interrupt after receiving the command.
After confirming correct command from the host, write a dummy data to the I2C data shift register
to wait for reception of the next slave address.
2
1(stop condition)
PIN (address 2D 16), bit 4 ?
• Judgment of bus hold
0(command received)
Receive data buffer ← S0(address 2B 16)
• Receive data read and save
Judgment of receive command
S2(address 2F 16) ← 10000101 2
• “ACK clock is used” select and “ACK is returned” set
S0(address 2B 16) ← 11111111 2
• Dummy data write to I 2C data shift register
End
S1(address 2D 16) ← 00010000 2
• Slave receive mode set
Error end
Fig. 2.4.24 Reception process of command
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2.4 Multi-master I2 C-BUS interface
➂ Reception of RESTART condition ane slave address + read bit
After receiving a slave address, prepare a transmission data.
Judgment whether receiving a data or transmitting is required, because the mode is automatically
switched between the receive mode and the transmit mode depending on the R/W bit of the
received slave address. Accordingly, judge whether read or write referring the slave address
comparison flag (AAS bit; bit 2 of address 002D 16 ).
3
1(stop condition)
PIN (address 2D 16), bit 4 ?
• Judgment of bus hold
0 (lower data received)
0(not corresponded)
AAS (address 2D 16), bit 2 ?
1(corresponded)
TRX (address 2D 16), bit 6 ?
0(received)
• Judgment of transmit/receive mode
1(transmitted)
S0(address 2B 16) ← lower data
• Output lower data write to I 2C data shift register
End
Slave receive processing, etc.
End
S1(address 2D 16) ← 00010000 2
• Slave receive mode set
Error end
Fig. 2.4.25 Reception process of RESTART condition and slave address + read bit
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➃ Transmission of lower data
Before transmitting the upper data, restart to transmit the data at ➃ and confirm correct completion
of transmission of the lower data set in the slave address reception interrupt.
After that, transmit the upper data.
4
1(stop condition)
PIN (address 2D 16), bit 4 ?
• Judgment of bus hold
0(lower data transmission completed)
1(NACK)
LRB (address 2D 16), bit 0 ?
• ACK confirmation
0(ACK)
S0(address 2B 16) ←Upper data
• Output upper data write to I 2C data shift register
End
S1(address 2D 16) ← 00010000 2
• Slave receive mode set
Error end
Fig. 2.4.26 Transmission process of lower data
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2.4 Multi-master I2 C-BUS interface
➄ Transmission of upper data
Confirm correct completion of the upper data transmission. The master returns the NACK toward
the transmitted second-byte data, the upper data. Accordingly, confirm that the last received bit
(LRB bit; bit 0 of address 002D 16 ) is “1”.
After that, write a dummy data to the I2C data shift register (address 002B 16) and wait for the
interrupt of STOP condition.
5
1(stop condition)
PIN (address 2D 16), bit 4 ?
• Judgment of bus hold
0(upper data transmission completed)
0(ACK)
LRB (address 2D 16), bit 0 ?
• ACK confirmation
1(NACK)
S0(address 2B 16) ← 11111111 2
• Dummy data write to I 2C data shift register
End
S1(address 2D 16) ← 00010000 2
• Slave receive mode set
Error end
Note: Use the branch bit instruction to check bus busy.
Fig. 2.4.27 Transmission process of upper data
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➅ Reception of STOP condition
Confirm that the STOP condition is correctly output and the bus is released.
6
0(address or data received)
PIN (address 2D 16), bit 4 ?
• Judgment of bus hold
1(stop condition)
End processing
S1(address 2D 16) ← 00010000 2
• Slave receive mode set
End
S1(address 2D 16) ← 00010000 2
Error end
Fig. 2.4.28 Reception of STOP condition
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• Slave receive mode set
APPLICATION
2.4 Multi-master I 2C-BUS interface
2.4.7 Notes on multi-master I 2C-BUS interface
(1) Read-modify-write instruction
Each register of the multi-master I 2C-BUS interface has bits to change by hardware. The precautions
when the read-modify-write instruction such as SEB, CLB etc. is executed for each register of the
multi-master I 2C-BUS interface are described below.
➀ I2C data shift register (S0: address 002B16 )
When executing the read-modify-write instruction for this register during transfer, data may become
a value not intended.
➁ I2C address register (S0D: address 002C 16)
When the read-modify-write instruction is executed for this register at detecting the STOP condition,
data may become a value not intended.
● Reason
It is because hardware changes the read/write bit (RBW) at detecting the STOP condition.
➂ I2C status register (S1: address 002D16 )
Do not execute the read-modify-write instruction for this register because all bits of this register
are changed by hardware.
➃ I2C control register (S1D: address 002E 16)
When the read-modify-write instruction is executed for this register at detecting the START condition
or at completing the byte transfer, data may become a value not intended.
● Reason
Because hardware changes the bit counter (BC0 to BC2).
➄ I2C clock control register (S2: address 002F16 )
The read-modify-write instruction can be executed for this register.
➅ I2C START/STOP condition control register (S2D: address 0030 16)
The read-modify-write instruction can be executed for this register.
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(2) START condition generating procedure using multi-master
➀ Procedure example (The necessary conditions of the generating procedure are described as the
following ➁ to ➄.
LDA #SLADR
(Taking out of slave address value)
SEI
(Interrupt disabled)
BBS 5, S1, BUSBUSY (BB flag confirming and branch process)
BUSFREE:
STA S0
(Writing of slave address value)
LDM #$F0, S1
(Trigger of START condition generating)
CLI
(Interrupt enabled)
:
:
BUSBUSY:
CLI
(Interrupt enabled)
:
:
➁ Use “Branch on Bit Set” of “BBS 5, S1, –” for the BB flag confirming and branch process.
➂ Use “STA, STX” or “STY” of the zero page addressing instruction for writing the slave address
value to the I2C data shift register (S0: address 002B16 ).
➃ Execute the branch instruction of above 2 and the store instruction of above 3 continuously shown
the above procedure example.
➄ Disable interrupts during the following three process steps:
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating
(3) RESTART condition generating procedure in master
➀ Procedure example (The necessary conditions of the generating procedure are described as the
following ➁ to ➃). Execute the following procedure when the PIN bit is “0”.
LDM #$00, S1
(Select slave receive mode)
LDA #SLADR
(Taking out of slave address value)
SEI
(Interrupt disabled)
STA S0
(Writing of slave address value)
LDM #$F0, S1
(Trigger of RESTART condition generating)
CLI
(Interrupt enabled)
:
:
➁ Select the slave receive mode when the PIN bit is “0”. Do not write “1” to the PIN bit. Neither “0” nor
“1” is specified for the writing to the BB bit. The TRX bit becomes “0” and the SDA pin is released.
➂ The SCL pin is released by writing the slave address value to the I2C data shift register.
➃ Disable interrupts during the following two process steps:
• Writing of slave address value
• Trigger of RESTART condition generating
(4) Writing to I 2C status register
Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and
TRX bits to “0” from “1” simultaneously. It is because it may enter the state that the SCL pin is
released and the SDA pin is released after about one machine cycle. Do not execute an instruction
to set the MST and TRX bits to “0” from “1” simultaneously when the PIN bit is “1”. It is because it
may become the same as above.
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2.4 Multi-master I 2C-BUS interface
(5) STOP condition generating procedure in master
➀ Procedure example (The necessary conditions of the generating procedure are described as the
following ➁ to ➄).
SEI
(Interrupt disabled)
LDM #$C0, S1
(Select master transmit mode)
NOP
(Set NOP)
LDM #$D0, S1
(Trigger of STOP condition generating)
CLI
(Interrupt enabled)
:
:
➁ When setting the master transmit mode, write “0” to the PIN bit.
➂ Execute the NOP instruction after the master transmit mode is set. In addition, set the STOP
condition to be triggered within 10 machine cycles after the master transmit mode has been set.
➃ Make sure all interrupts are disabled during the term from when the master transmit mode is set
until the triggering process, which generates the STOP condition, is complete.
➄ The above procedure is only applicable to the M38513E4.
(6) Process of after STOP condition generating
Do not write data in the I2C data shift register S0 and the I 2C status register S1 until the bus busy
flag BB becomes “0” after generating the STOP condition in the master mode. It is because the
STOP condition waveform might not be normally generated. Reading to the above registers do not
have the problem.
(7) STOP condition input at 7th clock pulse
In the slave mode, the STOP condition is input at the 7th clock pulse while receiving a slave address
or data. As the clock pulse is continuously input, the SDA line may be held at LOW even if flag BB
is set to “0”.
Countermeasure:
Write dummy data to the I2C shift register or reset the ES0 bit in the S1D register (ES0 = “L” →
ES0 = “H”) during a stop condition interrupt routine with flag PIN = “1”.
Note: Do not use the read-modify-write instruction at this time. Furthermore, when the ES0 bit is
set to “0”, it becomes a general-purpose port ; so that the port must be set to input mode or “H”.
Note: The M38514E6/M6 does not have this problem which is the SDA line remaining “L”.
(8) ES0 bit switch
In standard clock mode when SSC = “000102” or in high-speed clock mode, flag BB may switch to
“1” if ES0 bit is set to “1” when SDA is “L”.
Countermeasure:
Set ES0 to “1” when SDA is “H”.
3850/3851 Group User’s Manual
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APPLICATION
2.4 Multi-master I2C-BUS interface
2.4.8 Notes on programming for SMBUS interface
(1) Time out process
For a smart battery system, the time out process with a program is required so that the communication
can be completed even when communication is interrupted. It is because there is possibility of
extracting a battery from a PC.
The specifications are defined so that communication has been able to be completed within 25 ms
from START condition to STOP condition and within 10 ms from the ACK pulse from the ACK pulse
of each byte. Accordingly, the following two should be considered as count start conditions.
➀ SDA falling edge caused by SCL/SDA interrupt
This is the countermeasure for a communication interrupt in the middle of from START condition
to a slave address. However, the detection condition must be considered because a interrupt is
also generated by communication from other masters to other slaves.
➁ SMBUS interrupt after receiving slave address
This is the countermeasure for when communication is interrupted from receiving a slave address
until receiving a command.
(2) Low hold of communication line
The I2C-BUS interface conforms to the I2C-BUS Standard Specifications. However, because the use
condition of SMBUS differs from the I 2C-BUS’s, there is possibility of occurrences of the following two
problems.
➀ Low hold of SDA line caused by ACK pulse at voltage drop of communication line
When the SMBUS voltage slowly drops, that is caused by extracting a battery from equipment or
turning off a PC’s power or etc., it might be incorrectly treated as the SCL pulse near the threshold
level voltage.
When the SDA is judged “L” in that condition, it becomes the general call and the ACK is transmitted.
However, when the SCL remains “L” at the ACK pulse, the SDA continuously remains “L” until
input of the next SCL pulse.
Countermeasure:
As explained before, start the time out count at the falling of SDA line of START condition and
reset ES0 bit of the S1D register when the time out is satisfied (Note).
➁ STOP condition input at 7th clock pulse
In the slave mode, the STOP condition is input at the 7th clock pulse while receiving a slave
address or data. As the clock pulse is continuously input, the SDA line may be held at “L” even
if flag BB is set to “0”.
Countermeasure:
Write dummy data to the I2C shift register or reset the ES0 bit in the S1D register (ES0 = “L”
→ ES0 = “H”) during a stop condition interrupt routine with flag PIN = “1”.
Note: Do not use the read-modify-write instruction at this time. Furthermore, when the ES0 bit is
set to “0”, it becomes a general-purpose port ; so that the port must be set to input mode
or “H”.
Note: The M38514E6/M6 does not have this problem which is the SDA line remaining “L”.
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3850/3851 Group User’s Manual
APPLICATION
2.5 PWM
2.5 PWM
This paragraph explains the registers setting method and the notes relevant to the PWM.
2.5.1 Memory map
001D16
PWM control register (PWMCON)
001E 16
PWM prescaler (PREPWM)
001F 16
PWM register (PWM)
Fig. 2.5.1 Memory map of registers relevant to PWM
2.5.2 Related registers
PWM control register
b7 b6 b5 b4 b3 b2 b1 b0
PWM control register(PWMCON) [Address : 1D 16]
B
Name
Function
0: PWM disabled
1: PWM enabled
0: f(X IN)
1: f(X IN)/2
0
PWM function enable bit
1
Count source selection bit
2
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the valeu are “0”.
At reset
R W
0
0
0
✕
3
0
✕
4
0
✕
5
0
✕
6
0
✕
7
0
✕
Fig. 2.5.2 Structure of PWM control register
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APPLICATION
2.5 PWM
PWM prescaler
b7 b6 b5 b4 b3 b2 b1 b0
PWM prescaler (PREPWM) [Address : 1E 16]
B
Name
Function
0 • Set a PWM period.
At reset
R W
?
• The values set in this register is written to both the PWM
prescaler pre-latch and the PWM prescaler latch at the same
time.
2 • When data is written during PWM outputting, the pulses
corresponding to the changed contents are output starting at
the next cycle.
3 • When this register is read out, the contents of the PWM
prescaler latch is read out.
1
?
?
?
4
?
5
?
6
?
7
?
Fig. 2.5.3 Structure of PWM prescaler
PWM register
b7 b6 b5 b4 b3 b2 b1 b0
PWM register (PWM) [Address : 1F 16]
B
Name
Function
0 • Set a “H” level output period of PWM.
• The values set in this register is written to both the PWM
1
register pre-latch and the PWM register latch at the same
time.
2 • When data is written during PWM outputting , the pulses
corresponding to the changed contents are output starting at
the next cycle.
3 • When this register is read out, the contents of the PWM register
latch is read out.
?
?
?
?
4
?
5
?
6
?
7
?
Fig. 2.5.4 Structure of PWM register
2-86
At reset
3850/3851 Group User's Manual
R W
APPLICATION
2.5 PWM
2.5.3 PWM output circuit application example
<Motor control>
Outline : The rotation speed of the motor is controlled by using PWM (pulse width modulation) output.
Figure 2.5.5 shows a connection diagram ; Figures 2.5.6 shows PWM output timing, and Figure 2.5.7
shows a setting of the related registers.
P44/PWM
M
D-A converter
Motor driver
3851 group
Fig. 2.5.5 Connection diagram
Specifications : • Motor is controlled by using the PWM output function of 8-bit resolution.
• Clock f(XIN) = 5.0 MHz
• “T”, PWM cycle : 102 s
• “t”, “H” level width of output pulse : 40 s (Fixed speed)
✽ A motor speed can be changed by modifying the “H” level width of output pulse.
t = 40 s
PWM output
T = 102 s
Fig. 2.5.6 PWM output timing
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APPLICATION
2.5 PWM
PWM control register (Address : 1D 16)
b7
b0
0 1
PWMCON
PWM function enable bit : PWM enabled (Note)
Count source selection bit : f(X IN)
Note : The PWM output function has priority
even when bit 4 (corresponding bit to P4 4 pin)
of Port P4 direction register is set to “0”
(input mode).
PWM prescaler (Address : 1E 16)
b7
b0
n
PREPWM
Set “T”, PWM cycle
n=1
[Equation]
255 ✕ (n + 1)
T=
f(XIN)
Set “t”, “H” level width of PWM
m = 100
[Equation]
T✕m
t=
255
PWM register (Address : 1F 16)
b7
b0
m
PWM
Fig. 2.5.7 Setting of related registers
<About PWM output>
1. Set the PWM function enable bit to “1” : The P44/PWM pin is used as the PWM pin.
The pulse beginning with “H” level pulse is output.
2. Set the PWM function enable bit to “0” : The P44/PWM pin is used as the port P44.
Thus, when fixing the output level, take the following procedure:
(1) Write an output value to bit 4 of the port P4 register.
(2) Write “00010002” to the port P4 direction register.
3. After data is set to the PWM prescaler and the PWM register, the PWM waveforms corresponding to updated
data will be output from the next repetitive cycle.
PWM output
Change PWM
output data
From the next repetitive cycle,
output modified data
Fig. 2.5.8 PWM output
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APPLICATION
2.5 PWM
Control procedure : By setting the related registers as shown by Figure 2.5.7, PWM waveforms are output to
the externals. This PWM output is integrated through the low pass filter, and that
converted into DC signals is used for control of the motor.
Figure 2.5.9 shows control procedure.
~
~
• X : This bit is not used here.
Set it to “0” or “1” arbitrarily.
P4 (Address : 08 16), bit4
P4D (Address : 09 16)
0
XXX1XXXX 2
• “L” level output from P4 4/PWM pin
PREPWM (Address : 1E 16)
PWM
(Address : 1F 16)
PWMCON (Address : 1D 16)
1
100
XXXXXX01 2
• Set the PWM period.
• Set the “H” level width of PWM.
• Select the PWM count source, and enable the PWM output.
~
~
Fig. 2.5.9 Control procedure
2.5.4 Notes on PWM
The PWM starts after the PWM enable bit is set to enable and “L” level is output from the PWM pin.
The length of this “L“ level output is as follows:
n + 1
2 • f(X IN)
sec.
(Count source selection bit = 0, where n is the value set in the prescaler)
n + 1
f(X IN)
sec.
(Count source selection bit = 1, where n is the value set in the prescaler)
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APPLICATION
2.6 A-D converter
2.6 A-D converter
This paragraph explains the registers setting method and the notes relevant to the A-D converter.
2.6.1 Memory map
003416
A-D control register (ADCON)
003516
A-D conversion register (low-order); (ADL)
003616
A-D conversion register (high-order); (ADH)
003D16
Interrupt request register 2 (IREQ2)
003F16
Interrupt control register 2 (ICON2)
Fig. 2.6.1 Memory map of registers relevant to A-D converter
2.6.2 Relevant registers
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register (ADCON) [Address : 34 16 ]
B
Name
0
Analog input pin selection bits
Function
b2 b1 b0
0
0
0
0
1
1
1
1
1
2
0
0
1
1
0
0
1
1
0 : P3 0/AN0
1 : P3 1/AN1
0 : P3 2/AN2
1 : P3 3/AN3
0 : P3 4/AN4
1 : P3 5/AN5
0 : P3 6/AN6
1 : P3 7/AN7
R W
0
0
0
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
AD conversion completion bit 0 : Conversion in progress
1 : Conversion completed
0
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
0
✕
6
0
✕
7
0
✕
3
4
5
Fig. 2.6.2 Structure of A-D control register
2-90
At reset
3850/3851 Group User’s Manual
✕
1
APPLICATION
2.6 A-D converter
A-D conversion register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (high-order) (ADH) [Address : 36
B
Name
16 ]
Function
At reset
R W
?
✕
?
✕
?
✕
3
?
✕
4
?
✕
5
?
✕
6
?
✕
7
?
✕
0 The read-only register in which the A-D conversion’s results are
stored.
b7
1
< 10-bit read>
b0
b9 b8
2
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
Fig. 2.6.3 Structure of A-D conversion register (high-order)
A-D conversion register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (low-order) (ADL) [Address : 35
B
16]
Function
At reset
R W
?
✕
?
✕
b0
?
✕
b9 b8 b7 b6 b5 b4 b3 b2
?
✕
< 10-bit read>
?
✕
?
✕
6
?
✕
7
?
✕
0 The read-only register in which the A-D conversion’s results are
stored.
1
2
3
b7
4
b7
5
< 8-bit read>
b0
b7 b6 b5 b4 b3 b2 b1 b0
Fig. 2.6.4 Structure of A-D conversion register(low-order)
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APPLICATION
2.6 A-D converter
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2) [Address : 3D
B
16]
Function
Name
At reset
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
CNTR
1
interrupt
request
bit
0 : No interrupt request issued
5
1 : Interrupt request issued
6 AD converter interrupt request 0 : No interrupt request issued
1 : Interrupt request issued
bit
Nothing
is
allocated
for
this
bit.
This
is a write disabled bit.
7
When this bit is read out, the value is “0”.
0
✽
0
✽
0
✽
0
✕
0 Timer 1 interrupt request bit
1 Timer 2 interrupt request bit
2 Serial I/O receive interrupt
request bit
3 Serial I/O transmit interrupt
request bit
4 CNTR 0 interrupt request bit
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.6.5 Structure of Interrupt request register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2 (ICON2) [Address : 3F 16]
B
Function
Name
0 Timer 1 interrupt enable bit
1 Timer 2 interrupt enable bit
2 Serial I/O receive interrupt
enable bit
3 Serial I/O transmit interrupt
enable bit
4 CNTR 0 interrupt enable bit
5 CNTR 1 interrupt enable bit
6 AD converter interrupt enable
bit
7 Fix this bit to “0”.
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 2.6.6 Structure of Interrupt control register 2
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At reset
0
0
0
0
0
0
0
0
R W
APPLICATION
2.6 A-D converter
2.6.3 A-D converter application examples
(1) Conversion of analog input voltage
Outline : The analog input voltage input from a sensor is converted to digital values.
Figure 2.6.7 shows a connection diagram, and Figure 2.6.8 shows the relevant registers setting.
Sensor
P30/AN0
3851 Group
Fig. 2.6.7 Connection diagram
Specifications : •The analog input voltage input from a sensor is converted to digital values.
•P30/AN0 pin is used as an analog input pin.
A-D control register (address 34 16)
b7
ADCON
b0
0
0 0 0
Analog input pin : P3 0/AN0 selected
A-D conversion start
A-D conversion register (high-order); (address 36 16)
b7
b0
(Read-only)
ADH
A-D conversion register (low-order); (address 35 16)
b7
b0
(Read-only)
ADL
A result of A-D conversion is stored ( Note).
Note: After bit 4 of ADCON is set to “1”, read out that contents.
When reading 10-bit data, read address 0036 16 before address 0035 16;
when reading 8-bit data, read address 0035 16 only.
Fig. 2.6.8 Relevant registers setting
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APPLICATION
2.6 A-D converter
An analog input signal from a sensor is converted to the digital value according to the relevant
registers setting shown by Figure 2.6.8. Figure 2.6.9 shows the control procedure for 8-bit read, and
Figure 2.6.10 shows the control procedure for 10-bit read.
ADCON (address 34 16), bit2 – bit0
ADCON (address 34 16), bit4
•P3 0/AN0 pin selected as analog input pin
•A-D conversion start
0002
0
0
ADCON (address 34 16), bit4 ?
•Judgment of A-D conversion completion
1
•Read out of conversion result
Read out ADL (address 35 16)
Fig. 2.6.9 Control procedure for 8-bit read
ADCON (address 34 16), bit2 – bit0
ADCON (address 34 16), bit4
ADCON (address 34 16), bit4 ?
•P3 0/AN0 pin selected as analog input pin
•A-D conversion start
0002
0
0
•Judgment of A-D conversion completion
1
Read out ADH (address 36 16)
•Read out of high-order digit (b9, b8) of conversion result
Read out ADL (address 35 16)
•Read out of low-order digit (b7 – b0) of conversion result
Fig. 2.6.10 Control procedure for 10-bit read
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APPLICATION
2.6 A-D converter
2.6.4 Notes on A-D converter
(1) Analog input pin
Make the signal source impedance for analog input low, or equip an analog input pin with an external
capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application products on the
user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A-D conversion precision to be worse.
(2) A-D converter power source pin
Pins AV CC and AV SS are A-D converter power source pins. Regardless of using the A-D conversion
function or not, connect them as following :
• AVCC : Connect to the VCC line
• AVSS : Connect to the V SS line
● Reason
If the A VCC and the AVSS pin are opened, the microcomputer may have a failure because of noise
or others. Also, if the AVCC pin is connected to the VSS pin, current flows from AVCC to VSS .
(3) Clock frequency during A-D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A-D conversion.
• f(X IN) is 500 kHz or more
• Do not execute the STP instruction and WIT instruction
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APPLICATION
2.7 Reset
2.7 Reset
2.7.1 Connection example of reset IC
VCC
1
Power source
M62022L
5
Output
RESET
Delay capacity
4
GND
0.1 µF
3
VSS
3851 Group
Fig. 2.7.1 Example of poweron reset circuit
Figure 2.7.2 shows the system example which switches to the RAM backup mode by detecting a drop of
the system power source voltage with the INT interrupt.
System power
source voltage
+5 V
VCC
+
7
VCC1
RESET 5
2
VCC2
INT
V1
Cd
3
RESET
INT0
VSS
1
GND
4
6
M62009L,M62009P,M62009FP
Fig. 2.7.2 RAM backup system
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3851 Group
APPLICATION
2.7 Reset
2.7.2 Notes on RESET pin
Connecting capacitor
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the VSS pin. Use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
● Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
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APPLICATION
2.7 Reset
MEMORANDUM
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CHAPTER 3
APPENDIX
3.1 Electrical characteristics
3.2 Standard characteristics
3.3 Notes on use
3.4 Countermeasures against noise
3.5 List of registers
3.6 Mask ROM confirmation form
3.7 ROM programming confirmation form
3.8 Mark specification form
3.9 Package outline
3.10 Machine instructions
3.11 List of instruction codes
3.12 SFR memory map
3.13 Pin configurations
APPENDIX
3.1 Electrical characteristics
3.1 Electrical characteristics
3.1.1 Absolute maximum ratings
Table 3.1.1 Absolute maximum ratings
Symbol
VCC
Parameter
Input voltage
VI
VI
VI
VI
VO
VO
Pd
Topr
Tstg
3-2
Conditions
M38513E4/M4
M38514E6
M38514M6
Power source voltage
P00–P07 , P10–P17,
P24–P27 , P30–P34,
VREF
Input voltage P22, P23
Input voltage RESET, X IN
Input voltage CNVSS
Output voltage P00–P07 , P10–P17,
P24–P27 , P30–P34,
XOUT
Output voltage P22, P23
Power dissipation
Operating temperature
Storage temperature
P20 , P21,
P40–P44 ,
All voltages are based on VSS.
Output transistors are cut off.
P20 , P21,
P40–P44 ,
Ta = 25 °C
3850/3851 Group User’s Manual
Ratings
–0.3 to 7.0
Unit
V
–0.3 to 6.5
–0.3 to VCC +0.3
V
–0.3 to 5.8
–0.3 to VCC +0.3
–0.3 to 13
V
V
V
–0.3 to VCC +0.3
V
–0.3 to 5.8
300
–20 to 85
–40 to 125
V
mW
°C
°C
APPENDIX
3.1 Electrical characteristics
3.1.2 Recommended operating conditions
Table 3.1.2 Recommended operating conditions (1)
(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
VCC
VSS
VREF
AVSS
VIA
VIH
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
ΣI OH(peak)
ΣI OH(peak)
ΣI OL(peak)
ΣI OL(peak)
ΣI OL(peak)
ΣI OH(avg)
ΣI OH(avg)
ΣI OL(avg)
ΣI OL(avg)
ΣI OL(avg)
Parameter
Power source voltage (At 8 MHz)
Power source voltage (At 4 MHz)
Power source voltage
A-D convert reference voltage
Analog power source voltage
Analog input voltage
AN 0–AN4
“H” input voltage
P00–P07, P10 –P17, P20–P27 , P30–P34, P40 –P44
“H” input voltage (when I2C-BUS input level is selected)
SDA1, SCL1
“H” input voltage (when I2C-BUS input level is selected)
SDA2, SCL2
“H” input voltage (when SMBUS input level is selected)
SDA1, SCL1
“H” input voltage (when SMBUS input level is selected)
SDA2, SCL2
“H” input voltage
RESET, XIN, CNV SS
“L” input voltage
P00–P07, P10 –P17, P20–P27 , P30–P34, P40 –P44
“L” input voltage (when I2 C-BUS input level is selected)
SDA1, SDA2, SCL1, SCL2
“L” input voltage (when SMBUS input level is selected)
SDA1, SDA2, SCL1, SCL2
“L” input voltage
RESET, CNV SS
“L” input voltage
XIN
“H” total peak output current
P00–P07 , P10–P17, P3 0–P34 (Note)
“H” total peak output current
P20, P2 1, P24–P27, P4 0–P44 (Note)
“L” total peak output current
P00–P07 , P10–P12, P3 0–P34 (M38513E4/M4)
(Note)
P00–P07 , P30–P34 (M38514E6/M6)
“L” total peak output current
P13–P17 (M38513E4/M4)
(Note)
P10–P17 (M38514E6/M6)
“L” total peak output current
P20 –P27 ,P40–P44 (Note)
“H” total average output current P00–P07 , P10–P17, P3 0–P34 (Note)
“H” total average output current P20, P2 1, P24–P27, P4 0–P44 (Note)
“L” total average output current P00–P07 , P10–P12, P3 0–P34 (M38513E4/M4)
(Note)
P00–P07 , P30–P34 (M38514E6/M6)
“L” total average output current P13–P17 (M38513E4/M4)
(Note)
P10–P17 (M38514E6/M6)
“L” total average output current P20 –P27 ,P40 –P44 (Note)
Min.
4.0
2.7
Limits
Typ.
5.0
5.0
0
Max.
5.5
5.5
Unit
V
AVSS
0.8VCC
VCC
VCC
V
V
V
V
V
0.7VCC
5.8
V
0.7VCC
VCC
V
1.4
5.8
V
1.4
VCC
V
0.8VCC
0
VCC
0.2V CC
V
V
0
0.3V CC
V
0
0.6
V
0
0.2V CC
0.16VCC
V
V
–80
–80
mA
mA
80
mA
80
120
80
–40
–40
mA
mA
mA
mA
mA
40
mA
40
60
40
mA
mA
mA
2.0
VCC
0
0
Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
3850/3851 Group User’s Manual
3-3
APPENDIX
3.1 Electrical characteristics
Table 3.1.3 Recommended operating conditions (2)
(V CC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOL(avg)
IOL(avg)
f(XIN)
f(XIN)
Parameter
“H” peak output current
P00–P07, P10 –P17, P20, P21 , P24–P27, P30 –P34,
P40–P44 (Note 1)
“L” peak output current
P00–P07, P10 –P12, P20–P27, P3 0–P34, P40–P44
(Note 1)
(M38513E4/M4)
P00–P07, P20–P27, P30–P34, P40–P44 (M38514E6/M6)
“L” peak output current
P13–P17 (M38513E4/M4)
(Note 1)
P10–P17 (M38514E6/M6)
“H” average output current
P00–P07, P10 –P17, P20, P21 , P24–P27, P30 –P34,
P40–P44 (Note 2)
“L” average output current
P00–P07, P10 –P12, P20–P27, P3 0–P34, P40–P44
(Note 2)
(M38513E4/M4)
P00–P07, P20–P27, P30–P34, P40–P44 (M38514E6/M6)
“L” peak output current
P13–P17 (M38513E4/M4)
(Note 2)
P10–P17 (M38514E6/M6)
Internal clock oscillation frequency (VCC = 4.0 to 5.5V) (Note 3)
Internal clock oscillation frequency (VCC = 2.7 to 5.5V) (Note 3)
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current I OL(avg), IOH(avg) are average value measured over 100 ms.
3: When the oscillation frequency has a duty cycle of 50%.
3-4
3850/3851 Group User’s Manual
Min.
Limits
Typ.
Max.
Unit
–10
mA
10
mA
20
mA
–5
mA
5
mA
15
mA
8
4
MHz
MHz
APPENDIX
3.1 Electrical characteristics
3.1.3 Electrical characteristics
Table 3.1.4 Electrical characteristics (1)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
VOH
VOL
VOL
VOL
VOL
Parameter
Test conditions
“H” output voltage
P00–P07, P10 –P17 , P20, P21,
P24–P27, P30–P34 , P40–P44
(Note)
“L” output voltage
P00–P07, P10–P12 , P20–P27
P30–P34, P40–P44
(M38513E4/M4)
“L” output voltage
P00–P07, P20–P27 , P30–P34,
P40–P44 (M38514E6/M6)
“L” output voltage
P13–P17 (M38513E4/M4)
“L” output voltage
P10–P17 (M38514E6/M6)
I OH = –10 mA
VCC = 4.0–5.5 V
I OH = –1.0 mA
VCC = 2.7–5.5 V
I OL = 10 mA
VCC = 4.0–5.5 V
IOL = 1.0 mA
VCC = 2.7–5.5 V
I OL = 10 mA
VCC = 4.0–5.5 V
IOL = 1.0 mA
VCC = 2.7–5.5 V
I OL = 20 mA
VCC = 4.0–5.5 V
I OL = 10 mA
VCC = 2.7–5.5 V
I OL = 20 mA
VCC = 4.0–5.5 V
I OL = 10 mA
VCC = 2.7–5.5 V
Min.
Typ.
Max.
Unit
VCC–2.0
V
VCC–1.0
V
2.0
V
1.0
V
2.0
V
1.0
V
2.0
V
1.0
V
2.0
V
1.0
V
VT+ –VT–
Hysteresis
CNTR0, CNTR1 , INT0–INT 3
0.4
V
VT+ –VT–
Hysteresis
RxD, SCLK, SDA1, SDA2, SCL1, SCL2
0.5
V
0.5
V
VT+ –VT–
IIH
IIH
IIH
IIL
IIL
IIL
VRAM
Hysteresis RESET
“H” input current
P00–P07, P10 –P17 , P20, P21,
P24–P27, P30–P34 , P40–P44
“H” input current RESET, CNV SS
“H” input current XIN
“L” input current
P00–P07, P10–P17 , P20–P27
P30–P34, P40–P44
“L” input current RESET,CNVSS
“L” input current XIN
RAM hold voltage
VI = VCC
5.0
µA
VI = VCC
VI = VCC
5.0
µA
µA
–5.0
µA
–5.0
µA
µA
V
4
VI = VSS
VI = VSS
VI = VSS
When clock stopped
–4
2.0
5.5
Note: P25 is measured when the P25/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
3850/3851 Group User’s Manual
3-5
APPENDIX
3.1 Electrical characteristics
Table 3.1.5 Electrical characteristics (2)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
I CC
Limits
Parameter
Power source current
Test conditions
Min.
High-speed mode
f(XIN) = 8 MHz
f(XCIN ) = 32.768 kHz
Output transistors “off”
High-speed mode
f(XIN) = 8 MHz (in WIT state)
f(XCIN ) = 32.768 kHz
Output transistors “off”
Low-speed mode
f(XIN) = stopped
f(XCIN ) = 32.768 kHz
Output transistors “off”
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
Low-speed mode (VCC = 3 V)
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode (VCC = 3 V)
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
Middle-speed mode
f(XIN) = 8 MHz
f(XCIN ) = stopped
Output transistors “off”
Max.
6.8
13
1.6
Middle-speed mode
f(XIN) = 8 MHz (in WIT state)
f(XCIN ) = stopped
Output transistors “off”
Increment when A-D conversion is
executed
f(XIN) = 8 MHz
All oscillation stopped
(in STP state)
Output transistors “off”
Typ.
Ta = 25 °C
Unit
mA
mA
60
200
µA
20
40
µA
20
55
µA
5.0
10.0
µA
4.0
7.0
mA
1.5
mA
800
µA
0.1
Ta = 85 °C
1.0
µA
10
µA
3.1.4 A-D converter characteristics
Table 3.1.6 A-D converter characteristics
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(X IN) = 8 MHz, unless otherwise noted)
Symbol
–
–
t CONV
RLADDER
I VREF
I I(AD)
Parameter
Test conditions
Limits
Typ.
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
High-speed mode, Middle-speed mode
Low-speed mode (Note)
Ladder resistor
Reference power source input current
VREF = 5.0 V
A-D port input current
Note: Only M38514E6/M6 can operate the A-D conversion at low-speed mode.
3-6
Min.
3850/3851 Group User’s Manual
50
40
35
150
0.5
Max.
10
±4
61
200
5.0
Unit
bit
LSB
tc(φ)
µs
kΩ
µA
µA
APPENDIX
3.1 Electrical characteristics
3.1.5 Timing requirements
Table 3.1.7 Timing requirements (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
t W(RESET)
t C(X IN)
t WH (XIN)
t WL (XIN)
t C(CNTR)
t WH (CNTR)
t WL(CNTR)
t C(S CLK)
t WH (SCLK)
t WL (SCLK)
t su(Rx D-SCLK)
t h(S CLK-Rx D)
Parameter
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 , INT0–INT 3 input “H” pulse width
CNTR0, CNTR1 , INT0–INT 3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input setup time
Serial I/O input hold time
Min.
2
125
50
50
200
80
80
800
370
370
220
100
Limits
Typ.
Max.
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note : When f(XIN ) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN ) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Table 3.1.8 Timing requirements (2)
(VCC = 2.7 to 5.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
t W(RESET)
t C(X IN)
t WH (XIN)
t WL (XIN)
t C(CNTR)
t WH (CNTR)
t WL(CNTR)
t C(S CLK)
t WH (SCLK)
t WL (SCLK)
t su(Rx D-SCLK)
t h(S CLK-Rx D)
Parameter
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 , INT0–INT 3 input “H” pulse width
CNTR0, CNTR1 , INT0–INT 3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input setup time
Serial I/O input hold time
Limits
Min.
2
250
100
100
500
230
230
2000
950
950
400
200
Typ.
Max.
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note : When f(XIN ) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN ) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
3850/3851 Group User’s Manual
3-7
APPENDIX
3.1 Electrical characteristics
3.1.6 Switching characteristics
Table 3.1.9 Switching characteristics (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
t WH (S CLK)
t WL (SCLK)
t d (SCLK -TXD)
t v (S CLK-TXD)
t r (SCLK )
t f (S CLK)
t r (CMOS)
t f (CMOS)
Parameter
Test conditions
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
Fig. 3.1.1
Limits
Min.
Typ.
t C(SCLK )/2–30
t C(SCLK )/2–30
Max.
140
–30
10
10
30
30
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: For t WH(SCLK), tWL (SCLK), when the P25/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B 16) is “0”.
2: The XOUT pin is excluded.
Table 3.1.10 Switching characteristics (2)
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
t WH (S CLK)
t WL (SCLK)
t d (SCLK -TXD)
t v (S CLK-TXD)
t r (SCLK )
t f (S CLK)
t r (CMOS)
t f (CMOS)
Parameter
Test conditions
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
Fig. 3.1.1
Limits
Min.
Typ.
tC (SCLK)/2–50
tC (SCLK)/2–50
Max.
350
–30
20
20
50
50
50
50
Notes 1: For t WH(SCLK), tWL (SCLK), when the P25/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B 16) is “0”.
2: The XOUT pin is excluded.
3-8
3850/3851 Group User’s Manual
Unit
ns
ns
ns
ns
ns
ns
ns
ns
APPENDIX
3.1 Electrical characteristics
1kΩ
Measurement output pin
Measurement output pin
100pF
100pF
CMOS output
Fig. 3.1.1 Circuit for measuring output switching characteristics (1)
N-channel open-drain output
Fig. 3.1.2 Circuit for measuring output switching characteristics (2)
3850/3851 Group User’s Manual
3-9
APPENDIX
3.1 Electrical characteristics
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
0.8VCC
CNTR0, CNTR1
0.2VCC
tWL(INT)
tWH(INT)
0.8VCC
INT0 to INT3
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
tf
SCLK
0.2VCC
tWL(S CLK)
tC(SCLK)
tr
tWH(SCLK)
0.8VCC
0.2VCC
tsu(RxD-SCLK)
th(SCLK-RxD)
0.8VCC
0.2VCC
RXD
td(SCLK-TXD)
TX D
Fig. 3.1.3 Timing diagram
3-10
3850/3851 Group User’s Manual
tv(SCLK-TXD)
APPENDIX
3.1 Electrical characteristics
3.1.7 Multi-master I 2C-BUS bus line characteristics
Table 3.1.11 Multi-master I2C-BUS bus line characteristics
Standard clock mode High-speed clock mode
Symbol
Parameter
Min.
Max.
Max.
Unit
t BUF
Bus free time
4.7
Min.
1.3
t HD;STA
Hold time for START condition
4.0
0.6
µs
t LOW
Hold time for SCL clock = “0”
4.7
1.3
µs
tR
Rising time of both S CL and SDA signals
t HD;DAT
Data hold time
t HIGH
Hold time for SCL clock = “1”
tF
Falling time of both SCL and SDA signals
t SU;DAT
Data setup time
250
100
ns
t SU;STA
Setup time for repeated START condition
4.7
0.6
µs
t SU;STO
Setup time for STOP condition
4.0
0.6
µs
1000
µs
20+0.1Cb
300
ns
0
0.9
µs
0
µs
0.6
4.0
300
20+0.1Cb
300
ns
Note: C b = total capacitance of 1 bus line
SDA
tHD:STA
tBUF
tLOW
SCL
P
tR
tF
S
tHD:STA
Sr
tHD:DAT
tsu:STO
tHIGH
tsu:DAT
P
tsu:STA
S : START condition
Sr : RESTART condition
P : STOP condition
Fig. 3.1.4 Timing diagram of multi-master I 2C-BUS
3850/3851 Group User’s Manual
3-11
APPENDIX
3.2 Standard characteristics
3.2 Standard characteristics
3.2.1 Power source current characteristic examples
Figures 3.2.1, Figures 3.2.2, Figures 3.2.3, Figures 3.2.3, Figures 3.2.4 and Figures 3.2.5 show power
source current characteristic examples.
[Measuring condition : 25 °C, f(X IN) = 8MHz, in high-speed mode]
Power source current
(mA)
7.0
6.0
5.0
Standard mode
4.0
3.0
2.0
Wait mode
1.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage (V)
Fig. 3.2.1 Power source current characteristic examples (f(XIN ) = 8MHz, in high-speed mode)
[Measuring condition : 25 °C, f(X IN) = 8MHz, in middle-speed mode]
Power source current
(mA)
3.5
3.0
2.5
2.0
Standard mode
1.5
1.0
Wait mode
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage (V)
Fig. 3.2.2 Power source current characteristic examples (f(XIN ) = 8MHz, in middle-speed mode)
3-12
3850/3851 Group User’s Manual
APPENDIX
3.2 Standard characteristics
[Measuring condition : 25 °C, f(X IN) = 4MHz, in high-speed mode]
Power source current
(mA)
3.5
3.0
2.5
Standard mode
2.0
1.5
1.0
Wait mode
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage (V)
Fig. 3.2.3 Power source current characteristic examples (f(XIN ) = 4MHz, in high-speed mode)
[Measuring condition : 25 °C, f(X IN) = 4MHz, in middle-speed mode]
Power source current 1.4
(mA)
1.2
Standard mode
1.0
0.8
0.6
Wait mode
0.4
0.2
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage (V)
Fig. 3.2.4 Power source current characteristic examples (f(XIN ) = 4MHz, in middle-speed mode)
3850/3851 Group User’s Manual
3-13
APPENDIX
3.2 Standard characteristics
[Measuring condition : 25 °C, f(X CIN) = 32KHz, in low-speed mode]
Power source current
(µA)
70
60
50
40
Standard mode
30
20
Wait mode
10
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage (V)
Fig. 3.2.5 Power source current characteristic examples (f(XCIN) = 32KHz, in low-speed mode)
3-14
3850/3851 Group User’s Manual
APPENDIX
3.2 Standard characteristics
3.2.2 Port standard characteristic examples
Figures 3.2.6, Figures 3.2.7, Figures 3.2.8 and Figures 3.2.9 show port standard characteristic examples.
Port P2 0 IOH–VOH characteristic (P-channel drive)
(Pins with same characteristic : P0,P1,P2 1,P2 4–P2 7,P3,P4)
–50
–45
–40
–35
IOH –30
[mA]
Vcc = 5 V
–25
Vcc = 4.0V
–20
–15
Vcc = 2.7V
–10
–5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VOH[V]
Fig. 3.2.6 Standard characteristic examples of CMOS output port at P-channel drive
Port P2 0 IOL–VOL characteristic (N-channel drive)
(Pins with same characteristic : P0,P1,P2 1,P24–P27,P3,P4)
100
90
80
70
IOL
[mA]
60
Vcc = 5V
50
40
Vcc = 4.0V
30
20
Vcc = 2.7V
10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VOL[V]
Fig. 3.2.7 Standard characteristic examples of CMOS output port at N-channel drive
3850/3851 Group User’s Manual
3-15
APPENDIX
3.2 Standard characteristics
Port P2 2 IOL–VOL characteristic (N-channel drive)
(N-channel open-drain output: Pins with same characteristic : P2 3)
100
Vcc = 5V
90
80
70
IOL
[mA]
Vcc = 4.0V
60
50
40
Vcc = 2.7V
30
20
10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VOL[V]
Fig. 3.2.8 Standard characteristic examples of N-channel open-drain output port at N-channel drive
Port P1 3 IOL–VOL characteristic (N-channel drive)
(Large current output port: Pins with same characteristic :
P14–P1 7 for M38513E4/M4; P1 0–P1 2 and P1 4–P1 7 for M38514E6/M6)
100
Vcc = 5V
90
80
70
IOL
[mA]
Vcc = 4.0V
60
50
40
Vcc = 2.7V
30
20
10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VOL[V]
Fig. 3.2.9 Standard characteristic examples of CMOS large current output port at N-channel drive
3-16
3850/3851 Group User’s Manual
APPENDIX
3.2 Standard characteristics
3.2.3 A-D conversion standard characteristics
Figure 3.2.10 shows the A-D conversion standard characteristics.
The lower-side line on the graph indicates the absolute precision error. It represents the deviation from the
ideal value. For example, the conversion of output code from 0 to 1 occurs ideally at the point of AN0 =
2.5 mV, but the measured value is –4 mV. Accordingly, the measured point of conversion is represented
as “2.5 – 4 = –1.5 mV.”
The upper-side line on the graph indicates the width of input voltages equivalent to output codes. For
example, the measured width of the input voltage for output code 96 is 5 mV, so the differential nonlinear
error is represented as “5 – 5 = 0 mV” (0 LSB).
3851 grup A-D CONVERTER ERROR & STEP WIDTH MEASUREMENT
1LSB WIDTH
15
15.0
10
10.0
5
5.0
0
0.0
-5
1LSB WIDTH [mV]
ERROR [mV]
VCC=5.12 [V], VREF=5.12 [V]
XIN=8 [MHz], Temp=25 [deg.]
-10
0
16
32
48
64
80
96
112
ERROR [mV]
128
144
160
176
192
208
224
240
256
STEP No.
Absolute precision error
15
15.0
10
10.0
5
5.0
0
0.0
-5
1LSB WIDTH [mV]
-15
-10
-15
256
272
288
304
320
336
352
368
384
400
416
432
448
464
480
496
512
15
15.0
10
10.0
5
5.0
0
0.0
-5
1LSB WIDTH [mV]
ERROR [mV]
STEP No.
-10
-15
512
528
544
560
576
592
606
624
640
656
672
688
704
720
736
752
768
15
15.0
10
10.0
5
5.0
0
0.0
-5
1LSB WIDTH [mV]
ERROR [mV]
STEP No.
-10
-15
768
784
800
816
832
848
864
880
896
912
928
944
960
976
992
1008
1024
STEP No.
Fig. 3.2.10 A-D conversion standard characteristics
3850/3851 Group User’s Manual
3-17
APPENDIX
3.3 Notes on use
3.3 Notes on use
3.3.1 Notes on interrupts
(1) Setting of interrupt request bit and interrupt enable bit
To set an interrupt request bit and an interrupt enable bit for interrupts, execute as the following
sequence :
➀ Clear an interrupt request bit to “0” (no interrupt request issued).
➁ Set an interrupt enable bit to “1” (interrupts enabled).
● Reason
If the above setting ➀, ➁ are performed simultaneously with one instruction, an unnecessary
interrupt processing routine is executed. Because an interrupt enable bit is set to “1” (interrupts
enabled) before an interrupt request bit is cleared to “0”.
(2) Switching external interrupt detection edge
When switching the external interrupt detection edge, switch it as the following sequence.
Clear an interrupt enable bit to “0” (interrupt disabled)
↓
Switch the detection edge
↓
Clear an interrupt request bit to “0”
(no interrupt request issued)
↓
Set the interrupt enable bit to “1” (interrupt enabled)
Fig. 3.3.1 Sequence of switch the detection edge
● Reason
The interrupt circuit recognizes the switching of the detection edge as the change of external input
signals. This may cause an unnecessary interrupt.
(3) Check of interrupt request bit
When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request register
immediately after this bit is set to “0” by using a data transfer instruction, execute one or more
instructions before executing the BBC or BBS instruction.
Clear the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
● Reason
If the BBC or BBS instruction is executed
immediately after an interrupt request bit of
an interrupt request register is cleared to
“0”, the value of the interrupt request bit
before being cleared to “0” is read.
Data transfer instruction:
LDM, LDA, STA, STX, and STY instructions
Fig. 3.3.2 Sequence of check of interrupt request bit
3-18
3850/3851 Group User’s Manual
APPENDIX
3.3 Notes on use
3.3.2 Notes on timer
● If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
● When switching the count source by the timer 12, X and Y count source selection bit, the value
of timer count is altered in unconsiderable amount owing to generating of a thin pulses in the count
input signals.
Therefore, select the timer count source before set the value to the prescaler and the timer.
3.3.3 Notes on serial I/O
(1) Notes when selecting clock synchronous serial I/O
➀ Stop of transmission operation
Clear the serial I/O enable bit and the transmit enable bit to “0” (serial I/O and transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in
this case, since pins TxD, RxD, S CLK, and SRDY function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in this state, data starts to be shifted
to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during
internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O enable bit to “0” (serial
I/O disabled).
➂ Stop of transmit/receive operation
Clear both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled) at
the same time.
(when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
● Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.
If any one of transmission and reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,
the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clearing the serial I/O enable bit to “0”
(serial I/O disabled) (refer to (1) ➀).
3850/3851 Group User’s Manual
3-19
APPENDIX
3.3 Notes on use
(2) Notes when selecting clock asynchronous serial I/O
➀ Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in
this case, since pins TxD, RxD, S CLK, and SRDY function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in this state, data starts to be shifted
to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during
internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
➂ Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in
this case, since pins TxD, RxD, S CLK, and SRDY function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in this state, data starts to be shifted
to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during
internally shifting is output to the TxD pin and an operation failure occurs.
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
(3) S RDY output of reception side
When signals are output from the SRDY pin on the reception side by using an external clock in the
clock synchronous serial I/O mode, set all of the receive enable bit, the S RDY output enable bit, and
the transmit enable bit to “1” (transmit enabled).
(4) Setting serial I/O control register again
Set the serial I/O control register again after the transmission and the reception circuits are reset by
clearing both the transmit enable bit and the receive enable bit to “0.”
Clear both the transmit enable
bit (TE) and the receive enable
bit (RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O control register
↓
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to “1”
Fig. 3.3.3 Sequence of setting serial I/O control register again
3-20
3850/3851 Group User’s Manual
Can be set with the
LDM instruction at
the same time
APPENDIX
3.3 Notes on use
(5) Data transmission control with referring to transmit shift register completion flag
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(6) Transmission control when external clock is selected
When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the S CLK input level. Also, write the transmit data to the transmit buffer
register (serial I/O shift register) at “H” of the S CLK input level.
(7) Transmit interrupt request when transmit enable bit is set
The transmission interrupt request bit is set and the interruption request is generated even when
selecting timing that either of the following flags is set to “1” as timing where the transmission
interruption is generated.
• Transmit buffer empty flag is set to “1”
• Transmit shift register completion flag is set to “1”
Therefore, when the transmit interrupt is used, set the transmit interrupt enable bit to transmit
enabled as the following sequence.
➀ Transmit enable bit is set to “1”
➁ Transmit interrupt request bit is set to “0”
● Reason
When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift
register completion flag are set to “1”.
3.3.4 Notes on multi-master I 2C-BUS interface
(1) Read-modify-write instruction
Each register of the multi-master I 2C-BUS interface has bits to change by hardware. The precautions
when the read-modify-write instruction such as SEB, CLB etc. is executed for each register of the
multi-master I 2C-BUS interface are described below.
➀ I2C data shift register (S0: address 002B16 )
When executing the read-modify-write instruction for this register during transfer, data may become
a value not intended.
➁ I2C address register (S0D: address 002C 16)
When the read-modify-write instruction is executed for this register at detecting the STOP condition,
data may become a value not intended.
● Reason
It is because hardware changes the read/write bit (RBW) at detecting the STOP condition.
➂ I2C status register (S1: address 002D16 )
Do not execute the read-modify-write instruction for this register because all bits of this register
are changed by hardware.
➃ I2C control register (S1D: address 002E 16)
When the read-modify-write instruction is executed for this register at detecting the START condition
or at completing the byte transfer, data may become a value not intended.
● Reason
Because hardware changes the bit counter (BC0 to BC2).
➄ I2C clock control register (S2: address 002F16 )
The read-modify-write instruction can be executed for this register.
➅ I2C START/STOP condition control register (S2D: address 0030 16)
The read-modify-write instruction can be executed for this register.
3850/3851 Group User’s Manual
3-21
APPENDIX
3.3 Notes on use
(2) START condition generating procedure using multi-master
➀ Procedure example (The necessary conditions of the generating procedure are described as the
following ➁ to ➄.
LDA #SLADR
(Taking out of slave address value)
SEI
(Interrupt disabled)
BBS 5, S1, BUSBUSY (BB flag confirming and branch process)
BUSFREE:
STA S0
(Writing of slave address value)
LDM #$F0, S1
(Trigger of START condition generating)
CLI
(Interrupt enabled)
:
:
BUSBUSY:
CLI
(Interrupt enabled)
:
:
➁ Use “Branch on Bit Set” of “BBS 5, S1, –” for the BB flag confirming and branch process.
➂ Use “STA, STX” or “STY” of the zero page addressing instruction for writing the slave address
value to the I2C data shift register (S0: address 002B16 ).
➃ Execute the branch instruction of above 2 and the store instruction of above 3 continuously shown
the above procedure example.
➄ Disable interrupts during the following three process steps:
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating
(3) RESTART condition generating procedure in master
➀ Procedure example (The necessary conditions of the generating procedure are described as the
following ➁ to ➃). Execute the following procedure when the PIN bit is “0”.
LDM #$00, S1
(Select slave receive mode)
LDA #SLADR
(Taking out of slave address value)
SEI
(Interrupt disabled)
STA S0
(Writing of slave address value)
LDM #$F0, S1
(Trigger of RESTART condition generating)
CLI
(Interrupt enabled)
:
:
➁ Select the slave receive mode when the PIN bit is “0”. Do not write “1” to the PIN bit. Neither “0” nor
“1” is specified for the writing to the BB bit. The TRX bit becomes “0” and the SDA pin is released.
➂ The SCL pin is released by writing the slave address value to the I2C data shift register.
➃ Disable interrupts during the following two process steps:
• Writing of slave address value
• Trigger of RESTART condition generating
(4) Writing to I 2C status register
Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and
TRX bits to “0” from “1” simultaneously. It is because it may enter the state that the SCL pin is
released and the SDA pin is released after about one machine cycle. Do not execute an instruction
to set the MST and TRX bits to “0” from “1” simultaneously when the PIN bit is “1”. It is because it
may become the same as above.
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3850/3851 Group User’s Manual
APPENDIX
3.3 Notes on use
(5) STOP condition generating procedure in master
➀ Procedure example (The necessary conditions of the generating procedure are described as the
following ➁ to ➄).
SEI
(Interrupt disabled)
LDM #$C0, S1
(Select master transmit mode)
NOP
(Set NOP)
LDM #$D0, S1
(Trigger of STOP condition generating)
CLI
(Interrupt enabled)
:
:
➁ When setting the master transmit mode, write “0” to the PIN bit.
➂ Execute the NOP instruction after the master transmit mode is set. In addition, set the STOP
condition to be triggered within 10 machine cycles after the master transmit mode has been set.
➃ Make sure all interrupts are disabled during the term from when the master transmit mode is set
until the triggering process, which generates the STOP condition, is complete.
➄ The above procedure is only applicable to the M38513E4.
(6) Process of after STOP condition generating
Do not write data in the I2C data shift register S0 and the I 2C status register S1 until the bus busy
flag BB becomes “0” after generating the STOP condition in the master mode. It is because the
STOP condition waveform might not be normally generated. Reading to the above registers do not
have the problem.
(7) STOP condition input at 7th clock pulse
In the slave mode, the STOP condition is input at the 7th clock pulse while receiving a slave address
or data. As the clock pulse is continuously input, the SDA line may be held at LOW even if flag BB
is set to “0”.
Countermeasure:
Write dummy data to the I2C shift register or reset the ES0 bit in the S1D register (ES0 = “L” →
ES0 = “H”) during a stop condition interrupt routine with flag PIN = “1”.
Notes 1: Do not use the read-modify-write instruction at this time. Furthermore, when the ES0 bit
is set to “0”, it becomes a general-purpose port ; so that the port must be set to input mode
or “H”.
2: The M38514E6/M6 does not have this problem which is the SDA line remaining “L”.
(8) ES0 bit switch
In standard clock mode when SSC = “000102” or in high-speed clock mode, flag BB may switch to
“1” if ES0 bit is set to “1” when SDA is “L”.
Countermeasure:
Set ES0 to “1” when SDA is “H”.
3850/3851 Group User’s Manual
3-23
APPENDIX
3.3 Notes on use
3.3.5 Notes on A-D converter
(1) Analog input pin
Make the signal source impedance for analog input low, or equip an analog input pin with an external
capacitor of 0.01µF to 1µF. Further, be sure to verify the operation of application products on the
user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A-D conversion precision to be worse.
(2) A-D converter power source pin
Pins AVCC and AV SS are A-D converter power source pins. Regardless of using the A-D conversion
function or not, connect them as following :
• AVCC : Connect to the V CC line
• AVSS : Connect to the V SS line
● Reason
If the A VCC and the AVSS pin are opened, the microcomputer may have a failure because of noise
or others. Also, if the AVCC pin is connected to the VSS pin, current flows from AV CC to V SS.
(3) Clock frequency during A-D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A-D conversion.
• f(XIN ) is 500 kHz or more
• Do not execute the STP instruction and WIT instruction
3.3.6 Notes on watchdog timer
● The watchdog timer continues counting even while waiting for the stop release. Make sure the
watchdog timer does not underflow during this term.
● Once the STP instruction inhibit bit of the watchdog timer control register is set to “1”, the bit can
not be reprogrammed to “0”.
3.3.7 Notes on RESET pin
(1) Connecting capacitor
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the VSS pin. And use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
● Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
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3850/3851 Group User’s Manual
APPENDIX
3.3 Notes on use
3.3.8 Notes on input and output pins
(1) Notes in stand-by state
In stand-by state* 1 for low-power dissipation, do not make input levels of an input port and an I/O
port “undefined”, especially for I/O ports of the P-channel and the N-channel open-drain.
Pull-up (connect the port to V CC) or pull-down (connect the port to V SS ) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using built-in pull-up or pull-down resistor, note on varied current values:
• When setting as an input port : Fix its input level
• When setting as an output port : Prevent current from flowing out to external
● Reason
Even when setting as an output port with its direction register, in the following state :
• P-channel......when the content of the port latch is “0”
• N-channel......when the content of the port latch is “1”
the transistor becomes the OFF state, which causes the ports to be the high-impedance state.
Note that the level becomes “undefined” depending on external circuits.
Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the
state that input levels of a input port and an I/O port are “undefined”. This may cause power
source current.
*1 stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
(2) Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction*2, the value of the
unspecified bit may be changed.
● Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
• As for a bit which is set for an input port :
The pin state is read in the CPU, and is written to this bit after bit managing.
• As for a bit which is set for an output port :
The bit value of the port latch is read in the CPU, and is written to this bit after bit managing.
Note the following :
• Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
• As for a bit of the port latch which is set for an input port, its value may be changed even when
not specified with a bit managing instruction in case where the pin state differs from its port latch
contents.
*2 bit managing instructions : SEB, and CLB instructions
3850/3851 Group User’s Manual
3-25
APPENDIX
3.3 Notes on use
3.3.9 Notes on low-speed operation mode
(1) Using sub-clock
To use a sub-clock, fix the bit 3 of the CPU mode register to “1” (XCOUT drive capacity is “High”)
and control the Rd (refer to Figure 3.3.4) resistance value to a certain level to stabilize an oscillation.
For resistance value of Rd, consult the oscillator manufacturer.
XCIN
XCOUT
Rf
CCIN
Rd
CCOUT
Fig. 3.3.4 Ceramic resonator circuit
● Reason
When the bit 3 of CPU mode register is set to “0”, the sub-clock oscillation may stop.
3.3.10 Notes on restarting oscillation
(1) Restarting oscillation
Usually, when the MCU stops the clock oscillation by STP instruction and the STP instruction has
been released by an external interrupt source, the fixed values of Timer 1 and Prescaler 12 (Timer
1 = 01 16, Prescaler 12 = FF 16) are automatically reloaded in order for the oscillation to stabilize. The
user can inhibit the automatic setting by writing “1” to bit 0 of MISRG (address 0038 16 ).
However, by setting this bit to “1”, the previous values, set just before the STP instruction was
executed, will remain in Timer 1 and Prescaler 12. Therefore, you will need to set an appropriate
value to each register, in accordance with the oscillation stabilizing time, before executing the STP
instruction.
● Reason
Oscillation will restart when an external interrupt is received. However, internal clock phi is supplied
to the CPU only when Timer 1 starts to underflow. This ensures time for the clock oscillation using
the ceramic resonators to be stabilized.
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3850/3851 Group User’s Manual
APPENDIX
3.3 Notes on use
3.3.11 Notes on programming
(1) Processor status register
➀ Initializing of processor status register
Flags which affect program execution must be initialized after a reset.
In particular, it is essential to initialize the T and D flags because they have an important effect
on calculations.
● Reason
After a reset, the contents of the processor status register (PS) are undefined except for the I
flag which is “1”.
Reset
↓
Initializing of flags
↓
Main program
Fig. 3.3.5 Initialization of processor status register
➁ How to reference the processor status register
To reference the contents of the processor status register (PS), execute the PHP instruction once
then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its
original status.
A NOP instruction should be executed after every PLP instruction.
PLP instruction execution
↓
NOP
(S)
(S)+1
Fig. 3.3.6 Sequence of PLP instruction execution
Stored PS
Fig. 3.3.7 Stack memory contents after PHP
instruction execution
3850/3851 Group User’s Manual
3-27
APPENDIX
3.3 Notes on use
(2) BRK instruction
➀ Detection of interrupt source
It can be detected that the BRK instruction interrupt event or the least priority interrupt event by
referring the stored B flag state. Refer to the stored B flag state in the interrupt routine.
7
4
1
0
=B frag
PS
(S) PCL (Low-order of program counter)
(S)+1 PCH (High-order of program counter)
Fig. 3.3.8 Interrupt routine
➁ Interrupt priority level
When the BRK instruction is executed with the following conditions satisfied, the interrupt execution
is started from the address of interrupt vector which has the highest priority.
• Interrupt request bit and interrupt enable bit are set to “1”.
• Interrupt disable flag (I) is set to “1” to disable interrupt.
(3) Decimal calculations
➀ Execution of decimal calculations
The ADC and SBC are the only instructions which will yield proper decimal notation, set the
decimal mode flag (D) to “1” with the SED instruction. After executing the ADC or SBC instruction,
execute another instruction before executing the SEC, CLC, or CLD instruction.
➁ Notes on status flag in decimal mode
When decimal mode is selected, the values of three of the flags in the status register (the N, V,
and Z flags) are invalid after a ADC or SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared
to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C
flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be
initialized to “1” before each calculation.
Set D flag to “1”
↓
ADC or SBC instruction
↓
NOP instruction
↓
SEC, CLC, or CLD instruction
Fig. 3.3.9 Status flag at decimal calculations
(4) JMP instruction
When using the JMP instruction in indirect addressing mode, do not specify the last address on a
page as an indirect address.
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3850/3851 Group User’s Manual
APPENDIX
3.3 Notes on use
3.3.12 Programming and test of built-in PROM version
As for in the One Time PROM version (shipped in blank) and the built-in EPROM version, their built-in
PROM can be read or programmed with a general-purpose PROM programmer using a special programming
adapter.
The built-in EPROM version is available only for program development and on-chip program evaluation.
The programming test and screening for PROM of the One Time PROM version (shipped in blank) are not
performed in the assembly process and the following processes. To ensure reliability after programming,
performing programming and test according to the Figure 3.3.10 before actual use are recommended.
Programming with PROM programmer
Screening (Caution)
(Leave at 150 °C for 40 hours)
Verification with PROM programmer
Functional check in target device
Caution: The screening temperature is far higher than the
storage temperature. Never expose to 150 °C
exceeding 100 hours.
Fig. 3.3.10 Programming and testing of One Time PROM version
3.3.13 Notes on built-in PROM version
(1) Programming adapter
Use a special programming adapter shown in Table 3.3.2 and a general-purpose PROM programmer
when reading from or programming to the built-in PROM in the built-in PROM version.
Table 3.3.1 Programming adapters
Microcomputer
Programming adapter
M38513E4SS
M38514E6SS
M38513E4SP
M38514E6SP
M38513E4FP
M38514E6FP
(One
(One
(One
(One
Time
Time
Time
Time
PROM
PROM
PROM
PROM
version
version
version
version
shipped
shipped
shipped
shipped
in
in
in
in
blank)
blank)
blank)
blank)
3850/3851 Group User’s Manual
PCA4738S-42A
PCA4738F-42A
3-29
APPENDIX
3.3 Notes on use
(2) Programming/reading
In PROM mode, operation is the same as that of the M5M27C101AK, but programming conditions
of PROM programmer are not set automatically because there are no internal device ID codes.
Accurately set the following conditions for data programming /reading. Take care not to apply 21 V
to V PP pin (is also used as the CNV SS pin), or the product may be permanently damaged.
• Programming voltage: 12.5 V
• Setting of PROM programmer switch: refer to Table 3.3.3.
Table 3.3.2 PROM programmer address setting
PROM programmer
Product name format
start address
M38513E4SS
Address 0C08016 (Note 1)
M38513E4SP
PROM programmer
end address
Address 0FFFD16 (Note 1)
M38513E4FP
M38514E6SS
Address 0A08016 (Note 2)
Address 0FFFD16 (Note 2)
M38514E6SP
M38514E6FP
Notes 1: Addresses C080 16 to FFFD16 in the built-in PROM corresponds to addresses 0C08016 to 0FFFD16
in the PROM programmer.
2: Addresses A080 16 to FFFD16 in the built-in PROM corresponds to addresses 0A080 16 to 0FFFD16
in the PROM programmer.
(3) Erasing
Contents of the windowed EPROM are erased through an ultraviolet light source of the wavelength
2537 Ångstrom. At least 15 W • sec/cm are required to erase EPROM contents.
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3850/3851 Group User’s Manual
APPENDIX
3.3 Notes on use
3.3.14 Termination of unused pins
(1) Terminate unused pins
➀ Output ports : Open
➁ Input ports :
Connect each pin to VCC or V SS through each resistor of 1 kΩ to 10 kΩ.
As for pins whose potential affects to operation modes such as pins CNV SS, INT or others, select
the VCC pin or the V SS pin according to their operation mode.
➂ I/O ports :
• Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of
1 kΩ to 10 kΩ.
Set the I/O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input
mode. With regard to an effects on the system, thoroughly perform system evaluation on the user
side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
(2) Termination remarks
➀ Input ports and I/O ports :
Do not open in the input mode.
● Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➁ and
➂ shown on the above.
➁ I/O ports :
When setting for the input mode, do not connect to VCC or VSS directly.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and V CC (or VSS ).
➂ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to VCC or V SS through
a resistor.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
3850/3851 Group User’s Manual
3-31
APPENDIX
3.4 Countermeasures against noise
3.4 Countermeasures against noise
Countermeasures against noise are described below. The following countermeasures are effective against
noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use.
3.4.1 Shortest wiring length
The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer.
The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer.
(1) Package
Select the smallest possible package to make the total wiring length short.
● Reason
The wiring length depends on a microcomputer package. Use of a small package, for example
QFP and not DIP, makes the total wiring length short to reduce influence of noise.
DIP
SDIP
SOP
QFP
Fig. 3.4.1 Selection of packages
(2) Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin as short as possible. Especially,
connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within
20mm).
● Reason
The width of a pulse input into the RESET pin is determined by the timing necessary conditions.
If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is completely initialized. This may cause
a program runaway.
Noise
Reset
circuit
RESET
VSS
VSS
N.G.
Reset
circuit
VSS
RESET
VSS
O.K.
Fig. 3.4.2 Wiring for the RESET pin
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3850/3851 Group User’s Manual
APPENDIX
3.4 Countermeasures against noise
(3) Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected
to an oscillator and the VSS pin of a microcomputer as short as possible.
• Separate the V SS pattern only for oscillation from other V SS patterns.
● Reason
If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program
failure or program runaway. Also, if a potential difference is caused by the noise between the V SS
level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in
the microcomputer.
Noise
XIN
XOUT
VSS
XIN
XOUT
VSS
O.K.
N.G.
Fig. 3.4.3 Wiring for clock I/O pins
(4) Wiring to CNV SS pin
Connect the CNV SS pin to the V SS pin with the shortest possible wiring.
● Reason
The processor mode of a microcomputer is influenced by a potential at the CNV SS pin. If a
potential difference is caused by the noise between pins CNVSS and VSS, the processor mode may
become unstable. This may cause a microcomputer malfunction or a program runaway.
Noise
CNVSS
CNVSS
VSS
VSS
N.G.
O.K.
Fig. 3.4.4 Wiring for CNV SS pin
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3-33
APPENDIX
3.4 Countermeasures against noise
(5) Wiring to V PP pin of One Time PROM version and EPROM version
Connect an approximately 5 kΩ resistor to the VPP pin the shortest possible in series and also to the
V SS pin. When not connecting the resistor, make the length of wiring between the VPP pin and the
V SS pin the shortest possible.
Note: Even when a circuit which included an approximately 5 kΩ resistor is used in the Mask ROM
version, the microcomputer operates correctly.
● Reason
The V PP pin of the One Time PROM and the EPROM version is the power source input pin for
the built-in PROM. When programming in the built-in PROM, the impedance of the V PP pin is low
to allow the electric current for writing flow into the PROM. Because of this, noise can enter easily.
If noise enters the V PP pin, abnormal instruction codes or data are read from the built-in PROM,
which may cause a program runaway.
Approximately
5kΩ
CNVSS/VPP
VSS
In the shortest
distance
Fig. 3.4.5 Wiring for the VPP pin of the One Time PROM and the EPROM version
3.4.2 Connection of bypass capacitor across VSS line and V CC line
Connect an approximately 0.1 µF bypass capacitor across the V SS line and the V CC line as follows:
• Connect a bypass capacitor across the V SS pin and the V CC pin at equal length.
• Connect a bypass capacitor across the V SS pin and the V CC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for V SS line and V CC line.
• Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin.
VCC
VCC
VSS
VSS
N.G.
O.K.
Fig. 3.4.6 Bypass capacitor across the VSS line and the VCC line
3-34
3850/3851 Group User’s Manual
APPENDIX
3.4 Countermeasures against noise
3.4.3 Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog
input pin in series. Besides, connect the resistor to the microcomputer as close as possible.
• Connect an approximately 1000 pF capacitor across the V SS pin and the analog input pin. Besides,
connect the capacitor to the V SS pin as close as possible. Also, connect the capacitor across the analog
input pin and the V SS pin at equal length.
● Reason
Signals which is input in an analog input pin (such as an A-D converter/comparator input pin) are
usually output signals from sensor. The sensor which detects a change of event is installed far
from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer
necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer,
which causes noise to an analog input pin.
If a capacitor between an analog input pin and the VSS pin is grounded at a position far away from
the VSS pin, noise on the GND line may enter a microcomputer through the capacitor.
Noise
(Note)
Microcomputer
Analog
input pin
Thermistor
N.G.
O.K.
VSS
Note : The resistor is used for dividing
resistance with a thermistor.
Fig. 3.4.7 Analog signal line and a resistor and a capacitor
3.4.4 Oscillator concerns
Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected
by other signals.
(1) Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a
current larger than the tolerance of current value flows.
● Reason
In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and
thermal heads or others. When a large current flows through those signal lines, strong noise
occurs because of mutual inductance.
Microcomputer
Mutual inductance
M
XIN
XOUT
VSS
Large
current
GND
Fig. 3.4.8 Wiring for a large current signal line
3850/3851 Group User’s Manual
3-35
APPENDIX
3.4 Countermeasures against noise
(2) Installing oscillator away from signal lines where potential levels change frequently
Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential
levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines
which are sensitive to noise.
● Reason
Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect
other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms
may be deformed, which causes a microcomputer failure or a program runaway.
N.G.
Do not cross
CNTR
XIN
XOUT
VSS
Fig. 3.4.9 Wiring of RESET pin
(3) Oscillator protection using V SS pattern
As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the
position (on the component side) where an oscillator is mounted.
Connect the V SS pattern to the microcomputer V SS pin with the shortest possible wiring. Besides,
separate this V SS pattern from other V SS patterns.
An example of VSS patterns on the
underside of a printed circuit board
Oscillator wiring
pattern example
XIN
XOUT
VSS
Separate the VSS line for oscillation from other VSS lines
Fig. 3.4.10 VSS pattern on the underside of an oscillator
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3850/3851 Group User’s Manual
APPENDIX
3.4 Countermeasures against noise
3.4.5 Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an I/O port in series.
<Software>
• As for an input port, read data several times by a program for checking whether input levels are
equal or not.
• As for an output port, since the output data may reverse because of noise, rewrite data to its port
latch at fixed periods.
• Rewrite data to direction registers at fixed periods.
Note: When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse
may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise
pulse.
O.K.
Noise
Data bus
Noise
Direction register
N.G.
Port latch
I/O port
pins
Fig. 3.4.11 Setup for I/O ports
3850/3851 Group User’s Manual
3-37
APPENDIX
3.4 Countermeasures against noise
3.4.6 Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer
and the microcomputer can be reset to normal operation. This is equal to or more effective than program
runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer
provided by software.
In the following example, to reset a microcomputer to normal operation, the main routine detects errors of
the interrupt processing routine and the interrupt processing routine detects errors of the main routine.
This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
<The main routine>
• Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value
N in the SWDT once at each execution of the main routine. The initial value N should satisfy the
following condition:
N+1 ≥ ( Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others,
the initial value N should have a margin.
• Watches the operation of the interrupt processing routine by comparing the SWDT contents with
counts of interrupt processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and determines to branch to the program
initialization routine for recovery processing in the following case:
If the SWDT contents do not change after interrupt processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt processing.
• Determines that the main routine operates normally when the SWDT contents are reset to the
initial value N at almost fixed cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch to the program initialization
routine for recovery processing in the following case:
If the SWDT contents are not initialized to the initial value N but continued to decrement and if
they reach 0 or less.
≠N
Main routine
Interrupt processing routine
(SWDT)← N
(SWDT) ← (SWDT)—1
CLI
Interrupt processing
Main processing
(SWDT)
≤0?
(SWDT)
=N?
N
Interrupt processing
routine errors
>0
RTI
≤0
Return
Main routine
errors
Fig. 3.4.12 Watchdog timer by software
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3850/3851 Group User’s Manual
APPENDIX
3.5 List of registers
3.5 List of registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (Pi) (i = 0, 1, 2, 3, 4) [Address : 00 16, 0216, 04 16, 0616, 0816]
B
Name
0 Port Pi 0
Function
R W
?
●
In output mode
Write
Port latch
Read
●
In input mode
Write : Port latch
Read : Value of pins
1 Port Pi1
2 Port Pi2
At reset
?
?
3 Port Pi3
?
4 Port Pi4
?
5 Port Pi5
?
6 Port Pi6
?
7 Port Pi7
?
Fig. 3.5.1 Structure of Port Pi (i=0, 1, 2, 3, 4)
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4) [Address : 01
B
0 Port Pi direction register
1
2
3
4
5
6
7
Function
Name
0 : Port Pi 0 input mode
1 : Port Pi 0 output mode
0 : Port Pi 1 input mode
1 : Port Pi 1 output mode
0 : Port Pi 2 input mode
1 : Port Pi 2 output mode
0 : Port Pi 3 input mode
1 : Port Pi 3 output mode
0 : Port Pi 4 input mode
1 : Port Pi 4 output mode
0 : Port Pi 5 input mode
1 : Port Pi 5 output mode
0 : Port Pi 6 input mode
1 : Port Pi 6 output mode
0 : Port Pi 7 input mode
1 : Port Pi 7 output mode
16,
0316, 05 16, 07 16, 0916]
At reset
R W
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
Fig. 3.5.2 Structure of Port Pi direction register(i=0, 1, 2, 3, 4)
3850/3851 Group User’s Manual
3-39
APPENDIX
3.5 List of registers
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB) [Address : 18 16]
B
Name
Function
0 The transmission data is written to or the receive data is read out
At reset
R W
?
from this buffer register.
1 • At writing: A data is written to the transmit buffer register.
?
• At reading: The contents of the receive buffer register are read
out.
2
?
3
?
4
?
5
?
6
?
7
?
Note: The contents of transmit buffer register cannot be read out.
The data cannot be written to the receive buffer register.
Fig. 3.5.3 Structure of Transmit/Receive buffer register
Serial I/O status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O status register (SIOSTS) [Address : 19 16]
B
Function
Name
Transmit buffer empty flag
(TBE)
0 : Buffer full
1 : Buffer empty
0 : Buffer empty
1 : Buffer full
0 : Transmit shift in progress
1 : Transmit shift completed
R W
0
✕
0
✕
0
✕
3 Overrun error flag (OE)
0
✕
4
0
✕
0
✕
0
✕
1
✕
0
1 Receive buffer full flag (RBF)
2 Transmit shift register shift
completion flag (TSC)
5
6
7
0 : No error
1 : Overrun error
0 : No error
Parity error flag (PE)
1 : Parity error
0 : No error
Framing error flag (FE)
1 : Framing error
0 : (OE) ∪ (PE) ∪ (FE) = 0
Summing error flag (SE)
1 : (OE) ∪ (PE) ∪ (FE) = 1
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “1”.
Fig. 3.5.4 Structure of Serial I/O status register
3-40
At reset
3850/3851 Group User’s Manual
APPENDIX
3.5 List of registers
Serial I/O control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O control register (SIOCON) [Address : 1A
B
16]
Function
Name
At reset
0 : f(X IN)
1 : f(X IN)/4
0
• In clock synchronous serial I/O
0 : BRG output devided by 4
1 : External clock input
• In UART
0 : BRG output devided by 16
1 : External clock input devided by 16
0
2 SRDY output enable bit (SRDY) 0 : P2 7 pin operates as ordinary I/O pin
0
0 BRG count source
selection bit (CSS)
1 Serial I/O synchronous
clock selection bit (SCS )
R W
1 : P2 7 pin operates as S RDY output pin
3 Transmit interrupt
source selection bit (TIC)
4 Transmit enable bit (TE)
5 Receive enable bit (RE)
6 Serial I/O mode selection bit
(SIOM)
7 Serial I/O enable bit
(SIOE)
0 : Interrupt when transmit buffer has emptied
1 : Interrupt when transmit shift operation is
completed
0 : Transmit disabled
1 : Transmit enabled
0 : Receive disabled
1 : Receive enabled
0
0 : Clock asynchronous(UART) serial I/O
1 : Clock synchronous serial I/O
0
0 : Serial I/O disabled
(pins P2 4 to P2 7 operate as ordinary I/O pins)
1 : Serial I/O enabled
(pins P2 4 to P2 7 operate as serial I/O pins)
0
0
0
Fig. 3.5.5 Structure of Serial I/O control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register (UARTCON) [Address : 1B 16]
B
Name
Function
At reset
0 Character length selection bit
0
1
0
2
3
4
0 : 8 bits
(CHAS)
1 : 7 bits
Parity enable bit
0 : Parity checking disabled
(PARE)
1 : Parity checking enabled
Parity selection bit
0 : Even parity
(PARS)
1 : Odd parity
Stop bit length selection bit
0 : 1 stop bit
(STPS)
1 : 2 stop bits
In output mode
P25/TxD P-channel output
0 : CMOS output
disable bit (POFF)
1 : N-channel open-drain output
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “1”.
R W
0
0
0
1
✕
6
1
✕
7
1
✕
5
Fig. 3.5.6 Structure of UART control register
3850/3851 Group User’s Manual
3-41
APPENDIX
3.5 List of registers
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator (BRG) [Address : 1C 16]
Function
B
At reset
0 Set a count value of baud rate generator.
?
1
?
2
?
3
?
4
?
5
?
6
?
7
?
R W
Fig. 3.5.7 Structure of Baud rate generator
PWM control register
b7 b6 b5 b4 b3 b2 b1 b0
PWM control register(PWMCON) [Address : 1D 16]
B
Name
Function
0: PWM disabled
1: PWM enabled
0: f(X IN)
1: f(X IN)/2
0
PWM function enable bit
1
Count source selection bit
2
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
R W
0
0
0
✕
3
0
✕
4
0
✕
5
0
✕
6
0
✕
7
0
✕
Fig. 3.5.8 Structure of PWM control register
3-42
At reset
3850/3851 Group User’s Manual
APPENDIX
3.5 List of registers
PWM prescaler
b7 b6 b5 b4 b3 b2 b1 b0
PWM prescaler (PREPWM) [Address : 1E 16]
B
Name
Function
0 • Set a PWM period.
At reset
R W
?
• The values set in this register is written to both the PWM
1
prescaler pre-latch and the PWM prescaler latch at the same
time.
2 • When data is written during PWM outputting, the pulses
corresponding to the changed contents are output starting at
the next cycle.
3 • When this register is read out, the contents of the PWM
prescaler latch is read out.
?
?
?
4
?
5
?
6
?
7
?
Fig. 3.5.9 Structure of PWM prescaler
PWM register
b7 b6 b5 b4 b3 b2 b1 b0
PWM register (PWM) [Address : 1F 16]
B
Name
Function
0 • Set a “H” level output period of PWM.
• The values set in this register is written to both the PWM
1
register pre-latch and the PWM register latch at the same
time.
2 • When data is written during PWM outputting , the pulses
corresponding to the changed contents are output starting at
the next cycle.
3 • When this register is read out, the contents of the PWM register
latch is read out.
At reset
R W
?
?
?
?
4
?
5
?
6
?
7
?
Fig. 3.5.10 Structure of PWM register
3850/3851 Group User’s Manual
3-43
APPENDIX
3.5 List of registers
Prescaler 12, Prescaler X, Prescaler Y
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 12 (PRE12) [Address : 20 16]
Prescaler X (PREX) [Address : 24 16]
Prescaler Y (PREY) [Address : 26 16]
B
Name
Function
0 •Set a count value of each prescaler.
At reset
R W
1
•The value set in this register is written to both each prescaler
1 and the corresponding prescaler latch at the same time.
•When this register is read out, the count value of the corres2 ponding prescaler is read out.
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 3.5.11 Structure of Prescaler 12, Prescaler X, Prescaler Y
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1 (T1) [Address : 21 16]
B
Name
Function
0 •Set a count value of timer 1.
•The value set in this register is written to both timer 1 and timer 1
1 latch at the same time.
•When this register is read out, the timer 1’s count value is read
2 out.
1
0
0
3
0
4
0
5
0
6
0
7
0
Fig. 3.5.12 Structure of Timer 1
3-44
At reset
3850/3851 Group User’s Manual
R W
APPENDIX
3.5 List of registers
Timer 2, Timer X, Timer Y
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2 (T2) [Address : 22 16]
Timer X (TX) [Address : 25 16]
Timer Y (TY) [Address : 27 16]
B
Name
Function
At reset
0 •Set a count value of each timer.
R W
1
•The value set in this register is written to both each timer and
1 each timer latch at the same time.
•When this register is read out, each timer’s count value is read
2 out.
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 3.5.13 Structure of Timer 2, Timer X, Timer Y
Timer count source selection register
b7 b6 b5 b4 b3 b2 b1 b0
Timer count source selection register (TCSS) [Address : 28
B
0
1
2
Name
16]
Function
Timer X count source selection 0 : f(X IN)/16 (f(X CIN)/16 at low-speed mode)
bit
1 : f(X IN)/2 (f(XCIN)/2 at low-speed mode)
Timer Y count source selection 0 : f(X IN)/16 (f(X CIN)/16 at low-speed mode)
bit
1 : f(X IN)/2 (f(XCIN)/2 at low-speed mode)
Timer 12 count source
0 : f(X IN)/16 (f(X CIN)/16 at low-speed mode)
selection bit
1 : f(X CIN)
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
At reset
R W
0
0
0
0
✕
4
0
✕
5
0
✕
6
0
✕
7
0
✕
3
Fig. 3.5.14 Structure of timer count source selection register
3850/3851 Group User’s Manual
3-45
APPENDIX
3.5 List of registers
Timer XY mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer XY mode register (TM) [Address : 23 16 ]
B
Function
Name
0 Timer X operating mode bits
1
b1 b0
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement
mode
At reset
0
0
2 CNTR 0 active edge switch bit
The function depends on the
operating mode of Timer X.
(Refer to Table 3.5.1)
0
3 Timer X count stop bit
0 : Count start
1 : Count stop
0
b5 b4
0
4 Timer Y operating mode bits
5
6 CNTR 1 active edge switch bit
7 Timer Y count stop bit
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement
mode
The function depends on the
operating mode of Timer Y.
(Refer to Table 3.5.1)
0 : Count start
1 : Count stop
R W
0
0
0
Fig. 3.5.15 Structure of Timer XY mode register
Table 3.5.1 CNTR 0 /CNTR1 active edge switch bit function
Timer X /Timer Y operation
modes
Timer mode
Pulse output mode
Event counter mode
Pulse width measurement mode
CNTR0 / CNTR 1 active edge switch bit
(bits 2, 6 of address 23 16 ) contents
“0” CNTR0 / CNTR 1 interrupt request occurrence: Falling edge
; No influence to timer count
“1” CNTR0 / CNTR 1 interrupt request occurrence: Rising edge
; No influence to timer count
“0” Pulse output start: Beginning at “H” level
CNTR0 / CNTR 1 interrupt request occurrence: Falling edge
“1” Pulse output start: Beginning at “L” level
CNTR0 / CNTR 1 interrupt request occurrence: Rising edge
“0” Timer X
CNTR0 /
“1” Timer X
CNTR0 /
“0” Timer X
/ Timer Y: Rising edge count
CNTR 1 interrupt request occurrence: Falling edge
/ Timer Y: Falling edge count
CNTR 1 interrupt request occurrence: Rising edge
/ Timer Y: “H” level width measurement
CNTR0 / CNTR 1 interrupt request occurrence: Falling edge
“1” Timer X / Timer Y: “L” level width measurement
CNTR0 / CNTR 1 interrupt request occurrence: Rising edge
3-46
3850/3851 Group User’s Manual
APPENDIX
3.5 List of registers
I2C data shift register
b7 b6 b5 b4 b3 b2 b1 b0
I2C data shift register (S0) [Address : 2B 16]
Function
B
At reset
0 This register is an 8-bit shift register to store receive data or write
R W
?
transmit data.
1
?
2
?
3
?
4
?
5
?
6
?
7
?
Note: Secure 8 machine cycles from clearing MST bit to “0” (slave mode) until writing
data to I 2C data shift register.
If executing the read-modify-write instruction(SEB, CLB etc.) for this register
during transfer, data may become a value not intended.
Fig. 3.5.16 Structure of I2C data shift register
I2C address register
b7 b6 b5 b4 b3 b2 b1 b0
I2C address register (S0D) [Address : 2C 16 ]
B
1 Slave address
2
Function
At reset
0 : Write bit
1 : Read bit
These bits are compared with the
address data transmitted from the
master.
0
Name
0 Read / write bit (RWB)
(SAD0, SAD1, SAD2, SAD3,
SAD4, SAD5, SAD6)
R W
0
0
3
0
4
0
5
0
6
0
7
0
Note: If the read-modify-write instruction(SEB, CLB, etc.) is executed for this register
at detectiong the stop condition, data may become a value not to intend.
Fig. 3.5.17 Structure of I2C address register
3850/3851 Group User’s Manual
3-47
APPENDIX
3.5 List of registers
I2C status register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address : 2D 16]
B
Function
At reset
0 : Last bit = “0”
1 : Last bit = “1”
( Note1)
0 : No general call detected
1 : General call detected( Note1, 2)
0 : Address disagreement
1 : Address agreement ( Note1, 2)
0 : Not detected
1 : Detected
( Note1)
0 : SCL pin low hold
1 : SCL pin low release ( Note3)
0 : Bus free
1 : Bus busy
?
✕
0
✕
0
✕
0
✕
Name
0 Last receive bit (LRB)
1 General call detecting flag
(AD0)
2 Slave address comparison
flag (AAS)
3 Arbitration lost detecting flag
(AL)
4 SCL pin low hold bit (PIN)
5 Bus busy flag (BB)
6 Communication mode
specification bits (TRX, MST)
7
00 : Slave receive mode
01 : Slave transmit mode
10 : Master receive mode
11 : Master transmit mode
R W
1
0
0
0
Notes 1: These bits and flags can be read out, but cannot be written.
2
2: These bits can be detected when data format select bit (ALS) of I C control
register is “0” .
3: “1” can be written to this bit, but “0” cannot be written by program.
4: Do not execute the read-modify-write instruction (SEB, CLB) for this refgister,
because all bits of this register are changed by hardware.
Fig. 3.5.18 Structure of I2C status register
I2C control register
b7 b6 b5 b4 b3 b2 b1 b0
I2C control register (S1D) [Address : 2E 16]
B
Name
0 Bit counter (Number of
transmit/receive bits)
(BC0, BC1, BC2)
1
2
3 I2C-BUS interface enable bit
(ES0)
4 Data format selection bit
(ALS)
5 Addressing format selection
bit (10 BIT SAD)
Function
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0:8
1:7
0:6
1:5
0:4
1:3
0:2
1:1
0
0 : Addressing format
1 : Free data format
0
0 : 7-bit addressing format
1 : 10-bit addressing format
0
0 : Connect to ports P2 2, P2 3
1 : Connect to ports P2 4, P2 5
(Note 1)
7 I2C-BUS interface pin input
0 : CMOS input
1 : SMBUS input
level selection bit (TISS)
R W
0
0 : Disabled
1 : Enabled
6 SDA/SCL pin selection bit
(TSEL)
At reset
0
0
Notes 1: When using P2 4 and P2 5 as I2C-BUS interface, they are automatically
switched from CMOS output to P-channel output disabled.
2: When the read-modify-write instruction is executed for this register at
detectiong the START condition or at completing the byte transfer, data
may become a value not intended.
Fig. 3.5.19 Structure of I2C control register
3-48
3850/3851 Group User’s Manual
APPENDIX
3.5 List of registers
I2C clock control register
b7 b6 b5 b4 b3 b2 b1 b0
I2C clock control register (S2) [Address : 2F 16]
B
Function
Name
0 SCL frequency control bits
At reset
Refer to Table 3.5.2
0
0 : Standard clock mode
1 : High-speed clock mode
0 : ACK is returned
1 : ACK is not returned
0 : No ACK clock
1 : ACK clock
0
(CCR0, CCR1, CCR2, CCR3,
CCR4)
R W
1
2
3
4
5 SCL mode specification bit
(FAST MODE)
6 ACK bit (ACK BIT)
7 ACK clock bit (ACK)
0
0
Fig. 3.5.20 Structure of I2C clock control register
Table 3.5.2 Set value of I2C clock control register and SCL frequency
Setting value of
CCR4–CCR0
CCR4 CCR3 CCR2 CCR1 CCR0
…
0
1
0
1
0
1
0
…
0
0
1
1
0
0
1
…
0
0
0
0
1
1
1
…
0
0
0
0
0
0
0
…
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
SCL frequency
(at φ = 4 MHz, unit : kHz) (Note 1)
Standard clck
High-speed
mode
clock mode
Setting disabled
Setting disabled
Setting disabled
Setting disabled
Setting disabled
Setting disabled
– (Note 2)
333
– (Note 2)
250
400 (Note 3)
100
166
83.3
500/CCR value
(Note 3)
17.2
16.6
16.1
1000/CCR value
(Note 3)
34.5
33.3
32.3
Notes 1: Duty of SCL clock output is 50 %. The duty becomes 35 to 45 % only when the high-speed clock mode is selected
and CCR value = 5 (400 kHz, at φ = 4 MHz). “H” duration of the clock fluctuates from –4 to +2 machine cycles in
the standard clock mode, and fluctuates from –2 to +2 machine cycles in the high-speed clock mode. In the case of
negative fluctuation, the frequency does not increase because “L” duration is extended instead of “H” duration
reduction.
These are value when S CL clock synchronization by the synchronous function is not performed. CCR value is the
decimal notation value of the SCL frequency control bits CCR4 to CCR0.
2: Each value of SCL frequency exceeds the limit at φ = 4 MHz or more. When using these setting value, use φ of
4 MHz or less.
3: The data formula of S CL frequency is described below:
φ/(8 ✕ CCR value) Standard clock mode
φ/(4 ✕ CCR value) High-speed clock mode (CCR value ≠ 5)
φ/(2 ✕ CCR value) High-speed clock mode (CCR value = 5)
Do not set 0 to 2 as CCR value regardless of φ frequency.
Set 100 kHz (max.) in the standard clock mode and 400 kHz (max.) in the high-speed clock mode to the S CL
frequency by setting the S CL frequency control bits CCR4 to CCR0.
3850/3851 Group User’s Manual
3-49
APPENDIX
3.5 List of registers
I2C START/STOP condition control register
b7 b6 b5 b4 b3 b2 b1 b0
I2C START/STOP condition control register (S2D) [Address : 30
B
Function
Name
0 START/STOP condition set bit
(SSC0, SSC1, SSC2, SSC3,
SSC4)
(Note)
SCL release time
= φ(µs) ✕ (SSC+1)
1
Set up time
= φ(µs) ✕ (SSC+1)/2
2
16]
At reset
R W
?
Hold time
= φ(µs) ✕ (SSC+1)/2
3
4
0 : Falling edge active
1 : Rising edge active
selection bit(SIP)
0
: SDA valid
S
CL
/S
DA
interrupt
pin
select
on
6
1 : SCL valid
bit (SIS)
7 Fix this bit to “0”.
5 SCL/SDA interrupt pin polarity
0
0
0
Note : Fix SSC0 bit to “0”.
Fig. 3.5.21 Structure of I 2C START/STOP condition control register
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register (ADCON) [Address : 34 16 ]
B
Name
0
Analog input pin selection bits
Function
b2 b1 b0
0
0
0
0
1
1
1
1
1
2
0
0
1
1
0
0
1
1
0 : P3 0/AN0
1 : P3 1/AN1
0 : P3 2/AN2
1 : P3 3/AN3
0 : P3 4/AN4
1 : P3 5/AN5
0 : P3 6/AN6
1 : P3 7/AN7
R W
0
0
0
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
AD conversion completion bit 0 : Conversion in progress
1 : Conversion completed
0
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
0
✕
6
0
✕
7
0
✕
3
4
5
Fig. 3.5.22 Structure of A-D control register
3-50
At reset
3850/3851 Group User’s Manual
✕
1
APPENDIX
3.5 List of registers
A-D conversion register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (low-order) (ADL) [Address : 35
B
16]
Function
At reset
R W
?
✕
?
✕
b0
?
✕
b9 b8 b7 b6 b5 b4 b3 b2
?
✕
< 10-bit read>
?
✕
?
✕
6
?
✕
7
?
✕
0 The read-only register in which the A-D conversion’s results are
stored.
1
2
b7
3
4
b7
5
< 8-bit read>
b0
b7 b6 b5 b4 b3 b2 b1 b0
Fig. 3.5.23 Structure of A-D conversion register(low-order)
A-D conversion register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (high-order) (ADH) [Address : 36
B
Name
16 ]
Function
At reset
R W
?
✕
?
✕
?
✕
3
?
✕
4
?
✕
5
?
✕
6
?
✕
7
?
✕
0 The read-only register in which the A-D conversion’s results are
stored.
1
b7
< 10-bit read>
b0
b9 b8
2
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
Fig. 3.5.24 Structure of A-D conversion register (high-order)
3850/3851 Group User’s Manual
3-51
APPENDIX
3.5 List of registers
MISRG
b7 b6 b5 b4 b3 b2 b1 b0
MISRG [Address : 38 16 ]
B
Function
At reset
0 : Set automatically
(Note 1)
1 : Not set automatically
0
Name
Oscillation stabilization time
set bit after release of the
STP instruction
0
1 Middle-speed mode automatic 0 : Not set automatically
switch set bit
Middle-speed mode automatic
2 switch wait time set bit
Middle-speed mode automatic
switch start bit
(Depending on program)
3
1 : Automatic switching enable
(Notes 2, 3)
0 : 4.5 to 5.5 machine cycles
1 : 6.5 to 7.5 machine cycles
R W
0
0
0
0 : Invalid
1 : Automatic switch start
(Note 3)
4 Nothing is allocated for these bits. These are write disabled bits.
0
✕
5
0
✕
6
0
✕
7
0
✕
When these bits are read out, the values are “0”.
Notes 1: Automatically set “01 16” to timer 1, and “FF 16” to priscaler 12.
2: During operation in low-speed mode, it is possible automatically to switch to
middle-speed mode owing to S CL/SDA interrupt.
3: When automatic switch to middle-speed mode from low-speed mode
occurs, the values of CPU mode register (3B 16) change.
Fig. 3.5.25 Structure of MISRG
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog timer control register (WDTCON) [Address : 39
B
Name
16]
Function
R W
1
✕
1
✕
1
✕
3
1
✕
4
1
✕
5
1
✕
0 Watchdog timer H
1
2
6 STP instruction disable bit
(Note)
Watchdog
timer H count
7
source selection bit
•The watchdog timer starts to count
down by writing an optional value into
this register after resetting.
•This bits are cleared to “000000 2” by
writing an optional value into this
register.
0 : STP instruction enabled
1 : STP instruction disabled
0 : Watchdog timer L underflow
1 : f(X IN)/16 or f(X CIN)/16
Note: When this bit is set to “1”, it cannot be rewriten to “0” by program.
Fig. 3.5.26 Structure of Watchdog timer control register
3-52
At reset
3850/3851 Group User’s Manual
0
0
APPENDIX
3.5 List of registers
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A
B
16]
Function
Name
0 : Falling edge active
1 : Rising edge active
selection bit
INT 1 interrupt edge
0 : Falling edge active
selection bit
1 : Rising edge active
INT 2 interrupt edge
0 : Falling edge active
selection bit
1 : Rising edge active
INT 3 interrupt edge
0 : Falling edge active
selection bit
1 : Rising edge active
This is the reserved bit. Do not write “1” to this bit.
At reset
0 INT 0 interrupt edge
0
1
0
2
3
R W
0
0
0
✕
0
✕
6
0
✕
7
0
✕
4
5 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
Fig. 3.5.27 Structure of Interrupt edge selection register
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register (CPUM) [Address : 3B 16]
B
Function
Name
0 Processor mode bits
1
2 Stack page selection bit
b1 b0
0
0
1
1
0 : Single-chip mode
1 : Not available
0 : Not available
1 : Not available
0 : 0 page
1 : 1 page
3 Fix this bit to “1”.
4 Port Xc switch bit
5 Main clock (X IN-XOUT) stop bit
6 Main clock division ratio
selection bits
7
At reset
R W
0
0
(Note)
0
1
0 : I/O port function
1 : Xcin-Xcout operating function
0 : Operating
1 : Stopped
0
b7 b6
1
0 0 : φ = f(XIN)/2
(high-speedmode)
0 1 : φ = f(XIN)/8
(middle-speed mode)
1 0 : φ = f(XCIN)/2
(low-speed mode)
1 1 : φ = Not available
0
0
Note: An initial value of bit 1 depends on the CNV SS pin level.
Fig. 3.5.28 Structure of CPU mode register
3850/3851 Group User’s Manual
3-53
APPENDIX
3.5 List of registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address : 3C
B
Function
Name
0 INT 0 interrupt request bit
1 SCL/SDA interrupt request bit
2 INT 1 interrupt request bit
3 INT 2 interrupt request bit
4 INT 3 interrupt request bit
5 I2C interrupt request bit
6 Timer X interrupt request bit
7 Timer Y interrupt request bit
16]
At reset
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 3.5.29 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2) [Address : 3D
B
16]
Function
Name
At reset
0
✽
0
✽
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
1
interrupt
request
bit
CNTR
0 : No interrupt request issued
5
1 : Interrupt request issued
AD
converter
interrupt
request
0 : No interrupt request issued
6
1 : Interrupt request issued
bit
Nothing
is
allocated
for
this
bit.
This
is a write disabled bit.
7
When this bit is read out, the value is “0”.
0
✽
0
✽
0
✽
0
✕
1 Timer 2 interrupt request bit
2 Serial I/O receive interrupt
request bit
3 Serial I/O transmit interrupt
request bit
4 CNTR 0 interrupt request bit
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 3.5.30 Structure of Interrupt request register 2
3-54
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 Timer 1 interrupt request bit
3850/3851 Group User’s Manual
APPENDIX
3.5 List of registers
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E
B
Function
Name
0 INT 0 interrupt enable bit
1 SCL/SDA interrupt enable bit
2 INT 1 interrupt enable bit
3 INT 2 interrupt enable bit
4 INT 3 interrupt enable bit
5 I2C interrupt enable bit
6 Timer X interrupt enable bit
7 Timer Y interrupt enable bit
16]
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset
R W
0
0
0
0
0
0
0
0
Fig. 3.5.31 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2 (ICON2) [Address : 3F 16]
B
Function
Name
0 Timer 1 interrupt enable bit
1 Timer 2 interrupt enable bit
2 Serial I/O receive interrupt
enable bit
3 Serial I/O transmit interrupt
enable bit
4 CNTR 0 interrupt enable bit
5 CNTR 1 interrupt enable bit
6 AD converter interrupt enable
bit
7 Fix this bit to “0”.
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset
R W
0
0
0
0
0
0
0
0
Fig. 3.5.32 Structure of Interrupt control register 2
3850/3851 Group User’s Manual
3-55
APPENDIX
3.6 Mask ROM confirmation form
3.6 Mask ROM ordering method
GZZ-SH53-11B<86A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38503M2-XXXSP/FP
MITSUBISHI ELECTRIC
Date:
Receipt
Section head Supervisor
signature
signature
Note : Please fill in all items marked ❈.
Date
issued
)
Date:
Submitted by
Issuance
signature
❈ Customer
TEL
(
Company
name
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data.
We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name:
M38503M2-XXXSP
M38503M2-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27512
27256
EPROM address
000016
Product name
000F16
001016
607F16
608016
7FFD16
7FFE16
7FFF16
ASCII code :
‘M38503M2-’
data
ROM (8K-130) bytes
In the address space of the microcomputer, the internal
ROM area is from address E08016 to FFFD 16. The reset
vector is stored in addresses FFFC16 and FFFD16 .
EPROM address
000016
Product name
000F16
001016
E07F16
E08016
FFFD16
FFFE16
FFFF16
ASCII code :
‘M38503M2-’
data
ROM (8K-130) bytes
Address
000016
000116
000216
000316
000416
000516
000616
000716
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38503M2–”
must be entered in addresses 0000 16 to 0008 16. And
set the data “FF 16” in addresses 000916 to 000F16 .
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
(1/2)
3-56
3850/3851 Group User’s Manual
‘M’ = 4D16
‘3’ = 33 16
‘8’ = 38 16
‘5’ = 35 16
‘0’ = 30 16
‘3’ = 33 16
‘M’ = 4D16
‘2’ = 32 16
Address
000816
000916
000A16
000B16
000C 16
000D 16
000E16
000F 16
‘–’ = 2D16
FF 16
FF 16
FF 16
FF 16
FF 16
FF 16
FF 16
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH53-11B<86A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38503M2-XXXSP/FP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program because ASCII codes of the product name are written to addresses 0000 16 to 000816 of EPROM.
EPROM type
27256
27512
The pseudo-command
*= $8000
.BYTE ‘M38503M2–’
*= $0000
.BYTE ‘M38503M2–’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM
will not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate
mark specification form (42P4B for M38503M2-XXXSP, 42P2R-A for M38503M2-XXXFP) and attach it to the mask
ROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-X OUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
MHz
f(XIN) =
(2) Which function will you use the pins P21/X CIN and P20/XCOUT as P21 and P2 0, or XCIN and XCOUT ?
Ports P21 and P20 function
XCIN and XCOUT function (external resonator)
❈ 4. Comments
(2/2)
3850/3851 Group User’s Manual
3-57
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH11-40A<6YA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38503M4-XXXSP/FP
MITSUBISHI ELECTRIC
Date:
Receipt
Section head Supervisor
signature
signature
Note : Please fill in all items marked ❈.
Date
issued
)
Date:
Submitted by
Issuance
signature
❈ Customer
TEL
(
Company
name
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data.
We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name:
M38503M4-XXXSP
M38503M4-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
EPROM address
000016
Product name
000F16
001016
407F16
408016
7FFD16
7FFE16
7FFF 16
ASCII code :
‘M38503M4-’
data
ROM (16K-130) bytes
27512
In the address space of the microcomputer, the internal
ROM area is from address C08016 to FFFD 16. The reset
vector is stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
000F16
001016
C07F16
C08016
FFFD16
FFFE 16
FFFF16
ASCII code :
‘M38503M4-’
data
ROM (16K-130) bytes
Address
000016
000116
000216
000316
000416
000516
000616
000716
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38503M4–”
must be entered in addresses 0000 16 to 0008 16. And
set the data “FF 16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
(1/2)
3-58
3850/3851 Group User’s Manual
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘5’ = 3516
‘0’ = 3016
‘3’ = 3316
‘M’ = 4D16
‘4’ = 3416
Address
000816
000916
000A16
000B16
000C 16
000D 16
000E16
000F 16
‘–’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH11-40A<6YA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38503M4-XXXSP/FP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program because ASCII codes of the product name are written to addresses 0000 16 to 000816 of EPROM.
EPROM type
27256
27512
The pseudo-command
*= $8000
.BYTE ‘M38503M4–’
*= $0000
.BYTE ‘M38503M4–’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM
will not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate
mark specification form (42P4B for M38503M4-XXXSP, 42P2R-A for M38503M4-XXXFP) and attach it to the mask
ROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-X OUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
f(XIN) =
MHz
(2) Which function will you use the pins P21/X CIN and P20/XCOUT as P21 and P2 0, or XCIN and XCOUT ?
Ports P21 and P20 function
XCIN and XCOUT function (external resonator)
❈ 4. Comments
(2/2)
3850/3851 Group User’s Manual
3-59
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH54-31B<89A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38504M6-XXXSP/FP
MITSUBISHI ELECTRIC
Date:
Receipt
Section head Supervisor
signature
signature
Note : Please fill in all items marked ❈.
Date
issued
Date:
)
Submitted by
Issuance
signature
❈ Customer
TEL
(
Company
name
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data.
We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M38504M6-XXXSP
M38504M6-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
EPROM address
000016
Product name
000F16
001016
207F16
208016
7FFD16
7FFE16
7FFF16
ASCII code :
‘M38504M6-’
data
ROM (24K-130) bytes
27512
In the address space of the microcomputer, the internal
ROM area is from address A080 16 to FFFD16 . The reset
vector is stored in addresses FFFC16 and FFFD 16.
EPROM address
000016
Product name
000F16
001016
A07F16
A08016
FFFD16
FFFE16
FFFF16
ASCII code :
‘M38504M6-’
data
ROM (24K-130) bytes
Address
000016
000116
000216
000316
000416
000516
000616
000716
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38504M6–”
must be entered in addresses 000016 to 000816 . And
set the data “FF16” in addresses 000916 to 000F 16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
(1/2)
3-60
3850/3851 Group User’s Manual
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘5’ = 3516
‘0’ = 3016
‘4’ = 3416
‘M’ = 4D16
‘6’ = 3616
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘–’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH54-31B<89A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38504M6-XXXSP/FP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program.
EPROM type
27256
27512
The pseudo-command
*= $8000
.BYTE ‘M38504M6–’
*= $0000
.BYTE ‘M38504M6–’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM
will not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate
mark specification form (42P4B for M38504M6-XXXSP , 42P2R for M38504M6-XXXFP) and attach it to the mask ROM
confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
f(X IN) =
MHz
(2) Which function will you use the pins P21/XCIN and P20/X COUT as P21 and P20, or XCIN and XCOUT ?
Ports P21 and P2 0 function
XCIN and XCOUT function (external resonator)
❈ 4. Comments
(2/2)
3850/3851 Group User’s Manual
3-61
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH52-61B<83A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38513M4-XXXSP/FP
MITSUBISHI ELECTRIC
Date:
Receipt
Section head Supervisor
signature
signature
Note : Please fill in all items marked ❈.
Date
issued
)
Date:
Submitted by
Issuance
signature
❈ Customer
TEL
(
Company
name
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data.
We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name:
M38513M4-XXXSP
M38513M4-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27512
27256
EPROM address
000016
Product name
000F16
001016
407F16
408016
7FFD16
7FFE16
7FFF16
ASCII code :
‘M38513M4-’
data
ROM (16K-130) bytes
In the address space of the microcomputer, the internal
ROM area is from address C08016 to FFFD16 . The reset
vector is stored in addresses FFFC16 and FFFD16 .
EPROM address
000016
Product name
000F16
001016
C07F16
C08016
FFFD16
FFFE16
FFFF16
ASCII code :
‘M38513M4-’
data
ROM (16K-130) bytes
Address
000016
000116
000216
000316
000416
000516
000616
000716
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38513M4–”
must be entered in addresses 0000 16 to 0008 16. And
set the data “FF 16” in addresses 000916 to 000F16 .
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
(1/2)
3-62
3850/3851 Group User’s Manual
‘M’ = 4D16
‘3’ = 33 16
‘8’ = 38 16
‘5’ = 35 16
‘1’ = 31 16
‘3’ = 33 16
‘M’ = 4D16
‘4’ = 34 16
Address
000816
000916
000A16
000B16
000C 16
000D 16
000E16
000F 16
‘–’ = 2D16
FF 16
FF 16
FF 16
FF 16
FF 16
FF 16
FF 16
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH52-61B<83A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38513M4-XXXSP/FP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program because ASCII codes of the product name are written to addresses 0000 16 to 000816 of EPROM.
EPROM type
27256
27512
The pseudo-command
*= $8000
.BYTE ‘M38513M4–’
*= $0000
.BYTE ‘M38513M4–’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM
will not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate
mark specification form (42P4B for M38513M4-XXXSP, 42P2R for M38513M4-XXXFP) and attach it to the mask ROM
confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-X OUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
MHz
f(XIN) =
(2) Which function will you use the pins P21/X CIN and P20/XCOUT as P21 and P2 0, or XCIN and XCOUT ?
Ports P21 and P20 function
XCIN and XCOUT function (external resonator)
(3) Will you use the I2C-BUS function or the SM-BUS function ?
I2C-BUS function used
SM-BUS function used
Not used
❈ 4. Comments
(2/2)
3850/3851 Group User’s Manual
3-63
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH54-32B<89A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38514M6-XXXSP/FP
MITSUBISHI ELECTRIC
Date:
Receipt
Section head Supervisor
signature
signature
Note : Please fill in all items marked ❈.
Date
issued
Date:
)
Submitted by
Issuance
signature
❈ Customer
TEL
(
Company
name
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data.
We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M38514M6-XXXSP
M38514M6-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
EPROM address
000016
Product name
000F16
001016
207F16
208016
7FFD16
7FFE16
7FFF16
ASCII code :
‘M38514M6-’
data
ROM (24K-130) bytes
27512
In the address space of the microcomputer, the internal
ROM area is from address A080 16 to FFFD16 . The reset
vector is stored in addresses FFFC16 and FFFD 16.
EPROM address
000016
Product name
000F16
001016
A07F16
A08016
FFFD16
FFFE16
FFFF16
ASCII code :
‘M38514M6-’
data
ROM (24K-130) bytes
Address
000016
000116
000216
000316
000416
000516
000616
000716
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38514M6–”
must be entered in addresses 000016 to 000816 . And
set the data “FF16” in addresses 000916 to 000F 16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
(1/2)
3-64
3850/3851 Group User’s Manual
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘5’ = 3516
‘1’ = 31 16
‘4’ = 3416
‘M’ = 4D16
‘6’ = 3616
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘–’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH54-32B<89A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38514M6-XXXSP/FP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program.
EPROM type
27256
27512
The pseudo-command
*= $8000
.BYTE ‘M38514M6–’
*= $0000
.BYTE ‘M38514M6–’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM
will not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate
mark specification form (42P4B for M38514M6-XXXSP , 42P2R for M38514M6-XXXFP) and attach it to the mask ROM
confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
f(X IN) =
MHz
(2) Which function will you use the pins P21/XCIN and P20/X COUT as P21 and P20, or XCIN and XCOUT ?
Ports P21 and P2 0 function
XCIN and XCOUT function (external resonator)
(3) Will you use the I2C-BUS function or the SM-BUS function ?
I2C-BUS function used
SM-BUS function used
Not used
❈ 4. Comments
(2/2)
3850/3851 Group User’s Manual
3-65
APPENDIX
3.7 ROM programming confirmation form
3.7 ROM programming confirmation form
GZZ-SH11-41A<6YA0>
ROM number
Date:
Section head Supervisor
signature
signature
Receipt
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38503E4-XXXSP/FP
MITSUBISHI ELECTRIC
Note : Please fill in all items marked ❈.
Date
issued
Date:
)
Submitted by
Issuance
signature
❈ Customer
TEL
(
Company
name
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based
on this data. We shall assume the responsibility for errors only if the programming data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name:
M38503E4-XXXSP
M38503E4-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
EPROM address
000016
Product name
000F16
001016
407F16
408016
7FFD16
7FFE16
7FFF 16
ASCII code :
‘M38503E4-’
data
ROM (16K-130) bytes
27512
In the address space of the microcomputer, the internal
ROM area is from address C08016 to FFFD 16. The reset
vector is stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
000F16
001016
C07F16
C08016
FFFD16
FFFE 16
FFFF16
ASCII code :
‘M38503E4-’
data
ROM (16K-130) bytes
Address
000016
000116
000216
000316
000416
000516
000616
000716
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38503E4–”
must be entered in addresses 0000 16 to 0008 16. And
set the data “FF 16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
(1/2)
3-66
3850/3851 Group User’s Manual
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘5’ = 3516
‘0’ = 3016
‘3’ = 3316
‘E’ = 4516
‘4’ = 3416
Address
000816
000916
000A16
000B16
000C 16
000D 16
000E16
000F 16
‘–’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
APPENDIX
3.7 ROM programming confirmation form
GZZ-SH11-41A<6YA0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38503E4-XXXSP/FP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program because ASCII codes of the product name are written to addresses 0000 16 to 000816 of EPROM.
EPROM type
27256
27512
The pseudo-command
*= $8000
.BYTE ‘M38503E4–’
*= $0000
.BYTE ‘M38503E4–’
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation
form, the ROM will not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate
mark specification form; 42P2R-A for the M38503E4-XXXFP, the shrink DIP package Mark Specification Form (only for
built-in One Time PROM microcomputer) for the M38503E4-XXXSP; and attach it to the ROM programming confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-X OUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
f(XIN) =
MHz
(2) Which function will you use the pins P21/X CIN and P20/XCOUT as P21 and P2 0, or XCIN and XCOUT ?
Ports P21 and P20 function
XCIN and XCOUT function (external resonator)
❈ 4. Comments
(2/2)
3850/3851 Group User’s Manual
3-67
APPENDIX
3.7 ROM programming confirmation form
GZZ-SH53-16B<86A0>
ROM number
Date:
Section head Supervisor
signature
signature
Receipt
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38504E6-XXXFP/SP
MITSUBISHI ELECTRIC
Note : Please fill in all items marked ❈.
Date
issued
Date:
)
Submitted by
Issuance
signature
❈ Customer
TEL
(
Company
name
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based
on this data. We shall assume the responsibility for errors only if the programming data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Product name:
M38504E6-XXXFP
M38504E6-XXXSP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
EPROM address
000016
Product name
000F16
001016
207F16
208016
7FFD16
7FFE16
7FFF16
ASCII code :
‘M38504E6-’
data
ROM (24K-130) bytes
27512
In the address space of the microcomputer, the internal
ROM area is from address A080 16 to FFFD16 . The reset
vector is stored in addresses FFFC16 and FFFD 16.
EPROM address
0000 16
Product name
000F16
001016
A07F16
A08016
FFFD 16
FFFE 16
FFFF16
ASCII code :
‘M38504E6-’
data
ROM (24K-130) bytes
Address
000016
000116
000216
000316
000416
000516
000616
000716
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38504E6–”
must be entered in addresses 000016 to 000816 . And
set the data “FF16” in addresses 000916 to 000F 16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
(1/2)
3-68
3850/3851 Group User’s Manual
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘5’ = 3516
‘0’ = 3016
‘4’ = 3416
‘E’ = 4516
‘6’ = 3616
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘–’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
APPENDIX
3.7 ROM programming confirmation form
GZZ-SH53-16B<86A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38504E6-XXXFP/SP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program because ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
27256
27512
The pseudo-command
*= $8000
.BYTE ‘M38504E6–’
*= $0000
.BYTE ‘M38504E6–’
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation
form, the ROM will not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate
mark specification form; 42P2R for the M38504E6-XXXFP, the shrink DIP package Mark Specification Form (only for
built-in One Time PROM microcomputer) for the M38504E6-XXXSP; and attach it to the ROM programming confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
f(X IN) =
MHz
(2) Which function will you use the pins P21/XCIN and P20/X COUT as P21 and P20, or XCIN and XCOUT ?
Ports P21 and P2 0 function
XCIN and XCOUT function (external resonator)
❈ 4. Comments
(2/2)
3850/3851 Group User’s Manual
3-69
APPENDIX
3.7 ROM programming confirmation form
GZZ-SH11-43A<6YB0>
ROM number
Date:
Section head Supervisor
signature
signature
Receipt
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38513E4-XXXSP/FP
MITSUBISHI ELECTRIC
Note : Please fill in all items marked ❈.
Date
issued
Date:
)
Submitted by
Issuance
signature
❈ Customer
TEL
(
Company
name
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based
on this data. We shall assume the responsibility for errors only if the programming data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name:
M38513E4-XXXSP
M38513E4-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27512
27256
EPROM address
000016
Product name
000F16
001016
407F16
408016
7FFD16
7FFE16
7FFF16
ASCII code :
‘M38513E4-’
data
ROM (16K-130) bytes
In the address space of the microcomputer, the internal
ROM area is from address C08016 to FFFD16 . The reset
vector is stored in addresses FFFC16 and FFFD16 .
EPROM address
000016
Product name
000F16
001016
C07F16
C08016
FFFD16
FFFE16
FFFF16
ASCII code :
‘M38513E4-’
data
ROM (16K-130) bytes
Address
000016
000116
000216
000316
000416
000516
000616
000716
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38513E4–”
must be entered in addresses 0000 16 to 0008 16. And
set the data “FF 16” in addresses 000916 to 000F16 .
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
(1/2)
3-70
3850/3851 Group User’s Manual
‘M’ = 4D16
‘3’ = 33 16
‘8’ = 38 16
‘5’ = 35 16
‘1’ = 31 16
‘3’ = 33 16
‘E’ = 45 16
‘4’ = 34 16
Address
000816
000916
000A16
000B16
000C 16
000D 16
000E16
000F 16
‘–’ = 2D16
FF 16
FF 16
FF 16
FF 16
FF 16
FF 16
FF 16
APPENDIX
3.7 ROM programming confirmation form
GZZ-SH11-43A<6YB0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38513E4-XXXSP/FP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program because ASCII codes of the product name are written to addresses 0000 16 to 000816 of EPROM.
EPROM type
27256
27512
The pseudo-command
*= $8000
.BYTE ‘M38513E4–’
*= $0000
.BYTE ‘M38513E4–’
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation
form, the ROM will not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate
mark specification form; 42P2R for the M38513E4-XXXFP, the shrink DIP package Mark Specification Form (only for
built-in One Time PROM microcomputer) for the M38513E4-XXXSP; and attach it to the ROM programming confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-X OUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
f(XIN) =
MHz
(2) Which function will you use the pins P21/X CIN and P20/XCOUT as P21 and P2 0, or XCIN and XCOUT ?
Ports P21 and P20 function
XCIN and XCOUT function (external resonator)
(3) Will you use the I2C-BUS function or the SM-BUS function ?
I2C-BUS function used
SM-BUS function used
Not used
❈ 4. Comments
(2/2)
3850/3851 Group User’s Manual
3-71
APPENDIX
3.7 ROM programming confirmation form
GZZ-SH53-16B<86A0>
ROM number
Date:
Section head Supervisor
signature
signature
Receipt
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38514E6-XXXFP/SP
MITSUBISHI ELECTRIC
Note : Please fill in all items marked ❈.
Date
issued
Date:
)
Submitted by
Issuance
signature
❈ Customer
TEL
(
Company
name
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based
on this data. We shall assume the responsibility for errors only if the programming data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Product name:
M38514E6-XXXFP
M38514E6-XXXSP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
EPROM address
000016
Product name
000F16
001016
207F16
208016
7FFD16
7FFE16
7FFF16
ASCII code :
‘M38514E6-’
data
ROM (24K-130) bytes
27512
In the address space of the microcomputer, the internal
ROM area is from address A080 16 to FFFD16 . The reset
vector is stored in addresses FFFC16 and FFFD 16.
EPROM address
0000 16
Product name
000F16
001016
A07F16
A08016
FFFD 16
FFFE 16
FFFF16
ASCII code :
‘M38514E6-’
data
ROM (24K-130) bytes
Address
000016
000116
000216
000316
000416
000516
000616
000716
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38514E6–”
must be entered in addresses 000016 to 000816 . And
set the data “FF16” in addresses 000916 to 000F 16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
(1/2)
3-72
3850/3851 Group User’s Manual
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘5’ = 3516
‘1’ = 31 16
‘4’ = 3416
‘E’ = 4516
‘6’ = 3616
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘–’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
APPENDIX
3.7 ROM programming confirmation form
GZZ-SH53-16B<86A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38514E6-XXXFP/SP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program because ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
27256
27512
The pseudo-command
*= $8000
.BYTE ‘M38514E6–’
*= $0000
.BYTE ‘M38514E6–’
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation
form, the ROM will not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate
mark specification form; 42P2R for the M38514E6-XXXFP, the shrink DIP package Mark Specification Form (only for
built-in One Time PROM microcomputer) for the M38514E6-XXXSP; and attach it to the ROM programming confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
f(X IN) =
MHz
(2) Which function will you use the pins P21/XCIN and P20/X COUT as P21 and P20, or XCIN and XCOUT ?
Ports P21 and P2 0 function
(3) Will you use the
I2C-BUS
XCIN and XCOUT function (external resonator)
function or the SM-BUS function ?
I2C-BUS function used
SM-BUS function used
Not used
❈ 4. Comments
(2/2)
3850/3851 Group User’s Manual
3-73
APPENDIX
3.8 Mark specification form
3.8 Mark specification form
3-74
3850/3851 Group User’s Manual
APPENDIX
3.8 Mark specification form
3850/3851 Group User’s Manual
3-75
APPENDIX
3.9 Package outline
3.9 Package outline
42P2R-A
Plastic 42pin 450mil SSOP
EIAJ Package Code
SSOP42-P-450-0.80
Weight(g)
0.63
JEDEC Code
–
Lead Material
Alloy 42/Cu Alloy
e
b2
22
Caution !
E
HE
e1
I2
42
F
Symbol
TBD
21
1
A
D
Recommended Mount Pad
A1
A2
A
A1
A2
b
c
D
E
e
HE
L
L1
y
Dimension in Millimeters
Min
Nom
Max
2.4
–
–
–
–
0.05
–
2.0
–
0.5
0.4
0.35
0.2
0.15
0.13
17.7
17.5
17.3
8.6
8.4
8.2
–
0.8
–
12.23
11.93
11.63
0.7
0.5
0.3
–
1.765
–
0.15
–
–
0°
–
10°
–
0.5
–
–
11.43
–
–
1.27
–
42P2R-A package outline is to be updated.
y
b
L
L1
e
c
b2
e1
I2
Detail F
42P4B
Plastic 42pin 600mil SDIP
Weight(g)
4.1
JEDEC Code
–
Lead Material
Alloy 42/Cu Alloy
22
1
21
E
42
e1
c
EIAJ Package Code
SDIP42-P-600-1.78
Symbol
L
A1
A
A2
D
e
b1
b
SEATING PLANE
3-76
3850/3851 Group User’s Manual
b2
A
A1
A2
b
b1
b2
c
D
E
e
e1
L
Dimension in Millimeters
Min
Nom
Max
–
–
5.5
0.51
–
–
–
3.8
–
0.35
0.45
0.55
0.9
1.0
1.3
0.63
0.73
1.03
0.22
0.27
0.34
36.5
36.7
36.9
12.85
13.0
13.15
–
1.778
–
–
15.24
–
3.0
–
–
0°
–
15°
APPENDIX
3.9 Package outline
42S1B-A
Metal seal 42pin 600mil DIP
EIAJ Package Code
WDIP42-C-600-1.78
JEDEC Code
–
Weight(g)
1
21
e1
22
E
42
c
D
A1
L
A
A2
Symbol
Z
e
b
b1
SEATING PLANE
3850/3851 Group User’s Manual
A
A1
A2
b
b1
c
D
E
e
e1
L
Z
Dimension in Millimeters
Min
Nom
Max
5.0
–
–
–
–
1.0
3.44
–
–
0.38
0.54
0.46
0.7
0.8
0.9
0.17
0.33
0.25
–
–
41.1
–
15.8
–
–
–
1.778
–
–
15.24
3.05
–
–
–
–
3.05
3-77
APPENDIX
3.10 Machine instructions
3.10 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
ADC
(Note 1)
(Note 5)
When T = 0
A←A+M+C
When T = 1
M(X) ← M(X) + M + C
AND
(Note 1)
When TV= 0
A←A M
When T = 1 V
M(X) ← M(X) M
ASL
C←
7
0
←0
IMM
# OP n
A
# OP n
BIT,A,AR
BIT,
# OP n
ZP
# OP n
BIT,ZP,
ZPR
BIT,
# OP n
When T = 0, this instruction adds the contents
M, C, and A; and stores the results in A and C.
When T = 1, this instruction adds the contents
of M(X), M and C; and stores the results in
M(X) and C. When T=1, the contents of A remain unchanged, but the contents of status
flags are changed.
M(X) represents the contents of memory
where is indicated by X.
69 2
2
65 3
2
When T = 0, this instruction transfers the contents of A and M to the ALU which performs a
bit-wise AND operation and stores the result
back in A.
When T = 1, this instruction transfers the contents M(X) and M to the ALU which performs a
bit-wise AND operation and stores the results
back in M(X). When T = 1 the contents of A remain unchanged, but status flags are
changed.
M(X) represents the contents of memory
where is indicated by X.
29 2
2
25 3
2
06 5
2
This instruction shifts the content of A or M by
one bit to the left, with bit 0 always being set to
0 and bit 7 of A or M always being contained in
C.
0A 2
1
#
BBC
(Note 4)
Ai or Mi = 0?
This instruction tests the designated bit i of M
or A and takes a branch if the bit is 0. The
branch address is specified by a relative address. If the bit is 1, next instruction is
executed.
13
+ 4
20i
2
17
+ 5
20i
3
BBS
(Note 4)
Ai or Mi = 1?
This instruction tests the designated bit i of the
M or A and takes a branch if the bit is 1. The
branch address is specified by a relative address. If the bit is 0, next instruction is
executed.
03
+ 4
20i
2
07
+ 5
20i
3
BCC
(Note 4)
C = 0?
This instruction takes a branch to the appointed address if C is 0. The branch address
is specified by a relative address. If C is 1, the
next instruction is executed.
BCS
(Note 4)
C = 1?
This instruction takes a branch to the appointed address if C is 1. The branch address
is specified by a relative address. If C is 0, the
next instruction is executed.
BEQ
(Note 4)
Z = 1?
This instruction takes a branch to the appointed address when Z is 1. The branch
address is specified by a relative address.
If Z is 0, the next instruction is executed.
BIT
A
BMI
(Note 4)
N = 1?
This instruction takes a branch to the appointed address when N is 1. The branch
address is specified by a relative address.
If N is 0, the next instruction is executed.
BNE
(Note 4)
Z = 0?
This instruction takes a branch to the appointed address if Z is 0. The branch address
is specified by a relative address. If Z is 1, the
next instruction is executed.
3-78
V
M
This instruction takes a bit-wise logical AND of
A and M contents; however, the contents of A
and M are not modified.
The contents of N, V, Z are changed, but the
contents of A, M remain unchanged.
3850/3851 Group User’s Manual
24 3
2
APPENDIX
3.10 Machine instructions
Addressing mode
ZP, X
ZP, Y
OP n
# OP n
75 4
ABS
ABS, X
ABS, Y
IND
# OP n
# OP n
# OP n
# OP n
2
6D 4
3 7D 5
3 79 5
35 4
2
2D 4
3 3D 5
3 39 5
16 6
2
0E 6
3 1E 7
3
2C 4
Processor status register
ZP, IND
# OP n
IND, X
IND, Y
REL
SP
# OP n
7
5
4
3
2
1
0
N V
T
B
D
I
Z
C
# OP n
# OP n
# OP n
3
61 6
2 71 6
2
N V
•
•
•
•
Z
C
3
21 6
2 31 6
2
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
90 2
2
•
•
•
•
•
•
•
•
B0 2
2
•
•
•
•
•
•
•
•
F0 2
2
•
•
•
•
•
•
•
•
M7 M6 •
•
•
•
Z
•
3
3850/3851 Group User’s Manual
#
6
30 2
2
•
•
•
•
•
•
•
•
D0 2
2
•
•
•
•
•
•
•
•
3-79
APPENDIX
3.10 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
IMM
OP n
# OP n
00 7
1
BPL
(Note 4)
N = 0?
This instruction takes a branch to the appointed address if N is 0. The branch address
is specified by a relative address. If N is 1, the
next instruction is executed.
BRA
PC ← PC ± offset
This instruction branches to the appointed address. The branch address is specified by a
relative address.
BRK
B←1
(PC) ← (PC) + 2
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
M(S) ← PS
S←S–1
I← 1
PCL ← ADL
PCH ← ADH
When the BRK instruction is executed, the
CPU pushes the current PC contents onto the
stack. The BADRS designated in the interrupt
vector table is stored into the PC.
BVC
(Note 4)
V = 0?
This instruction takes a branch to the appointed address if V is 0. The branch address
is specified by a relative address. If V is 1, the
next instruction is executed.
BVS
(Note 4)
V = 1?
This instruction takes a branch to the appointed address when V is 1. The branch
address is specified by a relative address.
When V is 0, the next instruction is executed.
CLB
Ai or Mi ← 0
This instruction clears the designated bit i of A
or M.
CLC
C←0
This instruction clears C.
18 2
1
CLD
D←0
This instruction clears D.
D8 2
1
CLI
I←0
This instruction clears I.
58 2
1
CLT
T←0
This instruction clears T.
12 2
1
CLV
V←0
This instruction clears V.
B8 2
1
CMP
(Note 3)
When T = 0
A–M
When T = 1
M(X) – M
When T = 0, this instruction subtracts the contents of M from the contents of A. The result is
not stored and the contents of A or M are not
modified.
When T = 1, the CMP subtracts the contents
of M from the contents of M(X). The result is
not stored and the contents of X, M, and A are
not modified.
M(X) represents the contents of memory
where is indicated by X.
COM
M←M
This instruction takes the one’s complement of
the contents of M and stores the result in M.
CPX
X–M
This instruction subtracts the contents of M
from the contents of X. The result is not stored
and the contents of X and M are not modified.
E0 2
CPY
Y–M
This instruction subtracts the contents of M
from the contents of Y. The result is not stored
and the contents of Y and M are not modified.
C0 2
DEC
A ← A – 1 or
M←M–1
This instruction subtracts 1 from the contents
of A or M.
A
# OP n
BIT, A
# OP n
2
1B
+
20i
C9 2
ZP
# OP n
BIT, ZP
# OP n
#
1F
+ 5
20i
2
1
C5 3
2
44 5
2
2
E4 3
2
2
C4 3
2
C6 5
2
2
__
3-80
3850/3851 Group User’s Manual
1A 2
1
APPENDIX
3.10 Machine instructions
Addressing mode
ZP, X
OP n
D5 4
D6 6
ZP, Y
# OP n
2
2
ABS
# OP n
CD 4
ABS, X
# OP n
3 DD 5
ABS, Y
# OP n
3 D9 5
IND
# OP n
3
Processor status register
ZP, IND
# OP n
IND, X
# OP n
C1 6
IND, Y
# OP n
2 D1 6
REL
# OP n
2
SP
# OP n
7
#
6
5
4
3
2
1
0
N V
T
B
D
I
Z
C
10 2
2
•
•
•
•
•
•
•
•
80 4
2
•
•
•
•
•
•
•
•
•
•
•
1
•
1
•
•
50 2
2
•
•
•
•
•
•
•
•
70 2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
0
•
•
•
•
•
•
•
•
0
•
•
•
•
0
•
•
•
•
•
•
0
•
•
•
•
•
•
N
•
•
•
•
•
Z
C
N
•
•
•
•
•
Z
•
EC 4
3
N
•
•
•
•
•
Z
C
CC 4
3
N
•
•
•
•
•
Z
C
CE 6
3 DE 7
N
•
•
•
•
•
Z
•
3
3850/3851 Group User’s Manual
3-81
APPENDIX
3.10 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
IMM
# OP n
DEX
X←X–1
This instruction subtracts one from the current CA 2
contents of X.
1
DEY
Y←Y–1
This instruction subtracts one from the current
contents of Y.
88 2
1
DIV
A ← (M(zz + X + 1),
M(zz + X )) / A
M(S) ← one's complement of Remainder
S←S–1
Divides the 16-bit data in M(zz+(X)) (low-order
byte) and M(zz+(X)+1) (high-order byte) by the
contents of A. The quotient is stored in A and
the one's complement of the remainder is
pushed onto the stack.
EOR
(Note 1)
When T = 0
–M
A←AV
When T = 0, this instruction transfers the contents of the M and A to the ALU which
performs a bit-wise Exclusive OR, and stores
the result in A.
When T = 1, the contents of M(X) and M are
transferred to the ALU, which performs a bitwise Exclusive OR and stores the results in
M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
When T = 1
–M
M(X) ← M(X) V
49 2
A
# OP n
BIT, A
# OP n
2
ZP
# OP n
BIT, ZP
# OP n
45 3
2
E6 5
2
A5 3
2
3C 4
3
INC
A ← A + 1 or
M←M+1
This instruction adds one to the contents of A
or M.
INX
X←X+1
This instruction adds one to the contents of X.
E8 2
1
INY
Y←Y+1
This instruction adds one to the contents of Y.
C8 2
1
JMP
If addressing mode is ABS
PCL ← ADL
PCH ← ADH
If addressing mode is IND
PCL ← M (AD H, ADL)
PCH ← M (ADH, AD L + 1)
If addressing mode is ZP, IND
PCL ← M(00, AD L)
PCH ← M(00, AD L + 1)
This instruction jumps to the address designated by the following three addressing
modes:
Absolute
Indirect Absolute
Zero Page Indirect Absolute
JSR
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
After executing the above,
if addressing mode is ABS,
PCL ← ADL
PCH ← ADH
if addressing mode is SP,
PCL ← ADL
PCH ← FF
If addressing mode is ZP, IND,
PCL ← M(00, AD L)
PCH ← M(00, AD L + 1)
This instruction stores the contents of the PC
in the stack, then jumps to the address designated by the following addressing modes:
Absolute
Special Page
Zero Page Indirect Absolute
LDA
(Note 2)
When T = 0
A←M
When T = 1
M(X) ← M
When T = 0, this instruction transfers the contents of M to A.
When T = 1, this instruction transfers the contents of M to (M(X)). The contents of A remain
unchanged, but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
LDM
M ← nn
This instruction loads the immediate value in
M.
LDX
X←M
This instruction loads the contents of M in X.
A2 2
2
A6 3
2
LDY
Y←M
This instruction loads the contents of M in Y.
A0 2
2
A4 3
2
3-82
3A 2
3850/3851 Group User’s Manual
A9 2
2
1
#
APPENDIX
3.10 Machine instructions
Addressing mode
ZP, X
OP n
ZP, Y
# OP n
ABS
# OP n
ABS, X
# OP n
ABS, Y
# OP n
IND
# OP n
Processor status register
ZP, IND
# OP n
IND, X
# OP n
IND, Y
# OP n
REL
# OP n
SP
# OP n
7
#
E2 16 2
55 4
2
4D 4
3 5D 5
3 59 5
F6 6
2
EE 6
3 FE 7
3
B5 4
2
B6 4
B4 4
2
4C 3
3
20 6
3
AD 4
3 BD 5
2 AE 4
AC 4
41 6
6C 5
3 B9 5
3
3 BC 5
3
BE 5
3
3 B2 4
2
02 7
2
2 51 6
2
22 5
A1 6
2 B1 6
3
3
3850/3851 Group User’s Manual
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2
6
5
4
3
2
1
0
N V
T
B
D
I
Z
C
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
3-83
APPENDIX
3.10 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
LSR
7
0→
0
→C
Multiplies Accumulator with the memory specified by the Zero Page X address mode and
stores the high-order byte of the result on the
Stack and the low-order byte in A.
NOP
PC ← PC + 1
This instruction adds one to the PC but does EA 2
no otheroperation.
ORA
(Note 1)
When T = 0
A←AVM
When T = 0, this instruction transfers the contents of A and M to the ALU which performs a
bit-wise “OR”, and stores the result in A.
When T = 1, this instruction transfers the contents of M(X) and the M to the ALU which
performs a bit-wise OR, and stores the result
in M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
PHP
PLA
PLP
ROL
S←S–1
1
# OP n
BIT, ZP
# OP n
46 5
2
05 3
2
1
09 2
2
1
M(S) ← PS
S←S–1
This instruction pushes the contents of PS to
the memory location designated by S and decrements the contents of S by one.
08 3
1
S←S+1
A ← M(S)
This instruction increments S by one and
stores the contents of the memory designated
by S in A.
68 4
1
S←S+1
PS ← M(S)
This instruction increments S by one and
stores the contents of the memory location
designated by S in PS.
28 4
1
7
←
This instruction shifts either A or M one bit left
through C. C is stored in bit 0 and bit 7 is
stored in C.
2A 2
1
26 5
2
This instruction shifts either A or M one bit
right through C. C is stored in bit 7 and bit 0 is
stored in C.
6A 2
1
66 5
2
82 8
2
0
←C ←
RRF
7
→
3-84
# OP n
ZP
48 3
7
C→
RTS
BIT, A
This instruction pushes the contents of A to
the memory location designated by S, and
decrements the contents of S by one.
ROR
RTI
# OP n
4A 2
M(S) • A ← A ✽ M(zz + X)
S←S–1
PHA
# OP n
A
This instruction shifts either A or M one bit to
the right such that bit 7 of the result always is
set to 0, and the bit 0 is stored in C.
MUL
When T = 1
M(X) ← M(X) V M
IMM
0
→
0
→
This instruction rotates 4 bits of the M content
to the right.
S←S+1
PS ← M(S)
S←S+1
PCL ← M(S)
S←S+1
PCH ← M(S)
This instruction increments S by one, and
stores the contents of the memory location
designated by S in PS. S is again incremented
by one and stores the contents of the memory
location designated by S in PC L . S is again
incremented by one and stores the contents of
memory location designated by S in PC H.
S←S+1
PCL ← M(S)
S←S+1
PCH ← M(S)
(PC) ← (PC) + 1
This instruction increments S by one and
stores the contents of the memory location
designated by S in PCL. S is again
incremented by one and the contents of the
memory location is stored in PC H . PC is
incremented by 1.
40 6
1
60 6
1
3850/3851 Group User’s Manual
#
APPENDIX
3.10 Machine instructions
Addressing mode
ZP, X
ZP, Y
OP n
# OP n
56 6
2
ABS
ABS, X
ABS, Y
# OP n
# OP n
# OP n
4E 6
3 5E 7
3
IND
# OP n
Processor status register
ZP, IND
# OP n
IND, X
# OP n
IND, Y
# OP n
# OP n
62 15 2
15 4
2
0D 4
3 1D 5
3 19 5
3
01 6
2 11 6
REL
2
SP
# OP n
7
#
6
5
4
3
2
1
0
N V
T
B
D
I
Z
C
0
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
(Value saved in stack)
36 6
2
2E 6
3 3E 7
3
N
•
•
•
•
•
Z
C
76 6
2
6E 6
3 7E 7
3
N
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
(Value saved in stack)
•
3850/3851 Group User’s Manual
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•
•
•
•
•
•
3-85
APPENDIX
3.10 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
SBC
(Note 1)
(Note 5)
When T = 0 _
A←A–M–C
When T = 1
_
M(X) ← M(X) – M – C
IMM
# OP n
When T = 0, this instruction subtracts the
value of M and the complement of C from A,
and stores the results in A and C.
When T = 1, the instruction subtracts the contents of M and the complement of C from the
contents of M(X), and stores the results in
M(X) and C.
A remain unchanged, but status flag are
changed.
M(X) represents the contents of memory
where is indicated by X.
E9 2
SEB
Ai or Mi ← 1
This instruction sets the designated bit i of A
or M.
SEC
C←1
This instruction sets C.
38 2
1
SED
D←1
This instruction set D.
F8 2
1
SEI
I←1
This instruction set I.
78 2
1
SET
T←1
This instruction set T.
32 2
1
STA
M←A
This instruction stores the contents of A in M.
The contents of A does not change.
This instruction resets the oscillation control F/
F and the oscillation stops. Reset or interrupt
input is needed to wake up from this mode.
STP
A
# OP n
BIT, A
# OP n
# OP n
2
E5 3
0B
+ 2
20i
42 2
ZP
BIT, ZP
# OP n
2
1
0F
+ 5
20i
85 4
2
1
STX
M←X
This instruction stores the contents of X in M.
The contents of X does not change.
86 4
2
STY
M←Y
This instruction stores the contents of Y in M.
The contents of Y does not change.
84 4
2
TAX
X←A
This instruction stores the contents of A in X.
The contents of A does not change.
AA 2
1
TAY
Y←A
This instruction stores the contents of A in Y.
The contents of A does not change.
A8 2
1
TST
M = 0?
This instruction tests whether the contents of
M are “0” or not and modifies the N and Z.
64 3
2
TSX
X←S
This instruction transfers the contents of S in
X.
BA 2
1
TXA
A←X
This instruction stores the contents of X in A.
8A 2
1
TXS
S←X
This instruction stores the contents of X in S.
9A 2
1
TYA
A←Y
This instruction stores the contents of Y in A.
98 2
1
The WIT instruction stops the internal clock C2 2
but not the oscillation of the oscillation circuit
is not stopped.
CPU starts its function after the Timer X over
flows (comes to the terminal count). All registers or internal memory contents except Timer
X will not change during this mode. (Of course
needs VDD).
1
WIT
Notes 1
2
3
4
5
3-86
:
:
:
:
:
The number of cycles “n” is increased by 3 when T is 1.
The number of cycles “n” is increased by 2 when T is 1.
The number of cycles “n” is increased by 1 when T is 1.
The number of cycles “n” is increased by 2 when branching has occurred.
N, V, and Z flags are invalid in decimal operation mode.
3850/3851 Group User’s Manual
#
2
APPENDIX
3.10 Machine instructions
Addressing mode
ZP, X
ZP, Y
OP n
# OP n
F5 4
2
95 5
2
ABS, X
ABS, Y
IND
# OP n
# OP n
# OP n
# OP n
ED 4
3 FD 5
3 F9 5
3
8D 5
2
96 5
94 5
ABS
3 9D 6
3 99 6
3
Processor status register
ZP, IND
# OP n
IND, X
IND, Y
REL
# OP n
# OP n
# OP n
E1 6
2 F1 6
2
81 7
2 91 7
2
SP
# OP n
7
#
6
5
4
3
2
1
0
N V
T
B
D
I
Z
C
N V
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
•
•
•
•
1
•
•
•
•
•
•
•
•
1
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2 8E 5
3
•
•
•
•
•
•
•
•
8C 5
3
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
3850/3851 Group User’s Manual
3-87
APPENDIX
3.10 Machine instructions
Symbol
Contents
Symbol
IMP
IMM
A
BIT, A
BIT, A, R
ZP
BIT, ZP
BIT, ZP, R
ZP, X
ZP, Y
ABS
ABS, X
ABS, Y
IND
Implied addressing mode
Immediate addressing mode
Accumulator or Accumulator addressing mode
Accumulator bit addressing mode
Accumulator bit relative addressing mode
Zero page addressing mode
Zero page bit addressing mode
Zero page bit relative addressing mode
Zero page X addressing mode
Zero page Y addressing mode
Absolute addressing mode
Absolute X addressing mode
Absolute Y addressing mode
Indirect absolute addressing mode
ZP, IND
Zero page indirect absolute addressing mode
IND, X
IND, Y
REL
SP
C
Z
I
D
B
T
V
N
Indirect X addressing mode
Indirect Y addressing mode
Relative addressing mode
Special page addressing mode
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
X-modified arithmetic mode flag
Overflow flag
Negative flag
+
–
✽
/
V
V
–
V
–
←
X
Y
S
PC
PS
PCH
PCL
ADH
ADL
FF
nn
zz
M
M(X)
M(S)
M(AD H, ADL)
M(00, AD L)
Ai
Mi
OP
n
#
3-88
3851 Group User’s Manual
Contents
Addition
Subtraction
Multiplication
Division
Logical OR
Logical AND
Logical exclusive OR
Negation
Shows direction of data flow
Index register X
Index register Y
Stack pointer
Program counter
Processor status register
8 high-order bits of program counter
8 low-order bits of program counter
8 high-order bits of address
8 low-order bits of address
FF in Hexadecimal notation
Immediate value
Zero page address
Memory specified by address designation of any addressing mode
Memory of address indicated by contents of index
register X
Memory of address indicated by contents of stack
pointer
Contents of memory at address indicated by ADH and
ADL, in AD H is 8 high-order bits and ADL is 8 low-order bits.
Contents of address indicated by zero page ADL
Bit i (i = 0 to 7) of accumulator
Bit i (i = 0 to 7) of memory
Opcode
Number of cycles
Number of bytes
APPENDIX
3.11 List of instruction code
3.11 List of instruction code
D7 – D 4
D3 – D0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Hexadecimal
notation
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ORA
IMM
ASL
A
SEB
0, A
—
ORA
ABS
ASL
ABS
SEB
0, ZP
ORA
DEC
ABS, Y
A
CLB
0, A
—
0000
0
BRK
ORA
JSR
IND, X ZP, IND
BBS
0, A
—
ORA
ZP
ASL
ZP
BBS
0, ZP
PHP
0001
1
BPL
ORA
IND, Y
CLT
BBC
0, A
—
ORA
ZP, X
ASL
ZP, X
BBC
0, ZP
CLC
0010
2
JSR
ABS
AND
IND, X
JSR
SP
BBS
1, A
BIT
ZP
AND
ZP
ROL
ZP
BBS
1, ZP
PLP
AND
IMM
ROL
A
SEB
1, A
BIT
ABS
0011
3
BMI
AND
IND, Y
SET
BBC
1, A
—
AND
ZP, X
ROL
ZP, X
BBC
1, ZP
SEC
AND
ABS, Y
INC
A
CLB
1, A
ROL
CLB
LDM
AND
ZP ABS, X ABS, X 1, ZP
0100
4
RTI
EOR
IND, X
STP
BBS
2, A
COM
ZP
EOR
ZP
LSR
ZP
BBS
2, ZP
PHA
EOR
IMM
LSR
A
SEB
2, A
JMP
ABS
0101
5
BVC
EOR
IND, Y
—
BBC
2, A
—
EOR
ZP, X
LSR
ZP, X
BBC
2, ZP
CLI
EOR
ABS, Y
—
CLB
2, A
—
0110
6
RTS
MUL
ADC
IND, X ZP, X
BBS
3, A
TST
ZP
ADC
ZP
ROR
ZP
BBS
3, ZP
PLA
ADC
IMM
ROR
A
SEB
3, A
JMP
IND
0111
7
BVS
ADC
IND, Y
—
BBC
3, A
—
ADC
ZP, X
ROR
ZP, X
BBC
3, ZP
SEI
ADC
ABS, Y
—
CLB
3, A
—
1000
8
BRA
STA
IND, X
RRF
ZP
BBS
4, A
STY
ZP
STA
ZP
STX
ZP
BBS
4, ZP
DEY
—
TXA
SEB
4, A
STY
ABS
STA
ABS
STX
ABS
SEB
4, ZP
1001
9
BCC
STA
IND, Y
—
BBC
4, A
STY
ZP, X
STA
ZP, X
STX
ZP, Y
BBC
4, ZP
TYA
STA
ABS, Y
TXS
CLB
4, A
—
STA
ABS, X
—
CLB
4, ZP
1010
A
LDY
IMM
LDA
IND, X
LDX
IMM
BBS
5, A
LDY
ZP
LDA
ZP
LDX
ZP
BBS
5, ZP
TAY
LDA
IMM
TAX
SEB
5, A
LDY
ABS
LDA
ABS
LDX
ABS
SEB
5, ZP
1011
B
BCS
JMP
BBC
LDA
IND, Y ZP, IND 5, A
LDY
ZP, X
LDA
ZP, X
LDX
ZP, Y
BBC
5, ZP
CLV
LDA
ABS, Y
TSX
CLB
5, A
1100
C
CPY
IMM
CMP
IND, X
WIT
BBS
6, A
CPY
ZP
CMP
ZP
DEC
ZP
BBS
6, ZP
INY
CMP
IMM
DEX
SEB
6, A
CPY
ABS
1101
D
BNE
CMP
IND, Y
—
BBC
6, A
—
CMP
ZP, X
DEC
ZP, X
BBC
6, ZP
CLD
CMP
ABS, Y
—
CLB
6, A
—
1110
E
CPX
IMM
DIV
SBC
IND, X ZP, X
BBS
7, A
CPX
ZP
SBC
ZP
INC
ZP
BBS
7, ZP
INX
SBC
IMM
NOP
SEB
7, A
CPX
ABS
1111
F
BEQ
SBC
IND, Y
BBC
7, A
—
SBC
ZP, X
INC
ZP, X
BBC
7, ZP
SED
SBC
ABS, Y
—
CLB
7, A
—
—
ASL
CLB
ORA
ABS, X ABS, X 0, ZP
AND
ABS
EOR
ABS
ROL
ABS
LSR
ABS
SEB
1, ZP
SEB
2, ZP
LSR
CLB
EOR
ABS, X ABS, X 2, ZP
ADC
ABS
ROR
ABS
SEB
3, ZP
CLB
ADC ROR
ABS, X ABS, X 3, ZP
LDX
CLB
LDY
LDA
ABS, X ABS, X ABS, Y 5, ZP
CMP
ABS
DEC
ABS
SEB
6, ZP
DEC
CLB
CMP
ABS, X ABS, X 6, ZP
SBC
ABS
INC
ABS
SEB
7, ZP
INC
CLB
SBC
ABS, X ABS, X 7, ZP
: 3-byte instruction
: 2-byte instruction
: 1-byte instruction
3850/3851 Group User’s Manual
3-89
APPENDIX
3.12 SFR memory map
3.12 SFR memory map
000016
Port P0 (P0)
002016
Prescaler 12 (PRE12)
000116
Port P0 direction register (P0D)
002116
Timer 1 (T1)
000216
Port P1 (P1)
002216
Timer 2 (T2)
000316
Port P1 direction register (P1D)
002316
Timer XY mode register (TM)
000416
Port P2 (P2)
002416
Prescaler X (PREX)
000516
Port P2 direction register (P2D)
002516
Timer X (TX)
000616
Port P3 (P3)
002616
Prescaler Y (PREY)
000716
Port P3 direction register (P3D)
002716
Timer Y (TY)
Timer count source selection register (TCSS)
000816
Port P4 (P4)
002816
000916
Port P4 direction register (P4D)
002916
000A16
002A16
000B16
002B16
I2C data shift register (S0)
000C16
002C16
I2C address register (S0D)
000D16
002D16
I2C status register (S1)
000E16
002E16
I2C control register (S1D)
000F16
002F16
I2C clock control register (S2)
001016
003016
I2C start/stop condition control register (S2D)
001116
003116
Reserved ✽
001216
003216
001316
003316
003416
A-D control register (ADCON)
001516
Reserved ✽
003516
A-D conversion low-order register (ADL)
001616
Reserved ✽
003616
A-D conversion high-order register (ADH)
001716
Reserved ✽
003716
001816
Transmit/Receive buffer register (TB/RB)
003816
001916
Serial I/O status register (SIOSTS)
003916
Watchdog timer control register (WDTCON)
001A16
Serial I/O control register (SIOCON)
003A16
Interrupt edge selection register (INTEDGE)
001B16
UART control register (UARTCON)
003B16
CPU mode register (CPUM)
001C16
Baud rate generator (BRG)
003C16
Interrupt request register 1 (IREQ1)
001D16
PWM control register (PWMCON)
003D16
Interrupt request register 2 (IREQ2)
001E16
PWM prescaler (PREPWM)
003E16
Interrupt control register 1 (ICON1)
001F16
PWM register (PWM)
003F16
Interrupt control register 2 (ICON2)
001416
MISRG
✽ Reserved : Do not write “1” to this address.
3-90
3850/3851 Group User’s Manual
APPENDIX
3.13 Pin configurations
3.13 Pin configurations
PIN CONFIGURATION (TOP VIEW)
1
42
2
41
3
40
4
39
5
38
6
37
7
8
9
10
11
12
13
14
15
16
M38513M4-XXXFP
M38513M4-XXXSP
VCC
VREF
AVSS
P44/INT3/PWM
P43/INT2
P42/INT1
P41/INT0
P40/CNTR1
P27/CNTR0/SRDY
P26/SCLK
P25/SCL2/TxD
P24/SDA2/RxD
P23/SCL1
P22/SDA1
CNVSS
P21/XCIN
P20/XCOUT
RESET
XIN
XOUT
VSS
36
35
34
33
32
31
30
29
28
27
17
26
18
25
19
24
20
23
21
22
P30/AN0
P31/AN1
P32/AN2
P33/AN3
P34/AN4
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13/(LED0)
P14/(LED1)
P15/(LED2)
P16/(LED3)
P17/(LED4)
Package type : FP ........................... 42P2R-A (42-pin plastic-molded SSOP)
Package type : SP ........................... 42P4B (42-pin shrink plastic-molded DIP)
Fig. 3.13.1 M38513M4-XXXFP/SP pin configuration
3850/3851 Group User’s Manual
3-91
APPENDIX
3.13 Pin configurations
MEMORANDUM
3-92
3850/3851 Group User’s Manual
MITSUBISHI SEMICONDUCTORS
USER’S MANUAL
3850/3851 Group
Oct. First Edition 1998
Editioned by
Committee of editing of Mitsubishi Semiconductor USER’S MANUAL
Published by
Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission
of Mitsubishi Electric Corporation.
©1998 MITSUBISHI ELECTRIC CORPORATION
User’s Manual
3850/3851 Group
© 1998 MITSUBISHI ELECTRIC CORPORATION.
New publication, effective Oct. 1998.
Specifications subject to change without notice.