RENESAS 7534

REJ09B0178-0300
7534 Group
8
User’s Manual
RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 740 SERIES
Rev. 3.00
Revision date: Oct 23, 2006
www.renesas.com
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the
products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General
Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description
in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.
 The input pins of CMOS products are generally in the high-impedance state. In operation with an
unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an
associated shoot-through current flows internally, and malfunctions occur due to the false
recognition of the pin state as an input signal become possible. Unused pins should be handled as
described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
 The states of internal circuits in the LSI are indeterminate and the states of register settings and pins
are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states of pins are
not guaranteed from the moment when power is supplied until the reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function
are not guaranteed from the moment when power is supplied until the power reaches the level at
which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
 The reserved addresses are provided for the possible future expansion of functions. Do not access
these addresses; the correct operation of LSI is not guaranteed if they are accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become stable.
When switching the clock signal during program execution, wait until the target clock signal has
stabilized.
 When the clock signal is generated with an external resonator (or from an external oscillator) during
a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover,
when switching to a clock signal produced with an external resonator (or by an external oscillator)
while program execution is in progress, wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number, confirm that the
change will not lead to problems.
 The characteristics of MPU/MCU in the same group but having different type numbers may differ
because of the differences in internal memory capacity and layout pattern. When changing to
products of different type numbers, implement a system-evaluation test for each of the products.
BEFORE USING THIS MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development. Chapter 3 also includes necessary information for
systems development. You must refer to that chapter.
1. Organization
● CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
● CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on
setting examples of relevant registers.
● CHAPTER 3 APPENDIX
This chapter includes necessary information for systems development using the microcomputer, such
as the electrical characteristics, the list of registers.
2. Structure of register
The figure of each register structure describes its functions, contents at reset, and attributes as follows :
(Note 2)
Bit attributes
Bits
(Note 1)
Contents immediately after reset release
b7 b6 b5 b4 b3 b2 b1 b0
0
CPU mode register (CPUM) [Address : 3B 16]
B
Name
0
Processor mode bits
1
Function
At reset
R W
b1 b0
0 0 : Single-chip mode
01:
10:
Not available
11:
0 : 0 page
1 : 1 page
0
0
2
Stack page selection bit
3
0
✕
4
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
0
✕
5
Fix this bit to “0.”
1
6
Main clock (X IN-XOUT) stop bit
7
Internal system clock selection bit
: Bit in which nothing is arranged
0 : Operating
1 : Stopped
0 : XIN -XOUT selected
1 : XCIN -XCOUT selected
0
✽
✽
: Bit that is not used for control of the corresponding function
Note 1:. Contents immediately after reset release
0....... “0” at reset release
1....... “1” at reset release
?....... Undefined at reset release
✽.......Contents determined by option at reset release
Note 2: Bit attributes......... The attributes of control register bits are classified into 3 bytes : read-only, writeonly and read and write. In the figure, these attributes are represented as follows :
R....... Read
...... Read enabled
✕.......Read disabled
W......Write
..... Write enabled
✕...... Write disabled
✽.......“0” write
3. Supplementation
For details of software, refer to the “740 FAMILY SOFTWARE MANUAL.”
For details of development support tools, refer to the “Renesas Technology” Homepage (http://www.renesas.com).
Table of contents
7534 Group
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................... 2
FEATURES ......................................................................................................................................... 2
APPLICATION ................................................................................................................................... 2
PIN CONFIGURATION ..................................................................................................................... 2
FUNCTIONAL BLOCK ..................................................................................................................... 5
PIN DESCRIPTION ........................................................................................................................... 8
GROUP EXPANSION ....................................................................................................................... 9
FUNCTIONAL DESCRIPTION ....................................................................................................... 10
Central Processing Unit (CPU) ............................................................................................... 10
Memory ....................................................................................................................................... 14
I/O Ports ..................................................................................................................................... 16
Interrupts .................................................................................................................................... 20
Timers ......................................................................................................................................... 23
Serial Interface .......................................................................................................................... 25
A/D Converter ............................................................................................................................ 36
Reset Circuit .............................................................................................................................. 38
Clock Generating Circuit .......................................................................................................... 40
NOTES ON PROGRAMMING ........................................................................................................ 42
NOTES ON USE ............................................................................................................................. 42
DATA REQUIRED FOR MASK ORDERS ................................................................................... 43
FUNCTIONAL DESCRIPTION SUPPLEMENT ............................................................................ 45
Interrupt ...................................................................................................................................... 45
Timing After Interrupt ................................................................................................................ 46
A/D Converter ............................................................................................................................ 47
Stop mode .................................................................................................................................. 49
Wait mode .................................................................................................................................. 50
DESCRIPTION OF IMPROVED USB FUNCTION FOR 7534 GROUP ................................... 51
DIFFERENCES AMONG 32-PIN, 36-PIN AND 42-PIN ............................................................. 51
DESCRIPTION SUPPLEMENT FOR USE OF USB FUNCTION STABLY ............................. 53
CHAPTER 2 APPLICATION
2.1 I/O port ........................................................................................................................................ 2
2.1.1 Memory map ...................................................................................................................... 2
2.1.2 Relevant registers ............................................................................................................. 2
2.1.3 Application example of key-on wake up ........................................................................ 6
2.1.4 Handling of unused pins .................................................................................................. 7
2.1.5 Notes on input and output pins ...................................................................................... 8
2.1.6 Termination of unused pins ............................................................................................. 9
2.2 Timer .......................................................................................................................................... 10
2.2.1 Memory map .................................................................................................................... 10
2.2.2 Relevant registers ........................................................................................................... 10
2.2.3 Timer application examples ........................................................................................... 16
2.3 Serial I/O ................................................................................................................................... 29
2.3.1 Memory map .................................................................................................................... 29
2.3.2 Relevant registers ........................................................................................................... 29
2.3.3 Serial I/O connection examples .................................................................................... 35
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2.3.4 Serial I/O transfer data format ...................................................................................... 37
2.3.5 Serial I/O application examples .................................................................................... 38
2.3.6 Notes on serial I/O ......................................................................................................... 49
2.4 USB ............................................................................................................................................ 50
2.4.1 Outline of USB ................................................................................................................ 50
2.4.2 Memory map .................................................................................................................... 56
2.4.3 Relevant registers ........................................................................................................... 57
2.4.4 USB application example ............................................................................................... 62
2.4.5 Notes concerning USB ................................................................................................... 69
2.5 A/D converter .......................................................................................................................... 71
2.5.1 Memory map .................................................................................................................... 71
2.5.2 Relevant registers ........................................................................................................... 71
2.5.3 A/D converter application examples ............................................................................. 75
2.5.4 Notes on A/D converter ................................................................................................. 77
2.6 Reset .......................................................................................................................................... 78
2.6.1 Connection
example of reset IC ................................................................................... 78
_____________
2.6.2 Notes on RESET pin ...................................................................................................... 78
CHAPTER 3 APPENDIX
3.1 Electrical characteristics ........................................................................................................ 2
3.1.1 Absolute maximum ratings ............................................................................................... 2
3.1.2 Recommended operating conditions ............................................................................... 3
3.1.3 Electrical characteristics ................................................................................................... 4
3.1.4 A/D converter characteristics ........................................................................................... 5
3.1.5 Timing requirements ......................................................................................................... 6
3.1.6 Switching characteristics .................................................................................................. 6
3.2 Typical characteristics ............................................................................................................ 8
3.2.1 Power source current characteristic example (ICC-VCC characteristic) ........................ 8
3.2.2 VOH-IOH characteristic example ....................................................................................... 11
3.2.3 A/D conversion typical characteristics example .......................................................... 15
3.3 Notes on use ........................................................................................................................... 17
3.3.1 Notes on interrupts ......................................................................................................... 17
3.3.2 Notes on serial I/O ......................................................................................................... 18
3.3.3 Notes on A/D converter ................................................................................................. 19
3.3.4 Notes on _____________
watchdog timer ............................................................................................... 20
3.3.5 Notes on RESET pin ...................................................................................................... 20
3.3.6 Notes on input and output pins .................................................................................... 20
3.3.7 Notes on programming ................................................................................................... 21
3.3.8 Programming and test of built-in PROM version ........................................................ 22
3.3.9 Notes on built-in PROM version ................................................................................... 23
3.3.10 Termination of unused pins ......................................................................................... 24
3.3.11 Notes on CPU mode register ...................................................................................... 25
3.3.12 Notes on using 32-pin version .................................................................................... 25
3.3.13 Electric characteristic differences among mask ROM and One TIme PROM version MCUs ... 25
3.3.14 Note on power source voltage .................................................................................... 25
3.3.15 USB communication ...................................................................................................... 26
3.4 Countermeasures against noise ......................................................................................... 27
3.4.1 Shortest wiring length ..................................................................................................... 27
3.4.2 Connection of bypass capacitor across V SS line and V CC line .................................. 29
3.4.3 Wiring to analog input pins ........................................................................................... 30
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3.4.4 Oscillator concerns .......................................................................................................... 30
3.4.5 Setup for I/O ports .......................................................................................................... 32
3.4.6 Providing of watchdog timer function by software ..................................................... 33
3.5 List of registers ...................................................................................................................... 34
3.6 Package outline ...................................................................................................................... 53
3.7 List of instruction code ........................................................................................................ 55
3.8 Machine instructions ............................................................................................................. 56
3.9 SFR memory map ................................................................................................................... 67
3.10 Pin configurations ................................................................................................................ 68
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List of figures
7534 Group
List of figures
CHAPTER 1 HARDWARE
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1 Pin configuration of M37534M4-XXXFP, M37534E8FP .................................................... 2
2 Pin configuration of M37534M4-XXXGP, M37534E4GP .................................................. 3
3 Pin configuration of M37534RSS, M37534M4-XXXSP, M37534E8SP ........................... 4
4 Functional block diagram (PRSP0036GA-A package type) ............................................. 5
5 Functional block diagram (PLQP0032GB-A package type) ............................................. 6
6 Functional block diagram (PRDP0042BA-A package type) ............................................. 7
7 Memory expansion plan ........................................................................................................ 9
8 740 Family CPU register structure .................................................................................... 10
9 Register push and pop at interrupt generation and subroutine call ............................ 11
10 Structure of CPU mode register ...................................................................................... 13
11 Switching method of CPU mode register ....................................................................... 13
12 Memory map diagram ....................................................................................................... 14
13 Memory map of special function register (SFR) ........................................................... 15
14 Structure of pull-up control register ................................................................................ 16
15 Structure of port P1P3 control register .......................................................................... 16
16 Block diagram of ports (1) ............................................................................................... 18
17 Block diagram of ports (2) ............................................................................................... 19
18 Interrupt control .................................................................................................................. 21
19 Structure of Interrupt-related registers ........................................................................... 21
20 Connection example when using key input interrupt and port P0 block diagram ... 22
21 Structure of timer X mode register ................................................................................. 23
22 Timer count source set register ...................................................................................... 23
23 Block diagram of timer X, timer 1 and timer 2 ............................................................. 24
24 Block diagram of UART serial I/O1 ................................................................................ 25
25 Operation of UART serial I/O1 function ......................................................................... 25
26 Continuous transmission operation of UART serial I/O ............................................... 26
27 USB mode block diagram ................................................................................................ 27
28 USB transceiver block diagram ....................................................................................... 27
29 Structure of serial I/Orelated registers (1) ..................................................................... 28
30 Structure of serial I/O1-related registers (2) ................................................................. 29
31 Structure of serial I/O1-related registers (3) ................................................................. 30
32 Structure of serial I/O1-related registers (4) ................................................................. 31
33 Structure of serial I/O1-related registers (5) ................................................................. 32
34 Structure of serial I/O2 control registers ........................................................................ 34
35 Block diagram of serial I/O2 ............................................................................................ 34
36 Serial I/O2 timing (LSB first) ........................................................................................... 35
37 Structure of A/D control register ..................................................................................... 36
38 Structure of A/D conversion register .............................................................................. 36
39 Block diagram of A/D converter ...................................................................................... 36
40 Block diagram of watchdog timer .................................................................................... 37
41 Structure of watchdog timer control register ................................................................. 37
42 Example of reset circuit .................................................................................................... 38
43 Timing diagram at reset ................................................................................................... 38
44 Internal status of microcomputer at reset ...................................................................... 39
45 External circuit of ceramic resonator .............................................................................. 40
46 External clock input circuit ............................................................................................... 40
47 Structure of MISRG ........................................................................................................... 40
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List of figures
7534 Group
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48
49
50
51
52
53
54
55
56
57
58
Block diagram of system clock generating circuit (for ceramic resonator) ............... 41
Countermeasure (2) by software ..................................................................................... 43
Method to stabilize A/D conversion accuracy ............................................................... 43
Programming and testing of One Time PROM version ............................................... 44
Timing chart after an interrupt occurs ............................................................................ 46
Time up to execution of the interrupt processing routine ........................................... 46
A/D conversion equivalent circuit .................................................................................... 48
A/D conversion timing chart ............................................................................................. 48
Handling of V CC, USBVREFOUT pins of M37534M4-XXXFP, M37534E8FP ................... 53
Handling of V CC, USBV REFOUT pins of M37534M4-XXXGP, M37534E4GP .................. 54
Handling of VCC, USBVREFOUT pins of M37534E8SP, M37534M4-XXXSP, M37534RSS ........ 55
CHAPTER 2 APPLICATION
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2.1.1 Memory map of registers relevant to I/O port ............................................................ 2
2.1.2 Structure of Port Pi (i = 0 to 4) .................................................................................... 2
2.1.3 Structure of Port Pi direction register (i = 0 to 4) ..................................................... 3
2.1.4 Structure of Pull-up control register ............................................................................. 3
2.1.5 Structure of P1P3 control register ................................................................................ 4
2.1.6 Structure of Interrupt edge selection register ............................................................. 4
2.1.7 Structure of Interrupt request register 1 ...................................................................... 5
2.1.8 Structure of Interrupt control register 1 ....................................................................... 5
2.1.9 Relevant registers setting .............................................................................................. 6
2.1.10 Application circuit example .......................................................................................... 6
2.1.11 Control procedure .......................................................................................................... 7
2.2.1 Memory map of registers relevant to timers ............................................................. 10
2.2.2 Structure of Prescaler 12, Prescaler X ...................................................................... 10
2.2.3 Structure of Timer 1 ..................................................................................................... 11
2.2.4 Structure of Timer 2 ..................................................................................................... 11
2.2.5 Structure of Timer X ..................................................................................................... 12
2.2.6 Structure of Timer X mode register ............................................................................ 13
2.2.7 Structure of Timer count source set register ............................................................ 14
2.2.8 Structure of Interrupt edge selection register ........................................................... 14
2.2.9 Structure of Interrupt request register 1 .................................................................... 15
2.2.10 Structure of Interrupt control register 1 ................................................................... 15
2.2.11 Timers connection and setting of division ratios .................................................... 17
2.2.12 Relevant registers setting .......................................................................................... 18
2.2.13 Control procedure ........................................................................................................ 19
2.2.14 Peripheral circuit example .......................................................................................... 20
2.2.15 Timers connection and setting of division ratios .................................................... 20
2.2.16 Relevant registers setting .......................................................................................... 21
2.2.17 Control procedure ........................................................................................................ 22
2.2.18 Judgment method of valid/invalid of input pulses .................................................. 23
2.2.19 Relevant registers setting .......................................................................................... 24
2.2.20 Control procedure ........................................................................................................ 25
2.2.21 Timers connection and setting of division ratios .................................................... 26
2.2.22 Relevant registers setting .......................................................................................... 27
2.2.23 Control procedure ........................................................................................................ 28
2.3.1 Memory map of registers relevant to serial I/O ........................................................ 29
2.3.2 Structure of Transmit/Receive buffer register ........................................................... 29
2.3.3 Structure of UART status register .............................................................................. 30
2.3.4 Structure of Serial I/O1 control register ..................................................................... 30
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List of figures
7534 Group
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2.3.5 Structure of UART control register ............................................................................. 31
2.3.6 Structure of Baud rate generator ................................................................................ 31
2.3.7 Structure of Serial I/O2 control register ..................................................................... 32
2.3.8 Structure of Serial I/O2 register .................................................................................. 32
2.3.9 Structure of Interrupt edge selection register ........................................................... 33
2.3.10 Structure of Interrupt request register 1 .................................................................. 33
2.3.11 Structure of Interrupt control register 1 ................................................................... 34
2.3.12 Serial I/O connection examples (1) .......................................................................... 35
2.3.13 Serial I/O connection examples (2) .......................................................................... 36
2.3.14 Serial I/O transfer data format .................................................................................. 37
2.3.15 Connection diagram .................................................................................................... 38
2.3.16 Timing chart ................................................................................................................. 38
2.3.17 Registers setting relevant to transmission side ...................................................... 39
2.3.18 Transmission data setting of serial I/O2 .................................................................. 40
2.3.19 Registers setting relevant to reception side ............................................................ 40
2.3.20 Control procedure of transmission side ................................................................... 41
2.3.21 Control procedure of reception side ......................................................................... 42
2.3.22 Connection diagram .................................................................................................... 43
2.3.23 Timing chart ................................................................................................................. 43
2.3.24 Registers setting relevant to transmission side ...................................................... 45
2.3.25 Registers setting relevant to reception side ............................................................ 46
2.3.26 Control procedure of transmission side ................................................................... 47
2.3.27 Control procedure of reception side ......................................................................... 48
2.3.28 Sequence of clearing serial I/O ................................................................................ 49
2.4.1 Communication sequence of USB .............................................................................. 51
2.4.2 Data structure of USB packet ..................................................................................... 52
2.4.3 USB (L.S.) interface ...................................................................................................... 55
2.4.4 USB (L.S.) connection example .................................................................................. 55
2.4.5 Memory map of registers relevant to USB ................................................................ 56
2.4.6 Description of the register structure ........................................................................... 57
2.4.7 Register structures relevant to USB (1) .................................................................... 58
2.4.8 Register structures relevant to USB (2) .................................................................... 59
2.4.9 Register structures relevant to USB (3) .................................................................... 60
2.4.10 Register structures relevant to USB (4) .................................................................. 61
2.4.11 Control method of control sequence ........................................................................ 62
2.4.12 Timing chart of the transaction according to each token ..................................... 63
2.4.13 USB interrupt processing example (OUT token) .................................................... 65
2.4.14 USB interrupt processing example (IN token) ........................................................ 66
2.4.15 Data read timing of SETUP token ............................................................................ 67
2.4.16 Data read timing of OUT token ................................................................................ 67
2.4.17 Data read timing of IN token (endpoint 0) and IN token (endpoint 1) token .... 67
2.4.18 Timing chart of each signal ....................................................................................... 68
2.4.19 Example for determination of resume interrupt ...................................................... 69
2.4.20 Processing for width of SE0 signal .......................................................................... 69
2.4.21 Countermeasure (2) by software .............................................................................. 70
2.5.1 Memory map of registers relevant to A/D converter ................................................ 71
2.5.2 Structure of A/D control register ................................................................................. 71
2.5.3 Structure of A/D conversion register (high-order) .................................................... 72
2.5.4 Structure of A/D conversion register (low-order) ...................................................... 72
2.5.5 Structure of Interrupt edge selection register ........................................................... 73
2.5.6 Structure of Interrupt request register 1 .................................................................... 73
2.5.7 Structure of Interrupt control register 1 ..................................................................... 74
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List of figures
7534 Group
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Fig.
2.5.8 Connection diagram ...................................................................................................... 75
2.5.9 Relevant registers setting ............................................................................................ 75
2.5.10 Control procedure for 8-bit read ............................................................................... 76
2.5.11 Control procedure for 10-bit read ............................................................................. 76
2.5.12 Method to stabilize A/D conversion accuracy ......................................................... 77
2.6.1 Example of poweron reset circuit ............................................................................... 78
CHAPTER 3 APPENDIX
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
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Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
3.1.1 Power source current measurement circuit in USB mode at oscillation stop ........ 5
3.1.2 Output switching characteristics measurement circuit ............................................... 6
3.1.3 Timing chart ..................................................................................................................... 7
3.2.1 I CC-VCC characteristic example (in double-speed mode) ............................................. 8
3.2.2 I CC-V CC characteristic example (at WIT instruction execution) .................................. 8
3.2.3 I CC-V CC characteristic example (At STP instruction execution, Ta = 25 °C) ........... 9
3.2.4 I CC-V CC characteristic example (At STP instruction execution, Ta = 85 °C) ........... 9
3.2.5 I CC-V CC characteristic example (at USB suspend, Ta = 25 °C) .............................. 10
3.2.6 ICC-VCC characteristic example (A/D conversion executed/not executed, f(X IN) = 6MHz,
in double-speed mode) ................................................................................................. 10
3.2.7 V OH-IOH characteristic example of P-channel (Ta = 25 °C): normal port ............... 11
3.2.8 V OH-IOH characteristic example of P-channel (Ta = 85 °C): normal port ............... 11
3.2.9 V OL-IOL characteristic example of N-channel (Ta = 25 °C): Normal port ............... 12
3.2.10 V OL-IOL characteristic example of N-channel (Ta = 85 °C): Normal port ............. 12
3.2.11 V OL-I OL characteristic example of N-channel (Ta = 25 °C): LED drive port ........ 13
3.2.12 V OL-IOL characteristic example N-channel (Ta = 85 °C): LED drive port ............. 13
3.2.13 “L” input current of port at pull-up transistor connected ....................................... 14
3.2.14 Definition of A/D conversion accuracy ..................................................................... 15
3.2.15 A/D conversion typical characteristic example ........................................................ 16
3.3.1 Sequence of switch the detection edge ..................................................................... 17
3.3.2 Sequence of check of interrupt request bit ............................................................... 17
3.3.3 Structure of interrupt control register 1 ..................................................................... 18
3.3.4 Sequence of clearing serial I/O .................................................................................. 18
3.3.5 Method to stabilize A/D conversion accuracy ........................................................... 19
3.3.6 Initialization of processor status register ................................................................... 21
3.3.7 Sequence of PLP instruction execution ..................................................................... 21
3.3.8 Stack memory contents after PHP instruction execution ........................................ 21
3.3.9 Status flag at decimal calculations ............................................................................. 22
3.3.10 Programming and testing of One Time PROM version ......................................... 22
3.3.11 Switching method of CPU mode register ................................................................ 25
3.3.12 Countermeasure (2) by software .............................................................................. 26
3.4.1 Selection of packages
.................................................................................................. 27
_____________
3.4.2 Wiring for the RESET pin ............................................................................................ 27
3.4.3 Wiring for clock I/O pins .............................................................................................. 28
3.4.4 Wiring for CNV SS pin ................................................................................................... 28
3.4.5 Wiring for the V PP pin of the One Time PROM ........................................................ 29
3.4.6 Bypass capacitor across the V SS line and the V CC line ........................................... 29
3.4.7 Analog signal line and a resistor and a capacitor ................................................... 30
3.4.8 Wiring for a large current signal line ......................................................................... 30
3.4.9 Wiring of signal lines where potential levels change frequently ............................ 31
3.4.10 V SS pattern on the underside of an oscillator .......................................................... 31
3.4.11 Setup for I/O ports ...................................................................................................... 32
3.4.12 Watchdog timer by software ...................................................................................... 33
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 7 of 9
List of figures
7534 Group
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
3.5.1 Structure of Port Pi (i = 0 to 4) .................................................................................. 34
3.5.2 Structure of Port Pi direction register (i = 0 to 4) ................................................... 34
3.5.3 Structure of Pull-up control register ........................................................................... 35
3.5.4 Structure of Port P1P3 control register ..................................................................... 35
3.5.5 Structure of Transmit/Receive buffer register ........................................................... 36
3.5.6 Structure of UART status register .............................................................................. 36
3.5.7 Structure of USB status register ................................................................................. 37
3.5.8 Structure of Serial I/O1 control register ..................................................................... 38
3.5.9 Structure of UART control register ............................................................................. 38
3.5.10 Structure of Baud rate generator .............................................................................. 39
3.5.11 Structure of USB data toggle synchronization register ......................................... 39
3.5.12 Structure of USB interrupt source discrimination register 1 ................................. 39
3.5.13 Structure of USB interrupt source discrimination register 2 ................................. 40
3.5.14 Structure of USB interrupt control register .............................................................. 40
3.5.15 Structure of USB transmit data byte number set register 0 ................................. 41
3.5.16 Structure of USB transmit data byte number set register 1 ................................. 41
3.5.17 Structure of USB PID control register 0 .................................................................. 41
3.5.18 Structure of USB PID control register 1 .................................................................. 42
3.5.19 Structure of USB address register ........................................................................... 42
3.5.20 Structure of USB sequence bit initialization register ............................................. 42
3.5.21 Structure of USB control register ............................................................................. 42
3.5.22 Structure of Prescaler 12, Prescaler X .................................................................... 43
3.5.23 Structure of Timer 1 ................................................................................................... 43
3.5.24 Structure of Timer 2 ................................................................................................... 44
3.5.25 Structure of Timer X mode register ......................................................................... 45
3.5.26 Structure of Timer X ................................................................................................... 46
3.5.27 Structure of Timer count source set register .......................................................... 46
3.5.28 Structure of Serial I/O2 control register ................................................................... 47
3.5.29 Structure of Serial I/O2 register ................................................................................ 47
3.5.30 Structure of A/D control register ............................................................................... 48
3.5.31 Structure of A/D conversion register (high-order) .................................................. 49
3.5.32 Structure of A/D conversion register (low-order) .................................................... 49
3.5.33 Structure of MISRG .................................................................................................... 50
3.5.34 Structure of Watchdog timer control register .......................................................... 50
3.5.35 Structure of Interrupt edge selection register ......................................................... 51
3.5.36 Structure of CPU mode register ............................................................................... 51
3.5.37 Structure of Interrupt request register 1 .................................................................. 52
3.5.38 Structure of Interrupt control register 1 ................................................................... 52
3.10.1 M37534M4-XXXFP, M37534E8FP pin configuration .............................................. 68
3.10.2 M37534M4-XXXGP, M37534E4GP pin configuration ............................................. 69
3.10.3 M37534M4-XXXSP, M37534E8SP, M37534RSS pin configuration ...................... 70
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 8 of 9
List of tables
7534 Group
List of tables
CHAPTER 1 HARDWARE
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
1 Pin description .................................................................................................................... 8
2 List of supported products ................................................................................................ 9
3 Push and pop instructions of accumulator or processor status register .................. 11
4 Set and clear instructions of each bit of processor status register .......................... 12
5 I/O port function table ...................................................................................................... 17
6 Interrupt vector address and priority ............................................................................. 20
7 Relation of the width of SE0 and the state of the device ......................................... 33
8 Special programming adapter ......................................................................................... 43
9 Interrupt sources, vector addresses and interrupt priority .......................................... 44
10 Change of A/D conversion register during A/D conversion ..................................... 46
11 Stop mode state ............................................................................................................. 48
12 Wait mode state ............................................................................................................. 49
13 Description of improved USB function for 7534 Group ............................................ 50
14 Differences among 32-pin, 36-pin and 42-pin ............................................................ 50
15 Differences among 32-pin, 36-pin and 42-pin (SFR) ................................................ 51
CHAPTER 2 APPLICATION
Table
Table
Table
Table
Table
Table
Table
Table
2.1.1
2.2.1
2.3.1
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
Handling of unused pins ............................................................................................. 7
CNTR0 active edge switch bit function ................................................................... 13
Setting example of baud rate generator (BRG) and transfer bit rate values .... 44
Transfer types of USB ............................................................................................... 50
Packet types of USB ................................................................................................. 52
Data structure of USB packet .................................................................................. 53
PID ............................................................................................................................... 53
Special signal of USB ............................................................................................... 54
CHAPTER 3 APPENDIX
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.3.1
3.3.2
3.5.1
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
Absolute maximum ratings .......................................................................................... 2
Recommended operating conditions .......................................................................... 3
Electrical characteristics (1) ........................................................................................ 4
Electrical characteristics (2) ........................................................................................ 5
A/D Converter characteristics (1) ............................................................................... 5
Timing requirements .................................................................................................... 6
Switching characteristics ............................................................................................. 6
Programming adapters .............................................................................................. 23
PROM programmer address setting ........................................................................ 24
CNTR 0 active edge switch bit function ................................................................... 45
page 9 of 9
CHAPTER 1
HARDWARE
DESCRIPTION
FEATURES
APPLICATION
PIN CONFIGURATION
FUNCTIONAL BLOCK
PIN DESCRIPTION
GROUP EXPANSION
FUNCTIONAL DESCRIPTION
NOTES ON PROGRAMMING
NOTES ON USE
DATA REQUIRED FOR MASK ORDERS
ROM PROGRAMMING METHOD
FUNCTIONAL DESCRIPTION SUPPLEMENT
DESCRIPTION OF IMPROVED USB
FUNCTION FOR 7534 GROUP
DIFFERENCES AMONG 32-PIN, 36-PIN
AND 42-PIN
DESCRIPTION SUPPLEMENT FOR
USE OF USB FUNCTION STABLY
HARDWARE
7534 Group
DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION
•
DESCRIPTION
The 7534 Group is the 8-bit microcomputer based on the 740 family
core technology.
The 7534 Group has a USB, 8-bit timers, and an A/D converter, and
is useful for an input device for personal computer peripherals.
FEATURES
•
•
•
•
•
•
Basic machine-language instructions ....................................... 69
The minimum instruction execution time .......................... 0.34 µs
(at 6 MHz oscillation frequency for the shortest instruction)
Memory size
ROM ............................................... 8K to 16K bytes
RAM .............................................. 256 to 384 bytes
Programmable I/O ports ...................................... 28 (36-pin type)
............................................................................ 24 (32-pin type)
............................................................................ 33 (42-pin type)
Interrupts .................................................... 14 sources, 8 vectors
Timers ............................................................................ 8-bit ✕ 3
•
•
•
•
•
•
•
Serial Interface
Serial I/O1 ................................ used only for Low Speed in USB
(based on Low-Speed USB2.0 specification)
(USB/UART)
Serial I/O2 ...................................................................... 8-bit ✕ 1
(Clock-synchronized)
A/D converter ................................................ 10-bit ✕ 8 channels
Clock generating circuit ............................................. Built-in type
(connect to external ceramic resonator or quartz-crystal oscillator )
Watchdog timer ............................................................ 16-bit ✕ 1
Power source voltage
At 6 MHz XIN oscillation frequency at ceramic resonator
................................ 4.1 to 5.5 V(4.4 to 5.25 V at USB operation)
Power dissipation ............................................ 30 mW (standard)
Operating temperature range ................................... –20 to 85 °C
(0 to 70 °C at USB operation)
Built-in USB 3.3 V Regulator + transceiver based on Low-Speed
USB2.0 specification
APPLICATION
Input device for personal computer peripherals
PIN CONFIGURATION (TOP VIEW)
P27/AN7
VREF
RESET
CNVSS
Vcc
XIN
XOUT
VSS
1
36
2
35
3
34
4
33
5
6
7
8
9
10
11
12
13
14
15
M37534M4-XXXFP
M37534E8FP
P12/SCLK
P13/SDATA
P14/CNTR0
P20/AN0
P21/AN1
P22/AN2
P23/AN3
P24/AN4
P25/AN5
P26/AN6
32
31
30
29
28
27
26
25
24
23
22
16
21
17
20
18
19
P11/TXD/D+
P10/RXD/DP07
P06
P05
P04
P03
P02
P01
P00
USBVREFOUT
P37/INT0
P35(LED5)
P34(LED4)
P33(LED3)
P32(LED2)
P31(LED1)
P30(LED0)
Outline: PRSP0036GA-A (36P2R-A)
Fig. 1 Pin configuration of M37534M4-XXXFP, M37534E8FP
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 2 of 55
HARDWARE
7534 Group
PIN CONFIGURATION
17
18
19
20
21
22
25
16
26
15
27
14
28
29
M37534M4-XXXGP
M37534E4GP
13
12
8
P34(LED4)
P33(LED3)
P32(LED2)
P31(LED1)
P30(LED0)
VSS
XOUT
XIN
P22/AN2
P23/AN3
P24/AN4
P25/AN5
VREF
RESET
CNVSS
VCC
7
9
6
32
5
10
4
31
3
11
2
30
1
P07
P10/RXD/DP11/TXD/D+
P12/SCLK
P13/SDATA
P14/CNTR0
P20/AN0
P21/AN1
23
24
P06
P05
P04
P03
P02
P01
P00
USBVREFOUT
PIN CONFIGURATION (TOP VIEW)
Outline PLQP0032GB-A (32P6U-A)
Fig. 2 Pin configuration of M37534M4-XXXGP, M37534E4GP
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 3 of 55
HARDWARE
7534 Group
PIN CONFIGURATION
PIN CONFIGURATION (TOP VIEW)
1
42
2
41
3
40
4
39
5
38
6
37
7
8
9
10
11
12
13
14
15
16
17
M37534RSS
M37534M4-XXXSP
M37534E8SP
P14/CNTR0
P15
P16
P20/AN0
P21/AN1
NC
P22/AN2
P23/AN3
P24/AN4
P25/AN5
P26/AN6
P27/AN7
P40
P41
VREF
RESET
CNVSS
Vcc
XIN
XOUT
VSS
36
35
34
33
32
31
30
29
28
27
26
18
25
19
24
20
23
21
22
P13/SDATA
P12/SCLK
P11/TXD/D+
P10/RXD/DP07
P06
P05
P04
P03
P02
P01
P00
USBVREFOUT
P37/INT0
P36(LED6)/INT1
P35(LED5)
P34(LED4)
P33(LED3)
P32(LED2)
P31(LED1)
P30(LED0)
Outline 42S1M, PRDP0042BA-A (42P4B)
Fig. 3 Pin configuration of M37534RSS, M37534M4-XXXSP, M37534E8SP
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 4 of 55
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 5 of 55
Fig. 4 Functional block diagram (PRSP0036GA-A package type)
VREF
Reset
0
PC H
I/O port P3
I/O port P2
11 10 9 8 7 6 5 4
25 24 23 22 21 20 19
PS
PC L
S
Y
X
A
SI/O1(8)
USB(LS)
C P U
26
USBVREFOUT
P2(8)
INT0
ROM
15
18
P3(7)
RAM
VCC
VSS
SI/O2(8)
I/O port P1
3 2 1 36 35
P1(5)
CNTR0
13
RESET
Reset input
P0(8)
Timer X (8)
Timer 2 (8)
Timer 1 (8)
I/O port P0
34 33 32 31 30 29 28 27
Prescaler X (8)
Prescaler 12 (8)
14
CNVSS
7534 Group
12
A/D
converter
(1 0 )
Watchdog timer
Clock generating circuit
17
16
Clock output
XOUT
XIN
Clock input
Key-on wake up
FUNCTIONAL BLOCK DIAGRAM (Package: PRSP0036GA-A)
HARDWARE
FUNCTIONAL BLOCK
FUNCTIONAL BLOCK
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 6 of 55
Fig. 5 Functional block diagram (PLQP0032GB-A package type)
VREF
Reset
I/O port P3
16 15 14 13 12
P3(5)
RAM
ROM
0
PC H
I/O port P2
4 3 2 1 32 31
P2(6)
8
11
PS
PC L
S
Y
X
A
17
USBVREFOUT
SI/O1(8)
USB(LS)
C P U
VCC
VSS
SI/O2(8)
I/O port P1
30 29 28 27 26
P1(5)
CNTR0
6
RESET
Reset input
P0(8)
Timer X (8)
Timer 2 (8)
Timer 1 (8)
I/O port P0
25 24 23 22 21 20 19 18
Prescaler X (8)
Prescaler 12 (8)
7
CNVSS
7534 Group
5
A/D
converter
(1 0 )
Watchdog timer
Clock generating circuit
10
9
Clock output
XOUT
XIN
Clock input
Key-on wake up
FUNCTIONAL BLOCK DIAGRAM (Package: PLQP0032GB-A)
HARDWARE
FUNCTIONAL BLOCK
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
20
page 7 of 55
Fig. 6 Functional block diagram (PRDP0042BA-A package type)
I/O port P4
I/O port P3
29 28 27 26 25 24 23 22
7 5 4
I/O port P2
12 11 10 9 8
P2(8)
0
PS
30
SI/O1(8)
USB(LS)
USBVREFOUT
PC L
S
Y
X
A
SI/O2(8)
16
RESET
Reset input
3
CNTR0
1 42 41 40 39
I/O port P1
2
P1(7)
Prescaler X (8)
Prescaler 12 (8)
17
CNVSS
I/O port P0
38 37 36 35 34 33 32 31
P0(8)
Timer X (8)
Timer 2 (8)
Timer 1 (8)
7534 Group
VREF
15
13 14
PC H
18
21
C P U
VCC
VSS
INT0 INT1
ROM
P3(8)
A/D
converter
(1 0 )
Reset
RAM
P4(2)
Watchdog timer
Clock generating circuit
19
Clock input Clock output
X IN X OUT
FUNCTIONAL BLOCK DIAGRAM (Package: PRDP0042BA-A)
HARDWARE
FUNCTIONAL BLOCK
Key-on wakeup
HARDWARE
7534 Group
PIN DESCRIPTION
PIN DESCRIPTION
Table 1 Pin description
Pin
Name
Function
Function expect a port function
•Apply voltage of 4.1 to 5.5 V (4.4 to 5.25 V at USB operating) to Vcc, and 0 V to Vss.
Vcc, Vss
Power source
VREF
Analog reference
voltage
•Reference voltage input pin for A/D converter
USBVREFOUT
USB reference
voltage output
•Output pin for pulling up a D- line with 1.5 kΩ external resistor
CNVss
CNVss
•Chip operating mode control pin, which is always connected to Vss.
RESET
Reset input
•Reset input pin for active “L”
XIN
Clock input
•Input and output pins for main clock generating circuit
XOUT
Clock output
P00–P07
I/O port P0
•Connect a ceramic resonator or quartz crystal oscillator between the XIN and XOUT pins.
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
•8-bit I/O port.
•I/O direction register allows each pin to be individually programmed
as either input or output.
•Key-input (key-on wake up
interrupt input) pins
•CMOS 3-state output structure at CMOS compatible input level
•Whether a built-in pull-up resistor is to be used or not can be
determined by program.
P10/RxD/D-
•7-bit I/O port
•Serial I/O1 function pin
P12/SCLK
•I/O direction register allows each pin to be individually programmed
as either input or output.
•Serial I/O2 function pin
P13/SDATA
•CMOS 3-state output structure at CMOS compatible input level
P14/CNTR0
•CMOS/TTL level can be switched for P10, P12, P13.
P15, P16
•When using the USB function, input level of ports P10 and P11
becomes USB input level, and output level of them becomes
USB output level.
I/O port P1
P11/TxD/D+
P20/AN0–
I/O port P2
•Input pins for A/D converter
•CMOS 3-state output structure at CMOS compatible input level
P27/AN7
P30–P35
•8-bit I/O port having almost the same function as P0
•Timer X function pin
I/O port P3
•8-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS 3-state output structure at CMOS compatible input level (CMOS/TTL level can be switched
for P36, P37).
•P30 to P36 can output a large current for driving LED.
•Whether a built-in pull-up resistor is to be used or not can be
determined by program.
P36/INT1
P37/INT0
P40, P41
I/O port P4
•Interrupt input pins
•2-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 8 of 55
HARDWARE
7534 Group
GROUP EXPANSION
GROUP EXPANSION
Renesas plans to expand the 7534 group as follow:
Memory type
Support for Mask ROM version, One Time PROM version, and Emulator MCU .
Package
PRSP0036GA-A ......................... 0.8 mm-pitch plastic molded SOP
PLQP0032GB-A ........................ 0.8 mm-pitch plastic molded LQFP
PRDP0042BA-A .................................... 42 pin plastic molded SDIP
42SIM ...................................... 42 pin shrink ceramic PIGGY BACK
Memory size
ROM/PROM size .................................................. 8 K to 16 K bytes
RAM size ................................................................ 256 to 384 bytes
ROM size
(Byte)
16K
M37534E8
8K
M37534M4
M37534E4
128
0
256
384
RAM size
(Byte)
Fig. 7 Memory expansion plan
Currently supported products are listed below.
Table 2 List of supported products
(P) ROM size (bytes)
ROM size for User ()
RAM size
(bytes)
Package
M37534M4-XXXFP
8192 (8062)
256
PRSP0036GA-A
Mask ROM version
M37534M4-XXXGP
8192 (8062)
256
PLQP0032GB-A
Mask ROM version
M37534M4-XXXSP
8192 (8062)
256
PRDP0042BA-A
Mask ROM version
M37534E4GP
8192 (8062)
256
PLQP0032GB-A
One Time PROM version (blank)
M37534E8FP
16384 (16254)
384
PRSP0036GA-A
One Time PROM version (blank)
M37534E8SP
16384 (16254)
384
PRDP0042BA-A
One Time PROM version (blank)
384
42S1M
Part number
M37534RSS
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 9 of 55
Remarks
Emulator MCU
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
Stack pointer (S)
The 7534 group uses the standard 740 family instruction set. Refer to
the table of 740 family addressing modes and machine instructions or
the 740 Family Software Manual for details on the instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instructions cannot be used.
The MUL and DIV instructions cannot be used.
The WIT and STP instructions can be used.
The central processing unit (CPU) has the six registers.
Accumulator (A)
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
Index register X (X), Index register Y (Y)
Both index register X and index register Y are 8-bit registers. In the
index addressing modes, the value of the OPERAND is added to the
contents of register X or register Y and specifies the real address.
When the T flag in the processor status register is set to “1”, the value
contained in index register X becomes the address for the second
OPERAND.
b7
b7
b0
b7
Index Register X
b0
Index Register Y
Y
b7
b0
Stack Pointer
S
b7
b0
Program Counter
PCL
b7
The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed.
Accumulator
X
PCH
Program counter (PC)
b0
A
b15
The stack pointer is an 8-bit register used during sub-routine calls and
interrupts. The stack is used to store the current address data and
processor status when branching to subroutines or interrupt routines.
The lower eight bits of the stack address are determined by the contents of the stack pointer. The upper eight bits of the stack address are
determined by the Stack Page Selection Bit. If the Stack Page Selection Bit is “0”, then the RAM in the zero page is used as the stack area.
If the Stack Page Selection Bit is “1”, then RAM in page 1 is used as
the stack area.
The Stack Page Selection Bit is located in the SFR area in the zero
page. Note that the initial value of the Stack Page Selection Bit varies
with each microcomputer type. Also some microcomputer types have
no Stack Page Selection Bit and the upper eight bits of the stack address are fixed. The operations of pushing register contents onto the
stack and popping them from the stack are shown in Figure 9.
b0
N V T B D I Z C Processor Status Register (PS)
Carry Flag
Zero Flag
Interrupt Disable Flag
Decimal Mode Flag
Break Flag
Index X Mode Flag
Overflow Flag
Negative Flag
Fig. 8 740 Family CPU register structure
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page 10 of 55
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
On-going Routine
Interrupt request
(Note)
M (S)
Execute JSR
M (S)
Store Return Address
on Stack
(S)
(PC H)
(S)
(S – 1)
M (S)
(PCL)
(S)
(S – 1)
M (S)
Subroutine
Restore Return
Address
(S + 1)
(PCL)
M (S)
(S)
(S + 1)
(PCH)
M (S)
(S – 1)
(PC L)
(S)
(S – 1)
M (S)
(PS)
(S)
(S – 1)
Interrupt
Service Routine
Execute RTS
(S)
(PC H)
Execute RTI
Note : The condition to enable the interrupt
(S)
(S + 1)
(PS)
M (S)
(S)
(S + 1)
(PC L)
M (S)
(S)
(S + 1)
(PC H)
M (S)
Store Return Address
on Stack
Store Contents of Processor
Status Register on Stack
I Flag “0” to “1”
Fetch the Jump Vector
Restore Contents of
Processor Status Register
Restore Return
Address
Interrupt enable bit is “1”
Interrupt disable flag is “0”
Fig. 9 Register push and pop at interrupt generation and subroutine call
Table 3 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PLA
Processor status register
PHP
PLP
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REJ09B0178-0300
page 11 of 55
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
Processor status register (PS)
The processor status register is an 8-bit register consisting of flags
which indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C) flag,
Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal
mode, the Z, V, N flags are not valid.
After reset, the Interrupt disable (I) flag is set to “1”, but all other flags
are undefined. Since the Index X mode (T) and Decimal mode (D)
flags directly affect arithmetic operations, they should be initialized in
the beginning of a program.
(1) Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
(2) Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
(3) Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
When an interrupt occurs, this flag is automatically set to “1” to
prevent other interrupts from interfering until the current interrupt
is serviced.
(4) Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
(5) Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”. The saved processor
status is the only place where the break flag is ever set.
(6) Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory, e.g. the results of an
operation between two memory locations is stored in the
accumulator. When the T flag is “1”, direct arithmetic operations
and direct data transfers are enabled between memory locations,
i.e. between memory and memory, memory and I/O, and I/O and
I/O. In this case, the result of an arithmetic operation performed
on data in memory location 1 and memory location 2 is stored in
memory location 1. The address of memory location 1 is
specified by index register X, and the address of memory
location 2 is specified by normal addressing modes.
(7) Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
(8) Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 4 Set and clear instructions of each bit of processor status register
D flag
SEI
SED
B flag
_
T flag
SEC
Z flag
_
I flag
Set instruction
C flag
SET
V flag
_
N flag
_
Clear instruction
CLC
_
CLI
CLD
_
CLT
CLV
_
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REJ09B0178-0300
page 12 of 55
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
[CPU Mode Register] CPUM
The CPU mode register contains the stack page selection bit.
This register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM: address 003B16)
Processor mode bits
b1 b0
0 0 Single-chip mode
0 1
1 0
Not available
1 1
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (returns “0” when read)
(Do not write “1” to these bits )
Main clock division ratio selection bits
b7 b6
0 0 : f(φ) = f(XIN)/2 (High-speed mode)
0 1 : f(φ) = f(XIN)/8 (Middle-speed mode)
1 0 : applied from on-chip oscillator
1 1 : f(φ) = f(XIN) (Double-speed mode)
Fig. 10 Structure of CPU mode register
Switching method of CPU mode register
Switch the CPU mode register (CPUM) at the head of program after
releasing Reset in the following method.
After releasing reset
Note on stack page
When 1 page is used as stack area by the stack page selection bit,
the area which can be used as stack depends on RAM size. Especially, be careful that the RAM area varies in Mask ROM version,
One Time PROM version and Emulator MCU.
Start with an on-chip oscillator (Note)
Wait until establish ceramic oscillator
clock.
Switch the clock division ratio
selection bits (bits 6 and 7 of CPUM)
Switch to other mode except an on-chip oscillator
(Select one of 1/1, 1/2, and 1/8)
Main routine
Note. After releasing reset the operation starts by starting an on-chip oscillator automatically.
Do not use an on-chip oscillator at ordinary operation.
Fig. 11 Switching method of CPU mode register
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page 13 of 55
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
Memory
Special function register (SFR) area
The SFR area in the zero page contains control registers such as I/O
ports and timers.
RAM
RAM is used for data storage and for a stack area of subroutine calls
and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is a user area for storing programs.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
Zero page
The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
Special page
The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
000016
SFR area
Zero page
004016
RAM
010016
RAM area
RAM capacity
(bytes)
address
XXXX16
256
384
013F16
01BF16
XXXX16
Reserved area
044016
Not used
YYYY16
Reserved ROM area
(128 bytes)
ZZZZ16
ROM
FF0016
ROM area
ROM capacity
(bytes)
address
YYYY16
address
ZZZZ16
8192
16384
E00016
C00016
E08016
C08016
Fig. 12 Memory map diagram
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REJ09B0178-0300
page 14 of 55
Special page
FFEC16
Interrupt vector area
FFFE16
FFFF16
Reserved ROM area
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
000016
Port P0 (P0)
002016
USB interrupt control register (USBICON)
000116
Port P0 direction register (P0D)
002116
USB transmit data byte number set register 0 (EP0BYTE)
000216
Port P1 (P1)
002216
USB transmit data byte number set register 1 (EP1BYTE)
000316
Port P1 direction register (P1D)
002316
USBPID control register 0 (EP0PID)
000416
Port P2 (P2)
002416
USBPID control register 1 (EP1PID)
000516
Port P2 direction register (P2D)
002516
USB address register (USBA)
000616
Port P3 (P3)
002616
USB sequence bit initialization register (INISQ1)
000716
Port P3 direction register (P3D)
002716
USB control register (USBCON)
000816
Port P4 (P4)
002816
Prescaler 12 (PRE12)
000916
Port P4 direction register (P4D)
002916
Timer 1 (T1)
000A16
002A16
Timer 2 (T2)
000B16
002B16
Timer X mode register (TM)
000C16
002C16
Prescaler X (PREX)
000D16
002D16
Timer X (TX)
000E16
002E16
Timer count source set register (TCSS)
000F16
002F16
001016
003016
Serial I/O2 control register (SIO2CON)
001116
003116
Serial I/O2 register (SIO2)
001216
003216
001316
003316
001416
003416
001516
003516
A/D conversion register (low-order) (ADL)
A/D conversion register (high-order) (ADH)
A/D control register (ADCON)
001616
Pull-up control register (PULL)
003616
001716
Port P1P3 control register (P1P3C)
003716
001816
Transmit/Receive buffer register (TB/RB)
003816
MISRG
001916
USB status register (USBSTS)/UART status register (UARTSTS)
003916
Watchdog timer control register (WDTCON)
001A16
Serial I/O1 control register (SIO1CON)
003A16
Interrupt edge selection register (INTEDGE)
001B16
UART control register (UARTCON)
003B16
CPU mode register (CPUM)
001C16
Baud rate generator (BRG)
003C16
Interrupt request register 1 (IREQ1)
001D16
USB data toggle synchronization register ( TRSYNC)
003D16
001E16
USB interrupt source discrimination register 1 (USBIR1)
003E16
001F16
USB interrupt source discrimination register 2 (USBIR2)
003F16
Fig. 13 Memory map of special function register (SFR)
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REJ09B0178-0300
page 15 of 55
Interrupt control register 1 (ICON1)
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
I/O Ports
[Direction registers] PiD
The I/O ports have direction registers which determine the input/output direction of each pin. Each bit in a direction register corresponds
to individual pin, and each pin can be set to be input or output.
When “1” is set to the bit corresponding to a pin, this pin becomes an
output port. When “0” is set to the bit, the pin becomes an input port.
When data is read from a pin set to output, not the value of the pin
itself but the value of port latch is read. Pins set to input are floating,
and permit reading pin values.
If a pin set to input is written to, only the port latch is written to and the
pin remains floating.
b7
[Pull-up control] PULL
By setting the pull-up control register (address 001616), ports P0 and
P3 can exert pull-up control by program. However, pins set to output
are disconnected from this control and cannot exert pull-up control.
[Port P1P3 control] P1P3C
By setting the port P1P3 control register (address 001716), a CMOS
input level or a TTL input level can be selected for ports P10, P12,
P13, P36 and P37 by program.
Then, as for the 36-pin version, set “1” to each bit 6 of the port P3
direction register and port P3 register.
As for the 32-pin version, set “1” to respective bits 5, 6, 7 of the port
P3 direction register and port P3 register.
b0
Pull-up control register
(PULL: address 0016 16)
P00 pull-up control bit
P01 pull-up control bit
P02, P03 pull-up control bit
P04 – P07 pull-up control bit
P30 – P33 pull-up control bit
P34 pull-up control bit
P35, P36 pull-up control bit
P37 pull-up control bit
Note : Pins set to output ports are disconnected from pull-up control.
Fig. 14 Structure of pull-up control register
b7
b0
Port P1P3 control register
(P1P3C: address 0017 16)
P37/INT 0 input level selection bit
0 : CMOS level
1 : TTL level
P36/INT 1 input level selection bit
0 : CMOS level
1 : TTL level
P10,P1 2,P1 3 input level selection bit
0 : CMOS level
1 : TTL level
Not used
Fig. 15 Structure of port P1P3 control register
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REJ09B0178-0300
page 16 of 55
0: Pull-up off
1: Pull-up on
Initial value: FF16
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
Table 5 I/O port function table
Name
Pin
Input/output
I/O format
P00–P07
Port P0
•CMOS compatible input level
P10/RxD/D-
Port P1
I/O individual
bits
Non-port function
Key input interrupt
Related SFRs
Diagram No.
Pull-up control register
(1)
•CMOS 3-state output
•USB input/output level when
selecting USB function
Serial I/O1 function
input/output
Serial I/O1 control
register
(2)
P11/TxD/D+
P12/SCLK
•CMOS compatible input level
•CMOS 3-state output
Serial I/O2 control
register
(4)
P13/SDATA
Serial I/O2 function
input/output
P14/CNTR0
(Note)
Timer X function input/output Timer X mode register
(5)
(6)
(10)
P15, P16
P20/AN0–
P27/AN7
Port P2
P30–P35
Port P3
A/D conversion input
External interrupt input
P37/INT0
(7)
Interrupt edge selection
register
(9)
(10)
Port P4
Note: Port P10, P12, P13, P36, P37 is CMOS/TTL input level.
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REJ09B0178-0300
A/D control register
(8)
P36/INT1
P40, P41
(3)
page 17 of 55
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
(2) Port P10
(1) Port P0
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
Receive enable bit
Pull-up control
Direction
register
Data bus
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
Direction
register
Port latch
Data bus
Port latch
P10,P12,P13 input
level selection bit
To key input interrupt
generating circuit
Serial I/O1 input
*
(3) Port P11
D- input
P-channel output disable bit
D- output
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
USB output enable
(internal signal)
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
Transmit enable bit
Direction
register
Data bus
Port latch
+
USB differential input
Serial I/O1 output
D+ input
D+ output
USB output enable
(internal signal)
(5) Port P13
(4) Port P12
Signals during the
SDATA output action
SDATA pin selection bit
SCLK pin selection bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
SDATA pin
selection bit
P10,P12,P13 input
level selection bit
P10,P12,P13 input
level selection bit
Serial I/O2 clock output
Serial I/O2 clock input
Serial I/O2 clock output
*
Serial I/O2 clock input
*
P10, P12, P13, P36, P37 input levels are switched to the CMOS/TTL level by the port P1P3 control register.
* : When
the TTL level is selected, there is no hysteresis characteristics.
Fig. 16 Block diagram of ports (1)
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REJ09B0178-0300
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HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
(7) Ports P20–P27
(6) Ports P14
Direction register
Direction register
Port latch
Data bus
Data bus
Port latch
Pulse output mode
Timer output
A/D converter input
Analog input pin selection bit
CNTR0 interrupt input
(9) Ports P36, P37
(8) Ports P30–P35
Pull-up control
Pull-up control
Direction register
Direction register
Data bus
Data bus
Port latch
Port latch
P37/INT0 input
level selection bit
INT interrupt input
*
(10) Ports P15, P16, P40, P41
Direction register
Data bus
Port latch
* : P10, P12, P13, P36, P37 input levels are switched to the CMOS/TTL level by the port P1P3 control register.
When the TTL level is selected, there is no hysteresis characteristics.
Fig. 17 Block diagram of ports (2)
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page 19 of 55
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
Interrupts
Interrupts occur by 14 different sources : 4 external sources, 9 internal sources and 1 software source.
Interrupt control
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit, and they are controlled by the
interrupt disable flag. When the interrupt enable bit and the interrupt
request bit are set to “1” and the interrupt disable flag is set to “0”, an
interrupt is accepted.
The interrupt request bit can be cleared by program but not be set.
The interrupt enable bit can be set and cleared by program.
It becomes usable by switching CNTR0 and A/D interrupt sources
with bit 7 of the interrupt edge selection register, timer 2 and serial I/
O2 interrupt sources with bit 6, timer X and key-on wake-up interrupt
sources with bit 5, and serial I/O transmit and INT1 interrupt sources
with bit 4.
The reset and BRK instruction interrupt can never be disabled with
any flag or bit. All interrupts except these are disabled when the interrupt disable flag is set.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt operation
Upon acceptance of an interrupt the following operations are automatically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status register are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. Concurrently with the push operation, the interrupt destination
address is read from the vector table into the program counter.
Notes on use
When the active edge of an external interrupt (INT0, INT1, CNTR0) is
set, the interrupt request bit may be set.
Therefore, please take following sequence:
1. Disable the external interrupt which is selected.
2. Change the active edge in interrupt edge selection register. (in
case of CNTR0: Timer X mode register)
3. Clear the set interrupt request bit to “0”.
4. Enable the external interrupt which is selected.
Table 6 Interrupt vector address and priority
Interrupt source
Vector addresses (Note 1)
Priority
High-order
Low-order
Interrupt request generating conditions
Remarks
Reset (Note 2)
1
FFFD16
FFFC16
At reset input
Non-maskable
UART receive
2
FFFB16
FFFA16
At completion of UART data receive
Valid in UART mode
At detection of IN token
Valid in USB mode
3
FFF916
FFF816
At completion of UART transmit shift or
when transmit buffer is empty
Valid in UART mode
USB SETUP/OUT token
Reset/Suspend/Resume
At detection of SETUP/OUT token or
At detection of Reset/ Suspend/ Resume
Valid in USB mode
INT1
At detection of either rising or falling edge
of INT1 input
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
USB IN token
UART transmit
INT0
4
FFF716
FFF616
At detection of either rising or falling edge
of INT0 input
Timer X
5
FFF516
FFF416
At timer X underflow
Key-on wake-up
At falling of conjunction of input logical
level for port P0 (at input)
External interrupt (valid at falling)
STP release timer underflow
Timer 1
6
FFF316
FFF216
At timer 1 underflow
Timer 2
7
FFF116
FFF016
At timer 2 underflow
Serial I/O2
CNTR0
At completion of transmit/receive shift
8
FFEF16
A/D conversion
FFEE16
At detection of either rising or falling edge
of CNTR0 input
At completion of A/D conversion
BRK instruction
At BRK instruction execution
9
FFED16
FFEC16
Note 1: Vector addressed contain internal jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
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REJ09B0178-0300
External interrupt (active edge
selectable)
page 20 of 55
Non-maskable software interrupt
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
Interrupt request
Fig. 18 Interrupt control
b7
b0 Interrupt edge selection register
(INTEDGE : address 003A16)
INT0 interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
INT1 interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
Not used (returns “0” when read)
Serial I/O1 or INT1 interrupt selection bit
0 : Serial I/O1
1 : INT1
Timer X or key-on wake up interrupt selection bit
0 : Timer X
1 : Key-on wake up
Timer 2 or serial I/O2 interrupt selection bit
0 : Timer 2
1 : Serial I/O2
CNTR0 or AD converter interrupt selection bit
0 : CNTR0
1 : AD converter
b7
b0 Interrupt request register 1
(IREQ1 : address 003C16)
UART receive/USB IN token interrupt request bit
UART transmit/USB SETUP/OUT token/ Reset/Suspend/Resume/INT1 interrupt request bit
INT0 interrupt request bit
Timer X or key-on wake up interrupt request bit
Timer 1 interrupt request bit
Timer 2 or serial I/O2 interrupt request bit
CNTR0 or AD converter interrupt request bit
0 : No interrupt request issued
Not used (returns “0” when read)
1 : Interrupt request issued
b7
b0 Interrupt control register 1
(ICON1 : address 003E16)
UART receive/USB IN token interrupt enable bit
UART transmit/USB SETUP/OUT token/ Reset/Suspend/Resume/INT1 interrupt enable bit
INT0 interrupt enable bit
Timer X or key-on wake up interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 or serial I/O2 interrupt enable bit
CNTR0 or AD converter interrupt enable bit
Not used (returns “0” when read)
0 : Interrupts disabled
(Do not write “1” to this bit)
1 : Interrupts enabled
Fig. 19 Structure of Interrupt-related registers
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HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
Key Input Interrupt (Key-On Wake-Up)
A key-on wake-up interrupt request is generated by applying “L” level
to any pin of port P0 that has been set to input mode.
In other words, it is generated when the AND of input level goes from
“1” to “0”. An example of using a key input interrupt is shown in Figure 20, where an interrupt request is generated by pressing one of
the keys provided as an active-low key matrix which uses ports P00
to P03 as input ports.
Port PXx
“L” level output
PULL register
bit 3 = “0”
*
**
P07 output
Port P07
Direction register = “1”
Key input interrupt request
Port P07
latch
Falling edge
detection
PULL register
bit 3 = “0”
*
**
P06 output
Port P06
Direction register = “1”
Port P06
latch
Falling edge
detection
PULL register
bit 3 = “0”
*
**
P05 output
Port P05
Direction register = “1”
Port P05
latch
Falling edge
detection
PULL register
bit 3 = “0”
*
**
P04 output
Port P04
Direction register = “1”
Port P04
latch
PULL register
bit 2 = “1”
*
**
P03 input
Port P03
Direction register = “0”
Port P03
latch
PULL register
bit 2 = “1”
*
**
P02 input
Falling edge
detection
Falling edge
detection
Port P02
Direction register = “0”
Port P02
latch
Falling edge
detection
PULL register
bit 1 = “1”
*
**
P01 input
Port P01
Direction register = “0”
Port P01
latch
Falling edge
detection
PULL register
bit 0 = “1”
*
P00 input
**
Port P00
Direction register = “0”
Port P00
latch
Falling edge
detection
* P-channel transistor for pull-up
** CMOS output buffer
Fig. 20 Connection example when using key input interrupt and port P0 block diagram
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REJ09B0178-0300
page 22 of 55
Port P0
Input read circuit
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
Timers
The 7534 Group has 3 timers: timer X, timer 1 and timer 2.
The division ratio of every timer and prescaler is 1/(n+1) provided
that the value of the timer latch or prescaler is n.
All the timers are down count timers. When a timer reaches “0”, an
underflow occurs at the next count pulse, and the corresponding timer
latch is reloaded into the timer. When a timer underflows, the interrupt request bit corresponding to each timer is set to “1”.
b7
b0
Timer X mode register
(TM : Address 002B 16)
Timer X operating mode bits
b1 b0
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNTR0 active edge switch bit
0 : Interrupt at falling edge
Count at rising edge
(in event counter mode)
1 : Interrupt at rising edge
Count at falling edge
(in event counter mode)
●Timer 1, Timer 2
Prescaler 12 always counts f(XIN)/16. Timer 1 and timer 2 always
count the prescaler output and periodically sets the interrupt request
bit.
Timer X count stop bit
0 : Count start
1 : Count stop
●Timer X
Timer X can be selected in one of 4 operating modes by setting the
timer X mode register.
• Timer Mode
The timer counts the signal selected by the timer X count source
selection bit.
• Pulse Output Mode
The timer counts the signal selected by the timer X count source
selection bit, and outputs a signal whose polarity is inverted each
time the timer value reaches “0”, from the CNTR0 pin.
When the CNTR0 active edge switch bit is “0”, the output of the
CNTR0 pin is started with an “H” output.
At “1”, this output is started with an “L” output. When using a timer in
this mode, set the port P14 direction register to output mode.
• Event Counter Mode
The operation in the event counter mode is the same as that in the
timer mode except that the timer counts the input signal from the
CNTR0 pin.
When the CNTR0 active edge switch bit is “0”, the timer counts
the rising edge of the CNTR0 pin. When this bit is “1”, the timer
counts the falling edge of the CNTR0 pin.
• Pulse Width Measurement Mode
When the CNTR0 active edge switch bit is “0”, the timer counts the
signal selected by the timer X count source selection bit while the
CNTR0 pin is “H”. When this bit is “1”, the timer counts the signal
while the CNTR0 pin is “L”.
In any mode, the timer count can be stopped by setting the timer X
count stop bit to “1”. Each time the timer overflows, the interrupt
request bit is set.
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REJ09B0178-0300
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Not used (return “0” when read)
Fig. 21 Structure of timer X mode register
b7
b0
Timer count source set register
(TCSS : Address 002E 16)
Timer X count source selection bit (Note)
0 : f(X IN)/16
1 : f(X IN)/2
Not used (return “0” when read)
Note : To switch the timer X count source selection bit ,
stop the timer X count operation.
Fig. 22 Timer count source set register
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
Data bus
f(XIN)/16
f(XIN)/2
Prescaler X latch (8)
Timer X count
source selection bit
Pulse width
measurement
mode
CNTR0 active
edge switch bit
“0”
P14/CNTR0
Prescaler X (8)
Event
counter
mode
Timer X latch (8)
Timer mode
pulse output mode
Timer X (8)
To timer X
interrupt
request bit
Timer X count stop bit
To CNTR0
interrupt
request bit
“1”
CNTR0 active
edge switch bit
“1”
Q
Q
“0”
Toggle
flip-flop
R
T
Timer X latch write
Pulse output mode
Port P14 latch
Port P14 direction
register
Pulse output mode
Data bus
f(XIN)/16
Prescaler 12 latch (8)
Timer 1 latch (8)
Timer 2 latch (8)
Prescaler 12 (8)
Timer 1 (8)
Timer 2 (8)
To timer 2
interrupt
request bit
To timer 1
interrupt
request bit
Fig. 23 Block diagram of timer X, timer 1 and timer 2
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REJ09B0178-0300
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HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
Serial Interface
●Serial I/O1
• Asynchronous serial I/O (UART) mode
Serial I/O1 can be used as an asynchronous (UART) serial I/O. A
dedicated timer (baud rate generator) is also provided for baud rate
generation when serial I/O1 is in operation.
Eight serial data transfer formats can be selected, and the transfer
formats to be used by a transmitter and a receiver must be identical.
Each of the transmit and receive shift registers has a buffer register
(the same address on memory). Since the shift register cannot be
written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the respective buffer registers. These buffer registers can also hold the next data to be transmitted and receive 2-byte receive data in succession.
By selecting “1” for continuous transmit valid bit (bit 2 of SIO1CON),
continuous transmission of the same data is made possible.
This can be used as a simplified PWM.
Data bus
Address
(001816)
Serial I/O1 control register Address (001A 16)
Receive buffer full flag (RBF)
Receive Buffer Register
OE
Receive interrupt request (RI)
Character length selection bit
P10/RXD
ST Detector
7-bit
Receive Shift Register
1/16
8-bit
PE FE
UART Control Register
Address (001B 16)
SP Detector
Clock Control Circuit
BRG count source selection bit
Division ratio 1/(n+1)
XIN
Baud Rate Generator
Address (001C 16)
1/4
ST/SP/PA Generator
Transmit shift register shift
completion flag (TSC)
1/16
P11/TXD
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit Shift Register
Character length selection bit
Transmit buffer empty flag (TBE)
Transmit Buffer Register
Address
(001816)
Continuous transmit valid bit
Serial I/O1 status register Address (0019 16)
Data bus
Fig. 24 Block diagram of UART serial I/O1
Transmit/Receive Clock
Transmit Buffer Register
Write Signal
TBE=0
TSC=0
TBE=1
Serial Output T XD
TBE=0
TBE=1
ST
D0
D1
SP
TSC=1*
ST
D0
D1
1 Start Bit
7 or 8 Data Bit
1 or 0 Parity Bit
1 or 2 Stop Bit
Receive Buffer Register
Read Signal
SP
* Generated at second bit in 2-stop -bit
mode
RBF=0
RBF=1
Serial Input RXD
ST
D0
D1
SP
RBF=1
ST
D0
D1
SP
Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer at TSC = 1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC = 0.
Fig. 25 Operation of UART serial I/O1 function
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REJ09B0178-0300
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HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
[Serial I/O1 control register] SIO1CON
The serial I/O1 control register consists of eight control bits for the
serial I/O1 function.
[Baud Rate Generator] BRG
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
[UART control register] UARTCON
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set the
data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P11/TxD pin.
[UART status register] UARTSTS
The read-only UART status register consists of seven flags (bits 0 to
6) which indicate the operating status of the UART function and various errors. This register functions as the UART status register
(UARTSTS) when selecting the UART.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer, and the
receive buffer full flag is set. A write to the UART status register clears
all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively).
Writing “0” to the serial I/O1 mode selection bits MOD1 and MOD0
(bit 7 and 6 of the Serial I/O1 control register ) also clears all the
status flags, including the error flags.
All bits of the serial I/O1 status register are initialized to “8116” at
reset, but if the transmit enable bit (bit 4) of the serial I/O1 control
register has been set to “1”, the continuous transmit valid bit (bit 2)
becomes “1”.
[Transmit/Receive buffer register] TB/RB
The transmit buffer and the receive buffer are located at the same
address. The transmit buffer is write-only and the receive buffer is
read-only. If a character bit length is 7-bit, the MSB of data stored in
the receive buffer is “0”.
Transmit/Receive Clock
Transmit Buffer Register
Write Signal
TBE=0
TSC=0
TBE=1
Serial Output T XD
ST
D0
D1
SP
ST
D0
D1
SP
ST
1 Start Bit
7 or 8 Data Bit
1 or 0 Parity Bit
1 or 2 Stop Bit
Notes 1 : When the serial I/O1 mode selection bits (b7, b6) is “10”, the transmit enable bit is “1”, and continuous transmit valid bit is “1”, writing on the
transmit buffer initiates continuous transmission of the same data.
2 : Select 0 for continuous transmit valid bit to stop continuous transmission.
The T XD pin will stop at high level after completing transmission of 1 byte.
3 : If the transmit buffer contents are rewritten during a continuous transmission, transmission of the rewritten data will be started after
completing transmission of 1 byte.
Fig. 26 Continuous transmission operation of UART serial I/O
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REJ09B0178-0300
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HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
register functions as the USB status register (USBSTS).There is
the USBVREFOUT pin for the USB reference voltage output, and a Dline with 1.5 kΩ external resistor can be pull up. USB mode block
and USB transceiver block show in figures 27 and 28.
• Universal serial bus (USB) mode
By setting bits 7 and 6 of the serial I/O1 control register (address
001A16) to “11”, the USB mode is selected. This mode conforms to
Low-Speed USB2.0 specification. In this mode serial I/O1 interrupt
have 6 sources; USB in and out token receive, set-up token receive,
USB reset, suspend, and resume. The USB status/UART status
Data bus
Address 001816
1.5 MHz
6 MHz
XIN
RxRDY
Receive buffer register
NRZI,
bit stuffing decoder
Digital
PLL
Receive shift register
SYNC decoder
BSTFE
EOP
Differential input and
Single end input
PID decoder
Bus state
detection
Reset interrupt request
RxPID
OPID
PIDE
P10/DP11/D+
Suspend interrupt request
Address
comparative unit
USB
transceiver
Resume interrupt request
Token interrupt request
USBA
End pointer
decoder
RxEP
Output data and
I/O control
CRC check
CRCE
NRZI,
bit stuffing encoder
Transmit shift register
USB transmit unit
SYNC, PID
generating unit
CRC encoder
TxRDY
Transmit buffer register
EOP generating unit
EP0BYTE
EP1BYTE
Address 001816
EP0PID
EP1PID
Data bus
Fig. 27 USB mode block diagram
Serial I/O1 control register
MOD0
MOD1
USB control register
UVOE
(initial value “0”)
Output enable signal
USB reference
power source voltage
Voltage input
Internal D- output signal
Internal D+ output signal
Output amplifier
USBVREFOUT
D-
D+/Doutput amplifier
D+
Suspend
Signal for function stop
OE Output enable signal
(internal signal)
Differential input
Single end input
Single end input
Fig. 28 USB transceiver block diagram
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REJ09B0178-0300
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+
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
b7
b0
Transmit buffer register
(TB: address 0018 16)
After setting data to address 0018 16, a content of the
transmit buffer register transfers to the transmit shift
register automatically.
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
b7
b0
Receive buffer register
(RB: address 0018 16)
By reading data from address 0018 16, a content of the
receive buffer register can be read out.
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
b7
b0
USB status register
(USBSTS: address 0019 16)
Transmit buffer empty flag
0: Buffer full
1: Buffer empty
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
EOP detection flag
0: Not detected
1: Detect
False EOP error flag
0: No error
1: False EOP error
CRC error flag
0: No error
1: CRC error
PID error flag
0: No error
1: PID error
CPU read: Enabled
CPU write: Clear
Hardware read: Not used
Hardware write: Set
Bit stuffing error flag
0: No error
1: Bit stuffing error
Summing error flag
0: No error
1: Summing error
Receive buffer full flag
0: Buffer empty
1: Buffer full
Fig. 29 Structure of serial I/O1-related registers (1)
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REJ09B0178-0300
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CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
b7
b0
USB data toggle synchronization register
(TRSYNC: address 001D 16)
Not used (return “1” when read)
Sequence bit toggle flag
0: No toggle
1: Sequence toggle
b7
CPU read: Enabled
CPU write: Clear
Hardware read: Not used
Hardware write: Set
b0
USB interrupt source discrimination register 1
(USBIR1: address 001E 16)
Not used (return “1” when read)
Endpoint determination flag
0: Endpoint 0 interrupt
1: Endpoint 1 interrupt
b7
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
b0
USB interrupt source discrimination register 2
(USBIR2: address 001F 16)
Not used (return “1” when read)
Suspend request flag
0: No request
1: Suspend request
CPU read: Enabled
CPU write: Clear
Hardware read: Not used
Hardware write: Set
USB reset request flag
0: No request
1: Reset request
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
Not used (return “1” when read)
Token PID determination flag
0: SETUP interrupt
1: OUT interrupt
Token interrupt flag
0: No request
1: Token request
b7
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
b0
USB interrupt control register
(USBICON: address 0020 16)
Not used (return “1” when read)
Endpoint 1 enable
0: Endpoint 1 invalid
1: Endpoint 1 valid
USB reset interrupt enable
0: USB reset invalid
1: USB reset valid
Resume interrupt enable
0: Resume invalid
1: Resume valid
Token interrupt enable
0: Token invalid
1: Token valid
USB enable flag
0: USB invalid
1: USB valid
Fig. 30 Structure of serial I/O1-related registers (2)
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REJ09B0178-0300
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CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
HARDWARE
7534 Group
b7
FUNCTIONAL DESCRIPTION
b0
USB transmit data byte number set register 0
(EP0BYTE: address 002116)
Set a number of data byte for transmitting with endpoint 0.
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Not used (return “0” when read)
b7
b0
USB transmit data byte number set register 1
(EP1BYTE: address 002216)
Set a number of data byte for transmitting with endpoint 1.
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Not used (return “0” when read)
b7
b0
USB PID control register 0
(EP0PID: address 002316)
Not used (return “1” when read)
Endpoint 0 enable flag
0: Endpoint 0 invalid
1: Endpoint 0 valid
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Endpoint 0 PID selection flag
1xxx: IN token interrupt of DATA0/1 is valid
01xx: STALL handshake is valid for IN token
00xx: NAK handshake is valid for IN token
xxx1: STALL handshake is valid for OUT token (Note)
xx10: ACK handshake is valid for OUT token
xx00: NAK handshake is valid for OUT token
b4, b5, b6
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
x: any data
b7
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Clear
Note: In the status stage of the control read transfer, when PID
of data packet = DATA0 (incorrect PID), this bit is set forcibly
by hardware and STALL handshake is valid.
b7
b0
USB PID control register 1
(EP1PID: address 002416)
Not used (return “1” when read)
Endpoint 1 PID selection flag
1x: IN token interrupt of DATA0/1 is valid
01: STALL handshake is valid for IN token
00: NAK handshake is valid for IN token
x: any data
b7
b0
USB address register
(USBA: address 002516)
Set an address allocated by the USB host.
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Not used (returns “1” when read)
Fig. 31 Structure of serial I/O1-related registers (3)
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REJ09B0178-0300
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b6
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
b7
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Clear
HARDWARE
7534 Group
b7
FUNCTIONAL DESCRIPTION
b0
USB sequence bit initialization register
(INISQ1: address 0026 16)
A sequence bit of endpoint 1 is initialized.
CPU read: Disabled
CPU write: Dummy
Hardware read: Not used
Hardware write: Not used
b7
b0
USB control register
(USBCON: address 0027 16)
Not used (return “1” when read)
b7
USBVREFOUT output valid flag
0: Output off
1: Output on
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Remote wake up request flag
0: No request
1: Remote wake up request
CPU read: Disabled
CPU write: Set
Hardware read: Used
Hardware write: Clear
b0
UART status register
(UARTSTS: address 0019 16)
Transmit buffer empty flag
0: Buffer full
1: Buffer empty
Receive buffer full flag
0: Buffer empty
1: Buffer full
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
Transmit shift register shift completion flag
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag
0: No error
1: Overrun error
Parity error flag
0: No error
1: Parity error
Framing error flag
0: No error
1: Framing error
CPU read: Enabled
CPU write: Clear
Hardware read: Not used
Hardware write: Set
Summing error flag
0: No error
1: Summing error
Not used (returns “1” when read)
b7
b0
Baud rate generator
(BRG: address 001C 16)
This register is valid only when selecting the UART mode.
A baud rate value is set.
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Fig. 32 Structure of serial I/O1-related registers (4)
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REJ09B0178-0300
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HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
b7
b0
UART control register
(UARTCON: address 001B 16)
Character length selection bit
0: 8 bits
1: 7 bits
Parity enable bit
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit
0: Even parity
1: Odd parity
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Stop bit length selection bit
0: 1 stop bit
1: 2 stop bits
P-channel output disable bit
0: CMOS output
1: N-channel open-drain output
Not used (returns “1” when read)
b7
b0
Serial I/O1 control register
(SIO1CON: address 001A 16)
BRG count source selection bit
0: f(XIN)
1: f(XIN)/4
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Not used (returns “1” when read)
Continuous transmit valid bit
0: Continuous transmit invalid
1: Continuous transmit valid
Transmit interrupt source selection bit
0: Interrupt when transmit buffer has
emptied
1: Interrupt when transmit shift
operation is completed
Transmit enable bit
0: Transmit disabled
1: Transmit enabled
Receive enable bit
0: Receive disabled
1: Receive enabled
Serial I/O1 mode selection bits
00: I/O port
01: Not available
10: UART mode
11: USB mode
Fig. 33 Structure of serial I/O1-related registers (5)
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CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
Note on using USB mode
Handling of SE0 signal in program (at receiving)
7534 group has the border line to detect as USB RESET or EOP
(End of Packet) on the width of SE0 (Single Ended 0).
A response apposite to a state of the device is expected.
The name of the following short words which is used in table 5 shows
as follow.
•TKNE: Token interrupt enable (bit 6 of address 2016)
•RSME: Resume interrupt enable (bit 5 of address 2016)
•RSTE: USB reset interrupt enable (bit 4 of address 2016)
•Spec: A response of the device requested by Low-Speed USB2.0
specification
•SIE: Hardware operation in 7534 group
•F/W: Recommendation process in the program
•FEOPE: False EOP error flag (bit 2 of address 1916)
•RxPID: Token interrupt flag (bit 7 of address 1F16)
Table 7 Relation of the width of SE0 and the state of the device
State of device
Idle state
Width of SE0
Spec
0 µs
TKNE = X
TKNE = 1
RSME = 0
RSME = 0
RSTE =1
RSTE =1
RSME = 0
Ignore
Ignore
Not detected as EOP(in
case of no detection EOP,
SIE returns idle state as
time out. FEOPE flag is
set.)
Not detected as EOP(in
case of no detection EOP,
SIE returns idle state as
timeup. FEOPE flag is
set.)
F/W
Not acknowledge
Not acknowledge
Wait for the next EOP flag
Keep alive
EOP
EOP
Initialize suspend timer
count value
Token interrupt request
Set EOP flag
Not acknowledge
Token interrupt processing
execute
After checking the set of
EOP flag, go to the next
processing
Keep alive or Reset
EOP or Reset
EOP or Reset
may determine as keep
alive and Reset interrupt
may determine as EOP and
Reset interrupt
may determine as EOP
and Reset interrupt
Keep alive in case of no
interrupt request
RxPID = 1> Token interrupt
processing
Reset processing in case
of interrupt request
RxPID = 0> Reset interrupt
processing
Continue the processing
in case of no interrupt
request
Reset
Reset
Reset
SIE
Reset interrupt request
Reset interrupt request
Reset interrupt request
F/W
Reset processing
Reset processing
Reset processing
F/W
Spec
SIE
2.5 µs
2.67 µs
F/W
Spec
TKNE = 0
RSME = 1
RSTE = 0
RSTE = 0 or 1
Spec
SIE
Suspend state
TKNE = 0
Keep counting suspend
timer
SIE
2.5 µs
2.67 µs
End of data or handshake
in transaction
Ignore
0.5 µs
0.5 µs
End of Token in transaction
Reset processing in case
of interrupt request
Spec
SIE
F/W
Reset or resume
Reset interrupt
request
Reset interrupt
processing
Resume interrupt
processing
• Function of USBPID control register 0 (address 002316)
Bit 4 (STALL handshake control for OUT token) of this register is forcibly set by SIE under the special condition shown below.
Set condition; when PID of data packet = DATA0 (incorrect PID) in the status stage of the control read transfer.
• SYNC field at reception
Normally, the SYNC field consists of “KJKJKJKK” (8 bits). However, as for SIE of the 7534 Group, when the low-order 6 bits are “KJKJKK”, it is
determined as SYNC.
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HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
●Serial I/O2
b7
b0
The serial I/O2 function can be used only for clock synchronous serial I/O.
For clock synchronous serial I/O2 the transmitter and the receiver
must use the same clock. When the internal clock is used, transfer is
started by a write signal to the serial I/O2 register.
Serial I/O2 control register
(SIO2CON: address 003016)
Internal synchronous clock selection bits
000 : f(XIN)/8
001 : f(XIN)/16
010 : f(XIN)/32
011 : f(XIN)/64
110 : f(XIN)/128
111 : f(XIN)/256
SDATA pin selection bit (Note)
0 : I/O port/SDATA input
1 : SDATA output
[Serial I/O2 control register] SIO2CON
The serial I/O2 control register contains 8 bits which control various
serial I/O functions.
Not used
(returns “0” when read)
Transfer direction selection bit
0 : LSB first
1 : MSB first
SCLK pin selection bit
0 : External clock (SCLK is an input)
1 : Internal clock (SCLK is an output)
Transmit / receive shift completion flag
0 : shift in progress
1 : shift completed
• For receiving, set “0” to bit 3.
• When receiving, bit 7 is cleared by writing dummy data to serial I/
O2 register after shift is completed.
• Bit 7 is set earlier a half cycle of shift clock than completion of shift
operation. Accordingly, when checking shift completion by using
this bit, the setting is as follows:
(1) check that this bit is set to “1”,
(2) wait a half cycle of shift clock,
(3) read/write to serial I/O2 register.
Note : When using it as an SDATA input, set the port P13
direction register to “0”.
Fig. 34 Structure of serial I/O2 control registers
Data bus
1/8
1/16
1/32
Divider
XIN
1/64
1/128
1/256
SCLK pin
selection bit
“1”
SCLK
“0”
Internal synchronous
clock selection bits
SCLK pin selection bit
“0”
P12/SCLK
P12 latch
Serial I/O counter 2 (3)
“1”
SDATA pin selection bit
“0”
P13/SDATA
P13 latch
“1”
SDATA pin selection bit
Serial I/O shift register 2 (8)
Fig. 35 Block diagram of serial I/O2
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 34 of 55
Serial I/O2
interrupt request
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
Serial I/O2 operation
By writing to the serial I/O2 register(address 003116) the serial I/O2
counter is set to “7”.
After writing, the SDATA pin outputs data every time the transfer clock
shifts from a high to a low level. And, as the transfer clock shifts from
a low to a high, the SDATA pin reads data, and at the same time the
contents of the serial I/O2 register are shifted by 1 bit.
When the internal clock is selected as the transfer clock source, the
following operations execute as the transfer clock counts up to 8.
• Serial I/O2 counter is cleared to “0”.
• Transfer clock stops at an “H” level.
• Interrupt request bit is set.
• Shift completion flag is set.
Also, the SDATA pin is in a high impedance state after the data transfer is complete. Refer to Figure 36.
When the external clock is selected as the transfer clock source, the
interrupt request bit is set as the transfer clock counts up to 8, but
external control of the clock is required since it does not stop. Notice
that the SDATA pin is not in a high impedance state on the completion
of data transfer.
Synchronous clock
Transfer clock
Serial I/O2 register
write signal
(Note)
SDATA at serial I/O2
output transmit
D0
D1
D2
D3
D4
D5
D6
D7
SDATA at serial I/O2
input receive
Serial I/O2 interrupt request bit set
Note : When the internal clock is selected as the transfer and the direction register of P1 3/SDATA pin is set to the input mode,
the SDATA pin is in a high impedance state after the data transfer is completed.
Fig. 36 Serial I/O2 timing (LSB first)
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 35 of 55
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
A/D Converter
b7
b0
The functional blocks of the A/D converter are described below.
A/D control register
(ADCON : address 003416)
[A/D conversion register] AD
The A/D conversion register is a read-only register that stores the
result of A/D conversion. Do not read out this register during an A/D
conversion.
Analog input pin selection bits
000 : P20/AN0
001 : P21/AN1
010 : P22/AN2
011 : P23/AN3
100 : P24/AN4
101 : P25/AN5
110 : P26/AN6
111 : P27/AN7
[A/D control register] ADCON
The A/D control register controls the A/D converter. Bit 2 to 0 are
analog input pin selection bits. Bit 4 is the AD conversion completion
bit. The value of this bit remains at “0” during A/D conversion, and
changes to “1” at completion of A/D conversion.
A/D conversion is started by setting this bit to “0” except during an A/
D conversion.
Not used (returns “0” when read)
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
Not used (returns “0” when read)
Fig. 37 Structure of A/D control register
[Comparison voltage generator]
The comparison voltage generator divides the voltage between VSS
and VREF by 1024 by a resistor ladder, and outputs the divided voltages. Since the generator is disconnected from VREF pin and VSS
pin, current is not flowing into the resistor ladder.
Read 8-bit (Read out only address 003516)
b7
(Address 003516)
b9 b8
b7
b0
b6
b5
b7
(Address 003516)
b7 b6
b5
b4
b3
Fig. 38 Structure of A/D conversion register
Data bus
b0
A/D control register
(Address 003416)
3
Channel selector
A/D control circuit
A/D conversion register (high-order)
(Address 003616)
(Address 003516)
Resistor ladder
VREF
Fig. 39 Block diagram of A/D converter
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 36 of 55
A/D interrupt request
A/D conversion register (low-order)
10
VSS
b8
b0
b2
High-order 6-bit of address 003616 returns “0” when read.
b7
b2
b0
b9
(Address 003616)
[Comparator and control circuit]
The comparator and control circuit compares an analog input voltage with the comparison voltage and stores its result into the A/D
conversion register. When A/D conversion is completed, the control
circuit sets the AD conversion completion bit and the AD interrupt
request bit to “1”. Because the comparator is constructed linked to a
capacitor, set f(XIN) to 500 kHz or more during A/D conversion.
Comparator
b3
Read 10-bit (read out in order address 003616, 003516)
b7
[Channel Selector]
The channel selector selects one of ports P27/AN7 to P20/AN0, and
inputs the voltage to the comparator.
P20/AN0
P21/AN1
P22/AN2
P23/AN3
P24/AN4
P25/AN5
P26/AN6
P27/AN7
b4
b1
b0
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
Watchdog Timer
Operation of watchdog timer H count source selection bit
A watchdog timer H count source can be selected by bit 7 of the
watchdog timer control register (address 003916). When this bit is
“0”, the count source becomes a watchdog timer L underflow signal.
The detection time is 174.763 ms at f(XIN)=6 MHz.
When this bit is “1”, the count source becomes f(XIN)/16. In this
case, the detection time is 683 µs at f(XIN)=6 MHz.
This bit is cleared to “0” after reset.
The watchdog timer gives a means for returning to a reset status
when the program fails to run on its normal loop due to a runaway.
The watchdog timer consists of an 8-bit watchdog timer H and an 8bit watchdog timer L, being a 16-bit counter.
Standard operation of watchdog timer
The watchdog timer stops when the watchdog timer control register
(address 003916) is not set after reset. Writing an optional value to
the watchdog timer control register (address 003916) causes the
watchdog timer to start to count down. When the watchdog timer H
underflows, an internal reset occurs. Accordingly, it is programmed
that the watchdog timer control register (address 003916) can be set
before an underflow occurs.
When the watchdog timer control register (address 003916) is read,
the values of the high-order 6-bit of the watchdog timer H, STP instruction disable bit and watchdog timer H count source selection bit
are read.
Operation of STP instruction disable bit
When the watchdog timer is in operation, the STP instruction can be
disabled by bit 6 of the watchdog timer control register (address
003916).
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled, and an internal
reset occurs if the STP instruction is executed.
Once this bit is set to “1”, it cannot be changed to “0” by program.
This bit is cleared to “0” after reset.
Initial value of watchdog timer
By a reset or writing to the watchdog timer control register (address
003916), the watchdog timer H is set to “FF16” and the watchdog
timer L is set to “FF16”.
Data bus
Write “FF16” to the
watchdog timer
control register
Watchdog timer L (8)
1/16
XIN
“0”
“1”
Watchdog timer H (8)
Write “FF16” to the
watchdog timer
control register
Watchdog timer H count
source selection bit
STP Instruction Disable Bit
STP Instruction
Reset
circuit
RESET
Internal reset
Fig. 40 Block diagram of watchdog timer
b7
b0
Watchdog timer control register(address 0039 16)
WDTCON
Watchdog timer H (read-only for high-order 6-bit)
STP instruction disable bit
0 : STP instruction enabled
1 : STP instruction disabled
Watchdog timer H count source selection bit
0 : Watchdog timer L underflow
1 : f(XIN)/16
Fig. 41 Structure of watchdog timer control register
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 37 of 55
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
Reset Circuit
The microcomputer is put into a reset status by holding the RESET
pin at the “L” level for 15 µs or more when the power source voltage
is 4.1 to 5.5 V and XIN is in stable oscillation.
After that, this reset status is released by returning the RESET pin to
the “H” level. The program starts from the address having the contents of address FFFD16 as high-order address and the contents of
address FFFC16 as low-order address.
Note that the reset input voltage should be 0.82 V or less when the
power source voltage passes 4.1 V.
Poweron
RESET
VCC
Power source
voltage
0V
Reset input
voltage
0V
(Note)
0.2 VCC
Note : Reset release voltage Vcc = 4.1 V
RESET
VCC
Power source
voltage
detection circuit
Fig. 42 Example of reset circuit
Clock from on-chip
oscillator
φ
RESET
RESETOUT
SYNC
?
Address
?
?
Data
8-13 clock cycles
Fig. 43 Timing diagram at reset
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 38 of 55
?
?
?
?
FFFC
?
?
?
FFFD
ADL
ADH,ADL
ADH
Reset address from the
vector table
Notes 1 : An on-chip oscillator applies about 250 kHz frequency as clock f at average of Vcc = 5 V.
2 : The mark “?” means that the address is changeable depending on the previous state.
3 : These are all internal signals except RESET
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
Address
Register contents
(1) Port P0 direction register
000116
(2) Port P1 direction register
000316
(3) Port P2 direction register
000516
0016
(4) Port P3 direction register
000716
0016
(5) Port P4 direction register
000916
(6) Pull-up control register
001616
(7) USB/UART status register
001916
(8) Serial I/O1 control register
001A16
(9) UART control register
001B16
1
1
1
0
(10) USB data toggle synchronization register
001D16
0
1
1
(11) USB interrupt source discrimination register 1
001E16
0
1
(12) USB interrupt source discrimination register 2
001F16
0
(13) USB interrupt control register
002016
0
(14) USB transmit data byte number set register 0
002116
0016
(15) USB transmit data byte number set register 1
002216
0016
(16) USBPID control register 0
002316
0
0
0
0
(17) USBPID control register 1
002416
0
0
1
(18) USB address register
002516
1
0
0
(19) USB sequence bit initialization register
002616
1
1
(20) USB control register
002716
0
0
(21) Prescaler 12
002816
FF16
(22) Timer 1
002916
0116
(23) Timer 2
002A16
0016
(24) Timer X mode register
002B16
0016
(25) Prescaler X
002C16
FF16
(26) Timer X
002D16
FF16
(27) Timer count source set register
002E16
0016
(28) Serial I/O2 control register
003016
0016
(29) A/D control register
003416
1016
(30) MISRG
003816
0016
(31) Watchdog timer control register
003916
(32) Interrupt edge selection register
003A16
(33) CPU mode register
003B16
(34) Interrupt request register 1
003C16
0016
(35) Interrupt control register 1
003E16
0016
(36) Processor status register
(37) Program counter
(PS)
0016
X
0
0
0
0
0
0
X
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
X
X
X
X
X
X
1
0
0
0
0
X
FF16
0
0216
0
0
1
1
1
0016
1
X
0
X
0
X
0
X
0
X
(PCH)
Contents of address FFFD16
(PCL)
Contents of address FFFC16
Note X : Undefined
Fig. 44 Internal status of microcomputer at reset
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 39 of 55
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
Clock Generating Circuit
An oscillation circuit can be formed by connecting a resonator between XIN and XOUT.
Use the circuit constants in accordance with the resonator
manufacturer's recommended values. No external resistor is needed
between XIN and XOUT since a feed-back resistor exists on-chip. (An
external feed-back resistor may be needed depending on conditions.)
XIN
XOUT
Rd (Note)
●Oscillation control
• Stop mode
When the STP instruction is executed, the internal clock φ stops at
an “H” level and the XIN oscillator stops. At this time, timer 1 is set to
“01 16 ” and prescaler 12 is set to “FF 16 ” when the oscillation
stabilization time set bit after release of the STP instruction is “0”.
On the other hand, timer 1 and prescaler 12 are not set when the
above bit is “1”. Accordingly, set the wait time fit for the oscillation
stabilization time of the oscillator to be used.
f(XIN)/16 is forcibly connected to the input of prescaler 12.
When an external interrupt is accepted, oscillation is restarted but
the internal clock φ remains at “H” until timer 1 underflows. As soon
as timer 1 underflows, the internal clock φ is supplied. This is
because when a ceramic oscillator is used, some time is required
until a start of oscillation.
In case oscillation is restarted by reset, no wait time is generated.
______
So apply an “L” level to the RESET pin while oscillation becomes
stable.
• Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock restarts
if a reset occurs or when an interrupt is received.
Since the oscillator does not stop, normal operation can be started
immediately after the clock is restarted.
To ensure that interrupts will be received to release the STP or WIT
state, interrupt enable bits must be set to “1” before the STP or
WIT instruction is executed.
When the STP status is released, prescaler 12 and timer 1 will start
counting clock which is XIN divided by 16, so set the timer 1 interrupt enable bit to “0” before the STP instruction is executed.
Note
For use with the oscillation stabilization set bit after release of the
STP instruction set to “1”, set values in timer 1 and prescaler
12 after fully appreciating the oscillation stabilization time of the
oscillator to be used.
• Clock mode
Operation is started by an on-chip oscillator after releasing reset.
A division ratio (1/1,1/2,1/8) is selected by setting bits 7 and 6 of the
CPU mode register after releasing it.
COUT
CIN
Note : Insert a damping resistor if required.
The resistance will vary depending on the oscillator and the
oscillation drive capacity setting.
Use the value recommended by the maker of the oscillator.
Also, if the oscillator manufacturer's data sheet specifies that
a feedback resistor be added external to the chip though a
feedback resistor exists on-chip, insert a feedback resistor
between XIN and XOUT following the instruction.
Fig. 45 External circuit of ceramic resonator
XIN
XOUT
External oscillation
circuit
VCC
VSS
Fig. 46 External clock input circuit
b7
b0
MISRG(Address 0038 16)
Oscillation stabilization time set bit after
release of the STP instruction
0: Set “0116” in timer1, and “FF 16”
in prescaler 12 automatically
1: Not set automatically
Reserved bits (return “0” when read)
(Do not write “1” to these bits)
Not used (return “0” when read)
Fig. 47 Structure of MISRG
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 40 of 55
Open
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION
XIN
XOUT
(Note 2)
Rf
Rd
Clock division ratio selection bit
Middle-speed, High-speed, double -speed mode
1/2
1/2
1/4
Timer 1
Prescaler 12
On-chip oscillator
mode
Clock division ratio selection bit
Middle-speed mode
Timing φ
(Internal clock)
High-speed mode
Double-speed mode
On-chip oscillator
(Note 1)
1/8
On-chip oscillator mode
S
Q S
STP instruction
R
Reset
Interrupt disable flag l
Interrupt request
WIT
instruction
Q
R
page 41 of 55
S
R
STP instruction
Note 1: On-chip oscillator is used only for starting.
2: Although a feed-back resistor exists on-chip, an external feed-back
resistor may be needed depending on conditions.
Fig. 48 Block diagram of system clock generating circuit (for ceramic resonator)
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
Q
HARDWARE
7534 Group
NOTES ON PROGRAMMING/NOTES ON USE
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after reset are
undefined except for the interrupt disable flag I which is “1”. After
reset, initialize flags which affect program execution. In particular, it
is essential to initialize the T flag and the D flag because of their
effect on calculations.
Interrupts
The contents of the interrupt request bit do not change even if the
BBC or BBS instruction is executed immediately after they are
changed by program because this instruction is executed for the previous contents. For executing the instruction for the changed contents, execute one instruction before executing the BBC or BBS instruction.
Decimal Calculations
• For calculations in decimal notation, set the decimal mode flag D to
“1”, then execute the ADC instruction or SBC instruction. In this
case, execute SEC instruction, CLC instruction or CLD instruction
after executing one instruction before the ADC instruction or SBC
instruction.
• In the decimal mode, the values of the N (negative), V (overflow)
and Z (zero) flags are invalid.
Watchdog Timer
The internal reset may not be generated correctly in the middle-speed
mode, depending on the underflow timing of the watchdog timer.
When using the watchdog timer, operate the MCU in any mode other
than the middle-speed mode (i.e., high-speed, low-speed or doublespeed mode).
Instruction Execution Timing
The instruction execution time can be obtained by multiplying the
frequency of the internal clock φ by the number of cycles mentioned
in the machine-language instruction table.
The frequency of the internal clock φ is the same as that of the
X IN in double-speed mode, twice the X IN cycle in high-speed
mode and 8 times the XIN cycle in middle-speed mode.
Note on stack page
When 1 page is used as stack area by the stack page selection bit,
the area which can be used as stack depends on RAM size. Especially, be careful that the RAM area varies in Mask ROM version,
One Time PROM version and Emulator MCU.
NOTES ON USE
Handling of Power Source Pin
• When n (0 to 255) is written to a timer latch, the frequency division
ratio is 1/(n+1).
• When a count source of timer X is switched, stop a count of timer X.
In order to avoid a latch-up occurrence, connect a capacitor suitable
for high frequencies as bypass capacitor between power source pin
(Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to
as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic or electrolytic
capacitor of 1.0 µF is recommended.
Ports
Handling of USBVREFOUT Pin
• The values of the port direction registers cannot be read.
That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is “1”, addressing mode using direction register values as qualifiers, and bit test instructions such
as BBC and BBS.
It is also impossible to use bit operation instructions such as CLB
and SEB and read/modify/write instructions of direction registers
for calculations such as ROR.
For setting direction registers, use the LDM instruction, STA instruction, etc.
• As for the 36-pin version, set "1" to each bit 6 of the port P3 direction register and the port P3 register.
• As for the 32-pin version, set “1” to respective bits 5, 6, 7 of the port
P3 direction register and port P3 register.
In order to prevent the instability of the USBVREFOUT output due to
external noise, connect a capacitor as bypass capacitor between
USBVREFOUT pin and GND pin (VSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor, a ceramic or
electrolytic capacitor of 0.22 µF is recommended.
Timers
A/D Converter
The comparator uses internal capacitors whose charge will be lost if
the clock frequency is too low.
Make sure that f(XIN) is 500kHz or more during A/D conversion.
Do not execute the STP instruction during A/D conversion.
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 42 of 55
USB Communication
• In applications requiring high-reliability, we recommend providing
the system with protective measures such as USB function initialization by software or USB reset by the host to prevent USB communication from being terminated unexpectedly, for example due
to external causes such as noise.
• When USB suspend mode with TTL level on P10, P12, P13 input
level selection bit (bit 3 of address 1716) set to “1”, suspend current
as ICC might be greater than 300 µA as a spec.
[Countermeasure]
There are two countermeasures by software to avoid it as follows.
(1) Change from TTL input level to CMOS input level for P10, P12,
P13 port input.
(2) Change from TTL input level to CMOS input level before STP
instruction in suspend routine;
then after RESUME or Remote wake up interrupt, return to TTL
input level from CMOS input level. That is shown in Figure 49.
HARDWARE
7534 Group
DATA REQUIRED FOR MASK ORDERS/ROM PROGRAMMING METHOD
Note on A/D Converter
SUSPEND Routine
Configuration to CMOS input
level for P10, P12, P13 input level.
P1P3C xxxxx0xx2
Configuration to CMOS
input level for P10, P12, P13
input level.
P1P3C xxxxx1xx2
Configuration to TTL input
level for P10, P12, P13 input
level.
STP
Method to stabilize A/D Converter is described below.
(a) A/D conversion accuracy could be affected for Bus Powered*1
USB devices, while the communicating.
Figure 50 shows the method to stabilize A/D conversion accuracy, inserting a capacitor between Vref and VSS.
*1: Power supplied by USB VCC BUS.
RESUME Routine
AN0 to AN7
Configuration to TTL input level
for P10, P12, P13 input level.
1.5 kΩ
Vcc
0.01 to 1 µF
Remote wake up Routine
D-
USBVREFOUT
0.22 µF
1 µF
7534 Group
CNVss
Configuration to TTL input level
for P10, P12, P13 input level.
P1P3C xxxxx1xx2
Vref
Configuration to TTL input
level for P10, P12, P13 input
level.
1 to 10 kΩ
Vss
Fig. 49 Countermeasure (2) by software
0.1 to 1 µF
: Recommends for A/D accuracy
One Time PROM Version
The CNVss pin is connected to the internal memory circuit block by a
low-ohmic resistance, since it has the multiplexed function to be a
programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVss pin
and Vss pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNVss pin has no operational interference even if it is connected via a resistor.
Electric Characteristic Differences Among
Mask ROM and One TIme PROM Version MCUs
There are differences in electric characteristics, operation margin,
noise immunity, and noise radiation among mask ROM and One
Time PROM version MCUs due to the differences in the manufacturing processes.
When manufacturing an application system with One Time PROM
version and then switching to use of the mask ROM version, perform sufficient evaluations for the commercial samples of the
mask ROM version.
Note on Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and may
perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the supply voltage is less than the
recommended operating conditions and design a system not to
cause errors to the system by this unstable operation.
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 43 of 55
Fig. 50 Method to stabilize A/D conversion accuracy
(b) It is recommended for A/D accuracy to avoid converting while
USB communication, and use average value of several converted values.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production:
(1) Mask ROM Order Confirmation Form
(2) Mark Specification Form
(3) Data to be written to ROM, in EPROM form
(three identical copies)
* For the mask ROM confirmation and the mark specifications,
refer to the “Renesas Technology Corp.” Homepage
(http://www.renesas.com).
HARDWARE
7534 Group
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version can be
read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area.
Table 8 Special programming adapter
Package
Name of Programming Adapter
PLQP0032GB-A
PCA7435GPG03
PRSP0036GA-A
PCA7435FP, PCA7435FPG02
PRDP0042BA-A
PCA7435SP, PCA7435SPG02
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in
Figure 51 is recommended to verify programming.
Programming with
PROM programmer
Screening (Caution)
(150 °C for 40 hours)
Verification with PROM
programmer
Functional check in
target device
Caution: The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Fig. 51 Programming and testing of One Time PROM version
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 44 of 55
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION SUPPLEMENT
FUNCTIONAL DESCRIPTION SUPPLEMENT
Interrupt
7534 group permits interrupts on the 14 sources
for 42-pin version, 13 sources for 36-pin version
and 12 sources for 32-pin version. It is vector
interrupts with a fixed priority system. Accordingly,
when two or more interrupt requests occur during
the same sampling, the higher-priority interrupt is
accepted first. This priority is determined by
hardware, but variety of priority processing can be
performed by software, using an interrupt enable
bit and an interrupt disable flag.
For interrupt sources, vector addresses and interrupt
priority, refer to “Table 9.”
Table 9 Interrupt sources, vector addresses and interrupt priority
Interrupt source
Vector addresses (Note 1)
Priority
High-order
Low-order
Interrupt request generating conditions
Remarks
Reset (Note 2)
1
FFFD16
FFFC16
At reset input
Non-maskable
UART receive
2
FFFB16
FFFA16
At completion of UART data receive
Valid in UART mode
At detection of IN token
Valid in USB mode
At completion of UART transmit shift or
when transmit buffer is empty
Valid in UART mode
USB SETUP/OUT token
Reset/Suspend/Resume
At detection of SETUP/OUT token or
At detection of Reset/ Suspend/ Resume
Valid in USB mode
INT1 (Note 3)
At detection of either rising or falling edge
of INT1 input
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
USB IN token
UART transmit
3
FFF916
FFF816
INT0 (Note 4)
4
FFF716
FFF616
At detection of either rising or falling edge
of INT0 input
Timer X
5
FFF516
FFF416
At timer X underflow
Key-on wake-up
Timer 1
Timer 2
STP release timer underflow
FFF316
FFF216
At timer 1 underflow
7
FFF116
FFF016
At timer 2 underflow
At completion of transmit/receive shift
8
FFEF16
FFEE16
A/D conversion
BRK instruction
External interrupt (valid at falling)
6
Serial I/O2
CNTR0
At falling of conjunction of input logical
level for port P0 (at input)
At detection of either rising or falling edge
of CNTR0 input
External interrupt (active edge
selectable)
At completion of A/D conversion
9
FFED16
FFEC16
At BRK instruction execution
Note 1: Vector addressed contain internal jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3: The INT1 interrupt does not exist in the 36-pin and 32-pin version.
4: The INT0 interrupt does not exist in the 32-pin version.
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 45 of 55
Non-maskable software interrupt
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION SUPPLEMENT
Timing After Interrupt
instruction that is currently in execution.
Figure 52 shows a timing chart after an interrupt
occurs, and Figure 53 shows the time up to execution
of the interrupt processing routine.
The interrupt processing routine begins with the
machine cycle following the completion of the
φ
SYNC
RD
WR
Address bus
Data bus
PC
S, SPS
Not used
S-1, SPS S-2 , SPS
PCH PCL
BL
PS
BH
AL
AL, AH
AH
SYNC : CPU operation code fetch cycle
BL, BH : Vector address of each interrupt
AL, AH : Jump destination address of each interrupt
SPS : “0016” or “01 16”
Fig. 52 Timing chart after an interrupt occurs
Generation of interrupt request
Main routine
0 to 7 cycles
Start of interrupt processing
Waiting time for
post-processing
of pipeline
2 cycles
Stack push and
Vector fetch
5 cycles
7 to 14 cycles
(At performing 6.0 MHz, in double-speed mode,
1.17 µs to 2.34 µs)
Fig. 53 Time up to execution of the interrupt processing routine
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REJ09B0178-0300
page 46 of 55
Interrupt processing routine
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION SUPPLEMENT
A/D Converter
By repeating the above operations up to the lowestorder bit of the A/D conversion register, an analog
value converts into a digital value.
A/D conversion completes at 122 clock cycles (20.34
µs at f(X IN) = 6.0 MHz) after it is started, and the
result of the conversion is stored into the A/D
conversion register.
Concurrently with the completion of A/D conversion,
A/D conversion interrupt request occurs, so that
the AD conversion interrupt request bit is set to
“1.”
A/D conversion is started by setting AD conversion
completion bit to “0.” During A/D conversion, internal
operations are performed as follows.
1. After the start of A/D conversion, A/D conversion
register goes to “00 16 .”
2. The highest-order bit of A/D conversion register
is set to “1,” and the comparison voltage Vref is
input to the comparator. Then, Vref is compared
with analog input voltage V IN.
3. As a result of comparison, when Vref < VIN, the
highest-order bit of A/D conversion register becomes “1.” When Vref > V IN, the highest-order
bit becomes “0.”
Relative formula for a reference voltage V REF of A/D converter and Vref
When n = 0
Vref = 0
Vref = VREF ✕ n
1024
n : the value of A/D converter (decimal numeral)
When n = 1 to 1023
Table 10 Change of A/D conversion register during A/D conversion
Change of A/D conversion register
Value of comparison voltage (Vref)
At start of conversion
0
0
0
0
0
0
0
0
0
0
First comparison
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Second comparison
✽
Third comparison
✽
1
1
✽
2
••
•
After completion of
tenth comparison
VREF
2
VREF
2
VREF
2
±
VREF
4
VREF
±
4
••
•
✽
1
✽
2
✽
3
✽
4
✽
5
page 47 of 55
±
VREF
8
••
•
A result of A/D conversion
✽1–✽10: A result of the first to tenth comparison
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
0
✽
6
✽
7
✽
8
✽
9
✽
10
VREF
2
±
VREF
4
± •••
±
VREF
1024
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION SUPPLEMENT
Figures 54 shows A/D conversion equivalent circuit,
and Figure 55 shows A/D conversion timing chart.
VCC
(Note 1)
ANi (i=0 to 7: 42-pin version, 36-pin version
i=0 to 5: 32-pin version)
C2
1.5 pF(Typical)
R 1.5 kΩ(Typical)
SW1
(Note 2)
C1
12 pF(Typical)
(Note 1)
VSS
VSS
Typical voltage
generation circuit
Switch tree,
ladder resistor
Notes 1: This is a parasitic diode.
2: Only the selected analog input pin is turned on.
A/D control circuit
VSS
VREF
Fig. 54 A/D conversion equivalent circuit
XI N
Write signal for A/D control register
AD conversion completion bit
Sampling clock
Fig. 55 A/D conversion timing chart
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REJ09B0178-0300
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Chopper Amp.
122 XIN cycles
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION SUPPLEMENT
Stop mode
System enters the stop mode by executing the STP instruction. In the stop mode, the f(XIN) oscillation is
stopped, and the internal clock φ is stopped. Accordlingly, CPU and the peripheral devices are stopped.
(1) Stop mode state
Table 11 shows the state at stop mode.
Table 11 Stop mode state
Parameter
State
Parameter
State
Oscillation
Stop
Watchdog timer Stop
CPU
Stop
RAM
State retained
I/O port
State retained at STP instruction
execution
At selecting internal count source:
Stop
SFR
State retained (Timer 1 and
prescaler 12 excepted)
CPU register
State retained
• Accumulator
Timer
At selecting external count source:
Operating (only Timer X)
Stop
UART
A/D conversion Stop
At selecting internal synchronous
Serial I/O2
clock: Stop
• Index register X
• Index register Y
• Stack pointer
• Program counter
• Processor status register
At selecting external synchronous
clock: Operating
Stop (suspend state)
USB
(2) Stop mode release
Stop mode is released by reset input or interrupt occurrence. The interrupt sources which can be
used for return from stop mode are shown below.
•
•
•
•
•
•
•
INT 0
INT 1
CNTR 0
Timer (Timer X) when using external clock
Serial I/O2 when using external clock
Key-on wakeup
USB function (resume, reset)
When the above interrupt sources are used for return from stop mode, execute the STP instruction
after the following are set in order to enable the using interrupts.
➀ Clear the timer 1 interrupt enable bit to “0” (ICON1, bit 4)
➁ Clear the timer 2 interrupt enable bit to “0” (ICON1, bit 5)
➂ Clear the timer 1 interrupt request bit to “0” (IREQ1, bit 4)
➃ Clear the timer 2 interrupt request bit to “0” (IREQ1, bit 5)
➄ Clear the interupt request bit of the interrupt using for return to “0”
➅ Set the interupt enable bit of the interrupt using for return to “1”
➆ Clear the interrupt disable flag (I) to “0”
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REJ09B0178-0300
page 49 of 55
HARDWARE
7534 Group
FUNCTIONAL DESCRIPTION SUPPLEMENT
Wait mode
System enters the wait mode by executing the WIT instruction. In the wait mode, the oscillation is operating,
but the internal clock φ is stopped. Accordlingly, CPU is stopped, but the peripheral devices are operating.
(1) Wait mode state
Table 12 shows the state at wait mode.
Table 12 Wait mode state
Parameter
Oscillation
Stop
Parameter
Watchdog timer Operating
CPU
Stop
RAM
State retained
I/O port
State at WIT instruction execution
retained
SFR
State retained (Timer 1, timer 2 and
prescaler 12 excepted)
Timer
At selecting internal count source:
Operating
CPU register
State retained
State
State
• Accumulator
At selecting external count source:
Operating
Operating
• Index register X
• Index register Y
A/D conversion O p e r a t i n g ( C o n v e r s i o n i s
continued if the WIT instruction
is executed during conversion)
• Program counter
UART
Serial I/O2
• Stack pointer
• Processor status register
At selecting internal synchronous
clock: Operating
At selecting external synchronous
clock: Operating
Operating
USB
(2) Wait mode release
Wait mode is released by reset input or interrupt occurrence. In the wait mode, since the oscillation
is continued, the instruction is executed after the system is released from the wait mode. The
interrupt sources which can be used for return from wait mode are shown below.
•
•
•
•
•
•
•
•
•
INT 0
INT 1
CNTR0
Timer
Serial I/O2
A/D conversion
Key-on wakeup
USB function
UART
When the above interrupt sources are used for return from wait mode, execute the WIT instruction
after the following are set in order to enable the using interrupts.
➀ Clear the interupt request bit of the interrupt using for return to “0”
➁ Set the interupt enable bit of the interrupt using for return to “1”
➂ Clear the interrupt disable flag (I) to “0”
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REJ09B0178-0300
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HARDWARE
DESCRIPTION OF IMPROVED USB FUNCTION FOR 7534 GROUP/
DIFFERENCES AMONG 32-PIN, 36-PIN AND 42-PIN
7534 Group
DESCRIPTION OF IMPROVED USB FUNCTION
FOR 7534 GROUP
Table 13 Description of improved USB function for 7534 Group
Parameter
No.
1 Response at Control transfer
7532/7536 Group
Not deal with the host which performs the Control
transfer in parallel to plural device.
USB function can be used only at the condition of
CL = 150 pF to 350 pF.
2 D+/D- transceiver circuit
3 Power dissipation at Suspend
4 STALL in Status stage
5 6-bit decode of SYNC field
7534 Group
Connectable to the host which performs the Control transfer in parallel to plural device.
Deal with the following Low-Speed USB2.0 specification.
CL = 200 pF to 450 pF,
Trise and Tfall: 75 ns to 300 ns,
Tr/Tf: 80 % to 125 %,
Cross over Voltage: 1.3 V to 2.0 V.
Rating is Max. 300 µA not including the output cur- Rating is Max. 300 µA including the output current
rent of USBVREFOUT.
of USBVREFOUT, by low-power dissipation of D+/
D- input circuit and 3.3 V-regulator.
ACK is returned once to OUT (DATA0) to be valid STALL is set automaticcally by hardware when
in Status stage.
OUT (DATA0) is received in Status stage.
SYNC is detected only when 8-bit full code (8016) SYNC is detected only the low-order 6 bits even if
is complete.
the high-order 2 bits are corrupted.
DIFFERENCES AMONG 32-PIN, 36-PIN AND 42-PIN
The 7534 Group has three package types, and each of the number
of I/O ports are different. Accordingly, when the pins which have the
function except a port function are eliminated, be careful that the
functions are also eliminated.
Table 14 Differences among 32-pin, 36-pin and 42-pin
I/O port
42-pin SDIP
36-pin SSOP
32-pin LQFP
Port P1
P10–P16 (7-bit structure)
P10–P14 (5-bit structure)
P10–P14 (5-bit structure)
Port P2
P20–P27 (8-bit structure)
P20–P27 (8-bit structure)
P20–P25 (6-bit structure)
(A/D converter 8-channel)
(A/D converter 8-channel)
(A/D converter 6-channel)
P30–P37 (8-bit structure)
P30–P35, P37 (7-bit structure)
P30–P34 (5-bit structure)
(INT0, INT1 available)
(INT0 available)
(INT function not available)
P40, P41 (2-bit structure)
No port
No port
Port P3
Port P4
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REJ09B0178-0300
page 51 of 55
HARDWARE
7534 Group
DIFFERENCES AMONG 32-PIN, 36-PIN AND 42-PIN
Additionally, there are differences of SFR usage and functional definitions.
Table 15 Differences among 32-pin, 36-pin and 42-pin (SFR)
Register (Address)
36-pin SSOP
42-pin SDIP
32-pin LQFP
Bit 7 not available
Bits 5 to 7 not available
Bits 5 to 7 not available
All bits available
All bits available
Bits 6 and 7 not available
All bits available
Bit 6 not available
Bits 5 to 7 not available
Bits 2 to 7 not available
All bits not available
All bits not available
Pull-up control
Bit 6 definition:
Bit 6 definition:
Bits 6 and 7 not available
(1616)
“P35, P36 pull-up control”
“P35 pull-up control”
Bit 7 definition:
Bit 7 definition:
“P37 pull-up control”
“P37 pull-up control”
Port P1P3 control
Bit 0 definition:
Bit 0 definition:
(1716)
“P37/INT0 input level selection”
“P37/INT0 input level selection”
Bit 1 definition:
Bit 1 not available
Port P1/Direction
(0216/0316)
Port P2/Direction
(0416/0516)
Port P3/Direction
(0616/0716)
Port P4/Direction
(0816/0916)
Bits 0 and 1 not available
“P36/INT1 input level selection”
Bits 0 to 2
A/DControl
Bits 0 to 2
(3416)
“Input pins selected by setting these “Input pins selected by setting these
Bits 0 to 2
“Input pins selected by setting these
bits to 000 to 111”
bits to 000 to 111”
bits to 000 to 101”
Interrupt edge
Bit 0 definition
Bit 0 definition
Bits 0, 1 and 4 not available
selection
“INT0 interrupt edge selection”
“INT0 interrupt edge selection”
(3A16)
Bit 1 definition
Bits 1 and 4 not available
“INT1 interrupt edge selection”
Bit 4 definition
“Serial I/O1, INT1 interrupt selection”
Interrupt request
Bit 1 definition
(3C16)
“UART transmission, USB (except IN), “UART transmission, USB (except IN)” “UART transmission, USB (except IN)”
Bit 1 definition
INT1”
Bit 2 definition
Bit 2 definition
“INT0”
Bit 1 definition
Bit 2 not available
“INT0”
Bit 1 definition
Interrupt control
Bit 1 definition
(3E16)
“UART transmission, USB (except IN), “UART transmission, USB (except IN)” “UART transmission, USB (except IN)”
INT1”
Bit 2 definition
Bit 2 definition
“INT0”
“INT0”
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REJ09B0178-0300
page 52 of 55
Bit 1 definition
Bit 2 not available
HARDWARE
7534 Group
DESCRIPTION SUPPLEMENT FOR USE OF USB FUNCTION STABLY
DESCRIPTION SUPPLEMENT FOR USE OF USB FUNCTION STABLY
P27/AN7
VREF
RESET
CNVSS
Vcc
XIN
XOUT
VSS
1
36
2
35
3
34
4
33
5
6
7
8
9
10
11
12
13
14
15
M37534M4-XXXFP
M37534E8FP
P12/SCLK
P13/SDATA
P14/CNTR0
P20/AN0
P21/AN1
P22/AN2
P23/AN3
P24/AN4
P25/AN5
P26/AN6
32
31
30
29
28
27
26
25
24
23
22
16
21
17
20
18
19
P11/TXD/D+
P10/RXD/DP07
P06
P05
P04
P03
P02
P01
P00
USBVREFOUT
P37/INT0
P35(LED5)
P34(LED4)
P33(LED3)
P32(LED2)
P31(LED1)
P30(LED0)
1.5kΩ
Outline PRSP0036GA-A
➀ Connect a bypass capacitor to a device
as close as possible. For the capacitor,
a ceramic capacitor or an electrolytic
capacitor of 1.0 µF is recommended.
➁ Connect a capacitor to a device as
close as possible. For the capacitor,
a ceramic capacitor or an electrolytic
capacitor of 0.22 µF is recommended.
Reason of ➀ is to reduce the effect by switcing noise of microcomputer to the
analog circuit generating USBVREFOUT output. Use the bigger capacitor and
connect to device at the shortest distance.
Reason of ➁ is to prevent the instability of the USBVREFOUT output due to
external noise.
Fig. 56 Handling of VCC, USBVREFOUT pins of M37534M4-XXXFP, M37534E8FP
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 53 of 55
HARDWARE
7534 Group
DESCRIPTION SUPPLEMENT FOR USE OF USB FUNCTION STABLY
➁ Connect a capacitor to a device as
close as possible. For the capacitor,
a ceramic capacitor or an electrolytic
capacitor of 0.22 µF is recommended.
P07
P10/RXD/DP11/TXD/D+
P12/SCLK
P13/SDATA
P14/CNTR0
P20/AN0
P21/AN1
17
18
19
20
21
22
23
24
P06
P05
P04
P03
P02
P01
P00
USBVREFOUT
1.5kΩ
25
16
26
15
14
27
28
29
M37534M4-XXXGP
M37534E4GP
13
12
8
7
P22/AN2
P23/AN3
P24/AN4
P25/AN5
VREF
RESET
CNVSS
VCC
6
9
5
32
4
10
3
31
2
11
1
30
P34(LED4)
P33(LED3)
P32(LED2)
P31(LED1)
P30(LED0)
VSS
XOUT
XIN
Outline PLQP0032GB-A
➀ Connect a bypass capacitor to a device
as close as possible. For the capacitor,
a ceramic capacitor or an electrolytic
capacitor of 1.0 µF is recommended.
Reason of ➀ is to reduce the effect by switcing noise of microcomputer to the
analog circuit generating USBVREFOUT output. Use the bigger capacitor and
connect to device at the shortest distance.
Reason of ➁ is to prevent the instability of the USBVREFOUT output due to
external noise.
Fig. 57 Handling of VCC, USBVREFOUT pins of M37534M4-XXXGP, M37534E4GP
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 54 of 55
HARDWARE
7534 Group
1
42
2
41
3
40
4
39
5
38
6
37
7
8
9
10
11
12
13
14
15
16
17
M37534E8SP
M37534M4-XXXSP
M37534RSS
P14/CNTR0
P15
P16
P20/AN0
P21/AN1
NC
P22/AN2
P23/AN3
P24/AN4
P25/AN5
P26/AN6
P27/AN7
P40
P41
VREF
RESET
CNVSS
Vcc
XIN
XOUT
VSS
DESCRIPTION SUPPLEMENT FOR USE OF USB FUNCTION STABLY
36
35
34
33
32
31
30
29
28
27
26
18
25
19
24
20
23
21
22
P13/SDATA
P12/SCLK
P11/TXD/D+
P10/RXD/DP07
P06
P05
P04
P03
P02
P01
P00
USBVREFOUT
P37/INT0
P36(LED6)/INT1
P35(LED5)
P34(LED4)
P33(LED3)
P32(LED2)
P31(LED1)
P30(LED0)
Outline PRDP0042BA-A
➀ Connect a bypass capacitor to a device
as close as possible. For the capacitor,
a ceramic capacitor or an electrolytic
capacitor of 1.0 µF is recommended.
➁ Connect a capacitor to a device as
close as possible. For the capacitor,
a ceramic capacitor or an electrolytic
capacitor of 0.22 µF is recommended.
Reason of ➀ is to reduce the effect by switcing noise of microcomputer to the
analog circuit generating USBVREFOUT output. Use the bigger capacitor and
connect to device at the shortest distance.
Reason of ➁ is to prevent the instability of the USBVREFOUT output due to
external noise.
Fig. 58 Handling of VCC, USBVREFOUT pins of M37534E8SP, M37534M4-XXXSP, M37534RSS
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 55 of 55
1.5kΩ
THIS PAGE IS BLANK FOR REASONS OF LAYOUT.
CHAPTER 2
APPLICATION
2.1
2.2
2.3
2.4
2.5
2.6
I/O port
Timer
Serial I/O
USB
A/D converter
Reset
APPLICATION
7534 Group
2.1 I/O port
2.1 I/O port
This paragraph explains the registers setting method and the notes relevant to the I/O ports.
2.1.1 Memory map
000016
Port P0 (P0)
000116
Port P0 direction register (P0D)
000216
Port P1 (P1)
000316
Port P1 direction register (P1D)
000416
Port P2 (P2)
000516
Port P2 direction register (P2D)
000616
Port P3 (P3)
000716
Port P3 direction register (P3D)
000816
Port P4 (P4)
000916
Port P4 direction register (P4D)
Fig. 2.1.1 Memory map of registers relevant to I/O port
2.1.2 Relevant registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (Pi) (i = 0 to 4) [Address : 00 16, 0216, 04 16, 06 16, 0816]
B
Name
0 Port Pi 0
Function
●
In output mode
Write
Port latch
Read
●
In input mode
Write : Port latch
Read : Value of pins
1 Port Pi1
2 Port Pi2
At reset
R W
?
?
?
3 Port Pi3
?
4 Port Pi4
?
5 Port Pi5
?
6 Port Pi6
?
7 Port Pi7
?
Note: The following ports do not exist, so that the corresponding bits are not used.
• 42-pin version: Ports P1 7, P4 2–P4 7
• 36-pin version: Ports P1 5–P1 7, P3 6, P4 0–P4 7
• 32-pin version: Ports P1 5–P1 7, P2 6, P2 7, P3 5–P3 7, P4 0–P4 7
Fig. 2.1.2 Structure of Port Pi (i = 0 to 4)
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REJ09B0178-0300
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APPLICATION
7534 Group
2.1 I/O port
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 0 to 4) [Address : 01
B
1
2
3
4
5
6
7
0316, 05 16, 0716, 0916]
Function
Name
0 Port Pi direction register
16,
0 : Port Pi 0 input mode
1 : Port Pi 0 output mode
0 : Port Pi 1 input mode
1 : Port Pi 1 output mode
0 : Port Pi 2 input mode
1 : Port Pi 2 output mode
0 : Port Pi 3 input mode
1 : Port Pi 3 output mode
0 : Port Pi 4 input mode
1 : Port Pi 4 output mode
0 : Port Pi 5 input mode
1 : Port Pi 5 output mode
0 : Port Pi 6 input mode
1 : Port Pi 6 output mode
0 : Port Pi 7 input mode
1 : Port Pi 7 output mode
At reset
R W
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
Note: The following ports do not exist, so that the corresponding bits are not used.
• 42-pin version: Ports P1 7, P42–P4 7
• 36-pin version: Ports P1 5–P17, P36, P4 0–P4 7
• 32-pin version: Ports P1 5–P17, P26, P2 7, P3 5–P3 7, P4 0–P4 7
Fig. 2.1.3 Structure of Port Pi direction register (i = 0 to 4)
Pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register (PULL) [Address : 16 16]
Name
B
0 P00 pull-up control bit
1 P01 pull-up control bit
2 P02, P03 pull-up control bit
3 P04 – P07 pull-up control bit
4 P30 – P33 pull-up control bit
5 P34 pull-up control bit
6 P35, P36 pull-up control bit
(Note 2)
P3
7 pull-up control bit
7
(Note 3)
Function
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
Notes 1: Pins set to output are disconnected from the pull-up control.
2: • 36-pin version: P3 6 is not existed.
• 32-pin version: Not used.
3: 32-pin version: Not used.
Fig. 2.1.4 Structure of Pull-up control register
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 3 of 78
At reset
1
1
1
1
1
1
1
1
R W
APPLICATION
7534 Group
2.1 I/O port
Port P1P3 control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P1P3 control register (P1P3C) [Address : 17
B
Function
Name
0 P37/INT0 input level selection
bit (Note 1)
P3
6/INT 1 input level selection
1
bit (Note 2)
2 P10, P12,P1 3 input level
selection bit
16]
At reset
0 : CMOS level
1 : TTL level
0 : CMOS level
1 : TTL level
0 : CMOS level
1 : TTL level
R W
0
0
0
0
✕
4
0
✕
5
0
✕
6
0
✕
7
0
✕
3 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
Notes 1: For the 32-pin version, nothing is allocated for this bit.
This is a write disabled bit.
When this bit is read out, the value is “0”.
2: For the 32-pin and 36-pin versions, nothing is allocated for this bit.
This is a write disabled bit.
When this bit is read out, the value is “0”.
Fig. 2.1.5 Structure of P1P3 control register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A
Name
Function
0 INT 0 interrupt edge
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
B
selection bit (Note 1)
1 INT 1 interrupt edge
selection bit ( Note 2)
16]
2 Nothing is allocated for these bits. These are write disabled bits.
At reset
R W
0
0
0
✕
0
✕
When these bits are read out, the values are “0”.
3
4 Serial I/O1 or INT 1 interrupt
0 : Serial I/O1
1 : INT 1
0 : Timer X
5 Timer X or key-on wake up
1 : Key-on wake up
interrupt selection bit
Timer
2
or
serial
I/O2
interrupt
0 : Timer 2
6
selection bit
1 : Serial I/O2
CNTR
0 or AD converter
0 : CNTR 0
7
interrupt selection bit
1 : AD converter
selection bit
0
0
0
0
Notes 1: 32-pin version: Not used.
This is a write disabled bit. When this bit is read out, the value is “0”.
2: 36-pin and 32-pin version: Not used.
This is a write disabled bit. When this bit is read out, the value is “0”.
Fig. 2.1.6 Structure of Interrupt edge selection register
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 4 of 78
APPLICATION
7534 Group
2.1 I/O port
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address : 3C
B
Name
16]
Function
At reset
R W
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
5 Timer 2 or serial I/O2 interrupt 0 : No interrupt request issued
0
✽
6 CNTR 0 or AD converter
0
✽
0
✕
0
1
2
3
UART receive/USBIN token
interrupt request bit
UART transmit/USBSETUP/
OUT token/Reset/Suspend/
Resume/INT 1 interrupt
request bit (Note 1)
INT 0 interrupt request bit
(Note 2)
Timer X or key-on wake up
interrupt request bit
4 Timer 1 interrupt request bit
request bit
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
interrupt request bit
7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
✽: These bits can be cleared to “0” by program, but cannot be set.
Notes 1: 36-pin version and 32-pin version: INT1 interrupt does not exist.
2: 32-pin version: INT0 interrupt does not exist.
This is a write disabled bit. When this bit is read out, the value is “0”.
Fig. 2.1.7 Structure of Interrupt request register 1
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E
B
Name
0
UART receive/USBIN token
interrupt enable bit
UART transmit/USBSETUP/
OUT token/Reset/Suspend/
Resume/INT 1 interrupt enable
bit (Note 1)
INT 0 interrupt enable bit
(Note 2)
Timer X or key-on wake up
interrupt enable bit
1
2
3
4
5
6
7
16]
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
Timer 1 interrupt enable bit
1 : Interrupt enabled
Timer 2 or serial I/O2 interrupt 0 : Interrupt disabled
enable bit
1 : Interrupt enabled
0 : Interrupt disabled
CNTR 0 or AD converter
interrupt enable bit
1 : Interrupt enabled
Nothing is allocated for this bit. Do not write “1” to this bit.
When this bit is read out, the value is “0”.
At reset
0
0
0
0
0
0
0
0
Notes 1: 36-pin version and 32-pin version: INT 1 interrupt does not exist.
2: 32-pin version: INT 0 interrupt does not exist.
This is a write disabled bit. When this bit is read out, the value is “0”.
Fig. 2.1.8 Structure of Interrupt control register 1
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REJ09B0178-0300
page 5 of 78
R W
✕
APPLICATION
7534 Group
2.1 I/O port
2.1.3 Application example of key-on wake up
Outline: The built-in pull-up resistor is used.
Pull-up control register (address 16 16)
b7
b0
PULL
1 1 1
P00 – P03 pull-up on
Interrupt edge selection register (address 3A 16)
b7
b0
1
INTEDGE
Timer X or key-on wake up interrupt selection
: Key-on wake up selected
Interrupt control register 1 (address 3E 16)
b7
ICON1
b0
1
Timer X or key-on wake up interrupt: Enabled
Interrupt request register 1 (address 3C 16)
b7
IREQ1
b0
0
Timer X or key-on wake up interrupt request bit
Fig. 2.1.9 Relevant registers setting
7534 group
P03
P0i (i: 0 – 3)
P02
Key ON
P01
P00
Fig. 2.1.10 Application circuit example
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REJ09B0178-0300
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APPLICATION
7534 Group
2.1 I/O port
● ✕: This bit is not used here. Set it to “0” or “1” arbitrary.
RESET
Initialization
...
PULL
(address 16 16 )
XXXXX111 2
•P0 3 – P00 pull-up On
...
Power down procedure
...
INTEDGE (address 3A 16), bit5
IREQ1 (address 3C 16), bit3
ICON1 (address 3E 16), bit3
1
0
1
•Key-on wake up selected
•Clear the key-on wake up interrupt request bit to “0”
•Key-on wake up interrupt enabled
WIT
Key ON
Process continuation
.......
Interrupt process of
Key-on wake up
...
RTI
Fig. 2.1.11 Control procedure
2.1.4 Handling of unused pins
Table 2.1.1 Handling of unused pins
Pins/Ports name
Handling
P0, P1, P2, P3, P4 •Set to the input mode and connect each to Vcc or Vss through a resistor of 1 kΩ to
10 kΩ.
•Set to the output mode and open at “L” or “H” level.
VREF
XOUT
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
•Connect to Vss (GND).
•Open, only when using an external clock
page 7 of 78
APPLICATION
7534 Group
2.1 I/O port
2.1.5 Notes on input and output pins
(1) Notes in stand-by state
In stand-by state* 1 for low-power dissipation, do not make input levels of an input port and an I/O
port “undefined”.
Pull-up (connect the port to V CC ) or pull-down (connect the port to V SS ) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using a built-in pull-up resistor, note on varied current values:
• When setting as an input port : Fix its input level
• When setting as an output port : Prevent current from flowing out to external.
● Reason
The potential which is input to the input buffer in a microcomputer is unstable in the state that input
levels of a input port and an I/O port are “undefined”. This may cause power source current.
* 1 stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
(2) Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction*2, the value of the
unspecified bit may be changed.
● Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
• As for a bit which is set for an input port :
The pin state is read in the CPU, and is written to this bit after bit managing.
• As for a bit which is set for an output port :
The bit value of the port latch is read in the CPU, and is written to this bit after bit managing.
Note the following :
• Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
• As for a bit of the port latch which is set for an input port, its value may be changed even when
not specified with a bit managing instruction in case where the pin state differs from its port latch
contents.
* 2 bit managing instructions : SEB, and CLB instructions
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 8 of 78
APPLICATION
7534 Group
2.1 I/O port
2.1.6 Termination of unused pins
(1) Terminate unused pins
➀ Output ports : Open
➁ Input ports :
Connect each pin to V CC or VSS through each resistor of 1 kΩ to 10 kΩ.
Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. As for pins
whose potential affects to operation modes such as pins CNVSS, INT or others, select the VCC pin
or the VSS pin according to their operation mode.
➂ I/O ports :
• Set the I/O ports for the input mode and connect them to V CC or VSS through each resistor of
1 kΩ to 10 kΩ.
Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/
O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input
mode. With regard to an effects on the system, thoroughly perform system evaluation on the user
side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
(2) Termination remarks
➀ Input ports and I/O ports :
Do not open in the input mode.
● Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➁ and
➂ shown on the above.
➁ I/O ports :
When setting for the input mode, do not connect to V CC or V SS directly.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and V CC (or V SS ).
➂ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to V CC or V SS through
a resistor.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 9 of 78
APPLICATION
7534 Group
2.2 Timer
2.2 Timer
This paragraph explains the registers setting method and the notes relevant to the timers.
2.2.1 Memory map
002816
Prescaler 12 (PRE12)
002916
Timer 1 (T1)
002A16
Timer 2 (T2)
002B16
Timer X mode register (TM)
002C16
Prescaler X (PREX)
002D16
Timer X (TX)
002E16
Timer count source set register (TCSS)
003A16
Interrupt edge selection register (INTEDGE)
003C16
Interrupt request register 1 (IREQ1)
003E16
Interrupt control register 1 (ICON1)
Fig. 2.2.1 Memory map of registers relevant to timers
2.2.2 Relevant registers
Prescaler 12, Prescaler X
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 12 (PRE12) [Address : 28 16]
Prescaler X (PREX) [Address : 2C 16]
B
Function
0 •Set a count value of each prescaler.
•The value set in this register is written to both each prescaler
1 and the corresponding prescaler latch at the same time.
•When this register is read out, the count value of the corres2 ponding prescaler is read out.
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 2.2.2 Structure of Prescaler 12, Prescaler X
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REJ09B0178-0300
At reset
page 10 of 78
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APPLICATION
7534 Group
2.2 Timer
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1 (T1) [Address : 29 16]
B
Function
0 •Set a count value of timer 1.
•The value set in this register is written to both timer 1 and timer 1
1 latch at the same time.
•When this register is read out, the timer 1’s count value is read
2 out.
At reset
R W
1
0
0
3
0
4
0
5
0
6
0
7
0
Fig. 2.2.3 Structure of Timer 1
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2 (T2) [Address : 2A 16]
B
Function
0 •Set a count value of timer 2.
•The value set in this register is written to both timer 2 and timer 2
latch at the same time.
•When this register is read out, the timer 2’s count value is read
2 out.
1
0
0
0
3
0
4
0
5
0
6
0
7
0
Fig. 2.2.4 Structure of Timer 2
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
At reset
page 11 of 78
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APPLICATION
7534 Group
2.2 Timer
Timer X
b7 b6 b5 b4 b3 b2 b1 b0
Timer X (TX) [Address : 2D 16]
B
Function
0 •Set a count value of timer X.
•The value set in this register is written to both timer X and timer X
1 latch at the same time.
•When this register is read out, the timer X’s count value is read
2 out.
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 2.2.5 Structure of Timer X
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REJ09B0178-0300
At reset
page 12 of 78
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APPLICATION
7534 Group
2.2 Timer
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register (TM) [Address : 2B 16]
B
Function
Name
0 Timer X operating mode bits
1
At reset
b1 b0
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement
mode
R W
0
0
2 CNTR 0 active edge switch bit
The function depends on the
operating mode.
(Refer to Table 2.2.1)
0
3 Timer X count stop bit
0 : Count start
1 : Count stop
0
0
✕
5
0
✕
6
0
✕
7
0
✕
4 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
Fig. 2.2.6 Structure of Timer X mode register
Table 2.2.1 CNTR 0 active edge switch bit function
Timer X operation modes
Timer mode
CNTR 0 active edge switch bit (bit 2 of address 2B 16) contents
“0” CNTR 0 interrupt request occurrence: Falling edge
; No influence to timer count
“1” CNTR 0 interrupt request occurrence: Rising edge
; No influence to timer count
Pulse output mode
“0” Pulse output start: Beginning at “H” level
CNTR 0 interrupt request occurrence: Falling edge
“1” Pulse output start: Beginning at “L” level
CNTR 0 interrupt request occurrence: Rising edge
Event counter mode
“0” Timer X: Rising edge count
CNTR 0 interrupt request occurrence: Falling edge
“1” Timer X: Falling edge count
Pulse width measurement mode
CNTR 0 interrupt request occurrence: Rising edge
“0” Timer X: “H” level width measurement
CNTR 0 interrupt request occurrence: Falling edge
“1” Timer X: “L” level width measurement
CNTR 0 interrupt request occurrence: Rising edge
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 13 of 78
APPLICATION
7534 Group
2.2 Timer
Timer count source set register
b7 b6 b5 b4 b3 b2 b1 b0
Timer count source set register (TCSS) [Address : 2E
B
16]
Function
Name
0 Timer X count source
At reset
0 : f(X IN) / 16
1 : f(X IN) / 2
selection bit (Note)
R W
0
0
✕
2
0
✕
3
0
✕
4
0
✕
5
0
✕
6
0
✕
7
0
✕
1 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
Note: To switch the timer X count source selection bit, stop the timer X count
operation before do that.
Fig. 2.2.7 Structure of Timer count source set register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A
B
Function
Name
0 INT 0 interrupt edge
selection bit (Note 1)
1 INT 1 interrupt edge
selection bit ( Note 2)
16]
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
2 Nothing is allocated for these bits. These are write disabled bits.
At reset
R W
0
0
0
✕
0
✕
When these bits are read out, the values are “0”.
3
4 Serial I/O1 or INT 1 interrupt
0 : Serial I/O1
1 : INT 1
0
: Timer X
5 Timer X or key-on wake up
1 : Key-on wake up
interrupt selection bit
6 Timer 2 or serial I/O2 interrupt 0 : Timer 2
selection bit
1 : Serial I/O2
0 : CNTR 0
7 CNTR 0 or AD converter
interrupt selection bit
1 : AD converter
selection bit
0
0
0
0
Notes 1: 32-pin version: Not used.
This is a write disabled bit. When this bit is read out, the value is “0”.
2: 36-pin and 32-pin version: Not used.
This is a write disabled bit. When this bit is read out, the value is “0”.
Fig. 2.2.8 Structure of Interrupt edge selection register
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 14 of 78
APPLICATION
7534 Group
2.2 Timer
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address : 3C
B
Name
16]
Function
At reset
R W
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
5 Timer 2 or serial I/O2 interrupt 0 : No interrupt request issued
0
✽
6 CNTR 0 or AD converter
0
✽
0
✕
0
1
2
3
UART receive/USBIN token
interrupt request bit
UART transmit/USBSETUP/
OUT token/Reset/Suspend/
Resume/INT 1 interrupt
request bit (Note 1)
INT 0 interrupt request bit
(Note 2)
Timer X or key-on wake up
interrupt request bit
4 Timer 1 interrupt request bit
request bit
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
interrupt request bit
7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
✽: These bits can be cleared to “0” by program, but cannot be set.
Notes 1: 36-pin version and 32-pin version: INT1 interrupt does not exist.
2: 32-pin version: INT0 interrupt does not exist.
This is a write disabled bit. When this bit is read out, the value is “0”.
Fig. 2.2.9 Structure of Interrupt request register 1
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E
B
Name
0 UART receive/USBIN token
interrupt enable bit
1 UART transmit/USBSETUP/
OUT token/Reset/Suspend/
Resume/INT 1 interrupt enable
bit (Note 1)
2 INT 0 interrupt enable bit
(Note 2)
3 Timer X or key-on wake up
interrupt enable bit
4
5
6
7
16]
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
Timer 1 interrupt enable bit
1 : Interrupt enabled
Timer 2 or serial I/O2 interrupt 0 : Interrupt disabled
enable bit
1 : Interrupt enabled
0 : Interrupt disabled
CNTR 0 or AD converter
interrupt enable bit
1 : Interrupt enabled
Nothing is allocated for this bit. Do not write “1” to this bit.
When this bit is read out, the value is “0”.
At reset
0
0
0
0
0
0
0
Notes 1: 36-pin version and 32-pin version: INT 1 interrupt does not exist.
2: 32-pin version: INT 0 interrupt does not exist.
This is a write disabled bit. When this bit is read out, the value is “0”.
Fig. 2.2.10 Structure of Interrupt control register 1
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 15 of 78
R W
0
✕
APPLICATION
7534 Group
2.2 Timer
2.2.3 Timer application examples
(1) Basic functions and uses
[Function 1] Control of Event interval (Timer X, Timer 1, Timer 2)
When a certain time, by setting a count value to each timer, has passed, the timer interrupt request
occurs.
<Use>
•Generation of an output signal timing
•Generation of a wait time
[Function 2] Control of Cyclic operation (Timer X, Timer 1, Timer 2)
The value of the timer latch is automatically written to the corresponding timer each time the timer
underflows, and each timer interrupt request occurs in cycles.
<Use>
•Generation of cyclic interrupts
•Clock function (measurement of 100 ms); see Application example 1
•Control of a main routine cycle
[Function 3] Output of Rectangular waveform (Timer X)
The output level of the CNTR0 pin is inverted each time the timer underflows (in the pulse output
mode).
<Use>
•Piezoelectric buzzer output; see Application example 2
•Generation of the remote-control carrier waveforms
[Function 4] Count of External pulses (Timer X)
External pulses input to the CNTR0 pin are counted as the timer count source (in the event counter
mode).
<Use>
•Frequency measurement; see Application example 3
•Division of external pulses
•Generation of interrupts due to a cycle using external pulses as the count source; count of a
reel pulse
[Function 5] Measurement of External pulse width (Timer X)
The “H” or “L” level width of external pulses input to CNTR 0 pin is measured (in the pulse width
measurement mode).
<Use>
•Measurement of external pulse frequency (measurement of pulse width of FG pulse ✽ for a
motor); see Application example 4
•Measurement of external pulse duty (when the frequency is fixed)
FG pulse ✽: Pulse used for detecting the motor speed to control the motor speed.
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 16 of 78
APPLICATION
7534 Group
2.2 Timer
(2) Timer application example 1: Clock function (measurement of 100 ms)
Outline: The input clock is divided by the timer so that the clock can count up at 100 ms intervals.
Specifications: •The clock f(X IN) = 6.00 MHz is divided by the timer.
•The clock is counted up in the process routine of the timer X interrupt which occurs
at 100 ms intervals.
Figure 2.2.11 shows the timers connection and setting of division ratios; Figure 2.2.12 shows the
relevant registers setting; Figure 2.2.13 shows the control procedure.
Timer X count source
selection bit
Prescaler X
Timer X
Timer X interrupt
request bit
1/16
1/147
1/256
0 or 1
f(XIN) = 6.00 MHz
Dividing by 4 with software
1/10
100 ms
0 : No interrupt request issued
1 : Interrupt request issued
Fig. 2.2.11 Timers connection and setting of division ratios
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 17 of 78
1 second
APPLICATION
7534 Group
2.2 Timer
Timer count source set register (address 2E 16)
b7
b0
TCSS
0
Timer X count source : f(X IN)/16
Interrupt edge selection register (address 3A 16)
b7
b0
0
INTEDGE
Timer X or key-on wake up interrupt selection
: Timer X
Timer X mode register (address 2B 16)
b7
b0
1
TM
0 0
Timer X operating mode: Timer mode
Timer X count: Stop
Clear to “0” when starting count.
Prescaler X (address 2C 16)
b7
PREX
b0
146
Timer X (address 2D 16)
b7
Set “division ratio – 1”
b0
255
TX
Interrupt control register 1 (address 3E 16)
b7
b0
1
ICON1
Timer X interrupt: Enabled
Interrupt request register 1 (address 3C 16)
b7
IREQ1
b0
0
Timer X interrupt request
(becomes “1” at 100 ms intervals)
Fig. 2.2.12 Relevant registers setting
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REJ09B0178-0300
page 18 of 78
APPLICATION
7534 Group
2.2 Timer
RESET
Initialization
SEI
•All interrupts disabled
.....
0
INTEDGE (address 3A 16), bit5
(address 2B 16)
00001000 2
TM
0
(address 3C 16), bit3
IREQ1
1
(address 3E 16), bit3
ICON1
•Timer X interrupt selected
•Timer X operating mode : Timer mode
•Clear Timer X interrupt request bit
•Timer X interrupt enabled
.....
TCSS
PREX
TX
0
147 – 1
256 – 1
•Timer X count source : f(X IN/16)
•Set “division ratio – 1” to Prescaler X and Timer X
(address 2B 16), bit3
0
•Timer X count start
.....
(address 2E 16), bit0
(address 2C 16)
(address 2D 16)
TM
.....
CLI
•Interrupts enabled
Main processing
.....
<Procedure for completion of clock set>
(Note 1)
TM
PREX
TX
IREQ1
TM
(address 2B 16), bit3
(address 2C 16)
(address 2D 16)
(address 3C 16), bit3
(address 2B 16), bit3
•Reset Timer to restart count from 0 second after completion
of clock set
1
147– 1
256 – 1
0
0
Note 1: Perform procedure for completion of clock set only
when completing clock set.
Timer X interrupt process routine
CLT (Note 2)
CLD (Note 3)
Push registers to stack
Clock stop ?
Note 2: When using Index X mode flag (T)
Note 3: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
Y
•Judge whether clock stops
N
Clock count up (1/10 second to year)
Pop registers
RTI
Fig. 2.2.13 Control procedure
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•Clock count up
•Pop registers pushed to stack
APPLICATION
7534 Group
2.2 Timer
(3) Timer application example 2: Piezoelectric buzzer output
Outline: The rectangular waveform output function of the timer is applied for a piezoelectric buzzer
output.
Specifications: •The rectangular waveform, dividing the clock f(X IN) = 6.00 MHz into about 2 kHz
(1995 Hz), is output from the P1 4/CNTR 0 pin.
•The level of the P1 4/CNTR 0 pin is fixed to “H” while a piezoelectric buzzer output
stops.
Figure 2.2.14 shows a peripheral circuit example, and Figure 2.2.15 shows the timers connection and
setting of division ratios. Figures 2.2.16 shows the relevant registers setting, and Figure 2.2.17
shows the control procedure.
The “H” level is output while a piezoelectric buzzer output stops.
CNTR 0 output
P14/CNTR 0
PiPiPi.....
250 µs 250 µs
Set a division ratio so that the
underflow output period of the timer X
can be 250 µs.
7534 Group
Fig. 2.2.14 Peripheral circuit example
Timer X count source
selection bit
Prescaler X
f(XIN) = 6.00 MHz
1/16
1
Timer X
Fixed
1/94
1/2
Fig. 2.2.15 Timers connection and setting of division ratios
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REJ09B0178-0300
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CNTR 0
APPLICATION
7534 Group
2.2 Timer
Timer count source set register (address 2E 16)
b0
b7
0
TCSS
Timer X count source : f(X IN)/16
Timer X mode register (address 2B 16)
b7
b0
TM
1 0 0 1
Timer X operating mode: Pulse output mode
CNTR0 active edge switch: Output starting at “H” level
Timer X count: Stop
Clear to “0” when starting count.
Timer X (address 2D 16)
b7
b0
93
TX
Set “division ratio – 1”
Prescaler X (address 2C 16)
b7
b0
0
PREX
Interrupt control register 1 (address 3E 16)
b7
ICON1
b0
0
Timer X interrupt: Disabled
Fig. 2.2.16 Relevant registers setting
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REJ09B0178-0300
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APPLICATION
7534 Group
2.2 Timer
RESET
Initialization
.....
● ✕: This bit is not used here. Set it to “0” or “1” arbitrary.
P1
P1D
1
XXX1XXXX 2
(address 2E 16), bit0
(address 3E 16), bit3
(address 2B 16)
(address 2D 16)
(address 2C 16)
0
0
00001001 2
94 – 1
1–1
.....
(address 02 16), bit4
(address 03 16)
TCSS
ICON1
TM
TX
PREX
•Timer X count source : f(X IN)/16
•Timer X interrupt disabled
•Stop CNTR 0 output; Stop piezoelectric buzzer output
•Set “division ratio – 1” to Timer X and Prescaler X
.....
Main processing
.....
Output unit
Yes
•Process piezoelectric buzzer request, generated during
main processing, in output unit
Piezoelectric buzzer request ?
No
TM (address 2B 16), bit3
TX (address 2D 16)
1
94 – 1
TM (address 2B 16), bit3
0
Start piezoelectric buzzer output
Stop piezoelectric buzzer output
Fig. 2.2.17 Control procedure
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REJ09B0178-0300
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APPLICATION
7534 Group
2.2 Timer
(4) Timer application example 3: Frequency measurement
Outline: The following two values are compared to judge whether the frequency is within a valid
range.
•A value by counting pulses input to P1 4/CNTR 0 pin with the timer.
•A reference value
Specifications: •The pulse is input to the P1 4/CNTR 0 pin and counted by the timer X.
•A count value is read out at about 2 ms intervals, the timer 1 interrupt interval.
When the count value is 28 to 40, it is judged that the input pulse is valid.
•Because the timer is a down-counter, the count value is compared with 227 to 215
(Note).
Note: 227 – 215 = 255 (initial value of counter) – 28 to 40 (the number of valid count)
Figure 2.2.18 shows the judgment method of valid/invalid of input pulses; Figure 2.2.19 shows the
relevant registers setting; Figure 2.2.20 shows the control procedure.
Input pulse
•••••
•••••
71.4 µs or more
(14 kHz or less)
71.4 µs
(14 kHz)
Invalid
50 µs
(20 kHz)
Valid
2 ms = 28 counts
71.4 µs
Fig. 2.2.18 Judgment method of valid/invalid of input pulses
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REJ09B0178-0300
page 23 of 78
•••••
50 µs or less
(20 kHz or more)
Invalid
2 ms
50 µs
= 40 counts
APPLICATION
7534 Group
2.2 Timer
Interrupt edge selection register (address 3A 16)
b7
INTEDGE
b0
0
Timer X or key-on wake up interrupt selection
: Timer X
Timer X mode register (address 2B 16)
b7
b0
TM
1 1 1 0
Timer X operating mode: Event counter mode
CNTR0 active edge switch: Falling edge count
Timer X count: Stop
Clear to “0” when starting count
Prescaler 12 (address 28 16)
b7
PRE12
b0
93
Timer 1 (address 29 16)
b7
b0
7
T1
Set “division ratio – 1”
Prescaler X (address 2C 16)
b7
PREX
b0
0
Timer X (address 2D 16)
b7
TX
b0
Set 255 just before counting pulses
(After a certain time has passed, the number of input
pulses is decreased from this value.)
255
Interrupt control register 1 (address 3E 16)
b7
b0
1 0
ICON1
Timer X interrupt: Disabled
Timer 1 interrupt: Enabled
Interrupt request register 1 (address 3C 16)
b7
IREQ1
b0
0
Judgment of Timer X interrupt
request bit
( “1” of this bit when reading the
count value indicates the 256 or
more pulses input in the condition
of Timer X = 255)
Fig. 2.2.19 Relevant registers setting
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REJ09B0178-0300
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APPLICATION
7534 Group
2.2 Timer
RESET
● ✕: This bit is not used here. Set it to “0” or “1” arbitrary.
Initialization
SEI
•All interrupts disabled
.....
INTEDGE
TM
PRE12
T1
PREX
TX
ICON1
•Timer X interrupt selected
•Timer X operating mode : Event counter mode
(Count a falling edge of pulses input from CNTR 0 pin.)
•Set division ratio so that Timer 1 interrupt will occur at
2 ms intervals.
(address 2B 16), bit3
•Timer X count start
.....
(address 3A 16), bit5
0
00001110 2
(address 2B 16)
94 – 1
(address 28 16)
8–1
(address 29 16)
1–1
(address 2C 16)
256 – 1
(address 2D 16)
0XX10XXX 2
(address 3E 16)
TM
0
•Timer 1 interrupt enabled
•Timer X interrupt disabled
.....
•Interrupts enabled
CLI
Timer 1 interrupt process routine
CLT (Note 1)
CLD (Note 2)
Push registers to stack
Note 1: When using Index X mode flag (T)
Note 2: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
1
IREQ1(address 3C 16), bit3 ?
•Process as out of range when the count value is 256 or more
0
TX (address 2D 16)
(A)
•Read the count value
•Store the count value into Accumulator (A)
In range
•Compare the read value with
reference value
•Store the comparison result to
flag Fpulse
214 < (A) < 228
Out of range
Fpulse
TX
IREQ1
0
(address 2D 16)
(address 3C 16), bit3
Fpulse
256 – 1
0
•Initialize the counter value
•Clear Timer X interrupt request bit
Process judgment result
Pop registers
RTI
Fig. 2.2.20 Control procedure
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1
•Pop registers pushed to stack
APPLICATION
7534 Group
2.2 Timer
(5) Timer application example 4: Measurement of FG pulse width for motor
Outline: The timer X counts the “H” level width of the pulses input to the P1 4 /CNTR 0 pin. An
underflow is detected by the timer X interrupt and an end of the input pulse “H” level is
detected by the CNTR 0 interrupt.
Specifications: •The timer X counts the “H” level width of the FG pulse input to the P14/CNTR 0 pin.
<Example>
When the clock frequency is 6.00 MHz, the count source is 2.7 µs, which is obtained by dividing
the clock frequency by 16. Measurement can be made up to 174 ms in the range of FFFF 16 to
0000 16.
Figure 2.2.21 shows the timers connection and setting of division ratio; Figure 2.2.22 shows the
relevant registers setting; Figure 2.2.23 shows the control procedure.
Timer X count source
selection bit
f(XIN) = 6.00 MHz
1/16
Prescaler X
Timer X
Timer X interrupt
request bit
1/256
1/256
0 or 1
174 ms
0 : No interrupt request issued
1 : Interrupt request issued
Fig. 2.2.21 Timers connection and setting of division ratios
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REJ09B0178-0300
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APPLICATION
7534 Group
2.2 Timer
Interrupt edge selection register (address 3A 16)
b7
INTEDGE
b0
0
0
Timer X or key-on wake up interrupt selection
: Timer X
CNTR 0 or AD converter interrupt source selection
: CNTR 0
Timer X mode register (address 2B 16)
b7
b0
1 0 1 1
TM
Timer X operating mode: Pulse width measurement mode
CNTR 0 active edge switch: “H” level width measurement
Timer X count: Stop
Clear to “0” when starting count
Prescaler X (address 2C 16)
b7
b0
PREX
255
Timer X (address 2D 16)
b7
Set “division ratio – 1”
b0
TX
255
Interrupt control register 1 (address 3E 16)
b7
ICON1
b0
1
1
Timer X interrupt: Enabled
CNTR 0 interrupt: Enabled
Interrupt request register 1 (address 3C 16)
b7
IREQ1
b0
0
0
Timer X interrupt request
(Set to “1” automatically when Timer X underflows)
CNTR 0 interrupt request
Fig. 2.2.22 Relevant registers setting
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REJ09B0178-0300
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APPLICATION
7534 Group
2.2 Timer
RESET
Initialization
SEI
•All interrupts disabled
.....
INTEDGE (address 3A 16), bit5
0
, bit7
0
TM
(address 2B 16)
00001011 2
PREX
(address 2C 16)
256 – 1
TX
(address 2D 16)
256 – 1
IREQ1
(address 3C 16), bit3
0
, bit6
0
ICON1
(address 3E 16), bit3
1
, bit6
1
•Timer X or key-on wake up interrupt selection : Timer X
•CNTR0 or AD converter interrupt source selection : CNTR 0
•Timer X operating mode : Pulse width measurement mode
(Measure “H” level of pulses input from CNTR 0 pin.)
•Set division ratio so that Timer X interrupt will occur at
174 ms intervals.
•Clear Timer X interrupt request bit
•Clear CNTR 0 interrupt request bit
•Timer X interrupt enabled
•CNTR0 interrupt enabled
.....
(address 2B 16), bit3
TM
0
•Timer X count start
.....
•Interrupts enabled
CLI
Timer X interrupt process routine
•Error occurs
Process errors
RTI
CNTR0 interrupt process routine
CLT (Note 1)
CLD (Note 2)
Push registers to stack
(A)
Low-order 8-bit result of
pulse width measurement
(A)
High-order 8-bit result of
pulse width measurement
PREX (address 2C 16)
TX
(address 2D 16)
Pop registers
RTI
Fig. 2.2.23 Control procedure
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REJ09B0178-0300
page 28 of 78
PREX
Inverted (A)
Note 1: When using Index X mode flag (T)
Note 2: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
•Read the count value and store it to RAM
TX
Inverted (A)
256 – 1
256 – 1
•Set division ratio so that Timer X interrupt will occur at
174 ms intervals.
•Pop registers pushed to stack
APPLICATION
7534 Group
2.3 Serial I/O
2.3 Serial I/O
This paragraph explains the registers setting method and the notes relevant to the serial I/O.
2.3.1 Memory map
001816
Transmit/Receive buffer register (TB/RB)
001916
UART status register (UARTSTS)
001A16
Serial I/O1 control register (SIO1CON)
001B16
UART control register (UARTCON)
001C16
Baud rate generator (BRG)
003016
Serial I/O2 control register (SIO2CON)
003116
Serial I/O2 register (SIO2)
003A16
Interrupt edge selection register (INTEDGE)
003C16
Interrupt request register 1 (IREQ1)
003E16
Interrupt control register 1 (ICON1)
Fig. 2.3.1 Memory map of registers relevant to serial I/O
2.3.2 Relevant registers
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB) [Address : 18 16]
B
Function
0 The transmission data is written to or the receive data is read out
At reset
?
from this buffer register.
1 • At writing: A data is written to the transmit buffer register.
?
• At reading: The contents of the receive buffer register are read
out.
2
?
3
?
4
?
5
?
6
?
7
?
Note: The contents of transmit buffer register cannot be read out.
The data cannot be written to the receive buffer register.
Fig. 2.3.2 Structure of Transmit/Receive buffer register
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REJ09B0178-0300
page 29 of 78
R W
APPLICATION
7534 Group
2.3 Serial I/O
UART status register
b7 b6 b5 b4 b3 b2 b1 b0
UART status register (UARTSTS) [Address : 19 16]
B
Function
Name
0 Transmit buffer empty flag
0 : Buffer full
1 : Buffer empty
0 : Buffer empty
1 : Buffer full
0 : Transmit shift in progress
1 : Transmit shift completed
At reset
R W
1
✕
0
✕
0
✕
3 Overrun error flag (OE)
0
✕
4
0
✕
0
✕
0
✕
1
✕
(TBE)
1 Receive buffer full flag (RBF)
2 Transmit shift register shift
completion flag (TSC)
5
6
7
0 : No error
1 : Overrun error
0 : No error
Parity error flag (PE)
1 : Parity error
0 : No error
Framing error flag (FE)
1 : Framing error
0 : (OE) ∪ (PE) ∪ (FE) = 0
Summing error flag (SE)
1 : (OE) ∪ (PE) ∪ (FE) = 1
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “1”.
Fig. 2.3.3 Structure of UART status register
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register (SIO1CON) [Address : 1A
B
0
1
2
3
Function
Name
0 : f(X IN)
BRG count source
1 : f(X IN)/4
selection bit (CSS)
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “1”.
0 : Continuous transmit invalid
Continuous transmit valid bit
1 : Continuous transmit valid
Transmit interrupt
0 : Interrupt when transmit buffer
has emptied
source selection bit (TIC)
1 : Interrupt when transmit shift
operation is completed
4 Transmit enable bit (TE)
5 Receive enable bit (RE)
6 Serial I/O1 enable bit
(SIOE)
7
Fig. 2.3.4 Structure of Serial I/O1 control register
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16]
page 30 of 78
At reset
0
1
0
0
0 : Transmit disabled
1 : Transmit enabled
0 : Receive disabled
1 : Receive enabled
0
b7 b6
0
0
0
1
1
0 : I/O port
1 : Not available
0 : UART mode
1 : USB mode
R W
0
0
✕
APPLICATION
7534 Group
2.3 Serial I/O
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register (UARTCON) [Address : 1B 16]
B
0
1
2
3
4
Function
Name
Character length
selection bit (CHAS)
Parity enable bit
(PARE)
Parity selection bit
(PARS)
Stop bit length selection
bit (STPS)
P11/TxD P-channel
output disable bit
(POFF)
0 : 8 bits
1 : 7 bits
0 : Parity checking disabled
1 : Parity checking enabled
0 : Even parity
1 : Odd parity
0 : 1 stop bit
1 : 2 stop bits
In output mode
0 : CMOS output
1 : N-channel open-drain
output
At reset
R W
0
0
0
0
0
1
✕
6
1
✕
7
1
✕
5 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “1”.
Fig. 2.3.5 Structure of UART control register
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator (BRG) [Address : 1C 16]
B
At reset
0 Set a count value of baud rate generator.
?
1
?
2
?
3
?
4
?
5
?
6
?
7
?
Fig. 2.3.6 Structure of Baud rate generator
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Function
page 31 of 78
R W
APPLICATION
7534 Group
2.3 Serial I/O
Serial I/O2 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register (SIO2CON) [Address : 30
B
Function
Name
0 Internal synchronous
clock selection bits
1
2
16]
b2 b1 b0
0
0
0
0
1
1
0
0
1
1
1
1
0 : f(X IN)/8
1 : f(X IN)/16
0 : f(X IN)/32
1 : f(X IN)/64
0 : f(X IN)/128
1 : f(X IN)/256
0
0
0
4
0
6
7
R W
0
3 SDATA pin selection bit
5
0 : I/O port / S DATA input
(Note)
1 : SDATA output
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
Transfer direction selection bit 0 : LSB first
1 : MSB first
0 : External clock (S CLK is input)
SCLK pin selection bit
1 : Internal clock (S CLK is output)
Transmit / receive shift
0 : shift in progress
completion flag
1 : shift completed
At reset
✕
0
0
✕
0
Note: When using it as a S DATA input, set the port P1 3 direction register bit to “0”.
Fig. 2.3.7 Structure of Serial I/O2 control register
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 register (SIO2) [Address : 31 16]
B
Function
0 A shift register for serial transmission and reception.
1
• At transmitting : Set a transmission data.
• At receiving : A reception data is stored.
?
?
2
?
3
?
4
?
5
?
6
?
7
?
Fig. 2.3.8 Structure of Serial I/O2 register
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
At reset
page 32 of 78
R W
APPLICATION
7534 Group
2.3 Serial I/O
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A
B
Function
Name
0 INT 0 interrupt edge
selection bit (Note 1)
1 INT 1 interrupt edge
selection bit ( Note 2)
16]
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
2 Nothing is allocated for these bits. These are write disabled bits.
At reset
R W
0
0
0
✕
0
✕
When these bits are read out, the values are “0”.
3
4 Serial I/O1 or INT 1 interrupt
0 : Serial I/O1
1 : INT 1
0 : Timer X
5 Timer X or key-on wake up
1 : Key-on wake up
interrupt selection bit
Timer
2
or
serial
I/O2
interrupt
0 : Timer 2
6
selection bit
1 : Serial I/O2
CNTR
0 or AD converter
0 : CNTR 0
7
interrupt selection bit
1 : AD converter
selection bit
0
0
0
0
Notes 1: 32-pin version: Not used.
This is a write disabled bit. When this bit is read out, the value is “0”.
2: 36-pin and 32-pin version: Not used.
This is a write disabled bit. When this bit is read out, the value is “0”.
Fig. 2.3.9 Structure of Interrupt edge selection register
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address : 3C
B
Name
16]
Function
At reset
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
5 Timer 2 or serial I/O2 interrupt 0 : No interrupt request issued
0
✽
6 CNTR 0 or AD converter
0
✽
0
✕
0
1
2
3
4 Timer 1 interrupt request bit
request bit
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
interrupt request bit
7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
✽: These bits can be cleared to “0” by program, but cannot be set.
Notes 1: 36-pin version and 32-pin version: INT1 interrupt does not exist.
2: 32-pin version: INT0 interrupt does not exist.
This is a write disabled bit. When this bit is read out, the value is “0”.
Fig. 2.3.10 Structure of Interrupt request register 1
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
R W
0 : No interrupt request issued
1 : Interrupt request issued
UART receive/USBIN token
interrupt request bit
UART transmit/USBSETUP/
OUT token/Reset/Suspend/
Resume/INT 1 interrupt
request bit (Note 1)
INT 0 interrupt request bit
(Note 2)
Timer X or key-on wake up
interrupt request bit
page 33 of 78
APPLICATION
7534 Group
2.3 Serial I/O
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E
B
Name
0
UART receive/USBIN token
interrupt enable bit
UART transmit/USBSETUP/
OUT token/Reset/Suspend/
Resume/INT 1 interrupt enable
bit (Note 1)
INT 0 interrupt enable bit
(Note 2)
Timer X or key-on wake up
interrupt enable bit
1
2
3
4
5
6
7
16]
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
Timer 1 interrupt enable bit
1 : Interrupt enabled
Timer 2 or serial I/O2 interrupt 0 : Interrupt disabled
enable bit
1 : Interrupt enabled
0 : Interrupt disabled
CNTR 0 or AD converter
interrupt enable bit
1 : Interrupt enabled
Nothing is allocated for this bit. Do not write “1” to this bit.
When this bit is read out, the value is “0”.
At reset
0
0
0
0
0
0
0
0
Notes 1: 36-pin version and 32-pin version: INT 1 interrupt does not exist.
2: 32-pin version: INT 0 interrupt does not exist.
This is a write disabled bit. When this bit is read out, the value is “0”.
Fig. 2.3.11 Structure of Interrupt control register 1
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REJ09B0178-0300
page 34 of 78
R W
✕
APPLICATION
7534 Group
2.3 Serial I/O
2.3.3 Serial I/O connection examples
(1) Control of peripheral IC equipped with CS pin
Figure 2.3.12 shows connection examples with a peripheral IC equipped with the CS pin.
Each case uses the clock synchronous serial I/O mode.
(1) Only transmission
(2) Transmission and Reception
Port
CS
Port
CS
SCLK
CLK
SCLK
CLK
SDATA
7534 Group
SDATA
DATA
7534 Group
Peripheral IC
(OSD controller, etc.)
IN
OUT
Peripheral IC ]
(E 2PROM, etc.)
(3) Connection of plural IC
Port
CS
SCLK
CLK
SDATA
Port
7534 Group
IN
OUT
Peripheral IC1
]
✽ : Use the peripheral IC of which OUT pin has an
N-channel open-drain output structure and which
enters a high-impedance state while receiving
data.
Note: “Port” means an output port controlled by
software.
CS
CLK
IN
OUT
Peripheral IC2
]
Fig. 2.3.12 Serial I/O connection examples (1)
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APPLICATION
7534 Group
2.3 Serial I/O
(2) Connection with microcomputer
Figure 2.3.13 shows connection examples with another microcomputer.
(1) Selecting internal clock
S CLK
SDATA
CLK
IN
(2) Selecting external clock
SCLK
SDATA
OUT
7534 Group
Microcomputer
(3) In UART using serial I/O1
TXD
RXD
RXD
TXD
7534 Group
Microcomputer
Fig. 2.3.13 Serial I/O connection examples (2)
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CLK
IN
OUT
7534 Group
Microcomputer
APPLICATION
7534 Group
2.3 Serial I/O
2.3.4 Serial I/O transfer data format
The clock synchronous or the clock asynchronous (UART) can be selected as the serial I/O.
Figure 2.3.14 shows the serial I/O transfer data format.
1ST-8DATA-1SP
ST
LSB
MSB
SP
1ST-7DATA-1SP
ST
LSB
MSB
SP
1ST-8DATA-1PAR-1SP
ST
LSB
MSB
PAR
PAR
SP
MSB
2SP
SP
1ST-7DATA-1PAR-1SP
ST
Serial I/O1
UART
LSB
MSB
1ST-8DATA-2SP
ST
LSB
1ST-7DATA-2SP
ST
LSB
MSB
2SP
1ST-8DATA-1PAR-2SP
ST
LSB
MSB
PAR
PAR
2SP
1ST-7DATA-1PAR-2SP
ST
Serial I/O2
Clock
synchronous
Serial I/O
LSB first
MSB first
Fig. 2.3.14 Serial I/O transfer data format
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LSB
MSB
ST : Start bit
SP : Stop bit
PAR : Parity bit
2SP
APPLICATION
7534 Group
2.3 Serial I/O
2.3.5 Serial I/O application examples
(1) Communication using clock synchronous serial I/O (transmit/receive)
Outline : 2-byte data is transmitted and received, using the clock synchronous serial I/O. Port P00
is used for communication control and outputs the quasi-S RDY signal.
The following explain an example using the serial I/O2. Figure 2.3.15 shows a connection diagram,
and Figure 2.3.16 shows a timing chart.
Transmission side
Reception side
P37/INT0
P00
SCLK
SCLK
SDATA
SDATA
7534 Group
7534 Group
Fig. 2.3.15 Connection diagram
Specifications : •The Serial I/O2, clock synchronous serial I/O, is used.
•Synchronous clock frequency : 94 kHz; f(X IN) = 6 MHz divided by 64
•Transfer direction : LSB first
•The reception side outputs the quasi-SRDY signal at 2 ms intervals which the timer
generates, and 2-byte data is transferred from the transmission side to the reception
side.
SRDY
....
....
SCLK
SDATA
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
2 ms
Fig. 2.3.16 Timing chart
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D0 D1
....
APPLICATION
7534 Group
2.3 Serial I/O
Figures 2.3.17 and 2.3.19 show the registers setting relevant to the serial I/O2 and Figure 2.3.18
shows the transmission data setting of the serial I/O2.
Serial I/O2 control register (address 30 16)
b0
b7
SIO2CON
1 0
1 0 1 1
Internal synchronous clock : f(X IN)/64
SDATA pin : S DATA output
LSB first
Internal clock
Interrupt edge selection register (address 3A 16)
b0
b7
INTEDGE
1
0
INT0 interrupt edge : Falling edge active
Timer 2 or serial I/O2 interrupt selection : Serial I/O2
Interrupt control register 1 (address 3E 16)
b0
b7
ICON1
0
0
INT0 interrupt : Disabled
Serial I/O2 interrupt : Disabled
Interrupt request register 1 (address 3C 16)
b7
IREQ1
b0
0
0
INT0 interrupt request
Serial I/O2 interrupt request
Confirm transmission completion of one-byte unit
using this bit.
“1” : Shift of transmission completed
Fig. 2.3.17 Registers setting relevant to transmission side
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APPLICATION
7534 Group
2.3 Serial I/O
Serial I/O2 register (address 31 16)
b7
b0
Set transmission data
After confirming completion of the preceding
transmission, bit 5 of the interrupt request register 1 = “1”;
write data.
SIO2
Fig. 2.3.18 Transmission data setting of serial I/O2
Serial I/O2 control register (address 30 16)
b0
b7
SIO2CON
0 0
0 0 1 1
Internal synchronous clock : f(X IN)/64
SDATA pin : Input port/S DATA input
LSB first
External clock
Transmit/receive shift completion flag
Fig. 2.3.19 Registers setting relevant to reception side
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APPLICATION
7534 Group
2.3 Serial I/O
Figure 2.3.20 shows a control procedure of transmission side, and Figure 2.3.21 shows a control
procedure of reception side.
RESET
● ✕: This bit is not used here. Set it to “0” or “1” arbitrary.
Note: When the internal clock is selected and the direction
register of P1 3/SDATA pin is set to the input mode,
the SDATA pin is in a high impedance state
after the data transfer is completed.
Initialization
...
P1D
SIO2CON
INTEDGE
ICON1
(Note)
XXXX11XX 2
01001011 2
X1XXXXX0 2
0X0XX0XX 2
(address 03 16)
(address 30 16)
(address 3A 16)
(address 3E 16)
...
•Serial I/O2 setting
•INT 0 falling, Serial I/O2 selected
•INT 0 interrupt, serial I/O2 interrupt disabled
IREQ1 (address 3C 16), bit2 ?
0
•Detection of INT 0 falling edge
1
IREQ1 (address 3C 16), bit2
0
IREQ1 (address 3C 16), bit5
0
•Transmission data write
(One-byte transmission starts.)
The first byte of
transmission data
SIO2 (address 31 16)
0
IREQ1 (address 3C 16), bit5 ?
•Judgment of completion of one-byte
transmission
1
IREQ1 (address 3C 16), bit5
0
•Transmission data write
(One-byte transmission starts.)
The second byte of
transmission data
SIO2 (address 31 16)
0
IREQ1 (address 3C 16), bit5 ?
1
Fig. 2.3.20 Control procedure of transmission side
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•Judgment of completion of one-byte
transmission
APPLICATION
7534 Group
2.3 Serial I/O
RESET
● ✕: This bit is not used here. Set it to “0” or “1” arbitrary.
Initialization
...
P0D
P0
SIO2CON
P1D
1
(address 01 16), bit0
1
(address 00 16), bit0
(address 30 16)
00000011 2
(address 03 16)
XXXX00XX 2
•Quasi-S RDY signal “H”
•Serial I/O2 setting
...
N
2 ms pass ?
•Generation of a 2 ms interval using Timer
Y
P0 (address 00 16), bit0
0
P0 (address 00 16), bit0
1
•Quasi-S RDY signal output
Dummy data
SIO2 (address 31 16)
•Transmit/receive shift completion flag cleared
0
SIO2CON (address 30 16), bit7 ?
•Judgment of completion of one-byte reception
1
Wait for half cycle of clock
Read out received data from SIO2
SIO2 (address 31 16)
SIO2CON (address 30 16), bit7 ?
1
Wait for half cycle of shift clock
Read out received data from SIO2
Fig. 2.3.21 Control procedure of reception side
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•Transmit/receive shift completion flag cleared
Dummy data
0
•Judgment of completion of one-byte reception
APPLICATION
7534 Group
2.3 Serial I/O
(2) Communication using asynchronous serial I/O, UART (transmit/receive)
Outline : 2-byte data is transmitted and received, using the clock asynchronous serial I/O. Port P00
is used for communication control.
Figure 2.3.22 shows a connection diagram, and Figure 2.3.23 shows a timing chart.
Transmission side
Reception side
P00
P00
TxD
R XD
7534 Group
7534 Group
Fig. 2.3.22 Connection diagram
Specifications : •The Serial I/O1, asynchronous serial I/O, is used.
•Transfer bit rate : 9600 bps; f(X IN) = 4.9152 MHz divided by 512
•Communication control using port P00; Port P00 output level is controlled by software.
•2-byte data is transferred from the transmission side to the reception side at 10 ms
intervals which the timer generates
P00
TXD
•••••
ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2) ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2)
10 ms
Fig. 2.3.23 Timing chart
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ST D0
•••••
APPLICATION
7534 Group
2.3 Serial I/O
Table 2.3.1 shows a setting example of the baud rate generator (BRG) and transfer bit rate values;
Figure 2.3.24 shows the registers setting relevant to transmission side; Figure 2.3.25 shows the
registers setting relevant to reception side
Table 2.3.1 Setting example of baud rate generator (BRG) and transfer bit rate values
BRG count source
BRG set value
(Note 1)
Transfer bit rate (bps) (Note 2)
At f(X IN) = 4.9152 MHz
At f(X IN) = 6 MHz
f(X IN ) / 4
255 (FF 16)
300
366.2109375
f(X IN ) / 4
127 (7F16)
600
732.421875
f(X IN ) / 4
f(X IN ) / 4
63 (3F 16)
31 (1F 16)
1200
2400
1464.84375
2929.6875
f(X IN ) / 4
15 (0F 16)
4800
5859.375
f(X IN ) / 4
7 (07 16)
9600
11718.75
f(X IN ) / 4
3 (03 16)
19200
23437.5
f(X IN ) / 4
1 (01 16)
38400
46875
f(X IN)
f(X IN)
3 (03 16)
1 (01 16)
76800
153600
93750
187500
f(X IN)
0 (00 16)
307200
375000
Notes 1: Select the BRG count source with bit 0 of the serial I/O1 control register (address 1A 16).
2: Equation of transfer bit rate:
Transfer bit rate (bps) =
f(X IN)
(BRG set value + 1) ✕ 16 ✕ m ✽
m ✽: m = 1 in the case of bit
register (address 001A 16)
m = 4 in the case of bit
register (address 001A 16)
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0
=
0
=
of the serial I/O1 control
“0”
of the serial I/O1 control
“1”
APPLICATION
7534 Group
2.3 Serial I/O
Transmission side
UART status register (address 19 16)
b7
b0
UARTSTS
Transmit buffer empty flag
•Confirm that the data has been transferred from
the transmit buffer register to the transmit shift register.
•When this flag is “1”, it is possible to write the next
transmission data into the transmit buffer register.
Transmit shift register shift completion flag
Confirm transmission completion of one-byte
unit using this flag.
“1” : Shift of transmission completed
Serial I/O1 control register (addreess 1A 16)
b7
SIO1CON
b0
0
1 0 0 1
1
BRG count source : f(X IN)/4
Continuous transmit invalid
Transmit enabled
Receive disabled
UART mode
UART control register (address 1B 16)
b0
b7
0 1
UARTCON
0 0
Character length : 8 bits
Parity checking disabled
Stop bit length : 2 stop bits
TxD : CMOS output
Baud rate generator (address 1C 16)
b7
BRG
b0
7
f(XIN)
Set
Transfer bit rate ✕ 16 ✕ m✽
–1
✽ m = 1 in the case of bit 0 of SIO1CON (address 001A 16) = “0”
m = 4 in the case of bit 0 of SIO1CON (address 001A 16) = “1”
Fig. 2.3.24 Registers setting relevant to transmission side
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REJ09B0178-0300
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APPLICATION
7534 Group
2.3 Serial I/O
Reception side
UART status register (address 19 16)
b0
b7
UARTSTS
Receive buffer full flag
Confirm reception completion of one-byte unit
using this flag.
“1” : At completing reception
“0” : At readting out Receive buffer register
Overrun error flag
“1” : When data is ready into Receive shift
register while Receive buffer register
contains the data
Parity error flag
“1” : When a parity error occurs in the parity
checking enabled
Framing error flag
“1” : When stop bits cannot be detected at the
specified timing
Summing error flag
“1” : When any one of overrun, parity, and framing
errors occurs
Serial I/O1 control register (addreess 1A 16)
b7
SIO1CON
b0
0
1 0 1 0
1
BRG count source : f(X IN)/4
Continuous transmit invalid
Transmit disabled
Receive enabled
UART mode
UART control register (address 1B 16)
b7
b0
UARTCON
1
0 0
Character length : 8 bits
Parity checking disabled
Stop bit length : 2 stop bits
Baud rate generator (address 1C 16)
b0
b7
BRG
7
f(XIN)
Set
Transfer bit rate ✕ 16 ✕ m✽
–1
✽ m = 1 in the case of bit 0 of SIO1CON (address 001A 16) = “0”
m = 4 in the case of bit 0 of SIO1CON (address 001A 16) = “1”
Fig. 2.3.25 Registers setting relevant to reception side
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APPLICATION
7534 Group
2.3 Serial I/O
Figure 2.3.26 shows a control procedure of transmission side, and Figure 2.3.27 shows a control
procedure of reception side.
RESET
● ✕: This bit is not used here. Set it to “0” or “1” arbitrary.
Initialization
.....
SIO1CON
UARTCON
BRG
P0
P0D
(address 1A 16)
10010001 2
(address 1B 16)
00001000 2
(address 1C 16)
8–1
0
(address 00 16), bit0
(address 01 16)
XXXXXXX1 2
•Serial I/O1 setting
•Setting of port P0 0 for communication control
N
10 ms pass ?
•Generating of a 10 ms interval using Timer
Y
P0 (address 00 16), bit0
•Communication start
1
•Transmission data write
This write causes Transmit buffer empty
flag to be cleared to “0”.
The first byte of
transmission data
TB/RB (address 18 16)
UARTSTS (address 19 16), bit0 ?
0
•Confirmation of transfer from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
1
•Transmission data write
This write causes Transmit buffer empty
flag to be cleared to “0”.
The second byte of
transmission data
TB/RB (address 18 16)
UARTSTS (address 19 16), bit0 ?
0
•Confirmation of transfer from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
1
0
UARTSTS (address 19 16), bit2 ?
•Confirmation of Transmit shift register’s shift
completion
(Transmit shift register shift completion flag)
1
P0 (address 00 16), bit0
0
•Communication completion
Fig. 2.3.26 Control procedure of transmission side
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APPLICATION
7534 Group
2.3 Serial I/O
RESET
● ✕: This bit is not used here. Set it to “0” or “1” arbitrary.
Initialization
.....
SIO1CON
UARTCON
BRG
P0D
(address 1A 16)
(address 1B 16)
(address 1C 16)
(address 01 16)
•Serial I/O1 setting
10100001 2
00001000 2
8–1
XXXXXXX0 2
UARTSTS (address 19 16), bit1 ?
•Setting of port P0 0 for communication control
0
•Confirmation of reception completion
(Receive buffer full flag)
1
•Data receception of the first byte
This read causes Receive buffer full flag
to be cleared to “0”.
Read out received data from
RB (address 18 16)
1
•Error flag check
0
•Confirmation of reception
completion
(Receive buffer full flag)
UARTSTS (address 19 16), bit6 ?
0
UARTSTS (address 19 16), bit1 ?
1
•Data receception of the second
byte
This read causes Receive
buffer full flag to be cleared to
“0”.
Read out received data from
RB (address 18 16)
UARTSTS (address 19 16), bit6 ?
1
•Error flag check
Error process
0
1
P0 (address 00 16), bit0 ?
0
SIO1CON (address 1A 16)
11XXXXXX 2
•Serial I/O1 cleared
SIO1CON (address 1A 16)
00XXXXXX 2
•Serial I/O1 disabled
SIO1CON (address 1A 16)
10100001 2
•Serial I/O1 enabled
Fig. 2.3.27 Control procedure of reception side
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Countermeasure for a bit slip
(Serial I/O1 clear procedure)
APPLICATION
7534 Group
2.3 Serial I/O
2.3.6 Notes on serial I/O
(1) Handling of clear the serial I/O1
When serial I/O1 is set again or the transmit/receive operation is stopped/restarted while serial I/O1
is operating, clear the serial I/O1 as shown in Figure 2.3.28.
• Serial I/O1 enabled
Handling of clear the serial I/O1
○
○
SIO1CON (address 1A 16) bit 7, bit 6 ← 10 2
SIO1CON (address 1A 16) bit 7, bit 6 ← 11 2
• Serial I/O1 cleared
SIO1CON (address 1A 16) bit 7, bit 6 ← 00 2
• Serial I/O1 disabled
UARTCON (address 1B 16)
BRG (address 1C 16)
• Serial I/O1 register set again
→Set again (Note)
• Serial I/O1 enabled
○
○
SIO1CON (address 1A 16) ← 10✕✕✕✕✕✕ 2
Set again (Note)
Note: When the contents of register is not changed, setting again is not necessary.
Fig. 2.3.28 Sequence of clearing serial I/O
(2) Data transmission control with referring to transmit shift register completion flag
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(3) Writing transmit data
When an external clock is used as the synchronous clock for the clock synchronous serial I/O, write
the transmit data to the transmit buffer register (serial I/O shift register) at “H” of the transfer clock
input level.
(4) Serial I/O2 transmit/receive shift completion flag
•The transmit/receive shift completion flag (bit 7) of the serial I/O2 control register is set to “1” after
completing transmit/receive shift. In order to set this flag to “0”, write data (dummy data at reception)
to the serial I/O2 register by program.
•Bit 7 of the serial I/O2 control register is set to “1” a half cycle (of the shift clock) earlier than
completion of shift operation. Accordingly, when using this bit to confirm shift completion, a half
cycle or more of the shift clock must pass after confirming that this bit is set to “1”, before performing
read/write to the serial I/O2 register.
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APPLICATION
7534 Group
2.4 USB
2.4 USB
This paragraph explains operational outline, the registers relevant to the USB, the registers setting method,
the application example for communication and notes on use.
2.4.1 Outline of USB
7534 Group has USB functions in compliance with the Low-Speed USB2.0 specification which are connection
standard with PC peripherals.
In this section, the outline of USB communication function and the USB function of 7534 Group are
described.
(1) Transfer type
In present PC, 2 or more standards used for the connection with peripherals exist (RS-232C and
Centronics, etc.).
USB tries to unite all those communication standards.
The standard of USB has the host side (PC,Hub) which controls connected peripherals and the
connected peripherals side (device).
The following 3 types of communication standards exist depending on the data amount treated on
the peripherals side.
• Hi-Speed function: H.S.
USB operation at 480Mbps.
• Full-Speed function: F.S.
USB operation at 12Mbps.
• Low-Speed function: L.S.
USB operation at 1.5Mbps.
This communication standard depends on the kind of peripherals.
The transfer type for each peripheral is decided.
Table 2.4.1 shows the transfer types of USB.
Table 2.4.1 Transfer types of USB
Transfer type
Control
L.S./F.S./H.S.
Operation
L.S./F.S./H.S. This is used when setting up and for all devices common.
Interrupt
L.S./F.S./H.S. This is used when transferring a small amount of data in real time.
Bulk
F.S./H.S.
This is used when transferring a large amount of data in no real time.
Isochronous
F.S./H.S.
This is used when transferring a large amount of data in real time.
L.S.: Low-Speed function, F.S.: Full-Speed function, H.S.: Hi-Speed function
The 7534 Group has USB Low-Speed function, and the control transfer and interrupt transfer can be
used in Table 2.4.1
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APPLICATION
7534 Group
2.4 USB
(2) Communication sequence
The control transfer and the interrupt transfer have a different communication sequence, respectively.
The control transfer is used when setting up all devices common and communicates combining 3
types of stages in one processing.
The communication starts first in Setup Stage, and Data Stage of the content is executed, and then,
one processing of the communication sequence is completed by executing Status Stage.
Data can be set from host to device through this sequence (=Control Write), and the result can be
read out to host from device (=Control Read).
Use endpoint (ENDP) “0” in the control transfer.
The interrupt transfer is used when transferring a small amount of data in real time.
There is no stage unlike the control transfer.
Only when the host requests data (Token=IN), the device can transmit data.
Use the endpoint in the interrupt transfer excluding “0” (“1” is set for the 7534 Group).
Figure 2.4.1 shows the communication sequence of USB.
Control Transfer: ENDP (endpoint) = 0
● Control Read
Stage
Data
Handshake
1 transaction
Token = IN
Data
Handshake
1 or more transaction
Token = OUT
Data
Handshake
1 transaction
Setup Token = SETUP
Data
Handshake
1 transaction
Token = OUT
Data
Handshake
1 or more transaction
Token = IN
Data
Handshake
1 transaction
Data
Handshake
1 transaction
Data
Handshake
1 transaction
Data
Handshake
Setup Token = SETUP
Data
Status
● Control Write
Stage
Data
Status
● No-data Control
Stage
Setup Token = SETUP
Status
Token = IN
Interrupt Transfer: ENDP = 1
Token = IN
Note: The shaded parts show the case when the device transmits data to the host.
Fig. 2.4.1 Communication sequence of USB
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APPLICATION
7534 Group
2.4 USB
(3) Packet type
The host side controls all the communications in USB.
Basically, the host gives the device the instruction of the communication processing which the host
side executes (= Token), executes data transmit/receive (= Data), and indicates the completion of the
communication is shown at the end (= Handshake).
These communication processings are executed in order by each one unit which has the data
structure (= Packet format), and one processing (= Transaction) is completed.
The content of processing can be identified according to PID (Packet IDentifier field) which is one
unit of data (Field) which composes each packet.
Not only the content of processing, but also the data structure in the packet can be identified by this PID.
Table 2.4.2 shows the packet type of USB.
Table 2.4.2 Packet types of USB
Packet type
Transmitter
Operation
SOF (Start of Frame)
Host
Packet indicating the top of frame (1 ms) including all transfer types
Token
Host
Packet indicating the processing to execute
Data
Host/Device
Packet indicating the transmit/receive data for processing shown by token
Handshake
Host/Device
Packet indicating the result of communication processing
In 7534 Group, the token, data, and the handshake of packet types in Table 2.4.2 can be controlled
by software.
(4) Packet structure
As for the packet type of USB, the data and the structure are different by PID.
Each packet includes the following data shown with PID for which the control is required by 7534
Group;
• token: the receiver to communicate (ADDR) and transfer type (ENDP)
• data: execution (DATA) of the processing ordered by the token
• handshake: the completion of the communication
Figure 2.4.2 shows the data structure of the packet.
Packet type
SOF
(Start Of Frame)
8bits
8bits
11bits
5bits
2bits
SYNC
PID
Frame Number
CRC5
EOP
8bits
8bits
7bits
4bits
5bits
2bits
Token
SYNC
PID
ADDR
ENDP
CRC5
EOP
8bits
8bits
Data
SYNC
PID
8bits
8bits
2bits
Handshake
SYNC
PID
EOP
8bits ✕ 0 to 8bytes
DATA
16bits
2bits
CRC16
EOP
Notes 1: The shaded parts show the data which requires processing by software in 7534 Group.
2: The DATA number of data PID shows the number in L.S.
3: Determination of “Start Of Frame” is not executed because the processing is not required.
Fig. 2.4.2 Data structure of USB packet
In 7534 Group, the PID, ADDR, ENDP and DATA of packet structure data in Figure 2.4.2 can be
controlled by software.
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APPLICATION
7534 Group
2.4 USB
(5) Data structure
Data which composes the communication of USB transmits and receives data that the structure
number of bits is different as shown in Figure 2.4.2 continuously by the LSB first.
Basically, the contents except SYNC which is synchronizing signal and EOP which is the completion
signal are treated as data.
Accordingly, the difference of the number of bits can be detected by forecasting and determining the
following data from the content of PID.
Table 2.4.3 shows the content of data which composes the packet.
Table 2.4.3 Data structure of USB packet
Data name
Symbol
Structure
Operation
8 bits
Synchronized signal to communicate
Packet IDentifier PID
8 bits
Data indicating processing of packet
Frame Number
–
11 bits
Data to control the frame during communication by time
Address
ADDR
7 bits
Endpoint
ENDP
4 bits
Data to confirm the transmit destination of packet
and notify from transmitter
Data indicating transfer type used by device
Data
DATA
8 bits ✕ 0 to 8 bytes
Data to be used when the processing specified by
PID is executed
Token CRCs
CRC5
5 bits
Data to check error when PID is token and SOF
Synchronize
Sync
Data to check error when PID is DATA
16 bits
Data CRCs
CRC16
Data indicating the completion of packet
2 bits
End Of Packet
EOP
Note: The DATA numbers in L.S. are shown in this table.
PID is classified into 3 kinds in the structure data of Table 2.4.3.
Token is used to give the device the instruction of communication processing, and report on the
processing of the following stages. It is only a host to be able to issue the token.
Data is used to transmit and receive data which is the content of the instruction of the token, and
execute the processing in the stage. It is a host to be able to issue the data when the token is SETUP
and OUT, and it is a device when the token is IN.
Handshake indicates the completion of the communication at the end.
It is a host to be able to issue the handshake when the token is IN, and it is a host when the token
is SETUP and OUT.
Table 2.4.4 shows PID.
Table 2.4.4 PID
Packet
type
Token
Data
PID name
Processing
(bits 3 to 0)
SETUP
IN
11012
10012
The processing is reported by host to device
Data transmit is requested from host to device
OUT
00012
Data receive is requested from host to device
SOF
01012
Top of frame is indicated by host to device
DATA0
00112
The state that sequence bit of transmit/receive data is even is indicated
DATA1
10112
The state that sequence bit of transmit/receive data is odd is indicated
00102
10102
Normal completion of communication is reported
The state that device is waiting for communication is reported
STALL
11102
Completion error of communication is reported
PRE
11002
Communication to the L.S. device which has low-priority is enabled
Handshake ACK
NAK
Special
Bit structure
In 7534 Group, data except SOF and PRE of PID can be controlled by software.
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APPLICATION
7534 Group
2.4 USB
(6) USB special signal
The host side has function to control the state of the device side, and the device side has the function
to transmit the state to the host side and other devices on USB communications line by the signal
besides the above-mentioned data transfer.
Usually, the transfer confirmation [Keep alive, Idle: only for L.S.] is performed on the USB communication
line regardless of data transmit/receive. The contents of transfer confirmation are as follows;
• host confirms the connection of device on the communication line
• device confirms the normal data transfer of host.
The confirmation transfer is transmitted by host side for each frame (1ms/frame) which is the basic
time unit of the USB transfer.
When the host stops all the device, the host informs device of the stop of functions by suspending
the confirmation transfer for 3 ms or more.
The signal to stop the function is called “Suspend”.
The stopped device can be returned by 2 methods.
The return is performed basically when there is a change in the device in the stopped state.
One is a method (change on communications line) to return to a normal state by restarting the data
communication which is suspended before suspend.
The signal to return is called “Resume”.
The other is a method (change on the device) to return to a normal state by the change in an external
input of the device.
The host can inform all the other connected devices of the return of the device by the change in an
external input by outputting K state signal of 1 to 15 ms.
The signal to activate for other devices is called “Remote wake up”.
When the SE0 signal of 2.5 µs or more is input on communications line regardless of the state of
the stop/start of the function of the device side, the packet, and the stage processing, the device
makes all states concerning the USB function initial state.
The signal to initialize is called “Reset”.
Table 2.4.5 shows a special signal of USB.
Table 2.4.5 Special signal of USB
Signal type
Operation
Signal format
Suspend
Stop of all device function
No data transfer for 3 ms
Resume
Return of device function
K state input/reset input in the suspend state
Reset
Initialization of USB setting
SE0 input for 2.5 µs or more
Remote wake up
Report of return to other devices K state output for 1 to 15 ms
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APPLICATION
7534 Group
2.4 USB
(7) USB interface
In 7534 Group, the USB interface divides one communications line by 2 depending on the contents
of data.
Figure 2.4.3 shows the interface of USB.
7534 Group
Token: SETUP, IN, OUT
Control transfer
Endpoint 0
Token: IN
Interrupt transfer
Endpoint 1
Host system
(PC, Hub)
Low-Speed Function
Note: Transfer direction shows the DATA transmission direction of PID.
Fig. 2.4.3 USB (L.S.) interface
(8) System configuration of USB
In the system configuration used with the low-speed communication device of USB, the host side can
recognize the connection of the low-speed communication device by pull-up the D-pin with the
voltage of 3.0 to 3.6 V and the resistor of 1.5 kΩ of communications lines.
Figure 2.4.4 shows the example of connecting USB (L.S.).
7534 Group
D- pull-up resistor
(1.5kΩ)
USBVREFOUT
USB connector
D-/P10
D+/P11
VCC
VSS
Host system
(PC, Hub)
USB cable (for L.S.)
Untwisted, Unshielded, 3 Meters max.
Low-Speed communication device
Note: Use the USB connector and USB cable specified to the USB specifications.
Fig. 2.4.4 USB (L.S.) connection example
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APPLICATION
7534 Group
2.4 USB
2.4.2 Memory map
001816 Transmit/Receive buffer register (TB/RB)
001916 USB status register (USBSTS)
001A16 Serial I/O1 control register (SIO1CON)
001D16 USB data toggle synchronization register ( TRSYNC)
001E16 USB interrupt source discrimination register 1 (USBIR1)
001F16 USB interrupt source discrimination register 2 (USBIR2)
002016 USB interrupt control register (USBICON)
002116 USB transmit data byte number set register 0 (EP0BYTE)
002216 USB transmit data byte number set register 1 (EP1BYTE)
002316 USBPID control register 0 (EP0PID)
002416 USBPID control register 1 (EP1PID)
002516 USB address register (USBA)
002616 USB sequence bit initialization register (INISQ1)
002716 USB control register (USBCON)
003C16 Interrupt request register 1 (IREQ1)
003E16 Interrupt control register 1 (ICON1)
Fig. 2.4.5 Memory map of registers relevant to USB
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APPLICATION
7534 Group
2.4 USB
2.4.3 Relevant registers
In this section, the contents of control are described as follows;
•
•
•
•
•
Transmit/Receive buffer
Setting to enable/disable of each function including USB communication and interrupts
Determination of USB communication error occurrence
Setting to stage and handshake by unit of endpoint
Auto-determination of self-address of USB device
Figure 2.4.6 shows the description of the register structure, and Figure 2.4.7 to Figure 2.4.10 show the
register structures relevant to USB.
Register name: (Symbol): [Address]
b7
Initial value
b6
b5
b4
b3
b2
b1
b0
CPU
RD
Symbol of bit name
Bit name
0, 1 or ✕
✕: Initial value undfined.
CPU
WR
Function
Remarks
CPU RD: Read from CPU
Enable: Read enabled
CPU WR: Write from CPU
Set/Clear: Write “0”, “1” enabled
Set: Write only “1” enabled
Clear: Write only “0” enabled
Dummy: Initializing by dummy write enabled
H/W RD: Read by hardware
Use: used by hardware (data is no change)
H/W WR: Write by hardware
Set/Clear: Write “0”, “1” is executed by hardware
Set: Write only “1” is executed by hardware
Clear: Write only “0” is executed by hardware
Shaded area: no R/W function
Fig. 2.4.6 Description of the register structure
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H/W
RD
H/W
WR
APPLICATION
7534 Group
2.4 USB
Transmit buffer register (TB) [Address 18 16]
b7
b6
b5
b4
b3
b2
b1
b0
✕
✕
✕
✕
TB
Initial value
✕
✕
✕
✕
CPU
RD
–
CPU
WR
H/W
RD
H/W
WR
Set/ Use
Clear
After setting data to address 0018 16,
the data is transferred to the transmit
shift register automatically.
Transmit buffer empty flag (TxRDY) is cleared by writing data to this register.
Receive buffer register (RB) [Address 18 16]
b7
b6
b5
b4
b3
b2
b1
b0
RB
Initial value
0
0
0
0
0
0
0
CPU
RD
0
CPU
WR
H/W
RD
Receive buffer register can be read out Enaby reading data from address 0018 16. ble
Receive buffer full flag (RxRDY) is cleared by reading this register.
Set/
Clear
–
USB status register (USBSTS) [Address 19 16]
b7
b6
b5
b4
b3
b2
b1
RxRDY SUME BSTFE
Initial value
0
0
0
PIDE
0
CRCE FEOPE
0
0
H/W
WR
b0
EOP
TxRDY
0
1
CPU
RD
CPU
WR
H/W
RD
H/W
WR
EnaSet/
Transmit buffer
0: Buffer full
ble
Clear
empty flag
1: Buffer empty
This bit is set to “1” when data is transferred from buffer to shift register by hardware.
This bit is cleared to “0” by writing to buffer.
Ena- Clear
Set
EOP detection flag
0: Not detected
ble
1: Detect
Setting condition of this flag to “1” is as follows;
• Normal EOP detected by hardware
• False EOP flag (FEOPE) set
• Time is out with EOP not detected at data phase or handshake phase
This bit is cleared to “0” by writing dummy to this register.
Ena- Clear
Set
False EOP error flag 0: No error
ble
1: False EOP error
This bit is set to “1” when the phase is not completed normally.
This bit is cleared to “0” by writing dummy to this register.
Ena- Clear
Set
CRC error flag
0: No error
ble
1: CRC error
This bit is set to “1” when the CRC error occurs at the same timing of EOP detection
flag.
This bit is to “0” cleared by writing dummy to this register.
Set
Ena- Clear
0: No error
ble
1: PID error
Setting condition of this flag to “1” is as follows;
• PID of DATA0 or DATA1 cannot be detected at data phase after OUT or SETUP
token
• ACK PID cannot be received at handshake phase during IN transaction.
This bit is cleared to “0” by writing dummy to this register.
PID error flag
Set
0: No error
Ena- Clear
1: Bit stuffing error
ble
This bit is set to “1” when bit stuffing error occurs at data phase or handshake phase.
This bit is cleared to “0” by writing dummy to this register.
Set
Summing error flag
0: No error
Ena- Clear
1: Summing error
ble
This bit is set to “1” when any error of FEOPE, CRCE, PIDE, or BSTFE occurs.
This bit is cleared to “0” by writing dummy to this register.
Receive buffer full
0: Buffer empty
EnaSet/
flag
1: Buffer full
ble
Clear
This bit is set to “1” when data is transferred from shift register to buffer by hardware.
This bit is cleared to “0” by reading from buffer.
Bit stuffing error flag
Fig. 2.4.7 Register structures relevant to USB (1)
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APPLICATION
7534 Group
2.4 USB
USB data toggle synchronization register (TRSYNC) [Address 1D 16]
b7
b6
b5
b4
b3
b2
b1
b0
SQTGL
CPU
RD
Initial value 0
CPU
WR
H/W
RD
H/W
WR
Ena- Clear
Sequence bit toggle 0: No toggle
Set
ble
flag
1: Sequence toggle
Setting condition of this flag to “1” is as follows;
• Setting of handshake for OUT token in EP0PID is ACK, toggle of data PID is
performed normally, and errors do not occur at data phase during OUT and
SETUP transaction.
• When ACK is received during IN transaction.
This bit is cleared to “0” by writing dummy to this register.
USB interrupt source discrimination register 1 (USBIR1) [Address 1E 16 ]
b7
b6
b5
b4
b3
b2
b1
b0
RxEP
CPU
RD
Initial value 0
CPU
WR
H/W
RD
H/W
WR
Set/
Clear
Endpoint
0: Endpoint 0 interrupt
Enadetermination flag
1: Endpoint 1 interrupt
ble
This flag is set to “1” when IN token interrupt of endpoint 1 occurs.
This flag is cleared to “0” when IN token interrupt of endpoint 0 occurs.
Writing to this bit is invalid. Do not write “1” to bits 0 to 6.
USB interrupt source discrimination register 2 (USBIR2) [Address 1F 16]
b7
b6
RxPID
OPID
Initial value 0
b5
b4
b3
b2
b1
b0
RSTRQ SPRQ
1
0
CPU
RD
0
CPU
WR
H/W
RD
H/W
WR
Set
Ena- Clear
Suspend request flag 0: No request
ble
1: Suspend request
Suspend request is set to “1” when system enters to state J for 3 ms or more.
Suspend request is cleared to “0” by writing dummy to this register.
Set/
EnaUSB reset request
0: No request
Clear
ble
flag
1: Reset request
USB reset request is set to “1” when the SE0 signal is input for 2.5 µs or more.
USB reset request is cleared to “0” when the SE0 signal is stopped.
Set/
EnaToken PID
0: SETUP interrupt
Clear
determination flag
1: OUT interrupt
ble
This flag is set to “1” during no SETUP transaction.
This flag is cleared to “0” when PID of SETUP is detected.
Set/
EnaToken interrupt flag 0: No interrup
Clear
ble
1: OUT/SETUP token interrupt
This flag is set to “1” when OUT or SETUP interrupt occurs.
This flag is cleared to “0” after the end of transaction.
USB interrupt control register (USBICON) [Address 20 16]
b7
b6
USBE
TKNE
Initial value 0
0
b5
b4
RSME RSTE
0
0
b3
b2
b1
b0
EP1E
CPU
RD
0
Endpoint 1 enable
0: Endpoint 1 invalid
1: Endpoint 1 valid
CPU
WR
H/W
RD
H/W
WR
Ena- Set/ Use
ble Clear
0:USB reset invalid
USB reset interrupt
Ena- Set/ Use
1:USB reset valid
enable
ble Clear
This flag is invalid in suspend mode (USB reset is always valid in suspend mode).
Resume interrupt
enable
0: Resumue invalid
1: Resume valid
Ena- Set/ Use
ble Clear
Token interrupt
enable
0:Token invalid
1:Token valid
Ena- Set/ Use
ble Clear
Ena- Set/ Use
0:USB invalid
ble Clear
1:USB valid
The internal state can be initialized by clearing this flag to “0”.
The initial values of registers are as follows;
• USB status register [address 19 16] = (01 16)
• USB data toggle synchronization register [address 1D 16] = (7F16)
• USB interrupt source discrimination register 1 [address 1E 16] = (7F16)
• Bits 7, 6 and 2 of USB interrupt source discrimination register 2 [address 1F
= (00xxx0xx 2)
USB enable flag
Fig. 2.4.8 Register structures relevant to USB (2)
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16]
APPLICATION
7534 Group
2.4 USB
USB transmit data byte number set register 0 (EP0BYTE) [Address 21 16]
b7
b6
b5
b4
0
0
0
0
b3
b2
0
Initial value
b1
b0
EP0BYTE
0
0
CPU
RD
0
–
Set the number of data byte for
transmitting with endpoint 0
CPU
WR
H/W
RD
H/W
WR
Ena- Set/ Use
ble Clear
USB transmit data byte number set register 1 (EP1BYTE) [Address 22 16]
b7
b6
b5
b4
0
0
0
0
Initial value
b3
b2
b1
b0
EP1BYTE
0
0
0
CPU
RD
0
–
Set the number of data byte for
transmitting with endpoint 1
CPU
WR
H/W
RD
H/W
WR
Ena- Set/ Use
Clear
ble
USB PID control register 0 (EP0PID) [Address 23 16]
b7
b6
b5
b4
b3
b2
b1
b0
DPID0 SPID0I APID0 SPID0O EP0E
Initial value 0
0
0
0
CPU
RD
0
CPU
WR
H/W
RD
H/W
WR
Endpoint 0 enable
0: Endpoint 0 invalid
Ena- Set/ Use
flag
1: Endpoint 0 valid
Clear
ble
Unexpected IN or OUT transaction can be ignored by clearing this flag to “0”.
(SETUP transaction cannot be ignored, it is always valid.)
Endpoint 0 PID selection 1✕✕✕: IN token interrupt of DATA 0/1 is valid Ena- Set/ Use
01✕✕: STALL handshake is valid for IN token
flag (OUT STALL)
Clear
ble
00✕✕: NAK handshake is valid for IN token
Endpoint 0 PID selection ✕✕✕1: STALL handshake is valid for OUT
Ena- Set/ Use
flag (OUT ACK)
Clear
ble
token
Endpoint 0 PID selection ✕✕10: ACK handshake is valid for OUT token Ena- Set/ Use
✕✕00: NAK handshake is valid for OUT token
flag (IN STALL)
Clear
ble
Endpoint 0 PID selection
Ena- Set/ Use Clear
flag (IN DATA0/1)
Clear
ble
DPID0 and SPID0I are used to control the response for IN token.
DPID0 is used with the token interrupt enable flag (TKNE).
DPID0 is cleared to “0” automatically by hardware when ACK is received.
SPID0O and APID0 are used to control the response for OUT token.
When DPID0 is changed during token packet, the changed value is valid after end
of token.
✕: it can be set to 0 or 1.
USB PID control register 1 (EP1PID) [Address 24 16]
b7
b6
b5
b4
b3
b2
b1
b0
DPID1 SPID1
Initial value 0
CPU
RD
0
CPU
WR
H/W
RD
Endpoint 1 PID selection 1✕: IN token interrupt of DATA0/1 is valid
01: STALL handshake is valid for IN token
flag (IN STALL)
H/W
WR
Ena- Set/ Use
Clear
ble
Endpoint 1 PID selection
Ena- Set/ Use Clear
flag (IN DATA0/1)
Clear
ble
DPID1 and SPID1 are used to control the response for IN token.
DPID1 is used with the token interrupt enable flag (TKNE).
DPID1 is cleared to “0” automatically by hardware when ACK is received.
00: NAK handshake is valid for IN token
✕: it can be set to 0 or 1.
Fig. 2.4.9 Register structures relevant to USB (3)
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APPLICATION
7534 Group
2.4 USB
USB address register (USBA) [Address 25 16]
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
USBA
0
Initial value
0
0
0
CPU
RD
–
CPU
WR
H/W
RD
H/W
WR
Set/ Use
Clear
Set an address allocated by the
USB host
USB sequence bit initialization register (INISQ1) [Address 26 16]
b7
b6
b5
b4
b3
b2
b1
b0
✕
✕
✕
INISQ1
Initial value
✕
✕
✕
✕
✕
CPU
RD
As sequence bit of endpoint 1 is
initialized.
Sequence is initialized by writing dummy.
CPU
WR
H/W
RD
H/W
WR
H/W
RD
H/W
WR
Dummy
–
USB control register (USBCON) [Address 27 16]
b7
b6
b5
b4
b3
b2
b1
b0
WKUP UVOE
Initial value
0
CPU
RD
0
USBVREFOUT output
valid flag
0: Output off
1: Output on
CPU
WR
Set/ Use
Clear
Remote wake up
0: No request
Set Use Clear
request flag
1:Remote wake up request
Remote wake up request (K output) can be set by setting this flag to “1”.
This flag is cleaed to “0” automatically after 10 ms from remote wake up request.
Serial I/O1 control register (SIO1CON) [Address 1A 16]
b7
b6
MOD1 MOD0
Initial value
0
b5
b4
b3
b2
PE
TE
TIC
CTE
b1
b0
CSS
CPU
RD
0
Serial I/O1 mode
selection bit
Serial I/O1 mode
selection bit
00: I/O port
01:Not available
10:UART mode
11:USB mode
Note: Only bits 6 and 7 of SIO1CON are described in this figure because only these bits are used for USB.
Fig. 2.4.10 Register structures relevant to USB (4)
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CPU
WR
H/W
RD
Set/ Use
Clear
Set/ Use
Clear
H/W
WR
APPLICATION
7534 Group
2.4 USB
2.4.4 USB application example
In this section, the application examples when using the USB communication are described using examples
of the timing chart and register setting.
(1) Example of processing each control sequence
In 7534 Group, the control and the determination of the control sequence are executed by software.
The content of processing is executed in the setup stage, transmitting and receiving the data stage
of the content are executed, and the completion of the sequence is shown in the status stage.
Note that the contents of the control and the determination are different even in the software of 7534
Group, because the following processing is different respectively depending on the content of the
setup stage.
In the control transfer, the processing since the data stage is determined when receiving the setup
stage, the execution of the transmit and receive processing and the number of data bytes are
controlled, the status stage at the end is executed, and the sequence is completed.
Only the control of each packet is performed because there is no stage in the interrupt transfer.
Figure 2.4.11 shows the control method of control sequence.
1. Control Read
Setup Stage
Data Stage
SETUP DATA0
IN
DATA1
Status Stage
IN
DATA0
IN
DATA1
IN
DATA0
OUT
DATA1
Endpoint 0 invalid
Endpoint 0 valid
Endpoint 0 enable flag
(EP0E)
Endpoint 0 PID selection flag
OUT token:STALL, IN token:DATA0/1
OUT token:ACK, IN token:STALL
OUT STALL
(SPID0O)
OUT ACK
(APID0)
IN STALL
(SPID0I)
IN DATA0/1
(DPID0)
SETUP, no error
Sequence bit toggle flag
(SQTGL)
IN, ACK receive
(4 transaction)
OUT, no error
2. Control Write
Setup Stage
SETUP DATA0
Data Stage
OUT
DATA1
Status Stage
OUT
DATA0
OUT
Endpoint 0 valid
DATA1
OUT
DATA0
IN
DATA1
Endpoint 0 invalid
Endpoint 0 enable flag
(EP0E)
Endpoint 0 PID selection flag
OUT token:ACK, IN token:STALL
OUT token:STALL, IN token:DATA0/1
OUT STALL
(SPID0O)
OUT ACK
(APID0)
IN STALL
(SPID0I)
IN DATA0/1
(DPID0)
SETUP, no error
Sequence bit toggle flag
(SQTGL)
OUT, no error
(4 transaction)
Notes 1: Only token and DATA0/1 of PID are shown in this figure.
2: In this example, data stage is 4 transaction.
Fig. 2.4.11 Control method of control sequence
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IN, ACK receive
APPLICATION
7534 Group
2.4 USB
(2) Example of processing each transaction
In 7534 Group, the control and the determination of the packet are executed by software.
First, the content of the received token is determined, transmit and receive data according to it are
executed, the completion of the transaction is shown by the handshake.
Note that the contents of the control and the determination are different even of the software so that
processing is different depending on the content of the token.
Figure 2.4.12 shows timing chart of the transaction according to each token.
1. SETUP token transaction
Token
SYNC
Data
SETUP ADDR ENDP CRC5 EOP
SETUP PID detected
SYNC
Handshake
DATA0
DATAa
DATAb
CRC16
EOP
SYNC
ACK
EOP
SETUP interrupt occurs
OUT token interrupt
(Interrupt processing)
EOP detected
(Token)
EOP detection flag
(EOP)
EOP detected
(Data)
EOP detected
(Handshake)
Token PID determination flag
(OPID)
Token interrupt flag
(RxPID)
Data received/read (2 bytes)
Receive buffer full flag
(RxRDY)
False EOP error
occurs (FEOPE)
CRC error occurs
(CRCE)
Summing error flag
(SUME)
PID error occurs
(PIDE)
False EOP error occurs
(FEOPE)
CRC error occurs
(CRCE)
2. OUT token transaction
Token
SYNC
OUT
Data
ADDR ENDP CRC5 EOP
OUT PID detected
Handshake
SYNC DATA0/1 DATAa
DATAb
CRC16
EOP
SYNC
ACK
EOP
OUT interrupt occurs
OUT token interrupt
(Interrupt processing)
EOP detected
(Token)
EOP detection flag
(EOP)
EOP detected
(Data)
EOP detected
(Handshake)
Token PID determination flag
(OPID)
Token interrupt flag
(RxPID)
Data received/read (2 bytes)
Receive buffer full flag
(RxRDY)
False EOP error
occurs (FEOPE)
CRC error occurs
(CRCE)
Summing error flag
(SUME)
False EOP error occurs
(FEOPE)
PID error occurs
(PIDE)
CRC error occurs
(CRCE)
3. IN token transaction
Token
SYNC
Data
IN
ADDR ENDP CRC5 EOP
SYNC DATA0/1 DATAa
Handshake
DATAb
CRC16
EOP
SYNC
ACK
EOP
IN interrupt occurs
IN token interrupt
(Interrupt processing)
EOP detected
(Token)
EOP detection flag
(EOP)
EOP detected
(Data)
EOP detected
(Handshake)
Endpoint determination flag
(RxEP)
Data written and transmitted (2 bytes)
Transmit buffer empty flag
(TxRDY)
CRC error occurs
(CRCE)
False EOP error occurs
(FEOPE)
PID error occurs
(PIDE)
Summing error flag
(SUME)
Notes 1: The data number of PID = DATA0/1 is 2 bytes in this example.
2: Endpoint (ENDP) is 0 in this example.
3: The dot line on SUME shows the timing of each error occur.
Fig. 2.4.12 Timing chart of the transaction according to each token
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 63 of 78
False EOP error occurs
(FEOPE)
APPLICATION
7534 Group
2.4 USB
(3) Interrupt processing
In 7534 Group, the interrupt related to the USB communication processes 7 sources 2 jump destination.
Accordingly, determine the interrupt source and execute the processing after executing the interrupt
processing.
Moreover, control the USB function and the interrupt source which has been enabled before interrupt
is enabled.
The interrupt jump destination and the source are shown as follows.
IN token interrupt: IN token (endpoint 0) and IN token (endpoint 1)
OUT token interrupt: OUT token, SETUP token, Reset, Suspend, and Resume
The determination (processing at the OUT token in figure) by the interrupt and the setting of a related
register when using the interrupt of the OUT token is shown in Figure 2.4.13. The determination
(processing at the IN token (endpoint 0) in figure) by the interrupt and the setting a related register
when using the interrupt of the IN token in Figure 2.4.14.
In the OUT token interrupt, read data of OUT token and SETUP token at the timing shown in Figures
2.4.15 and 2.4.16. Also, in the IN token interrupt, write data to IN token (endpoint 0) and IN token
(endpoint 1) at the timing shown in Figure 2.4.17.
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page 64 of 78
APPLICATION
7534 Group
2.4 USB
[Flow chart]
[Program description]
Main processing
Set USB communication
Set OUT token enabled
Set OUT token interrupt
enabled
( USBA
✕0000000
●✕: Not used here.
Set it to “0” or “1” arbitrary.
Initial USB address = “0”
2
)
SIO1CON 11✕✕✕✕✕✕ 2 Set hardware (I/O port) to USB mode
USBCON ✕1✕✕✕✕✕✕ 2 Use USBV REFOUT pin
USBICON 1✕✕✕✕✕✕✕
2
Set internal state to USB enabled
✕✕✕✕1✕✕✕
2
Set endpoint 0 to be valid
EP0PID
USBICON ✕1✕✕✕✕✕✕ 2 Set token interrupt to be valid
( IREQ1
✕✕✕✕✕✕0✕ 2 Initialize OUT token interrupt request )
( ICON1
)
✕✕✕✕✕✕1✕ 2 Set OUT token interrupt enable
OUT token interrupt
Reset/Supend/
Resume processing
To Reset/Supend/
Resume processing
No token
RTI
SETUP
To Setup processing
Interrupt source = Reset/
Supend/Resume processing ?
No Reset/Supend/Resume
processing
USBIR2
✕✕✕✕?✕✕✕ 2 Interrupt by reset if ? = “1”
USBIR2
✕✕✕✕✕?✕✕ 2 Interrupt by suspend if ? = “1”
USBICON ✕✕?✕✕✕✕✕ 2 Interrupt by resume if ? = “1”
Note: Set RSME to “1” only in suspend processing
Interrupt source = token ?
Token
USBIR2
?✕✕✕✕✕✕✕
2
Interrupt by token if ? = “1”
OUT token ?
OUT
USBIR2
✕?✕✕✕✕✕✕
2
Interrupt by OUT token if ? = “1”
Data receive executed
RB
????????
Communication error occur ?
USBSTS
✕?????✕✕ 2 No error if all ? = “0”
Error/No error can be determined by SUME of bit 6
Yes
No
No
Data toggle ?
Read receive data
(Max. 8 bytes in 1 interrupt
processing)
2
TRSYNC ?✕✕✕✕✕✕✕
2
Toggle normally if ? = “1”
Yes
*B
*A
Set handshake
In normal receive, handshake is set to ACK (*A).
When communication error or data doggle error occur, handshake is
set to NAK or STALL according to the contents (*B).
*D
*C
Store this receive data
In normal receive, data is stored (*C).
When communication error or data doggle error occur, received data
in this time is canceled (*D).
RTI
Notes 1: In this figure, only USB in interrupt processing is described.
Note that the storing stack, etc. is not described.
2: Data shown by ? in program description expresses determination
or data setting.
Fig. 2.4.13 USB interrupt processing example (OUT token)
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REJ09B0178-0300
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APPLICATION
7534 Group
2.4 USB
●✕: Not used here.
Set it to “0” or “1” arbitrary.
[Flow chart]
[Program description]
Main processing
✕0000000
Initial USB address = “0”
2
11✕✕✕✕✕✕ 2 Set I/O port to USB mode
✕1✕✕✕✕✕✕ 2 Use USBV REFOUT pin
USBICON
1✕✕✕✕✕✕✕ 2 Set internal state to USB enabled
Set IN token enabled
EP0PID
USBICON
✕✕✕✕1✕✕✕ 2 Set endpoint 0 to be valid
✕✕✕✕1✕✕✕2 Set endpoint 1 to be valid
Set IN token interrupt
enabled
USBICON
( IREQ1
( ICON1
✕1✕✕✕✕✕✕ 2 Set token interrupt to be valid
✕✕✕✕✕✕✕0 2 Initialize IN token interrupt request )
)
✕✕✕✕✕✕✕1 2 Set IN token interrupt enable
( EP0BYTE
????????
IN token interrupt
Set the number of transmit data
in this stage
2
Yes
Endpoint = 0 or 1 ?
USBIR1
?✕✕✕✕✕✕✕
Data transmit executed
EP0BYTE
TB
✕✕✕✕???? 2
???????? 2
Set the number of transmit data byte
Write transmit data
(Max. 8 bytes in 1 interrupt processing)
Communication error occur ?
USBSTS
✕?????✕✕ 2
No error if all ? = “0”
Error/No error can be determined
by SUME of bit 6
TRSYNC
?✕✕✕✕✕✕✕
2
No
No
Endpoint 0 interrupt occurs if ? = “0”
Data toggle ?
Yes
*A
Store next transmit data
2
Toggle normally if ? = “1”
In normal tramsmit, the next transmit data is set (*A).
When communication error or data doggle error occur,
transmit is executed again (*B).
RTI
Notes 1: In this figure, only USB in interrupt processing is described.
Note that the storing stack, etc. is not described.
2: IN token interrupt processing of only endpoint 0 is shown in this example.
3: Data shown by ? in program description expresses determination or data setting.
Fig. 2.4.14 USB interrupt processing example (IN token)
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
)
0
To endpoint processing
*B
)
SIO1CON
USBCON
Set USB communication
1
( USBA
page 66 of 78
APPLICATION
7534 Group
SYNC
2.4 USB
PID
ADDR
ENDP
CRC
EOP
SYNC
PID
Data X
Data Y
34 bit times = 22.7 µs = 136 cycle
SETUP token interrupt occurs
CRC16
EOP
Read Data 0
Notes 1: In this case, Data: 2 bytes, Cycle: 6 MHz.
2: Max. 14 cycles are required until the interrupt occurs.
Fig. 2.4.15 Data read timing of SETUP token
SYNC
PID
ADDR
ENDP
CRC
EOP
SYNC
PID
Data X
Data Y
CRC16
EOP
34 bit times = 22.7 µs = 136 cycle
OUT token interrupt occurs
Read Data 0
Notes 1: In this case, Data: 2 bytes, Cycle: 6 MHz.
2: Max. 14 cycles are required until the interrupt occurs.
Fig. 2.4.16 Data read timing of OUT token
SYNC
PID
ADDR
ENDP
CRC
EOP
SYNC
PID
Data X
CRC16
22.5 bit times = 15 µs = 90 cycle
IN token interrupt occurs
Read Data 0
Notes 1: In this case, Data: 1 byte, Cycle: 6 MHz.
2: Max. 14 cycles are required until the interrupt occurs.
Fig. 2.4.17 Data read timing of IN token (endpoint 0) and IN token (endpoint 1) token
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EOP
APPLICATION
7534 Group
2.4 USB
(4) Processing to special signal
In 7534 Group, control the USB function to the signal shown in Table 2.4.5 by software.
At USB reset, initialize the registers relevant to USB described in the above section 2.4.3.
Also, at Suspend, execute the STP instruction after the interrupt is enabled.
Set an external interrupt which is the return condition from the stopped state before STP instruction.
The enable of resume is included in this condition.
The generation of these signals can be recognized by the interrupt request.
The interrupt to a special signal is all included in the OUT token interrupt.
IN token interrupt: IN token (endpoint 0) and IN token (endpoint 1)
OUT token interrupt: OUT token, SETUP token, Reset, Suspend, and Resume
The remote wake up function is used to output signals when to output as USB function is required
for the return from the stopped state by an external input.
Figure 2.4.18 shows timing chart of each signal.
1. Resume interrupt return from Suspend
Keep alive
(1 ms interval)
No change of
communication line
(3 ms or more)
Reset signal input
(2.5 µs or more)
D-pin state
STP instruction executed
Microcomputer
operation
Suspend interrupt occurs
Resume interrupt occurs
Reset interrupt occurs
OUT token interrupt
(Interrupt processing)
Suspend request flag
(SPRQ)
USB reset request flag
(RSTRQ)
Resume interrupt enable
(RSME)
2. External interrupt return from SUSPEND
Keep alive
(1 ms interval)
No change of
communication line
(3 ms or more)
Remote wake up signal output
(10 ms)
Reset signal input
(2.5 µs or more)
D-pin state
STP instruction executed
Microcomputer
operation
Suspend interrupt occurs
External input interrupt occurs
OUT token interrupt
(Interrupt processing)
Suspend request flag
(SPRQ)
USB reset request flag
(RSTRQ)
Resume interrupt enable
(RSME)
Remote wake up signal output request
Remote wake up request
flag
(WKUP)
Notes 1: In this example, USB reset interrupt enable flag (RSTE) = “1” (enabled).
2: The remote wake up request flag (WKUP) is not set to “1” when host does not request
the remote wake up signal output.
3: External input interrupts: key on wake up, INT 0, INT1 and CNTR 0 interrupt.
Fig. 2.4.18 Timing chart of each signal
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REJ09B0178-0300
page 68 of 78
Reset interrupt occurs
APPLICATION
7534 Group
2.4 USB
2.4.5 Notes concerning USB
(1) Determination of interrupt condition in OUT token interrupt processing
Determine the occurrence of the reset/suspend/resume interrupt from other interrupt conditions in the
order as shown in Figure 2.4.19 when they occur in the OUT token interrupt processing.
●✕: Not used here.
Set it to “0” or “1” arbitrary.
OUT token interrupt
Reset
To Reset
processing
Interrupt source = Reset ?
No Reset
USBIR2
✕✕✕✕?✕✕✕ 2 Interrupt by Reset occurs if ? = “1”
Interrupt source = Suspend ?
No Suspend
USBIR2
✕✕✕✕✕?✕✕ 2 Interrupt by Suspend occurs if ? = “1”
Interrupt control = Enabled ?
Resume disabled
USBICON ✕✕?✕✕✕✕✕ 2 Interrupt by Resume occurs if ? (RSME) = “1”
Note: Set “1” to RSME only in Suspend processing.
Interrupt source = Token ?
Token
USBIR2
?✕✕✕✕✕✕✕2 Interrupt by the source except token occurs if ? = “0
Token processing = SETUP ?
OUT
USBIR2
✕?✕✕✕✕✕✕2 Interrupt by the source SETUP token occurs if ? =
Interrupt by the source OUT token occurs if ? = “1”
Suspend
To Suspend
processing
Resume enabled
To Resume
processing
No Token
RTI
SETUP
To SETUP token
processing
To OUT token processing
Fig. 2.4.19 Example for determination of resume interrupt
(2) Clear of suspend request flag
When the request of the suspend interrupt occurs, the suspend request flag is set to “1”. After the
suspend state is fixed, the state of this flag is retained during fixed time (13 µs).
The purpose of this is to retain the internal state until the count source to measure the time (3 ms)
until suspend is fixed is updated.
Accordingly, the state might not change even if this flag is cleared to “0” immediately after the
suspend request flag is “1” is determined.
Clear this flag to “0” after the wait of 13 µs or 79 machine cycle (f(XIN) =6 MHz time) after this flag is “1”.
(3) Determination of SE0 signal
In 7534 Group, USB reset and EOP can be distinguished according to the width of the SE0 signal.
However, there is the time zone which corresponds any on the dividing line of the time of the width of the signal.
Moreover, the control in a present state is required because there is a difference in processing by
the state of the device.
Accordingly, select the processing method in software by the state of the device.
Figure 2.4.20 shows processing to the width of the signal according to the situation.
TKNE, RSME, RSTE
0 µs
0.50 µs
2.50 µs
2.67 µs
D-pin state
✕
0
1
Signal ignored
Token phase state 1
0
1
Data/Handshake 0
phase state
0
Suspend state
1
Idle state
0
Keep Alive
Keep Alive/Reset(RSTRQ=1)
Reset(RSTRQ=1)
Signal ignored(FEOPE=1) EOP(RxPID=1)
EOP(RxPID=1)/Reset(RxPID=0)
Reset(RSTRQ=1)
0/1
Signal ignored(FEOPE=1) EOP(EOP=1)
EOP(RSTRQ=0)/Reset(RSTRQ=1)
Reset(RSTRQ=1)
0
Reset(RSTRQ=1)/Resume(RSTRQ=0)
Note: Each active state represents the processing is required in “H” state.
Fig. 2.4.20 Processing for width of SE0 signal
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REJ09B0178-0300
page 69 of 78
APPLICATION
7534 Group
2.4 USB
(4) USB communication
In applications requiring high-reliability, we recommend providing the system with protective measures
such as USB function initialization by software or USB reset by the host to prevent USB communication
from being terminated unexpectedly, for example due to external causes such as noise.
(5) USB suspend current
When USB suspend mode with TTL level on P10, P12, P1 3 input level selection bit (bit 3 of address
17 16) set to “1”, suspend current as I CC might be greater than 300 µA as a spec.
[Countermeasure]
There are two countermeasures by software to avoid it as follows.
(1) Change from TTL input level to CMOS input level for P1 0, P1 2 , P1 3 port input.
(2) Change from TTL input level to CMOS input level before STP instruction in suspend routine;
then after RESUME or Remote wake up interrupt, return to TTL input level from CMOS input
level. That is shown in Figure 2.4.21.
SUSPEND Routine
Configuration to CMOS input
level for P10, P12, P13 input level.
P1P3C xxxxx0xx2
Configuration to CMOS
input level for P10, P12, P13
input level.
P1P3C xxxxx1xx2
Configuration to TTL input
level for P10, P12, P13 input
level.
P1P3C xxxxx1xx2
Configuration to TTL input
level for P10, P12, P13 input
level.
STP
RESUME Routine
Configuration to TTL input level
for P10, P12, P13 input level.
Remote wake up Routine
Configuration to TTL input level
for P10, P12, P13 input level.
Fig. 2.4.21 Countermeasure (2) by software
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REJ09B0178-0300
page 70 of 78
APPLICATION
7534 Group
2.5 A/D converter
2.5 A/D converter
This paragraph explains the registers setting method and the notes relevant to the A/D converter.
2.5.1 Memory map
003416
A/D control register (ADCON)
003516
A/D conversion register (low-order); (ADL)
003616
A/D conversion register (high-order); (ADH)
003A16 Interrupt edge selection register (INTEDGE)
003C16 Interrupt request register 1 (IREQ1)
003E16 Interrupt control register 1 (ICON1)
Fig. 2.5.1 Memory map of registers relevant to A/D converter
2.5.2 Relevant registers
A/D control register
b7 b6 b5 b4 b3 b2 b1 b0
A/D control register (ADCON) [Address : 3416]
B
0
Function
Name
Analog input pin selection bits
1
2
0
0
1
1
0
0
1
1
0 : P20/AN0
1 : P21/AN1
0 : P22/AN2
1 : P23/AN3
0 : P24/AN4
1 : P25/AN5
0 : P26/AN6
1 : P27/AN7
0
(Note)
(Note)
0
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
AD conversion completion bit 0 : Conversion in progress
1 : Conversion completed
0
✕
1
✽
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
0
✕
6
0
✕
7
0
✕
3
4
5
Note: P26/AN6, P27/AN7 can be selected in the 36-pin and 42-pin versions.
✽: This bit can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.5.2 Structure of A/D control register
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REJ09B0178-0300
R W
0
b2 b1 b0
0
0
0
0
1
1
1
1
At reset
page 71 of 78
APPLICATION
7534 Group
2.5 A/D converter
A/D conversion register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
A/D conversion register (high-order) (ADH) [Address : 3616]
B
Function
At reset
R W
?
✕
?
✕
?
✕
3
?
✕
4
?
✕
5
?
✕
6
?
✕
7
?
✕
0 The read-only register in which the A/D conversion’s results are
stored.
b7
1
< 10-bit read>
b0
b9 b8
2 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
Fig. 2.5.3 Structure of A/D conversion register (high-order)
A/D conversion register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
A/D conversion register (low-order) (ADL) [Address : 3516]
B
Function
At reset
R W
?
✕
?
✕
b0
?
✕
b9 b8 b7 b6 b5 b4 b3 b2
?
✕
< 10-bit read>
?
✕
?
✕
6
?
✕
7
?
✕
0 The read-only register in which the A/D conversion’s results are
stored.
1
2
3
b7
4
b7
5
< 8-bit read>
b7 b6 b5 b4 b3 b2 b1 b0
Fig. 2.5.4 Structure of A/D conversion register (low-order)
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REJ09B0178-0300
page 72 of 78
b0
APPLICATION
7534 Group
2.5 A/D converter
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A
Name
Function
0 INT 0 interrupt edge
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
B
selection bit (Note 1)
1 INT 1 interrupt edge
selection bit ( Note 2)
16]
2 Nothing is allocated for these bits. These are write disabled bits.
At reset
R W
0
0
0
✕
0
✕
When these bits are read out, the values are “0”.
3
4 Serial I/O1 or INT 1 interrupt
0 : Serial I/O1
1 : INT 1
0
: Timer X
Timer
X
or
key-on
wake
up
5
1 : Key-on wake up
interrupt selection bit
6 Timer 2 or serial I/O2 interrupt 0 : Timer 2
selection bit
1 : Serial I/O2
CNTR
0 or AD converter
0 : CNTR 0
7
interrupt selection bit
1 : AD converter
selection bit
0
0
0
0
Notes 1: 32-pin version: Not used.
This is a write disabled bit. When this bit is read out, the value is “0”.
2: 36-pin and 32-pin version: Not used.
This is a write disabled bit. When this bit is read out, the value is “0”.
Fig. 2.5.5 Structure of Interrupt edge selection register
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address : 3C
B
Name
16]
Function
At reset
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
5 Timer 2 or serial I/O2 interrupt 0 : No interrupt request issued
0
✽
6 CNTR 0 or AD converter
0
✽
0
✕
0
1
2
3
4 Timer 1 interrupt request bit
request bit
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
interrupt request bit
7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
✽: These bits can be cleared to “0” by program, but cannot be set.
Notes 1: 36-pin version and 32-pin version: INT1 interrupt does not exist.
2: 32-pin version: INT0 interrupt does not exist.
This is a write disabled bit. When this bit is read out, the value is “0”.
Fig. 2.5.6 Structure of Interrupt request register 1
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
R W
0 : No interrupt request issued
1 : Interrupt request issued
UART receive/USBIN token
interrupt request bit
UART transmit/USBSETUP/
OUT token/Reset/Suspend/
Resume/INT 1 interrupt
request bit (Note 1)
INT 0 interrupt request bit
(Note 2)
Timer X or key-on wake up
interrupt request bit
page 73 of 78
APPLICATION
7534 Group
2.5 A/D converter
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E
B
Name
0
UART receive/USBIN token
interrupt enable bit
UART transmit/USBSETUP/
OUT token/Reset/Suspend/
Resume/INT 1 interrupt enable
bit (Note 1)
INT 0 interrupt enable bit
(Note 2)
Timer X or key-on wake up
interrupt enable bit
1
2
3
4
5
6
7
16]
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
Timer 1 interrupt enable bit
1 : Interrupt enabled
Timer 2 or serial I/O2 interrupt 0 : Interrupt disabled
enable bit
1 : Interrupt enabled
0 : Interrupt disabled
CNTR 0 or AD converter
interrupt enable bit
1 : Interrupt enabled
Nothing is allocated for this bit. Do not write “1” to this bit.
When this bit is read out, the value is “0”.
At reset
0
0
0
0
0
0
0
0
Notes 1: 36-pin version and 32-pin version: INT 1 interrupt does not exist.
2: 32-pin version: INT 0 interrupt does not exist.
This is a write disabled bit. When this bit is read out, the value is “0”.
Fig. 2.5.7 Structure of Interrupt control register 1
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REJ09B0178-0300
page 74 of 78
R W
✕
APPLICATION
7534 Group
2.5 A/D converter
2.5.3 A/D converter application examples
(1) Conversion of analog input voltage
Outline : The analog input voltage from a sensor is converted to digital values.
Figure 2.5.8 shows a connection diagram, and Figure 2.5.9 shows the relevant registers setting.
Sensor
P20/AN0
7534 Group
Fig. 2.5.8 Connection diagram
Specifications : •The analog input voltage from a sensor is converted to digital values.
•P2 0/AN 0 pin is used as an analog input pin.
A/D control register (address 3416)
b7
ADCON
b0
0
0 0 0
Analog input pin : P20/AN0 selected
A/D conversion start
A/D conversion register (high-order); (address 3616)
b7
b0
(Read-only)
ADH
A/D conversion register (low-order); (address 3516)
b7
b0
(Read-only)
ADL
A result of A/D conversion is stored (Note).
Note: After bit 4 of ADCON is set to “1”, read out that contents.
When reading 10-bit data, read address 003616 before address 003516;
when reading 8-bit data, read address 003516 only.
Fig. 2.5.9 Relevant registers setting
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 75 of 78
APPLICATION
7534 Group
2.5 A/D converter
An analog input signal from a sensor is converted to the digital value according to the relevant
registers setting shown by Figure 2.5.9. Figure 2.5.10 shows the control procedure for 8-bit read, and
Figure 2.5.11 shows the control procedure for 10-bit read.
ADCON (address 3416), bit0 – bit2
ADCON (address 3416), bit4
•P20/AN0 pin selected as analog input pin
•A/D conversion start
0002
0
0
ADCON (address 3416), bit4 ?
•Judgment of A/D conversion completion
1
•Read out of conversion result
Read out ADL (address 3516)
Fig. 2.5.10 Control procedure for 8-bit read
ADCON (address 3416), bit0 – bit2
ADCON (address 3416), bit4
•P20/AN0 pin selected as analog input pin
•A/D conversion start
0 0 02
0
0
ADCON (address 3416), bit4 ?
•Judgment of A/D conversion completion
1
Read out ADH (address 3616)
•Read out of high-order digit (b9, b8) of conversion result
Read out ADL (address 3516)
•Read out of low-order digit (b7 – b0) of conversion result
Fig. 2.5.11 Control procedure for 10-bit read
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 76 of 78
APPLICATION
7534 Group
2.5 A/D converter
2.5.4 Notes on A/D converter
(1) Analog input pin
Make the signal source impedance for analog input low, or equip an analog input pin with an external
capacitor of 0.01µF to 1µF. Further, be sure to verify the operation of application products on the
user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A/D conversion/comparison precision to be worse.
(2) Clock frequency during A/D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A/D conversion.
• f(X IN) is 500 kHz or more
• Do not execute the STP instruction
(3) Method to stabilize A/D Converter
Method to stabilize A/D Converter is described below.
(a) A/D conversion accuracy could be affected for Bus Powered*1 USB devices, while the communicating.
Figure 2.5.12 shows the method to stabilize A/D conversion accuracy, inserting a capacitor between
Vref and V SS.
*1: Power supplied by USB V CC BUS.
AN0 to AN7
D-
1.5 kΩ
Vcc
0.01 to 1 µF
USBVREFOUT
0.22 µF
1 µF
7534 Group
CNVss
Vref
1 to 10 kΩ
Vss
0.1 to 1 µF
: Recommends for A/D accuracy
Fig. 2.5.12 Method to stabilize A/D conversion accuracy
(b) It is recommended for A/D accuracy to avoid converting while USB communication, and use
average value of several converted values.
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 77 of 78
APPLICATION
7534 Group
2.6 Reset
2.6 Reset
2.6.1 Connection example of reset IC
Figure 2.6.1 shows the system example to switch to the RAM back-up mode when detecting the falling of
system power source by the INT interrupt.
System power
source
+5V
VCC
+
7
VCC1
RESET 5
2
VCC2
INT
V1
Cd
3
RESET
INT
VSS
1
GND
4
6
7534 Group
M62009L,M62009P,M62009FP
Fig. 2.6.1 Example of poweron reset circuit
2.6.2 Notes on RESET pin
Connecting capacitor
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the V SS pin. Use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
● Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 78 of 78
CHAPTER 3
APPENDIX
3.1 Electrical characteristics
3.2 Typical characteristics
3.3 Notes on use
3.4 Countermeasures against noise
3.5 List of registers
3.6 Package outline
3.7 List of instruction code
3.8 Machine instructions
3.9 SFR memory map
3.10 Pin configurations
APPENDIX
7534 Group
3.1 Electrical characteristics
3.1 Electrical characteristics
3.1.1 Absolute maximum ratings
Table 3.1.1 Absolute maximum ratings
Parameter
Symbol
VCC
Power source voltage
VI
Input voltage
VI
P00–P07, P10–P16, P20–P27, P30–
P37, VREF, P40, P41
Input voltage
RESET, XIN
VI
Input voltage
CNVSS (Note 1)
VO
Output voltage
P00–P07, P10–P16, P20–P27, P30–
P37, XOUT, USBVREFOUT, P40, P41
Pd
Power dissipation
(Note 2)
Conditions
All voltages are
based on VSS.
Output transistors
are cut off.
Ta = 25°C
Ratings
Unit
–0.3 to 7.0
V
–0.3 to VCC + 0.3
V
–0.3 to VCC + 0.3
V
–0.3 to 13
V
–0.3 to VCC + 0.3
V
1000 (Note 3)
mW
°C
°C
Topr
Operating temperature
–20 to 85
Tstg
Storage temperature
–40 to 125
Notes 1: It is a rating only for the One Time PROM version. Connect to VSS for mask ROM version.
2: The rating value depends on packages.
3: This is the value for the 42-pin version.
The value of the 36-pin version is 300 mW.
The value of the 32-pin version is 200 mW.
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 2 of 70
APPENDIX
7534 Group
3.1 Electrical characteristics
3.1.2 Recommended operating conditions
Table 3.1.2 Recommended operating conditions
(VCC = 4.1 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Limits
Parameter
VCC
Power source voltage
VSS
Power source voltage
VREF
Analog reference voltage
VIH
“H” input voltage
P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
VIH
“H” input voltage (TTL input level selected)
P10, P12, P13, P36, P37
VIH
“H” input voltage
RESET, XIN
VIH
“H” input voltage
D+, D-
f(XIN) = 6 MHz
Min.
Typ.
Max.
4.1
5.0
5.5
0
Unit
V
V
2.0
VCC
V
0.8 VCC
VCC
V
2.0
VCC
V
0.8 VCC
VCC
V
2.0
3.6
V
P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
0
0.3 VCC
V
VIL
“L” input voltage
VIL
“L” input voltage (TTL input level selected)
P10, P12, P13, P36, P37
0
0.8
V
VIL
“L” input voltage
RESET, CNVSS
0
0.2 VCC
V
VIL
“L” input voltage
D+, D-
0
0.8
V
VIL
“L” input voltage
XIN
0
0.16VCC
V
I OH(peak)
“H” total peak output current (Note 1)
P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
–80
mA
I OL(peak)
“L” total peak output current (Note 1)
P00–P07, P10–P16, P20–P27,
P37, P40, P41
80
mA
I OL(peak)
“L” total peak output current (Note 1)
P30–P36
60
mA
I OH(avg)
“H” total average output current (Note 1)
P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
–40
mA
I OL(avg)
“L” total average output current (Note 1)
P00–P07, P10–P16, P20–P27,
P37, P40, P41
40
mA
I OL(avg)
“L” total average output current (Note 1)
P30–P36
30
mA
IOH(peak)
“H” peak output current (Note 2)
P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
–10
mA
IOL(peak)
“L” peak output current (Note 2)
P00–P07, P10–P16, P20–P27,
P37 , P40, P41
10
mA
IOL(peak)
“L” peak output current (Note 2)
P30–P36
30
mA
IOH(avg)
“H” average output current (Note 3)
P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
–5
mA
IOL(avg)
“L” average output current (Note 3)
P00–P07, P10–P16, P20–P27,
P37, P40, P41
5
mA
IOL(avg)
“L” average output current (Note 3)
P30–P36
15
mA
f(XIN)
Oscillation frequency (Note 4)
at ceramic oscillation or external clock input
6
MHz
VCC = 4.1 to 5.5 V
Double-speed mode
Note 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average
value measured a term of 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current IOL (avg), IOH (avg) in an average value measured a term of 100 ms.
4: When the oscillation frequency has a duty cycle of 50 %.
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 3 of 70
APPENDIX
7534 Group
3.1 Electrical characteristics
3.1.3 Electrical characteristics
Table 3.1.3 Electrical characteristics (1) (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
VOH
Parameter
“H” output voltage P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41 (Note 1)
Test conditions
Limits
Min.
Typ.
Max.
Unit
IOH = –5 mA
VCC = 4.1 to 5.5 V
VCC–1.5
V
IOH = –1.0 mA
VCC = 4.1 to 5.5 V
VCC–1.0
V
VOH
“H” output voltage D+, D-
VCC = 4.4 to 5.25 V
Pull-down through
15kΩ ±5 % for D+, DPull-up through 1.5kΩ
±5 % by USBVREFOUT
for D- (Ta = 0 to 70 °C)
VOL
“L” output voltage P00–P07, P10–P16, P20–P27,
P37, P40, P41
3.6
V
IOL = 5 mA
VCC = 4.1 to 5.5 V
1.5
V
IOL = 1.5 mA
VCC = 4.1 to 5.5 V
0.3
V
0.3
V
2.8
VOL
“L” output voltage D+, D-
VCC = 4.4 to 5.25 V
Pull-down through
15kΩ ±5 % for D+, DPull-up through 1.5kΩ
±5 % by USBVREFOUT
for D-(Ta = 0 to 70 °C)
VOL
“L” output voltage P30–P36
IOL = 15 mA
VCC = 4.1 to 5.5 V
2.0
V
IOL = 1.5 mA
VCC = 4.1 to 5.5 V
0.3
V
VT+–VT–
Hysteresis
D+, D-
0.15
V
VT+–VT–
Hysteresis
CNTR0, INT0, INT1 (Note 2),
P00–P07(Note 3)
0.4
V
VT+–VT–
Hysteresis
RXD, SCLK, SDATA (Note 2)
0.5
V
VT+–VT–
IIH
Hysteresis
RESET
“H” input current
P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
VI = VCC
(Pin floating. Pull-up
transistors “off”)
5.0
µA
IIH
“H” input current
RESET
VI = VCC
5.0
µA
IIH
“H” input current
XIN
VI = VCC
V
0.5
IIL
“L” input current
P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
VI = VSS
(Pin floating. Pull-up
transistors “off”)
IIL
“L” input current
RESET, CNVSS
VI = VSS
IIL
“L” input current
XIN
VI = VSS
IIL
“L” input current
P00–P07, P30–P37
VI = VSS
(Pull-up transistors“on”)
VRAM
RAM hold voltage
When clock stopped
4
µA
–5.0
µA
–5.0
µA
–4
–0.2
2.0
µA
–0.5
mA
5.5
V
Note 1: P11 is measured when the P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: RXD, SCLK, SDATA, INT0 and INT1 have hystereses only when bits 0, 1 and 2 of the port P1P3 control register are set to “0” (CMOS
level).
3: It is available only when operating key-on wake-up.
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 4 of 70
APPENDIX
7534 Group
3.1 Electrical characteristics
Table 3.1.4 Electrical characteristics (2) (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Power source current
ICC
Limits
Test conditions
Min.
Unit
Typ.
Max.
6
10
mA
f(XIN) = 6 MHz, (in WIT state)
Output transistors “off”
1.6
3.2
mA
Increment when A/D conversion is executed
f(XIN) = 6 MHz, VCC = 5 V
0.8
Double-speed mode, f(XIN) = 6 MHz,
Output transistors “off”
All oscillation stopped (in STP state)
Output transistors “off”
VCC = 4.4 V to 5.25 V
Oscillation stopped in USB mode
USB (SUSPEND), (pull-up resistor
output included) (Fig. 3.1.1)
mA
0.1
Ta = 25 °C
1.0
Ta = 85 °C
µA
10
µA
300
µA
Ta = 0 to 70 °C
3.1.4 A/D converter characteristics
Table 3.1.5 A/D Converter characteristics (1) (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
—
Resolution
—
Linearity error
—
Test conditions
Limits
Min.
Typ.
Max.
10
Unit
Bits
VCC = 4.1 to 5.5 V
Ta = 25 °C
±3
LSB
Differential nonlinear error
VCC = 4.1 to 5.5 V
Ta = 25 °C
±0.9
LSB
VOT
Zero transition voltage
VCC = VREF = 5.12 V
0
5
20
mV
VFST
Full scale transition voltage
VCC = VREF = 5.12 V
5105
5115
5125
mV
tCONV
Conversion time
122
tc(XIN)
RLADDER
Ladder resistor
IVREF
II(AD)
Reference power source input current
A/D port input current
VCC
VCC
USBVREFOUT
1.5 kΩ
D15 kΩ
VSS
IOUT
IOUT is included to this ratings.
Fig. 3.1.1 Power source current measurement circuit in USB
mode at oscillation stop
page 5 of 70
VREF = 5.0 V
50
150
200
VREF = 3.0 V
30
70
120
5.0
ICC
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
kΩ
55
µA
µA
APPENDIX
7534 Group
3.1 Electrical characteristics
3.1.5 Timing requirements
Table 3.1.6 Timing requirements (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
Typ.
Max.
Unit
tW(RESET)
Reset input “L” pulse width
15
µs
tC(XIN)
External clock input cycle time
166
ns
tWH(XIN)
External clock input “H” pulse width
70
ns
tWL(XIN)
External clock input “L” pulse width
70
ns
tC(CNTR)
CNTR0 input cycle time
200
ns
tWH(CNTR)
CNTR0, INT0, INT1 input “H” pulse width
80
ns
tWL(CNTR)
CNTR0, INT0, INT1 input “L” pulse width
80
ns
tC(SCLK)
Serial I/O2 clock input cycle time
1000
ns
ns
Serial I/O2 clock input “H” pulse width
400
tWL(SCLK)
Serial I/O2 clock input “L” pulse width
400
ns
tsu(SDATA–SCLK)
Serial I/O2 input set up time
200
ns
th(SCLK–SDATA)
Serial I/O2 input hold time
200
ns
tWH(SCLK)
3.1.6 Switching characteristics
Table 3.1.7 Switching characteristics (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
tWH(SCLK)
Serial I/O2 clock output “H” pulse width
tC(SCLK)/2–30
tWL(SCLK)
Serial I/O2 clock output “L” pulse width
tC(SCLK)/2–30
td(SCLK–SDATA)
Serial I/O2 output delay time
tv(SCLK–SDATA)
Serial I/O2 output valid time
Typ.
Max.
Unit
ns
ns
140
ns
ns
0
tr(SCLK)
Serial I/O2 clock output rising time
30
ns
tf(SCLK)
Serial I/O2 clock output falling time
30
ns
tr(CMOS)
CMOS output rising time (Note)
10
30
ns
tf(CMOS)
CMOS output falling time (Note)
10
30
ns
tr(D+), tr(D-)
USB output rising time, CL = 200 to 450 pF, Ta = 0 to 70 °C, VCC =
4.4 to 5.25 V
75
150
300
ns
tf(D+), tf(D-)
USB output falling time, CL = 200 to 450 pF, Ta = 0 to 70 °C, VCC =
4.4 to 5.25 V
75
150
300
ns
Notes: XOUT pin is excluded.
Measured
output pin
100 pF
CMOS output
Fig. 3.1.2 Output switching characteristics measurement circuit
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 6 of 70
APPENDIX
7534 Group
3.1 Electrical characteristics
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
CNTR0
0.8VCC
0.2VCC
tWL(INT)
tWH(INT)
0.8VCC
INT0/INT1
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
0.2VCC
tC(SCLK)
tf
SCLK
tWL(SCLK)
tr
tWH(SCLK)
0.8VCC
0.2VCC
tsu(SDATA-SCLK)
th(SCLK-SDATA)
0.8VCC
0.2VCC
SDATA(at receive)
td(SCLK-SDATA)
tv(SCLK-SDATA)
SDATA(at transmit)
tf
D+, D-
0.1V0H
Fig. 3.1.3 Timing chart
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
tr
page 7 of 70
0.9V0H
APPENDIX
7534 Group
3.2 Typical characteristics
3.2 Typical characteristics
3.2.1 Power source current characteristic example (ICC -VCC characteristic)
Measuring condition: Typical sample, Ta = 25 °C, ceramic oscillation, when operating system in double-speed
mode (A/D conversion not executed)
Power source current I CC [mA]
8.0
7.0
6.0
f(X IN ) = 6 MHz
5.0
4.0
3.0
2.0
1.0
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Power source voltage VCC [V]
Fig. 3.2.1 ICC-V CC characteristic example (in double-speed mode)
Measuring condition: Typical sample, Ta = 25 °C, ceramic oscillation, At WIT instruction execution (at wait)
Power source current I CC [mA]
2.5
2.0
f(X IN )=6 MHz
1.5
1.0
0.5
0.0
2.5
3.0
3.5
4.0
4.5
5.0
Power source voltage VCC [V]
Fig. 3.2.2 ICC-V CC characteristic example (at WIT instruction execution)
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REJ09B0178-0300
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5.5
6.0
6.5
APPENDIX
7534 Group
3.2 Typical characteristics
Measuring condition: At STP instruction execution (at stop), Typical sample, Ta = 25 °C
Power source current I CC [nA]
1.5
1.2
0.9
0.6
0.3
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Power source voltage VCC [V]
Fig. 3.2.3 I CC -VCC characteristic example (At STP instruction execution, Ta = 25 °C)
Measuring condition: At STP instruction execution (at stop), Typical sample, Ta = 85 °C
30
Power source current I CC [nA]
25
20
15
10
5
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage VCC [V]
Fig. 3.2.4 I CC -VCC characteristic example (At STP instruction execution, Ta = 85 °C)
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REJ09B0178-0300
page 9 of 70
6.0
6.5
APPENDIX
7534 Group
3.2 Typical characteristics
Measuring condition: At STP instruction execution (at USB suspend)
(output current from USBV REFOUT pin included)
Typical sample, Ta = 25 °C
USBV REFOUT = 3.29 V
Power source current I CC [µA]
270
260
250
240
230
220
210
200
4.0
4.5
5.0
5.5
Power source voltage VCC [V]
Fig. 3.2.5 I CC -V CC characteristic example ( at USB suspend, Ta = 25 °C)
Measuring condition: A/D conversion executed/not executed (f(X IN) = 6MHz, in double-speed mode),
Typical sample, Ta = 25 °C, At ceramic oscillation
Power source current I CC [mA]
8.0
7.0
During A/D conversion
6.0
During not A/D conversion
5.0
4.0
3.0
2.0
1.0
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Power source voltage VCC [V]
Fig. 3.2.6 I CC-VCC characteristic example ( A/D conversion executed/not executed, f(XIN) = 6MHz, in doublespeed mode )
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
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APPENDIX
7534 Group
3.2 Typical characteristics
3.2.2 VOH-I OH characteristic example
Measuring condition: Ta = 25 °C, IOH –VOH characteristics of P-channel (normal port)
(same charactersistics pins: P0 0–P0 7, P1 0–P1 6, P2 0–P27, P3 0–P3 7, P4 0, P4 1)
“H” output current I OH [mA]
-40
-30
-20
V CC = 5.0 V
-10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
“H” output voltage VOH [V]
Fig. 3.2.7 V OH-I OH characteristic example of P-channel (Ta = 25 °C): normal port
Measuring condition: Ta = 85 °C, I OH–V OH characteristics of P-channel (normal port)
(same charactersistics pins: P00–P07, P10–P1 6, P20–P27, P30–P37, P40, P41)
“H” output current I OH [mA]
-40
-30
V CC = 5.0 V
-20
-10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
“H” output voltage VOH [V]
Fig. 3.2.8 V OH-I OH characteristic example of P-channel (Ta = 85 °C): normal port
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REJ09B0178-0300
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4.5
5.0
APPENDIX
7534 Group
3.2 Typical characteristics
Measuring condition: Ta = 25 °C, VOL–I OL characteristics of N-channel (normal port)
(same charactersistics pins: P0 0–P0 7, P10–P1 6, P2 0–P27, P37, P40, P41)
50
“L” output current IOL [mA]
V CC = 5.0 V
40
30
20
V CC = 3.0 V
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
“L” output voltage VOL [V]
Fig. 3.2.9 V OL-IOL characteristic example of N-channel (Ta = 25 °C): Normal port
Measuring condition: Ta = 85 °C, V OL–I OL characteristics of N-channel (normal port)
(same charactersistics pins: P00–P07, P1 0–P16, P20–P27, P3 7, P40, P4 1)
“L” output current IOL [mA]
50
40
V CC = 5.0 V
30
20
V CC = 3.0 V
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
“L” output voltage VOL [V]
Fig. 3.2.10 V OL-IOL characteristic example of N-channel (Ta = 85 °C): Normal port
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APPENDIX
7534 Group
3.2 Typical characteristics
Measuring condition: Ta = 25 °C, V OL–IOL characteristics of N-channel (LED drive port)
(same charactersistics pins: P30–P3 6)
“L” output current I OL [mA]
100
80
V CC = 5.0 V
60
40
V CC = 3.0 V
20
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
“L” output voltage V OL [V]
Fig. 3.2.11 V OL-I OL characteristic example of N-channel (Ta = 25 °C): LED drive port
Measuring condition: Ta = 85 °C, V OL–IOL characteristics of N-channel (LED drive port)
(same charactersistics pins: P3 0–P36)
“L” output current I OL [mA]
100
80
V CC = 5.0 V
60
40
V CC = 3.0 V
20
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
“L” output voltage VOL [V]
Fig. 3.2.12 V OL-I OL characteristic example N-channel (Ta = 85 °C): LED drive port
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4.5
5.0
APPENDIX
7534 Group
3.2 Typical characteristics
Measuring condition: “L” input current of port at pull-up transistor connected
(same charactersistics pins: P0 0–P0 7, P3 0–P3 7)
-500
“L” input current I IL [µA]
-450
Ta = –25 °C
-400
-350
Ta = 25 °C
-300
Ta = 85 °C
-250
-200
-150
-100
-50
0
2.5
3.0
3.5
4.0
4.5
5.0
Power source voltage VCC [V]
Fig. 3.2.13 “L” input current of port at pull-up transistor connected
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APPENDIX
7534 Group
3.2 Typical characteristics
3.2.3 A/D conversion typical characteristics example
(1) Definition of A/D conversion accuracy
The A/D conversion accuracy is defined below (refer to Fig. 3.2.14).
●Relative accuracy
➀ Zero transition voltage (V OT)
This means an analog input voltage when the actual A/D conversion output data changes from
“0” to “1.”
➁ Full-scale transition voltage (V FST)
This means an analog input voltage when the actual A/D conversion output data changes from
“1023” to “1022.”
➂ Non-linearity error
This means a deviation from the line between VOT and VFST of a converted value between VOT and
VFST.
➃ Differential non-linearity error
This means a deviation from the input potential difference required to change a converted value
between V OT and V FST by 1 LSB of the 1 LSB at the relative accuracy.
●Absolute accuracy
This means a deviation from the ideal characteristics between 0 to V REF of actual A/D conversion
characteristics.
Ou tp u t d a ta
Full-scale transition voltage (VFST)
1023
1022
Differential non-linearity error=
c
Non-linearity error= a [LSB]
b-a
a [LSB]
b
a
n+1
n
Actual A/D conversion
characteristics
c
a: 1LSB at relative accuracy
b: Vn+1-Vn
c: Difference between
the ideal Vn and actual Vn
Ideal line of A/D
conversion between
V0 to V1022
1
0
V0
V1
Vn
Zero transition voltage (V0T)
Vn+1
V1022
Analog voltage VREF
Fig. 3.2.14 Definition of A/D conversion accuracy
Vn: Analog input voltage when the output data changes from “n” to “n + 1” (n = 0 to 1022)
V FST – V OT
1022
VREF
• 1 LSB at absolute accuracy →
1024
• 1 LSB at relative accuracy →
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(V)
(V)
APPENDIX
7534 Group
3.2 Typical characteristics
M37534M4-XXXFP A/D CONVERTER STEP WIDTH MEASUREMENT
•V CC = 5 [V]
•V REF = 5 [V]
•X IN = 6 [MHz]
•Temp. = 25 [°C]
•CPU mode = double-speed mode
•Zero transition voltage: 6.714 mV
•Full-scale transition voltage: 4994.812 mV
•Differential non-linearity error: 1.373 mV (0.281 LSB)
•Non-linearity error: –5.201 mV (–1.066 LSB)
7.32
4.88
1LSB WIDTH
2.44
0.00
ERROR
-2.44
-4.88
-7.32
0
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
256
400
416
432
448
464
480
496
512
656
672
688
704
720
736
752
768
912
928
944
960
976
992
1008
1024
STEP
7.32
4.88
2.44
0.00
-2.44
-4.88
-7.32
256
272
288
304
320
336
352
368
384
STEP
7.32
4.88
2.44
0.00
-2.44
-4.88
-7.32
512
528
544
560
576
592
608
624
640
STEP
7.32
4.88
2.44
0.00
-2.44
-4.88
-7.32
768
784
800
816
832
848
864
880
896
STEP
Fig. 3.2.15 A/D conversion typical characteristic example
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APPENDIX
7534 Group
3.3 Notes on use
3.3 Notes on use
3.3.1 Notes on interrupts
(1) Switching external interrupt detection edge
For the products able to switch the external interrupt detection edge, switch it as the following
sequence.
Clear an interrupt enable bit to “0” (interrupt disabled)
↓
Switch the detection edge
↓
Clear an interrupt request bit to “0”
(no interrupt request issued)
↓
Set the interrupt enable bit to “1” (interrupt enabled)
Fig. 3.3.1 Sequence of switch the detection edge
● Reason
The interrupt circuit recognizes the switching of the detection edge as the change of external input
signals. This may cause an unnecessary interrupt.
(2) Check of interrupt request bit
When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request register
immediately after this bit is set to “0” by using a data transfer instruction, execute one or more
instructions before executing the BBC or BBS instruction.
Clear the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Data transfer instruction:
LDM, LDA, STA, STX, and STY instructions
Fig. 3.3.2 Sequence of check of interrupt request bit
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● Reason
If the BBC or BBS instruction is executed
immediately after an interrupt request bit of
an interrupt request register is cleared to
“0”, the value of the interrupt request bit
before being cleared to “0” is read.
APPENDIX
7534 Group
3.3 Notes on use
(3) Structure of interrupt control register 1
Fix the bit 7 of the interrupt control register 1 to “0”. Figure 3.3.3 shows the structure of the interrupt
control register 1.
b7
b0
0
Interrupt control register 1 (address: 003E 16)
Interrupt enable bit
Not used (fix this bit to “0”)
Fig. 3.3.3 Structure of interrupt control register 1
3.3.2 Notes on serial I/O
(1) Handling of serial I/O1 clear
When serial I/O1 is set again or the transmit/receive operation is stopped/restarted while serial I/O1
is operating, clear the serial I/O1 as shown in Figure 3.3.4.
• Serial I/O1 enabled
Handling of clear serial I/O1
○
○
SIO1CON (address 1A 16) bit 7, bit 6 ← 10 2
SIO1CON (address 1A 16) bit 7, bit 6 ← 11 2
• Serial I/O1 cleared
SIO1CON (address 1A 16) bit 7, bit 6 ← 00 2
• Serial I/O1 disabled
UARTCON (address 1B 16)
BRG (address 1C 16)
• Serial I/O1 register set again
→Set again (Note)
• Serial I/O1 enabled
○
○
SIO1CON (address 1A 16) ← 10✕✕✕✕✕✕ 2
Set again (Note)
Note: When the contents of register is not changed, setting again is not necessary.
Fig. 3.3.4 Sequence of clearing serial I/O
(2) Data transmission control with referring to transmit shift register completion flag
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(3) Writing transmit data
When an external clock is used as the synchronous clock for the clock synchronous serial I/O, write
the transmit data to the transmit buffer register (serial I/O shift register) at “H” of the transfer clock
input level.
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APPENDIX
7534 Group
3.3 Notes on use
(4) Serial I/O2 transmit/receive shift completion flag
•The transmit/receive shift completion flag of the serial I/O2 control register is set to “1” after completing
transmit/receive shift. In order to set this flag to “0”, write data (dummy data at reception) to the
serial I/O2 register by program.
•Bit 7 of the serial I/O2 control register is set to “1” a half cycle (of the shift clock) earlier than
completion of shift operation. Accordingly, when using this bit to confirm shift completion, a half
cycle or more of the shift clock must pass after confirming that this bit is set to “1”, before performing
read/write to the serial I/O2 register.
3.3.3 Notes on A/D converter
(1) Analog input pin
Make the signal source impedance for analog input low, or equip an analog input pin with an external
capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application products on the
user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A/D conversion precision to be worse.
(2) Clock frequency during A/D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A/D conversion.
• f(X IN) is 500 kHz or more
• Do not execute the STP instruction
(3) Method to stabilize A/D Converter
Method to stabilize A/D Converter is described below.
(a) A/D conversion accuracy could be affected for Bus Powered*1 USB devices, while the communicating.
Figure 3.3.5 shows the method to stabilize A/D conversion accuracy, inserting a capacitor between
Vref and V SS.
*1: Power supplied by USB V CC BUS.
AN0 to AN7
D-
1.5 kΩ
Vcc
0.01 to 1 µF
USBVREFOUT
0.22 µF
1 µF
7534 Group
CNVss
Vref
1 to 10 kΩ
Vss
0.1 to 1 µF
: Recommends for A/D accuracy
Fig. 3.3.5 Method to stabilize A/D conversion accuracy
(b) It is recommended for A/D accuracy to avoid converting while USB communication, and use
average value of several converted values.
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APPENDIX
7534 Group
3.3 Notes on use
3.3.4 Notes on watchdog timer
The internal reset may not be generated correctly in the middle-speed mode, depending on the
underflow timing of the watchdog timer.
When using the watchdog timer, operate the MCU in any mode other than the middle-speed mode
(i.e., high-speed, low-speed or double-speed mode).
_____________
3.3.5 Notes on RESET pin
(1) Connecting capacitor
_____________
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
_____________
RESET pin and the V SS pin. And use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
● Reason
_____________
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
3.3.6 Notes on input and output pins
(1) Notes in stand-by state
In stand-by state*1 for low-power dissipation, do not make input levels of an input port and an I/O
port “undefined”.
Pull-up (connect the port to V CC ) or pull-down (connect the port to V SS ) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using built-in pull-up or pull-down resistor, note on varied current values:
• When setting as an input port : Fix its input level
• When setting as an output port : Prevent current from flowing out to external
● Reason
The potential which is input to the input buffer in a microcomputer is unstable in the state that input
levels of a input port and an I/O port are “undefined”. This may cause power source current.
* 1 stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
(2) Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction*2, the value of the
unspecified bit may be changed.
● Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
• As for a bit which is set for an input port :
The pin state is read in the CPU, and is written to this bit after bit managing.
• As for a bit which is set for an output port :
The bit value of the port latch is read in the CPU, and is written to this bit after bit managing.
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APPENDIX
7534 Group
3.3 Notes on use
Note the following :
• Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
• As for a bit of the port latch which is set for an input port, its value may be changed even when
not specified with a bit managing instruction in case where the pin state differs from its port latch
contents.
* 2 bit managing instructions : SEB, and CLB instructions
3.3.7 Notes on programming
(1) Processor status register
➀ Initializing of processor status register
Flags which affect program execution must be initialized after a reset.
In particular, it is essential to initialize the T and D flags because they have an important effect
on calculations.
● Reason
After a reset, the contents of the processor status register (PS) are undefined except for the I
flag which is “1”.
Reset
↓
Initializing of flags
↓
Main program
Fig. 3.3.6 Initialization of processor status register
➁ How to reference the processor status register
To reference the contents of the processor status register (PS), execute the PHP instruction once
then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its
original status.
A NOP instruction should be executed after every PLP instruction.
PLP instruction execution
↓
NOP
Fig. 3.3.7 Sequence of PLP instruction execution
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(S)
(S)+1
Stored PS
Fig. 3.3.8 Stack memory contents after PHP
instruction execution
APPENDIX
7534 Group
3.3 Notes on use
(2) Decimal calculations
➀ Execution of decimal calculations
The ADC and SBC are the only instructions which will yield proper decimal notation, set the
decimal mode flag (D) to “1” with the SED instruction. After executing the ADC or SBC instruction,
execute another instruction before executing the SEC, CLC, or CLD instruction.
➁ Notes on status flag in decimal mode
When decimal mode is selected, the values of three of the flags in the status register (the N, V,
and Z flags) are invalid after a ADC or SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared
to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C
flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be
initialized to “1” before each calculation.
Set D flag to “1”
↓
ADC or SBC instruction
↓
NOP instruction
↓
SEC, CLC, or CLD instruction
Fig. 3.3.9 Status flag at decimal calculations
(3) JMP instruction
When using the JMP instruction in indirect addressing mode, do not specify the last address on a
page as an indirect address.
3.3.8 Programming and test of built-in PROM version
As for in the One Time PROM version (shipped in blank), its built-in PROM can be read or programmed
with a general-purpose PROM programmer using a special programming adapter.
The programming test and screening for PROM of the One Time PROM version (shipped in blank) are not
performed in the assembly process and the following processes. To ensure reliability after programming,
performing programming and test according to the Figure 3.3.9 before actual use are recommended.
Programming with PROM programmer
Screening (Caution)
(Leave at 150 °C for 40 hours)
Verification with PROM programmer
Functional check in target device
Caution: The screening temperature is far higher than the
storage temperature. Never expose to 150 °C
exceeding 100 hours.
Fig. 3.3.10 Programming and testing of One Time PROM version
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APPENDIX
7534 Group
3.3 Notes on use
3.3.9 Notes on built-in PROM version
(1) Programming adapter
Use a special programming adapter shown in Table 3.3.1 and a general-purpose PROM programmer
when reading from or programming to the built-in PROM in the built-in PROM version.
Table 3.3.1 Programming adapters
Microcomputer
Programming adapter
M37534E4GP (One Time PROM version shipped in blank)
PCA7435GPG03
M37534E8SP (One Time PROM version shipped in blank)
PCA7435SP, PCA7435SPG02
PCA7435FP, PCA7435FPG02
M37534E8FP (One Time PROM version shipped in blank)
(2) Programming/reading
In PROM mode, operation is the same as that of the M5M27C101AK, but programming conditions
of PROM programmer are not set automatically because there are no internal device ID codes.
Accurately set the following conditions for data programming /reading. Take care not to apply 21 V
to V PP pin (is also used as the CNVSS pin), or the product may be permanently damaged.
• Programming voltage: 12.5 V
• Setting of PROM programmer switch: refer to Table 3.3.2.
Table 3.3.2 PROM programmer address setting
PROM programmer
Product name format
start address
Address
0E08016 (Note 1)
M37534E4GP
M37534E8SP
Address 0C080 16 (Note 2)
M37534E8FP
PROM programmer
end address
Address 0FFFD 16 (Note 1)
Address 0FFFD 16 (Note 2)
Notes 1: Addersses E08016 to FFFD 16 in the built-in PROM corresponds to addresses 0E08016 to 0FFFD16
in the PROM programmer.
2: Addersses C08016 to FFFD16 in the built-in PROM corresponds to addresses 0C08016 to 0FFFD16
in the PROM programmer.
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APPENDIX
7534 Group
3.3 Notes on use
3.3.10 Termination of unused pins
(1) Terminate unused pins
➀ Output ports : Open
➁ Input ports :
Connect each pin to V CC or VSS through each resistor of 1 kΩ to 10 kΩ.
Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. As for pins
whose potential affects to operation modes such as pins CNVSS, INT or others, select the VCC pin
or the VSS pin according to their operation mode.
➂ I/O ports :
• Set the I/O ports for the input mode and connect them to V CC or VSS through each resistor of
1 kΩ to 10 kΩ.
Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/
O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input
mode. With regard to an effects on the system, thoroughly perform system evaluation on the user
side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
(2) Termination remarks
➀ Input ports and I/O ports :
Do not open in the input mode.
● Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➁ and
➂ shown on the above.
➁ I/O ports :
When setting for the input mode, do not connect to V CC or V SS directly.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and V CC (or V SS ).
➂ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to V CC or V SS through
a resistor.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
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APPENDIX
7534 Group
3.3 Notes on use
3.3.11 Notes on CPU mode register
(1) Switching method of CPU mode register after releasing reset
Switch the CPU mode register (CPUM) at the head of program after releasing reset in the following
method.
After releasing reset
Start with an on-chip oscillator (Note)
Wait until ceramic oscillator clock is
stabilized.
Switch the clock division ratio
selection bits (bits 6 and 7 of CPUM)
Switch to other mode except an on-chip oscillator
(Select one of 1/1, 1/2, and 1/8)
Main routine
Note. After releasing reset the operation starts by starting an on-chip oscillator automatically.
Do not use an on-chip oscillator at ordinary operation.
Fig. 3.3.11 Switching method of CPU mode register
3.3.12 Notes on using 32-pin version
• Do not change the P3 5 , P3 6 pull-up control bit of the pull-up control register from the initial value “1”.
• Do not write to “1” to the serial I/O1 or INT1 interrupt selection bit of the interrupt edge selection register.
3.3.13 Electric characteristic differences among mask ROM and One TIme PROM version MCUs
There are differences in electric characteristics, operation margin, noise immunity, and noise radiation
among mask ROM and One Time PROM version MCUs due to the differences in the manufacturing
processes.
When manufacturing an application system with One Time PROM version and then switching to use of the
mask ROM version, perform sufficient evaluations for the commercial samples of the mask ROM version.
3.3.14 Note on power source voltage
When the power source voltage value of a microcomputer is less than the value which is indicated as the
recommended operating conditions, the microcomputer does not operate normally and may perform unstable
operation.
In a system where the power source voltage drops slowly when the power source voltage drops or the
power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended
operating conditions and design a system not to cause errors to the system by this unstable operation.
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APPENDIX
7534 Group
3.3 Notes on use
3.3.15 USB communication
• In applications requiring high-reliability, we recommend providing the system with protective measures
such as USB function initialization by software or USB reset by the host to prevent USB communication
from being terminated unexpectedly, for example due to external causes such as noise.
• When USB suspend mode with TTL level on P10, P12, P13 input level selection bit (bit 3 of address 1716)
set to “1”, suspend current as I CC might be greater than 300 µA as a spec.
[Countermeasure]
There are two countermeasures by software to avoid it as follows.
(1) Change from TTL input level to CMOS input level for P1 0, P1 2 , P1 3 port input.
(2) Change from TTL input level to CMOS input level before STP instruction in suspend routine;
then after RESUME or Remote wake up interrupt, return to TTL input level from CMOS input level.
That is shown in Figure 3.3.12.
SUSPEND Routine
Configuration to CMOS input
level for P10, P12, P13 input level.
P1P3C xxxxx0xx2
Configuration to CMOS
input level for P10, P12, P13
input level.
P1P3C xxxxx1xx2
Configuration to TTL input
level for P10, P12, P13 input
level.
P1P3C xxxxx1xx2
Configuration to TTL input
level for P10, P12, P13 input
level.
STP
RESUME Routine
Configuration to TTL input level
for P10, P12, P13 input level.
Remote wake up Routine
Configuration to TTL input level
for P10, P12, P13 input level.
Fig. 3.3.12 Countermeasure (2) by software
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APPENDIX
7534 Group
3.4 Countermeasures against noise
3.4 Countermeasures against noise
3.4.1 Shortest wiring length
(1) Package
Select the smallest possible package to make the total wiring length short.
● Reason
The wiring length depends on a microcomputer package. Use of a small package, for example
QFP and not DIP, makes the total wiring length short to reduce influence of noise.
DIP
SDIP
SOP
QFP
Fig. 3.4.1 Selection of packages
(2) Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin as short as possible. Especially,
connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within
20mm).
● Reason
The width of a pulse input into the RESET pin is determined by the timing necessary conditions.
If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is completely initialized. This may cause
a program runaway.
Noise
Reset
circuit
RESET
VSS
VSS
N.G.
Reset
circuit
VSS
RESET
VSS
O.K.
Fig. 3.4.2 Wiring for the RESET pin
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APPENDIX
7534 Group
3.4 Countermeasures against noise
(3) Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected
to an oscillator and the V SS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS patterns.
● Reason
If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program
failure or program runaway. Also, if a potential difference is caused by the noise between the V SS
level of a microcomputer and the V SS level of an oscillator, the correct clock will not be input in
the microcomputer.
Noise
XIN
XOUT
VSS
XIN
XOUT
VSS
O.K.
N.G.
Fig. 3.4.3 Wiring for clock I/O pins
(4) Wiring to CNVSS pin
Connect the CNV SS pin to the VSS pin with the shortest possible wiring.
● Reason
The processor mode of a microcomputer is influenced by a potential at the CNV SS pin. If a
potential difference is caused by the noise between pins CNVSS and VSS, the processor mode may
become unstable. This may cause a microcomputer malfunction or a program runaway.
Noise
CNVSS
CNVSS
VSS
VSS
N.G.
Fig. 3.4.4 Wiring for CNV SS pin
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O.K.
APPENDIX
7534 Group
3.4 Countermeasures against noise
(5) Wiring to V PP pin of One Time PROM version
Connect an approximately 5 kΩ resistor to the VPP pin the shortest possible in series and also to the
V SS pin. When not connecting the resistor, make the length of wiring between the V PP pin and the
V SS pin the shortest possible.
Note: Even when a circuit which included an approximately 5 kΩ resistor is used in the Mask ROM
version, the microcomputer operates correctly.
● Reason
The V PP pin of the One Time PROM is the power source input pin for the built-in PROM. When
programming in the built-in PROM, the impedance of the VPP pin is low to allow the electric current
for writing flow into the PROM. Because of this, noise can enter easily. If noise enters the VPP pin,
abnormal instruction codes or data are read from the built-in PROM, which may cause a program
runaway.
Approximately
5kΩ
CNVSS/VPP
VSS
In the shortest
distance
Fig. 3.4.5 Wiring for the VPP pin of the One Time PROM
3.4.2 Connection of bypass capacitor across V SS line and V CC line
Connect an approximately 1.0 µ F bypass capacitor across the V SS line and the V CC line as follows:
• Connect a bypass capacitor across the V SS pin and the VCC pin at equal length.
• Connect a bypass capacitor across the V SS pin and the V CC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for V SS line and V CC line.
• Connect the power source wiring via a bypass capacitor to the V SS pin and the V CC pin.
AA
AA
AA
AA
AA
VCC
VSS
N.G.
AA
AA
AA
AA
AA
VCC
VSS
O.K.
Fig. 3.4.6 Bypass capacitor across the V SS line and the V CC line
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APPENDIX
7534 Group
3.4 Countermeasures against noise
3.4.3 Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog
input pin in series. Besides, connect the resistor to the microcomputer as close as possible.
• Connect an approximately 1000 pF capacitor across the V SS pin and the analog input pin. Besides,
connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog
input pin and the V SS pin at equal length.
● Reason
Signals which is input in an analog input pin (such as an A/D converter/comparator input pin) are
usually output signals from sensor. The sensor which detects a change of event is installed far from
the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily.
This long wiring functions as an antenna which feeds noise into the microcomputer, which causes
noise to an analog input pin.
If a capacitor between an analog input pin and the V SS pin is grounded at a position far away from
the V SS pin, noise on the GND line may enter a microcomputer through the capacitor.
Noise
(Note)
Microcomputer
Analog
input pin
Thermistor
N.G.
O.K.
VSS
Note : The resistor is used for dividing
resistance with a thermistor.
Fig. 3.4.7 Analog signal line and a resistor and a capacitor
3.4.4 Oscillator concerns
Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected
by other signals.
(1) Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a
current larger than the tolerance of current value flows.
● Reason
In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and
thermal heads or others. When a large current flows through those signal lines, strong noise
occurs because of mutual inductance.
Microcomputer
Mutual inductance
M
XIN
XOUT
VSS
Large
current
GND
Fig. 3.4.8 Wiring for a large current signal line
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APPENDIX
7534 Group
3.4 Countermeasures against noise
(2) Installing oscillator away from signal lines where potential levels change frequently
Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential
levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines
which are sensitive to noise.
● Reason
Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect
other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms
may be deformed, which causes a microcomputer failure or a program runaway.
N.G.
Do not cross
CNTR
XIN
XOUT
VSS
Fig. 3.4.9 Wiring of signal lines where potential levels change frequently
(3) Oscillator protection using VSS pattern
As for a two-sided printed circuit board, print a V SS pattern on the underside (soldering side) of the
position (on the component side) where an oscillator is mounted.
Connect the V SS pattern to the microcomputer V SS pin with the shortest possible wiring. Besides,
separate this V SS pattern from other V SS patterns.
An example of VSS patterns on the
underside of a printed circuit board
A
AAA
A
AAA
A
A
AA
AAA
A
A
AA
Oscillator wiring
pattern example
XIN
XOUT
VSS
Separate the VSS line for oscillation from other VSS lines
Fig. 3.4.10 V SS pattern on the underside of an oscillator
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APPENDIX
7534 Group
3.4 Countermeasures against noise
3.4.5 Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an I/O port in series.
<Software>
• As for an input port, read data several times by a program for checking whether input levels are
equal or not.
• As for an output port, since the output data may reverse because of noise, rewrite data to its port
latch at fixed periods.
• Rewrite data to direction registers and pull-up control registers at fixed periods.
Note: When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse
may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise
pulse.
O.K.
Noise
Data bus
Noise
Direction register
N.G.
Port latch
I/O port
pins
Fig. 3.4.11 Setup for I/O ports
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APPENDIX
7534 Group
3.4 Countermeasures against noise
3.4.6 Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer
and the microcomputer can be reset to normal operation. This is equal to or more effective than program
runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer
provided by software.
In the following example, to reset a microcomputer to normal operation, the main routine detects errors of
the interrupt processing routine and the interrupt processing routine detects errors of the main routine.
This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
<The main routine>
• Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value
N in the SWDT once at each execution of the main routine. The initial value N should satisfy the
following condition:
N+1 ≥ ( Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others,
the initial value N should have a margin.
• Watches the operation of the interrupt processing routine by comparing the SWDT contents with
counts of interrupt processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and determines to branch to the program
initialization routine for recovery processing in the following case:
If the SWDT contents do not change after interrupt processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt processing.
• Determines that the main routine operates normally when the SWDT contents are reset to the
initial value N at almost fixed cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch to the program initialization
routine for recovery processing in the following case:
If the SWDT contents are not initialized to the initial value N but continued to decrement and if
they reach 0 or less.
≠N
Main routine
Interrupt processing routine
(SWDT)← N
(SWDT) ← (SWDT)—1
CLI
Interrupt processing
Main processing
(SWDT)
≤0?
>0
RTI
≤0
(SWDT)
=N?
N
Return
Interrupt processing
routine errors
Main routine
errors
Fig. 3.4.12 Watchdog timer by software
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APPENDIX
7534 Group
3.5 List of registers
3.5 List of registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (Pi) (i = 0 to 4) [Address : 00 16, 0216, 04 16, 06 16, 0816]
B
Name
0 Port Pi 0
Function
●
In output mode
Write
Port latch
Read
●
In input mode
Write : Port latch
Read : Value of pins
1 Port Pi1
2 Port Pi2
At reset
R W
?
?
?
3 Port Pi3
?
4 Port Pi4
?
5 Port Pi5
?
6 Port Pi6
?
7 Port Pi7
?
Note: The following ports do not exist, so that the corresponding bits are not used.
• 42-pin version: Ports P1 7, P4 2–P4 7
• 36-pin version: Ports P1 5–P1 7, P3 6, P4 0–P4 7
• 32-pin version: Ports P1 5–P1 7, P2 6, P2 7, P3 5–P3 7, P4 0–P4 7
Fig. 3.5.1 Structure of Port Pi (i = 0 to 4)
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 0 to 4) [Address : 01
B
1
2
3
4
5
6
7
0316, 05 16, 0716, 0916]
Function
Name
0 Port Pi direction register
16,
0 : Port Pi 0 input mode
1 : Port Pi 0 output mode
0 : Port Pi 1 input mode
1 : Port Pi 1 output mode
0 : Port Pi 2 input mode
1 : Port Pi 2 output mode
0 : Port Pi 3 input mode
1 : Port Pi 3 output mode
0 : Port Pi 4 input mode
1 : Port Pi 4 output mode
0 : Port Pi 5 input mode
1 : Port Pi 5 output mode
0 : Port Pi 6 input mode
1 : Port Pi 6 output mode
0 : Port Pi 7 input mode
1 : Port Pi 7 output mode
At reset
R W
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
Note: The following ports do not exist, so that the corresponding bits are not used.
• 42-pin version: Ports P1 7, P42–P4 7
• 36-pin version: Ports P1 5–P17, P36, P4 0–P4 7
• 32-pin version: Ports P1 5–P17, P26, P2 7, P3 5–P3 7, P4 0–P4 7
Fig. 3.5.2 Structure of Port Pi direction register (i = 0 to 4)
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APPENDIX
7534 Group
3.5 List of registers
Pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register (PULL) [Address : 16 16]
Name
B
0 P00 pull-up control bit
1 P01 pull-up control bit
2 P02, P03 pull-up control bit
3 P04 – P07 pull-up control bit
4 P30 – P33 pull-up control bit
5 P34 pull-up control bit
6 P35, P36 pull-up control bit
(Note 2)
7 P37 pull-up control bit
(Note 3)
Function
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
At reset
R W
1
1
1
1
1
1
1
1
Notes 1: Pins set to output are disconnected from the pull-up control.
2: • 36-pin version: P3 6 is not existed.
• 32-pin version: Not used.
3: 32-pin version: Not used.
Fig. 3.5.3 Structure of Pull-up control register
Port P1P3 control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P1P3 control register (P1P3C) [Address : 17
B
Name
0 P37/INT0 input level selection
bit (Note 1)
1 P36/INT1 input level selection
bit (Note 2)
2 P10, P12,P1 3 input level
selection bit
16]
Function
0 : CMOS level
1 : TTL level
0 : CMOS level
1 : TTL level
0 : CMOS level
1 : TTL level
At reset
R W
0
0
0
0
✕
4
0
✕
5
0
✕
6
0
✕
7
0
✕
3 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
Notes 1: For the 32-pin version, nothing is allocated for this bit.
This is a write disabled bit.
When this bit is read out, the value is “0”.
2: For the 32-pin and 36-pin versions, nothing is allocated for this bit.
This is a write disabled bit.
When this bit is read out, the value is “0”.
Fig. 3.5.4 Structure of Port P1P3 control register
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APPENDIX
7534 Group
3.5 List of registers
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB) [Address : 18 16]
B
Function
At reset
0 The transmission data is written to or the receive data is read out
R W
?
from this buffer register.
1 • At writing: A data is written to the transmit buffer register.
?
• At reading: The contents of the receive buffer register are read
out.
2
?
3
?
4
?
5
?
6
?
7
?
Note: The contents of transmit buffer register cannot be read out.
The data cannot be written to the receive buffer register.
Fig. 3.5.5 Structure of Transmit/Receive buffer register
UART status register
b7 b6 b5 b4 b3 b2 b1 b0
UART status register (UARTSTS) [Address : 19 16]
B
Name
0 Transmit buffer empty flag
0 : Buffer full
1 : Buffer empty
0 : Buffer empty
1 : Buffer full
0 : Transmit shift in progress
1 : Transmit shift completed
At reset
R W
1
✕
0
✕
0
✕
3 Overrun error flag (OE)
0
✕
4
0
✕
0
✕
0
✕
1
✕
(TBE)
1 Receive buffer full flag (RBF)
2 Transmit shift register shift
completion flag (TSC)
5
6
7
0 : No error
1 : Overrun error
0 : No error
Parity error flag (PE)
1 : Parity error
0 : No error
Framing error flag (FE)
1 : Framing error
0 : (OE) ∪ (PE) ∪ (FE) = 0
Summing error flag (SE)
1 : (OE) ∪ (PE) ∪ (FE) = 1
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “1”.
Fig. 3.5.6 Structure of UART status register
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Function
page 36 of 70
APPENDIX
7534 Group
3.5 List of registers
Refer to “Figure 2.4.6 Description of register structure” for registers relevant to USB.
USB status register (USBSTS) [Address 19 16]
b7
b6
b5
b4
b3
b2
b1
RxRDY SUME BSTFE
Initial value
0
0
0
PIDE
0
CRCE FEOPE
0
0
b0
EOP
TxRDY
0
1
CPU
RD
CPU
WR
H/W
RD
H/W
WR
Transmit buffer
0: Buffer full
EnaSet/
empty flag
1: Buffer empty
ble
Clear
This bit is set to “1” when data is transferred from buffer to shift register by hardware.
This bit is cleared to “0” by writing to buffer.
Ena- Clear
Set
EOP detection flag
0: Not detected
ble
1: Detect
Setting condition of this flag to “1” is as follows;
• Normal EOP detected by hardware
• False EOP flag (FEOPE) set
• Time is out with EOP not detected at data phase or handshake phase
This bit is cleared to “0” by writing dummy to this register.
False EOP error flag 0: No error
Ena- Clear
Set
1: False EOP error
ble
This bit is set to “1” when the phase is not completed normally.
This bit is cleared to “0” by writing dummy to this register.
CRC error flag
0: No error
Ena- Clear
Set
1: CRC error
ble
This bit is set to “1” when the CRC error occurs at the same timing of EOP detection
flag.
This bit is to “0” cleared by writing dummy to this register.
PID error flag
0: No error
Set
Ena- Clear
1: PID error
ble
Setting condition of this flag to “1” is as follows;
• PID of DATA0 or DATA1 cannot be detected at data phase after OUT or SETUP
token
• ACK PID cannot be received at handshake phase during IN transaction.
This bit is cleared to “0” by writing dummy to this register.
Bit stuffing error flag
0: No error
Set
Ena- Clear
1: Bit stuffing error
ble
This bit is set to “1” when bit stuffing error occurs at data phase or handshake phase.
This bit is cleared to “0” by writing dummy to this register.
Summing error flag
0: No error
Set
Ena- Clear
1: Summing error
ble
This bit is set to “1” when any error of FEOPE, CRCE, PIDE, or BSTFE occurs.
This bit is cleared to “0” by writing dummy to this register.
EnaSet/
Receive buffer full
0: Buffer empty
ble
Clear
flag
1: Buffer full
This bit is set to “1” when data is transferred from shift register to buffer by hardware.
This bit is cleared to “0” by reading from buffer.
Fig. 3.5.7 Structure of USB status register
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APPENDIX
7534 Group
3.5 List of registers
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register (SIO1CON) [Address : 1A
B
16]
Function
Name
0 : f(X IN)
1 : f(X IN)/4
selection bit (CSS)
1 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “1”.
0 : Continuous transmit invalid
2 Continuous transmit valid bit
1 : Continuous transmit valid
0 : Interrupt when transmit buffer
3 Transmit interrupt
has emptied
source selection bit (TIC)
1 : Interrupt when transmit shift
operation is completed
0 BRG count source
4 Transmit enable bit (TE)
5 Receive enable bit (RE)
6 Serial I/O1 enable bit
(SIOE)
1
✕
0
0
0
b7 b6
0
0 : I/O port
1 : Not available
0 : UART mode
1 : USB mode
R W
0
0 : Transmit disabled
1 : Transmit enabled
0 : Receive disabled
1 : Receive enabled
0
0
1
1
7
At reset
0
0
Fig. 3.5.8 Structure of Serial I/O1 control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register (UARTCON) [Address : 1B 16]
B
Name
0 Character length
selection bit (CHAS)
1 Parity enable bit
(PARE)
2 Parity selection bit
(PARS)
3 Stop bit length selection
bit (STPS)
4
P11/TxD P-channel
output disable bit
(POFF)
Function
0 : 8 bits
1 : 7 bits
0 : Parity checking disabled
1 : Parity checking enabled
0 : Even parity
1 : Odd parity
0 : 1 stop bit
1 : 2 stop bits
In output mode
0 : CMOS output
1 : N-channel open-drain
output
At reset
R W
0
0
0
0
0
1
✕
6
1
✕
7
1
✕
5 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “1”.
Fig. 3.5.9 Structure of UART control register
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APPENDIX
7534 Group
3.5 List of registers
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator (BRG) [Address : 1C 16]
B
Function
At reset
0 Set a count value of baud rate generator.
?
1
?
2
?
3
?
4
?
5
?
6
?
7
?
R W
Fig. 3.5.10 Structure of Baud rate generator
Refer to “Figure 2.4.6 Description of register structure” for registers relevant to USB.
USB data toggle synchronization register (TRSYNC) [Address 1D 16]
b7
b6
b5
b4
b3
b2
b1
b0
SQTGL
CPU
RD
Initial value 0
CPU
WR
H/W
RD
H/W
WR
Ena- Clear
Sequence bit toggle 0: No toggle
Set
ble
flag
1: Sequence toggle
Setting condition of this flag to “1” is as follows;
• Setting of handshake for OUT token in EP0PID is ACK, toggle of data PID is
performed normally, and errors do not occur at data phase during OUT and
SETUP transaction.
• When ACK is received during IN transaction.
This bit is cleared to “0” by writing dummy to this register.
Fig. 3.5.11 Structure of USB data toggle synchronization register
USB interrupt source discrimination register 1 (USBIR1) [Address 1E 16 ]
b7
b6
b5
b4
b3
b2
b1
b0
RxEP
CPU
RD
Initial value 0
CPU
WR
Endpoint
0: Endpoint 0 interrupt
Enadetermination flag
1: Endpoint 1 interrupt
ble
This flag is set to “1” when IN token interrupt of endpoint 1 occurs.
This flag is cleared to “0” when IN token interrupt of endpoint 0 occurs.
Writing to this bit is invalid. Do not write “1” to bits 0 to 6.
Fig. 3.5.12 Structure of USB interrupt source discrimination register 1
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H/W
RD
H/W
WR
Set/
Clear
APPENDIX
7534 Group
3.5 List of registers
Refer to “Figure 2.4.6 Description of register structure” for registers relevant to USB.
USB interrupt source discrimination register 2 (USBIR2) [Address 1F 16]
b7
b6
RxPID
OPID
Initial value 0
b5
b4
b3
b2
b1
b0
RSTRQ SPRQ
1
0
CPU
RD
0
CPU
WR
H/W
RD
H/W
WR
Set
Ena- Clear
Suspend request flag 0: No request
ble
1: Suspend request
Suspend request is set to “1” when system enters to state J for 3 ms or more.
Suspend request is cleared to “0” by writing dummy to this register.
Set/
EnaUSB reset request
0: No request
Clear
ble
flag
1: Reset request
USB reset request is set to “1” when the SE0 signal is input for 2.5 µs or more.
USB reset request is cleared to “0” when the SE0 signal is stopped.
Set/
EnaToken PID
0: SETUP interrupt
Clear
ble
determination flag
1: OUT interrupt
This flag is set to “1” during no SETUP transaction.
This flag is cleared to “0” when PID of SETUP is detected.
Set/
EnaToken interrupt flag 0: No request
Clear
ble
1: OUT/SETUP token request
This flag is set to “1” when OUT or SETUP interrupt occurs.
This flag is cleared to “0” after the end of transaction.
Fig. 3.5.13 Structure of USB interrupt source discrimination register 2
USB interrupt control register (USBICON) [Address 20 16]
b7
b6
USBE
TKNE
Initial value 0
b5
b4
RSME RSTE
0
0
0
b3
b2
b1
b0
EP1E
CPU
RD
0
Endpoint 1 enable
0: Endpoint 1 invalid
1: Endpoint 1 valid
CPU
WR
H/W
RD
H/W
WR
Ena- Set/ Use
ble Clear
0:USB reset invalid
USB reset interrupt
Ena- Set/ Use
1:USB reset valid
enable
ble Clear
This flag is invalid in suspend mode (USB reset is always valid in suspend mode).
Resume interrupt
enable
0: Resumue invalid
1: Resume valid
Ena- Set/ Use
ble Clear
Token interrupt
enable
0:Token invalid
1:Token valid
Ena- Set/ Use
ble Clear
Ena- Set/ Use
0:USB invalid
ble Clear
1:USB valid
The internal state can be initialized by clearing this flag to “0”.
The initial values of registers are as follows;
• USB status register [address 19 16] = (01 16)
• USB data toggle synchronization register [address 1D 16] = (7F16)
• USB interrupt source discrimination register 1 [address 1E 16] = (7F16)
• Bits 7, 6 and 2 of USB interrupt source discrimination register 2 [address 1F
= (00xxx0xx 2)
USB enable flag
Fig. 3.5.14 Structure of USB interrupt control register
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 40 of 70
16]
APPENDIX
7534 Group
3.5 List of registers
Refer to “Figure 2.4.6 Description of register structure” for registers relevant to USB.
USB transmit data byte number set register 0 (EP0BYTE) [Address 21 16]
b7
b6
b5
b4
0
0
0
0
b3
b2
b1
b0
EP0BYTE
0
Initial value
0
0
CPU
RD
0
–
Set the number of data byte for
transmitting with endpoint 0
CPU
WR
H/W
RD
H/W
WR
Ena- Set/ Use
ble Clear
Fig. 3.5.15 Structure of USB transmit data byte number set register 0
USB transmit data byte number set register 1 (EP1BYTE) [Address 22 16]
b7
b6
b5
b4
0
0
0
0
Initial value
b3
b2
b1
b0
EP1BYTE
0
0
0
CPU
RD
0
–
Set the number of data byte for
transmitting with endpoint 1
CPU
WR
H/W
RD
H/W
WR
Ena- Set/ Use
Clear
ble
Fig. 3.5.16 Structure of USB transmit data byte number set register 1
USB PID control register 0 (EP0PID) [Address 23 16]
b7
b6
b5
b4
b3
b2
b1
b0
DPID0 SPID0I APID0 SPID0O EP0E
Initial value 0
0
0
0
CPU
RD
0
CPU
WR
H/W
RD
H/W
WR
Endpoint 0 enable
0: Endpoint 0 invalid
Ena- Set/ Use
flag
1: Endpoint 0 valid
Clear
ble
Unexpected IN or OUT transaction can be ignored by clearing to this flag to “0”.
(SETUP transaction cannot be ignored, it is always valid.)
Endpoint 0 PID selection 1✕✕✕: IN token interrupt of DATA 0/1 is valid Ena- Set/ Use
01✕✕: STALL handshake is valid for IN token
flag (OUT STALL)
Clear
ble
00✕✕: NAK handshake is valid for IN token
Endpoint 0 PID selection ✕✕✕1: STALL handshake is valid for OUT
Ena- Set/ Use
flag (OUT ACK)
Clear
ble
token
Endpoint 0 PID selection ✕✕10: ACK handshake is valid for OUT token Ena- Set/ Use
✕✕00: NAK handshake is valid for OUT token
flag (IN STALL)
Clear
ble
Endpoint 0 PID selection
Ena- Set/ Use Clear
flag (IN DATA0/1)
Clear
ble
DPID0 and SPID0I are used to control the response for IN token.
DPID0 is used with the token interrupt enable flag (TKNE).
DPID0 is cleared to “0” automatically by hardware when ACK is received.
SPID0O and APID0 are used to control the response for OUT token.
When DPID0 is changed during token packet, the changed value is valid after end
of token.
✕: it can be set to 0 or 1.
Fig. 3.5.17 Structure of USB PID control register 0
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 41 of 70
APPENDIX
7534 Group
3.5 List of registers
Refer to “Figure 2.4.6 Description of register structure” for registers relevant to USB.
USB PID control register 1 (EP1PID) [Address 24 16]
b7
b6
b5
b4
b3
b2
b1
b0
DPID1 SPID1
Initial value 0
CPU
RD
0
Endpoint 1 PID selection 1✕: IN token interrupt of DATA0/1 is valid
01: STALL handshake is valid for IN token
flag (IN STALL)
CPU
WR
H/W
RD
H/W
WR
Enable Set/
Use
Clear
Endpoint 1 PID selection
Enable Set/ Use Clear
flag (IN DATA0/1)
Clear
DPID1 and SPID1 are used to control the response for IN token.
DPID1 is used with the token interrupt enable flag (TKNE).
DPID1 is cleared to “0” automatically by hardware when ACK is received.
00: NAK handshake is valid for IN token
✕: it can be set to 0 or 1.
Fig. 3.5.18 Structure of USB PID control register 1
USB address register (USBA) [Address 25 16]
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
USBA
0
Initial value
0
0
0
CPU
RD
–
Set an address allocated by the
USB host
CPU
WR
H/W
RD
H/W
WR
Set/ Use
Clear
Fig. 3.5.19 Structure of USB address register
USB sequence bit initialization register (INISQ1) [Address 26 16]
b7
b6
b5
b4
b3
b2
b1
b0
✕
✕
✕
INISQ1
Initial value
✕
✕
✕
✕
✕
CPU
RD
As sequence bit of endpoint 1 is
initialized.
Sequence is initialized by writing dummy.
–
CPU
WR
H/W
RD
H/W
WR
Dummy
Fig. 3.5.20 Structure of USB sequence bit initialization register
USB control register (USBCON) [Address 27 16]
b7
b6
b5
b4
b3
b2
b1
b0
WKUP UVOE
Initial value
0
CPU
RD
0
USBVREFOUT output
valid flag
0: Output off
1: Output on
CPU
WR
H/W
RD
H/W
WR
Set/ Use
Clear
Remote wake up
0: No request
Set Use Clear
request flag
1:Remote wake up request
Remote wake up request (K output) can be set by setting this flag to “1”.
This flag is cleaed to “0” automatically after 10 ms from remote wake up request.
Fig. 3.5.21 Structure of USB control register
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 42 of 70
APPENDIX
7534 Group
3.5 List of registers
Prescaler 12, Prescaler X
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 12 (PRE12) [Address : 28 16]
Prescaler X (PREX) [Address : 2C 16]
B
Function
0 •Set a count value of each prescaler.
•The value set in this register is written to both each prescaler
1 and the corresponding prescaler latch at the same time.
•When this register is read out, the count value of the corres2 ponding prescaler is read out.
At reset
R W
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 3.5.22 Structure of Prescaler 12, Prescaler X
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1 (T1) [Address : 29 16]
B
Function
0 •Set a count value of timer 1.
•The value set in this register is written to both timer 1 and timer 1
1 latch at the same time.
•When this register is read out, the timer 1’s count value is read
2 out.
1
0
0
3
0
4
0
5
0
6
0
7
0
Fig. 3.5.23 Structure of Timer 1
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
At reset
page 43 of 70
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APPENDIX
7534 Group
3.5 List of registers
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2 (T2) [Address : 2A 16]
B
Function
0 •Set a count value of timer 2.
•The value set in this register is written to both timer 2 and timer 2
latch at the same time.
•When this register is read out, the timer 2’s count value is read
2 out.
1
0
0
0
3
0
4
0
5
0
6
0
7
0
Fig. 3.5.24 Structure of Timer 2
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
At reset
page 44 of 70
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APPENDIX
7534 Group
3.5 List of registers
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register (TM) [Address : 2B 16]
B
Function
Name
0 Timer X operating mode bits
1
At reset
b1 b0
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement
mode
R W
0
0
2 CNTR 0 active edge switch bit
The function depends on the
operating mode.
(Refer to Table 3.5.1)
0
3 Timer X count stop bit
0 : Count start
1 : Count stop
0
0
✕
5
0
✕
6
0
✕
7
0
✕
4 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
Fig. 3.5.25 Structure of Timer X mode register
Table 3.5.1 CNTR 0 active edge switch bit function
Timer X operation modes
Timer mode
CNTR 0 active edge switch bit (bit 2 of address 2B 16) contents
“0” CNTR 0 interrupt request occurrence: Falling edge
; No influence to timer count
“1” CNTR 0 interrupt request occurrence: Rising edge
; No influence to timer count
Pulse output mode
“0” Pulse output start: Beginning at “H” level
CNTR 0 interrupt request occurrence: Falling edge
“1” Pulse output start: Beginning at “L” level
CNTR 0 interrupt request occurrence: Rising edge
Event counter mode
“0” Timer X: Rising edge count
CNTR 0 interrupt request occurrence: Falling edge
“1” Timer X: Falling edge count
CNTR 0 interrupt request occurrence: Rising edge
Pulse width measurement mode
“0” Timer X: “H” level width measurement
CNTR 0 interrupt request occurrence: Falling edge
“1” Timer X: “L” level width measurement
CNTR 0 interrupt request occurrence: Rising edge
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
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APPENDIX
7534 Group
3.5 List of registers
Timer X
b7 b6 b5 b4 b3 b2 b1 b0
Timer X (TX) [Address : 2D 16]
B
Function
At reset
R W
1
0 •Set a count value of timer X.
•The value set in this register is written to both timer X and timer X
latch at the same time.
•When this register is read out, the timer X’s count value is read
2 out.
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 3.5.26 Structure of Timer X
Timer count source set register
b7 b6 b5 b4 b3 b2 b1 b0
Timer count source set register (TCSS) [Address : 2E
B
Function
Name
0 Timer X count source
selection bit (Note)
16]
0 : f(X IN) / 16
1 : f(X IN) / 2
1 Nothing is allocated for these bits. These are write disabled bits.
At reset
R W
0
0
✕
2
0
✕
3
0
✕
4
0
✕
5
0
✕
6
0
✕
7
0
✕
When these bits are read out, the values are “0”.
Note: To switch the timer X count source selection bit, stop the timer X count
operation before do that.
Fig. 3.5.27 Structure of Timer count source set register
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 46 of 70
APPENDIX
7534 Group
3.5 List of registers
Serial I/O2 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register (SIO2CON) [Address : 30
B
Function
Name
0 Internal synchronous
clock selection bits
1
2
16]
b2 b1 b0
0
0
0
0
1
1
0
0
1
1
1
1
0 : f(X IN)/8
1 : f(X IN)/16
0 : f(X IN)/32
1 : f(X IN)/64
0 : f(X IN)/128
1 : f(X IN)/256
0
0
0
4
0
6
7
R W
0
3 SDATA pin selection bit
5
0 : I/O port / S DATA input
(Note)
1 : SDATA output
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
Transfer direction selection bit 0 : LSB first
1 : MSB first
0 : External clock (S CLK is input)
SCLK pin selection bit
1 : Internal clock (S CLK is output)
Transmit / receive shift
0 : shift in progress
completion flag
1 : shift completed
At reset
✕
0
0
✕
0
Note: When using it as a S DATA input, set the port P1 3 direction register bit to “0”.
Fig. 3.5.28 Structure of Serial I/O2 control register
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 register (SIO2) [Address : 31 16]
B
Function
0 A shift register for serial transmission and reception.
At reset
?
• At transmitting : Set a transmission data.
1 • At receiving : A reception data is stored.
?
2
?
3
?
4
?
5
?
6
?
7
?
Fig. 3.5.29 Structure of Serial I/O2 register
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 47 of 70
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APPENDIX
7534 Group
3.5 List of registers
A/D control register
b7 b6 b5 b4 b3 b2 b1 b0
A/D control register (ADCON) [Address : 3416]
B
Name
0
Analog input pin selection bits
Function
1
2
0
0
1
1
0
0
1
1
0 : P20/AN0
1 : P21/AN1
0 : P22/AN2
1 : P23/AN3
0 : P24/AN4
1 : P25/AN5
0 : P26/AN6
1 : P27/AN7
0
(Note)
(Note)
0
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
AD conversion completion bit 0 : Conversion in progress
1 : Conversion completed
0
✕
1
✽
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
0
✕
6
0
✕
7
0
✕
3
4
5
Note: P26/AN6, P27/AN7 can be selected in the 36-pin and 42-pin versions.
✽: This bit can be cleared to “0” by program, but cannot be set to “1”.
Fig. 3.5.30 Structure of A/D control register
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
R W
0
b2 b1 b0
0
0
0
0
1
1
1
1
At reset
page 48 of 70
APPENDIX
7534 Group
3.5 List of registers
A/D conversion register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
A/D conversion register (high-order) (ADH) [Address : 3616]
B
Function
At reset
R W
?
✕
?
✕
?
✕
3
?
✕
4
?
✕
5
?
✕
6
?
✕
7
?
✕
0 The read-only register in which the A/D conversion’s results are
stored.
b7
1
< 10-bit read>
b0
b9 b8
2 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
Fig. 3.5.31 Structure of A/D conversion register (high-order)
A/D conversion register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
A/D conversion register (low-order) (ADL) [Address : 3516]
B
Function
At reset
R W
?
✕
?
✕
b0
?
✕
b9 b8 b7 b6 b5 b4 b3 b2
?
✕
< 10-bit read>
?
✕
?
✕
6
?
✕
7
?
✕
0 The read-only register in which the A/D conversion’s results are
stored.
1
2
3
b7
4
b7
5
< 8-bit read>
b7 b6 b5 b4 b3 b2 b1 b0
Fig. 3.5.32 Structure of A/D conversion register (low-order)
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 49 of 70
b0
APPENDIX
7534 Group
3.5 List of registers
MISRG
b7 b6 b5 b4 b3 b2 b1 b0
MISRG [Address : 38 16]
B
Function
Name
0 Oscillation stabilization time
set bit after release of the
STP instruction
At reset
0 : Set “01 16” in timer 1, and
“FF16” in prescaler 12
automatically
1 : Not set automatically
R W
0
0
✕
2
0
✕
3
0
✕
0
✕
5
0
✕
6
0
✕
7
0
✕
1 These are reserved bits. “0”
Do not write “1” to these bits.
4 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
Fig. 3.5.33 Structure of MISRG
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog timer control register (WDTCON) [Address : 39
B
Name
16]
Function
At reset
R W
1
✕
1
1
✕
2
1
✕
3
1
✕
4
1
✕
5
1
✕
0 Watchdog timer H
(The high-order 6 bits are read-only bits.)
6 STP instruction disable bit
7 Watchdog timer H count
source selection bit
0 : STP instruction enabled
1 : STP instruction disabled
0 : Watchdog timer L underflow
1 : f(X IN)/16
Fig. 3.5.34 Structure of Watchdog timer control register
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 50 of 70
0
0
APPENDIX
7534 Group
3.5 List of registers
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A
Name
Function
0 INT 0 interrupt edge
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
B
selection bit (Note 1)
1 INT 1 interrupt edge
selection bit ( Note 2)
16]
At reset
2 Nothing is allocated for these bits. These are write disabled bits.
R W
0
0
0
✕
0
✕
When these bits are read out, the values are “0”.
3
4 Serial I/O1 or INT 1 interrupt
0 : Serial I/O1
1 : INT 1
0 : Timer X
5 Timer X or key-on wake up
1 : Key-on wake up
interrupt selection bit
Timer
2
or
serial
I/O2
interrupt
0 : Timer 2
6
selection bit
1 : Serial I/O2
CNTR
0 or AD converter
0 : CNTR 0
7
interrupt selection bit
1 : AD converter
selection bit
0
0
0
0
Notes 1: 32-pin version: Not used.
This is a write disabled bit. When this bit is read out, the value is “0”.
2: 36-pin and 32-pin version: Not used.
This is a write disabled bit. When this bit is read out, the value is “0”.
Fig. 3.5.35 Structure of Interrupt edge selection register
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register (CPUM) [Address : 3B16]
B
0
Processor mode bits
b1 b0
0
0
1
1
1
2
Function
Name
Stack page selection bit
0 : Single-chip mode
1 : Not available
0 : Not available
1 : Not available
0 : 0 page
1 : 1 page
3 Nothing is allocated for these bits. These are write disabled bits.
4
When these bits are read out, the values are “0”.
(Do not write “1”.)
5
6
Clock division ratio selection
bits
7
Fig. 3.5.36 Structure of CPU mode register
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 51 of 70
b7 b6
0 0 : φ = f(XIN)/2
(high-speedmode)
0 1 : φ = f(XIN)/8
(middle-speed mode)
1 0 : Applied from on-chip oscillator
1 1 : φ = f(XIN)
(double-speed mode)
At reset
R W
0
0
0
0
✕
0
✕
0
✕
0
1
APPENDIX
7534 Group
3.5 List of registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address : 3C
B
Name
16]
Function
At reset
R W
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
5 Timer 2 or serial I/O2 interrupt 0 : No interrupt request issued
0
✽
6 CNTR 0 or AD converter
0
✽
0
✕
0
1
2
3
UART receive/USBIN token
interrupt request bit
UART transmit/USBSETUP/
OUT token/Reset/Suspend/
Resume/INT 1 interrupt
request bit (Note 1)
INT 0 interrupt request bit
(Note 2)
Timer X or key-on wake up
interrupt request bit
4 Timer 1 interrupt request bit
request bit
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
interrupt request bit
7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
✽: These bits can be cleared to “0” by program, but cannot be set.
Notes 1: 36-pin version and 32-pin version: INT1 interrupt does not exist.
2: 32-pin version: INT0 interrupt does not exist.
This is a write disabled bit. When this bit is read out, the value is “0”.
Fig. 3.5.37 Structure of Interrupt request register 1
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E
B
Name
0
UART receive/USBIN token
interrupt enable bit
UART transmit/USBSETUP/
OUT token/Reset/Suspend/
Resume/INT 1 interrupt enable
bit (Note 1)
INT 0 interrupt enable bit
(Note 2)
Timer X or key-on wake up
interrupt enable bit
1
2
3
4
5
6
7
16]
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
Timer 1 interrupt enable bit
1 : Interrupt enabled
Timer 2 or serial I/O2 interrupt 0 : Interrupt disabled
enable bit
1 : Interrupt enabled
0 : Interrupt disabled
CNTR 0 or AD converter
interrupt enable bit
1 : Interrupt enabled
Nothing is allocated for this bit. Do not write “1” to this bit.
When this bit is read out, the value is “0”.
At reset
0
0
0
0
0
0
0
0
Notes 1: 36-pin version and 32-pin version: INT 1 interrupt does not exist.
2: 32-pin version: INT 0 interrupt does not exist.
This is a write disabled bit. When this bit is read out, the value is “0”.
Fig. 3.5.38 Structure of Interrupt control register 1
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 52 of 70
R W
✕
APPENDIX
7534 Group
3.6 Package outline
3.6 Package outline
PRDP0042BA-A
RENESAS Code
PRDP0042BA-A
Previous Code
42P4B
MASS[Typ.]
4.1g
22
1
21
*1
E
42
e1
JEITA Package Code
P-SDIP42-13x36.72-1.78
NOTE)
1.
c
INCLUDE TRIM OFFSET.
D
A
2
*2
*2"
2.
Reference Dimension in Millimeters
Symbol
L
A1
Min Nom Max
e1 14.94 15.24 15.54
D 36.5 36.7 36.9
E 12.85 13.0 13.15
A
5.5
A1 0.51
A2
3.8
bp 0.35 0.45 0.55
b2 0.63 0.73 1.03
b3
0.9 1.0 1.3
c
0.22 0.27 0.34
0°
15°
1.528 1.778 2.028
L
3.0
SEATING PLANE
*3
e
*3
bp
b3
b2
PRSP0036GA-A
JEITA Package Code
P-SSOP36-8.4x15-0.80
RENESAS Code
PRSP0036GA-A
Previous Code
36P2R-A
MASS[Typ.]
0.5g
E
19
*1
HE
36
F
NOTE)
1. DIMENSIONS "*1" AND "*2"
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
1
18
Index mark
c
*2
D
A1
A
A2
*
y
bp
L
e
Detail F
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 53 of 70
Reference
Symbol
D
E
A2
A
A1
bp
c
HE
e
y
L
Min Nom Max
14.8 15.0 15.2
8.2 8.4 8.6
2.0
2.4
0.05
0.35 0.4 0.5
0.13 0.15 0.2
0°
10°
11.63 11.93 12.23
0.65 0.8 0.95
0.15
0.3 0.5 0.7
APPENDIX
7534 Group
3.6 Package outline
PLQP0032GB-A
JEITA Package Code
P-LQFP32-7x7-0.80
RENESAS Code
PLQP0032GB-A
Previous Code
32P6U-A
MASS[Typ.]
0.2g
HD
*1
D
24
17
NOTE)
1.
*
*2"
*
INCLUDE TRIM OFFSET.
16
25
bp
c
*2
E
HE
b1
Reference
Symbol
D
E
A
HD
32
9
ZE
Terminal cross section
E
1
Dimension in Millimeters
Min Nom Max
6.9 7.0 7.1
6.9 7.0 7.1
8.8
8.8
9.0
9.2
0
0.32
0.1
0.2
0.42
8
ZD
Index mark
c
A2
p
A1
A
A1
F
L
b1
c
c1
L1
y
e
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
*3
Detail F
bp
page 54 of 70
e
x
y
ZD
ZE
L
L1
0.35
0.09 0.145 0.20
0.125
0°
8°
0.8
0.20
0.10
0.7
0.7
0.3 0.5 0.7
1.0
APPENDIX
7534 Group
3.7 List of instruction code
3.7 List of instruction code
D7 – D4
D3 – D0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Hexadecimal
notation
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ORA
ABS
ASL
ABS
SEB
0, ZP
0000
0
BRK
BBS
ORA
JSR
IND, X ZP, IND 0, A
—
ORA
ZP
ASL
ZP
BBS
0, ZP
PHP
ORA
IMM
ASL
A
SEB
0, A
—
0001
1
BPL
ORA
IND, Y
CLT
BBC
0, A
—
ORA
ZP, X
ASL
ZP, X
BBC
0, ZP
CLC
ORA
ABS, Y
DEC
A
CLB
0, A
—
0010
2
JSR
ABS
AND
IND, X
JSR
SP
BBS
1, A
BIT
ZP
AND
ZP
ROL
ZP
BBS
1, ZP
PLP
AND
IMM
ROL
A
SEB
1, A
BIT
ABS
0011
3
BMI
AND
IND, Y
SET
BBC
1, A
—
AND
ZP, X
ROL
ZP, X
BBC
1, ZP
SEC
AND
ABS, Y
INC
A
CLB
1, A
ROL
CLB
LDM
AND
ZP ABS, X ABS, X 1, ZP
0100
4
RTI
EOR
IND, X
STP
BBS
2, A
COM
ZP
EOR
ZP
LSR
ZP
BBS
2, ZP
PHA
EOR
IMM
LSR
A
SEB
2, A
JMP
ABS
0101
5
BVC
EOR
IND, Y
—
BBC
2, A
—
EOR
ZP, X
LSR
ZP, X
BBC
2, ZP
CLI
EOR
ABS, Y
—
CLB
2, A
—
0110
6
RTS
ADC
IND, X
—
BBS
3, A
TST
ZP
ADC
ZP
ROR
ZP
BBS
3, ZP
PLA
ADC
IMM
ROR
A
SEB
3, A
JMP
IND
0111
7
BVS
ADC
IND, Y
—
BBC
3, A
—
ADC
ZP, X
ROR
ZP, X
BBC
3, ZP
SEI
ADC
ABS, Y
—
CLB
3, A
—
1000
8
BRA
STA
IND, X
RRF
ZP
BBS
4, A
STY
ZP
STA
ZP
STX
ZP
BBS
4, ZP
DEY
—
TXA
SEB
4, A
STY
ABS
STA
ABS
STX
ABS
SEB
4, ZP
1001
9
BCC
STA
IND, Y
—
BBC
4, A
STY
ZP, X
STA
ZP, X
STX
ZP, Y
BBC
4, ZP
TYA
STA
ABS, Y
TXS
CLB
4, A
—
STA
ABS, X
—
CLB
4, ZP
1010
A
LDY
IMM
LDA
IND, X
LDX
IMM
BBS
5, A
LDY
ZP
LDA
ZP
LDX
ZP
BBS
5, ZP
TAY
LDA
IMM
TAX
SEB
5, A
LDY
ABS
LDA
ABS
LDX
ABS
SEB
5, ZP
1011
B
BCS
JMP
BBC
LDA
IND, Y ZP, IND 5, A
LDY
ZP, X
LDA
ZP, X
LDX
ZP, Y
BBC
5, ZP
CLV
LDA
ABS, Y
TSX
CLB
5, A
1100
C
CPY
IMM
CMP
IND, X
WIT
BBS
6, A
CPY
ZP
CMP
ZP
DEC
ZP
BBS
6, ZP
INY
CMP
IMM
DEX
SEB
6, A
CPY
ABS
1101
D
BNE
CMP
IND, Y
—
BBC
6, A
—
CMP
ZP, X
DEC
ZP, X
BBC
6, ZP
CLD
CMP
ABS, Y
—
CLB
6, A
—
1110
E
CPX
IMM
SBC
IND, X
—
BBS
7, A
CPX
ZP
SBC
ZP
INC
ZP
BBS
7, ZP
INX
SBC
IMM
NOP
SEB
7, A
CPX
ABS
1111
F
BEQ
SBC
IND, Y
—
BBC
7, A
—
SBC
ZP, X
INC
ZP, X
BBC
7, ZP
SED
SBC
ABS, Y
—
CLB
7, A
—
: 3-byte instruction
: 2-byte instruction
: 1-byte instruction
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 55 of 70
ASL
CLB
ORA
ABS, X ABS, X 0, ZP
AND
ABS
EOR
ABS
ROL
ABS
LSR
ABS
SEB
1, ZP
SEB
2, ZP
LSR
CLB
EOR
ABS, X ABS, X 2, ZP
ADC
ABS
ROR
ABS
SEB
3, ZP
ROR
CLB
ADC
ABS, X ABS, X 3, ZP
LDX
CLB
LDY
LDA
ABS, X ABS, X ABS, Y 5, ZP
CMP
ABS
DEC
ABS
SEB
6, ZP
DEC
CLB
CMP
ABS, X ABS, X 6, ZP
SBC
ABS
INC
ABS
SEB
7, ZP
INC
CLB
SBC
ABS, X ABS, X 7, ZP
APPENDIX
7534 Group
3.8 Machine instructions
3.8 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
ADC
(Note 1)
(Note 5)
When T = 0
A←A+M+C
When T = 1
M(X) ← M(X) + M + C
AND
(Note 1)
When TV= 0
A←A M
When T = 1 V
M(X) ← M(X) M
7
ASL
C←
0
←0
IMM
# OP n
A
# OP n
BIT,A,AR
BIT,
# OP n
ZP
# OP n
BIT,ZP,
ZPR
BIT,
# OP n
When T = 0, this instruction adds the contents
M, C, and A; and stores the results in A and C.
When T = 1, this instruction adds the contents
of M(X), M and C; and stores the results in
M(X) and C. When T=1, the contents of A remain unchanged, but the contents of status
flags are changed.
M(X) represents the contents of memory
where is indicated by X.
69 2
2
65 3
2
When T = 0, this instruction transfers the contents of A and M to the ALU which performs a
bit-wise AND operation and stores the result
back in A.
When T = 1, this instruction transfers the contents M(X) and M to the ALU which performs a
bit-wise AND operation and stores the results
back in M(X). When T = 1, the contents of A
remain unchanged, but status flags are
changed.
M(X) represents the contents of memory
where is indicated by X.
29 2
2
25 3
2
06 5
2
This instruction shifts the content of A or M by
one bit to the left, with bit 0 always being set to
0 and bit 7 of A or M always being contained in
C.
0A 2
1
#
BBC
(Note 4)
Ai or Mi = 0?
This instruction tests the designated bit i of M
or A and takes a branch if the bit is 0. The
branch address is specified by a relative address. If the bit is 1, next instruction is
executed.
13 4
+
20i
2
17 5
+
20i
3
BBS
(Note 4)
Ai or Mi = 1?
This instruction tests the designated bit i of the
M or A and takes a branch if the bit is 1. The
branch address is specified by a relative address. If the bit is 0, next instruction is
executed.
03 4
+
20i
2
07 5
+
20i
3
BCC
(Note 4)
C = 0?
This instruction takes a branch to the appointed address if C is 0. The branch address
is specified by a relative address. If C is 1, the
next instruction is executed.
BCS
(Note 4)
C = 1?
This instruction takes a branch to the appointed address if C is 1. The branch address
is specified by a relative address. If C is 0, the
next instruction is executed.
BEQ
(Note 4)
Z = 1?
This instruction takes a branch to the appointed address when Z is 1. The branch
address is specified by a relative address.
If Z is 0, the next instruction is executed.
BIT
A
BMI
(Note 4)
N = 1?
This instruction takes a branch to the appointed address when N is 1. The branch
address is specified by a relative address.
If N is 0, the next instruction is executed.
BNE
(Note 4)
Z = 0?
This instruction takes a branch to the appointed address if Z is 0. The branch address
is specified by a relative address. If Z is 1, the
next instruction is executed.
V
M
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
This instruction takes a bit-wise logical AND of
A and M contents; however, the contents of A
and M are not modified.
The contents of N, V, Z are changed, but the
contents of A, M remain unchanged.
page 56 of 70
24 3
2
APPENDIX
7534 Group
3.8 Machine instructions
Addressing mode
ZP, X
ZP, Y
OP n
# OP n
75 4
ABS
ABS, X
ABS, Y
IND
# OP n
# OP n
# OP n
# OP n
2
6D 4
3 7D 5
3 79 5
35 4
2
2D 4
3 3D 5
3 39 5
16 6
2
0E 6
3 1E 7
3
2C 4
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
Processor status register
ZP, IND
# OP n
IND, X
IND, Y
REL
SP
# OP n
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
# OP n
# OP n
# OP n
3
61 6
2 71 6
2
N
V
•
•
•
•
Z
C
3
21 6
2 31 6
2
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
90 2
2
•
•
•
•
•
•
•
•
B0 2
2
•
•
•
•
•
•
•
•
F0 2
2
•
•
•
•
•
•
•
•
M7 M6 •
•
•
•
Z
•
3
page 57 of 70
#
7
30 2
2
•
•
•
•
•
•
•
•
D0 2
2
•
•
•
•
•
•
•
•
APPENDIX
7534 Group
3.8 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
IMM
OP n
# OP n
00 7
1
BPL
(Note 4)
N = 0?
This instruction takes a branch to the appointed address if N is 0. The branch address
is specified by a relative address. If N is 1, the
next instruction is executed.
BRA
PC ← PC ± offset
This instruction branches to the appointed address. The branch address is specified by a
relative address.
BRK
B←1
(PC) ← (PC) + 2
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
M(S) ← PS
S←S–1
I← 1
PCL ← ADL
PCH ← ADH
When the BRK instruction is executed, the
CPU pushes the current PC contents onto the
stack. The BADRS designated in the interrupt
vector table is stored into the PC.
BVC
(Note 4)
V = 0?
This instruction takes a branch to the appointed address if V is 0. The branch address
is specified by a relative address. If V is 1, the
next instruction is executed.
BVS
(Note 4)
V = 1?
This instruction takes a branch to the appointed address when V is 1. The branch
address is specified by a relative address.
When V is 0, the next instruction is executed.
CLB
Ai or Mi ← 0
This instruction clears the designated bit i of A
or M.
CLC
C←0
This instruction clears C.
18 2
1
CLD
D←0
This instruction clears D.
D8 2
1
CLI
I←0
This instruction clears I.
58 2
1
CLT
T←0
This instruction clears T.
12 2
1
CLV
V←0
This instruction clears V.
B8 2
1
CMP
(Note 3)
When T = 0
A–M
When T = 1
M(X) – M
When T = 0, this instruction subtracts the contents of M from the contents of A. The result is
not stored and the contents of A or M are not
modified.
When T = 1, the CMP subtracts the contents
of M from the contents of M(X). The result is
not stored and the contents of X, M, and A are
not modified.
M(X) represents the contents of memory
where is indicated by X.
COM
M←M
This instruction takes the one’s complement of
the contents of M and stores the result in M.
CPX
X–M
This instruction subtracts the contents of M
from the contents of X. The result is not stored
and the contents of X and M are not modified.
E0 2
CPY
Y–M
This instruction subtracts the contents of M
from the contents of Y. The result is not stored
and the contents of Y and M are not modified.
C0 2
DEC
A ← A – 1 or
M←M–1
This instruction subtracts 1 from the contents
of A or M.
__
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 58 of 70
A
# OP n
BIT, A
# OP n
1B 2
+
20i
C9 2
ZP
# OP n
BIT, ZP
# OP n
#
1F 5
+
20i
2
1
C5 3
2
44 5
2
2
E4 3
2
2
C4 3
2
C6 5
2
2
1A 2
1
APPENDIX
7534 Group
3.8 Machine instructions
Addressing mode
ZP, X
OP n
D5 4
D6 6
ZP, Y
# OP n
2
2
ABS
# OP n
CD 4
ABS, X
# OP n
3 DD 5
ABS, Y
# OP n
3 D9 5
IND
# OP n
3
Processor status register
ZP, IND
# OP n
IND, X
# OP n
C1 6
IND, Y
# OP n
2 D1 6
REL
# OP n
2
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
10 2
2
•
•
•
•
•
•
•
•
80 4
2
•
•
•
•
•
•
•
•
•
•
•
1
•
1
•
•
50 2
2
•
•
•
•
•
•
•
•
70 2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
0
•
•
•
•
•
•
•
•
0
•
•
•
•
0
•
•
•
•
•
•
0
•
•
•
•
•
•
N
•
•
•
•
•
Z
C
N
•
•
•
•
•
Z
•
EC 4
3
N
•
•
•
•
•
Z
C
CC 4
3
N
•
•
•
•
•
Z
C
CE 6
3 DE 7
N
•
•
•
•
•
Z
•
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
3
page 59 of 70
APPENDIX
7534 Group
3.8 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
IMM
# OP n
DEX
X←X–1
This instruction subtracts one from the current CA 2
contents of X.
1
DEY
Y←Y–1
This instruction subtracts one from the current
contents of Y.
88 2
1
EOR
(Note 1)
When T = 0
–M
A←AV
When T = 0, this instruction transfers the contents of the M and A to the ALU which
performs a bit-wise Exclusive OR, and stores
the result in A.
When T = 1, the contents of M(X) and M are
transferred to the ALU, which performs a bitwise Exclusive OR and stores the results in
M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
When T = 1
–M
M(X) ← M(X) V
49 2
A
# OP n
BIT, A
# OP n
2
ZP
# OP n
BIT, ZP
# OP n
45 3
2
E6 5
2
A5 3
2
3C 4
3
INC
A ← A + 1 or
M←M+1
This instruction adds one to the contents of A
or M.
INX
X←X+1
This instruction adds one to the contents of X.
E8 2
1
INY
Y←Y+1
This instruction adds one to the contents of Y.
C8 2
1
JMP
If addressing mode is ABS
PCL ← ADL
PCH ← ADH
If addressing mode is IND
PCL ← M (ADH, ADL)
PCH ← M (ADH, ADL + 1)
If addressing mode is ZP, IND
PCL ← M(00, ADL)
PCH ← M(00, ADL + 1)
This instruction jumps to the address designated by the following three addressing
modes:
Absolute
Indirect Absolute
Zero Page Indirect Absolute
JSR
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
After executing the above,
if addressing mode is ABS,
PCL ← ADL
PCH ← ADH
if addressing mode is SP,
PCL ← ADL
PCH ← FF
If addressing mode is ZP, IND,
PCL ← M(00, ADL)
PCH ← M(00, ADL + 1)
This instruction stores the contents of the PC
in the stack, then jumps to the address designated by the following addressing modes:
Absolute
Special Page
Zero Page Indirect Absolute
LDA
(Note 2)
When T = 0
A←M
When T = 1
M(X) ← M
When T = 0, this instruction transfers the contents of M to A.
When T = 1, this instruction transfers the contents of M to (M(X)). The contents of A remain
unchanged, but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
LDM
M ← nn
This instruction loads the immediate value in
M.
LDX
X←M
This instruction loads the contents of M in X.
A2 2
2
A6 3
2
LDY
Y←M
This instruction loads the contents of M in Y.
A0 2
2
A4 3
2
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 60 of 70
3A 2
A9 2
2
1
#
APPENDIX
7534 Group
3.8 Machine instructions
Addressing mode
ZP, X
OP n
ZP, Y
# OP n
ABS
# OP n
ABS, X
# OP n
ABS, Y
# OP n
55 4
2
4D 4
3 5D 5
3 59 5
F6 6
2
EE 6
3 FE 7
3
B5 4
2
B6 4
B4 4
2
4C 3
3
20 6
3
AD 4
3 BD 5
2 AE 4
AC 4
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
# OP n
3 B9 5
BE 5
3
page 61 of 70
ZP, IND
# OP n
3
3
IND, X
# OP n
3
41 6
6C 5
3
3 BC 5
IND
Processor status register
3 B2 4
2
02 7
2
IND, Y
# OP n
2 51 6
REL
# OP n
SP
# OP n
2
22 5
A1 6
2 B1 6
#
2
2
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
APPENDIX
7534 Group
3.8 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
LSR
7
0→
IMM
# OP n
A
# OP n
This instruction shifts either A or M one bit to
the right such that bit 7 of the result always is
set to 0, and the bit 0 is stored in C.
0
→C
4A 2
NOP
PC ← PC + 1
This instruction adds one to the PC but does EA 2
no otheroperation.
ORA
(Note 1)
When T = 0
A←AVM
When T = 0, this instruction transfers the contents of A and M to the ALU which performs a
bit-wise “OR”, and stores the result in A.
When T = 1, this instruction transfers the contents of M(X) and the M to the ALU which
performs a bit-wise OR, and stores the result
in M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
When T = 1
M(X) ← M(X) V M
BIT, A
# OP n
1
ZP
# OP n
BIT, ZP
# OP n
46 5
2
05 3
2
1
09 2
2
PHA
S←S–1
This instruction pushes the contents of A to
the memory location designated by S, and
decrements the contents of S by one.
48 3
1
PHP
M(S) ← PS
S←S–1
This instruction pushes the contents of PS to
the memory location designated by S and decrements the contents of S by one.
08 3
1
PLA
S←S+1
A ← M(S)
This instruction increments S by one and
stores the contents of the memory designated
by S in A.
68 4
1
PLP
S←S+1
PS ← M(S)
This instruction increments S by one and
stores the contents of the memory location
designated by S in PS.
28 4
1
ROL
7
←
This instruction shifts either A or M one bit left
through C. C is stored in bit 0 and bit 7 is
stored in C.
2A 2
1
26 5
2
This instruction shifts either A or M one bit
right through C. C is stored in bit 7 and bit 0 is
stored in C.
6A 2
1
66 5
2
82 8
2
0
←C ←
ROR
7
C→
RRF
7
→
0
→
0
→
This instruction rotates 4 bits of the M content
to the right.
RTI
S←S+1
PS ← M(S)
S←S+1
PCL ← M(S)
S←S+1
PCH ← M(S)
This instruction increments S by one, and
stores the contents of the memory location
designated by S in PS. S is again incremented
by one and stores the contents of the memory
location designated by S in PC L . S is again
incremented by one and stores the contents of
memory location designated by S in PCH.
40 6
1
RTS
S←S+1
PCL ← M(S)
S←S+1
PCH ← M(S)
(PC) ← (PC) + 1
This instruction increments S by one and
stores the contents of the memory location
d e s i g n a t e d b y S i n P C L. S i s a g a i n
incremented by one and the contents of the
memory location is stored in PC H . PC is
incremented by 1.
60 6
1
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 62 of 70
#
APPENDIX
7534 Group
3.8 Machine instructions
Addressing mode
ZP, X
ZP, Y
OP n
# OP n
56 6
2
15 4
2
ABS
ABS, X
ABS, Y
# OP n
# OP n
# OP n
4E 6
3 5E 7
3
0D 4
3 1D 5
3 19 5
IND
# OP n
3
Processor status register
ZP, IND
# OP n
IND, X
# OP n
01 6
IND, Y
# OP n
2 11 6
REL
# OP n
2
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
0
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
(Value saved in stack)
36 6
2
2E 6
3 3E 7
3
N
•
•
•
•
•
Z
C
76 6
2
6E 6
3 7E 7
3
N
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
(Value saved in stack)
•
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 63 of 70
•
•
•
•
•
•
•
APPENDIX
7534 Group
3.8 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
SBC
(Note 1)
(Note 5)
When T = 0 _
A←A–M–C
When T = 1
_
M(X) ← M(X) – M – C
IMM
# OP n
E9 2
When T = 0, this instruction subtracts the
value of M and the complement of C from A,
and stores the results in A and C.
When T = 1, the instruction subtracts the contents of M and the complement of C from the
contents of M(X), and stores the results in
M(X) and C.
A remain unchanged, but status flag are
changed.
M(X) represents the contents of memory
where is indicated by X.
SEB
Ai or Mi ← 1
This instruction sets the designated bit i of A
or M.
SEC
C←1
This instruction sets C.
38 2
1
SED
D←1
This instruction set D.
F8 2
1
SEI
I←1
This instruction set I.
78 2
1
SET
T←1
This instruction set T.
32 2
1
STA
M←A
This instruction stores the contents of A in M.
The contents of A does not change.
This instruction resets the oscillation control F/
F and the oscillation stops. Reset or interrupt
input is needed to wake up from this mode.
STP
A
# OP n
BIT, A
# OP n
# OP n
2
E5 3
0B 2
+
20i
42 2
ZP
BIT, ZP
# OP n
2
1
0F 5
+
20i
85 4
2
1
STX
M←X
This instruction stores the contents of X in M.
The contents of X does not change.
86 4
2
STY
M←Y
This instruction stores the contents of Y in M.
The contents of Y does not change.
84 4
2
TAX
X←A
This instruction stores the contents of A in X. AA 2
The contents of A does not change.
1
TAY
Y←A
This instruction stores the contents of A in Y.
The contents of A does not change.
1
TST
M = 0?
This instruction tests whether the contents of
M are “0” or not and modifies the N and Z.
64 3
2
TSX
X←S
This instruction transfers the contents of S in BA 2
X.
1
TXA
A←X
This instruction stores the contents of X in A.
8A 2
1
TXS
S←X
This instruction stores the contents of X in S.
9A 2
1
TYA
A←Y
This instruction stores the contents of Y in A.
98 2
1
The WIT instruction stops the internal clock
but not the oscillation of the oscillation circuit
is not stopped.
CPU starts its function after the Timer X over
flows (comes to the terminal count). All registers or internal memory contents except Timer
X will not change during this mode. (Of course
needs VDD).
C2 2
1
WIT
Notes 1
2
3
4
5
:
:
:
:
:
The number of cycles “n” is increased by 3 when T is 1.
The number of cycles “n” is increased by 2 when T is 1.
The number of cycles “n” is increased by 1 when T is 1.
The number of cycles “n” is increased by 2 when branching has occurred.
N, V, and Z flags are invalid in decimal operation mode.
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 64 of 70
A8 2
#
2
APPENDIX
7534 Group
3.8 Machine instructions
Addressing mode
ZP, X
ZP, Y
OP n
# OP n
F5 4
2
95 5
2
2
ABS, X
ABS, Y
IND
# OP n
# OP n
# OP n
# OP n
ED 4
3 FD 5
3 F9 5
3
8D 5
96 5
94 5
ABS
3 9D 6
3 99 6
3
Processor status register
ZP, IND
# OP n
IND, X
IND, Y
REL
# OP n
# OP n
# OP n
E1 6
2 F1 6
2
81 7
2 91 7
2
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
N
V
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
•
•
•
•
1
•
•
•
•
•
•
•
•
1
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2 8E 5
3
•
•
•
•
•
•
•
•
8C 5
3
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 65 of 70
APPENDIX
7534 Group
3.8 Machine instructions
Symbol
Contents
IMP
IMM
A
BIT, A
BIT, A, R
ZP
BIT, ZP
BIT, ZP, R
ZP, X
ZP, Y
ABS
ABS, X
ABS, Y
IND
Implied addressing mode
Immediate addressing mode
Accumulator or Accumulator addressing mode
Accumulator bit addressing mode
Accumulator bit relative addressing mode
Zero page addressing mode
Zero page bit addressing mode
Zero page bit relative addressing mode
Zero page X addressing mode
Zero page Y addressing mode
Absolute addressing mode
Absolute X addressing mode
Absolute Y addressing mode
Indirect absolute addressing mode
ZP, IND
Zero page indirect absolute addressing mode
IND, X
IND, Y
REL
SP
C
Z
I
D
B
T
V
N
Indirect X addressing mode
Indirect Y addressing mode
Relative addressing mode
Special page addressing mode
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
X-modified arithmetic mode flag
Overflow flag
Negative flag
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 66 of 70
Symbol
+
–
V
V
–
V
–
←
X
Y
S
PC
PS
PCH
PCL
ADH
ADL
FF
nn
zz
M
M(X)
M(S)
M(ADH, ADL)
M(00, ADL)
Ai
Mi
OP
n
#
Contents
Addition
Subtraction
Logical OR
Logical AND
Logical exclusive OR
Negation
Shows direction of data flow
Index register X
Index register Y
Stack pointer
Program counter
Processor status register
8 high-order bits of program counter
8 low-order bits of program counter
8 high-order bits of address
8 low-order bits of address
FF in Hexadecimal notation
Immediate value
Zero page address
Memory specified by address designation of any addressing mode
Memory of address indicated by contents of index
register X
Memory of address indicated by contents of stack
pointer
Contents of memory at address indicated by ADH and
ADL, in ADH is 8 high-order bits and ADL is 8 low-order bits.
Contents of address indicated by zero page ADL
Bit i (i = 0 to 7) of accumulator
Bit i (i = 0 to 7) of memory
Opcode
Number of cycles
Number of bytes
APPENDIX
7534 Group
3.9 SFR memory map
3.9 SFR memory map
000016
Port P0 (P0)
002016
USB interrupt control register (USBICON)
000116
Port P0 direction register (P0D)
002116
USB transmit data byte number set register 0 (EP0BYTE)
000216
Port P1 (P1)
002216
USB transmit data byte number set register 1 (EP1BYTE)
000316
Port P1 direction register (P1D)
002316
USBPID control register 0 (EP0PID)
000416
Port P2 (P2)
002416
USBPID control register 1 (EP1PID)
000516
Port P2 direction register (P2D)
002516
USB address register (USBA)
000616
Port P3 (P3)
002616
USB sequence bit initialization register (INISQ1)
000716
Port P3 direction register (P3D)
002716
USB control register (USBCON)
000816
Port P4 (P4)
002816
Prescaler 12 (PRE12)
000916
Port P4 direction register (P4D)
002916
Timer 1 (T1)
000A16
002A16
Timer 2 (T2)
000B16
002B16
Timer X mode register (TM)
000C16
002C16
Prescaler X (PREX)
000D16
002D16
Timer X (TX)
000E16
002E16
Timer count source set register (TCSS)
000F16
002F16
001016
003016
Serial I/O2 control register (SIO2CON)
001116
003116
Serial I/O2 register (SIO2)
001216
003216
001316
003316
001416
003416
A/D control register (ADCON)
001516
003516
A/D conversion register (low-order) (ADL)
A/D conversion register (high-order) (ADH)
001616
Pull-up control register (PULL)
003616
001716
Port P1P3 control register (P1P3C)
003716
001816
Transmit/Receive buffer register (TB/RB)
003816
MISRG
001916
USB status register (USBSTS)/UART status register (UARTSTS)
003916
Watchdog timer control register (WDTCON)
001A16
Serial I/O1 control register (SIO1CON)
003A16
Interrupt edge selection register (INTEDGE)
001B16
UART control register (UARTCON)
003B16
CPU mode register (CPUM)
001C16
Baud rate generator (BRG)
003C16
Interrupt request register 1 (IREQ1)
001D16
USB data toggle synchronization register ( TRSYNC)
003D16
001E16
USB interrupt source discrimination register 1 (USBIR1)
003E16
001F16
USB interrupt source discrimination register 2 (USBIR2)
003F16
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 67 of 70
Interrupt control register 1 (ICON1)
APPENDIX
7534 Group
3.10 Pin configurations
3.10 Pin configurations
(Top view)
P27/AN7
VREF
RESET
CNVSS
Vcc
XIN
XOUT
VSS
1
36
2
35
3
34
4
33
5
6
7
8
9
10
11
12
13
14
15
M37534M4-XXXFP
M37534E8FP
P12/SCLK
P13/SDATA
P14/CNTR0
P20/AN0
P21/AN1
P22/AN2
P23/AN3
P24/AN4
P25/AN5
P26/AN6
32
31
30
29
28
27
26
25
24
23
22
16
21
17
20
18
19
Outline: PRSP0036GA-A
Fig. 3.10.1 M37534M4-XXXFP, M37534E8FP pin configuration
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 68 of 70
P11/TXD/D+
P10/RXD/DP07
P06
P05
P04
P03
P02
P01
P00
USBVREFOUT
P37/INT0
P35(LED5)
P34(LED4)
P33(LED3)
P32(LED2)
P31(LED1)
P30(LED0)
APPENDIX
7534 Group
3.10 Pin configurations
17
18
19
20
21
22
25
16
26
15
27
14
28
29
M37534M4-XXXGP
M37534E4GP
13
12
8
P22/AN2
P23/AN3
P24/AN4
P25/AN5
VREF
RESET
CNVSS
VCC
7
9
6
32
5
10
4
31
3
11
2
30
1
P07
P10/RXD/DP11/TXD/D+
P12/SCLK
P13/SDATA
P14/CNTR0
P20/AN0
P21/AN1
23
24
P06
P05
P04
P03
P02
P01
P00
USBVREFOUT
(Top view)
Outline PLQP0032GB-A
Fig. 3.10.2 M37534M4-XXXGP, M37534E4GP pin configuration
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 69 of 70
P34(LED4)
P33(LED3)
P32(LED2)
P31(LED1)
P30(LED0)
VSS
XOUT
XIN
APPENDIX
7534 Group
3.10 Pin configurations
(Top view)
1
42
2
41
3
40
4
39
5
38
6
37
7
8
9
10
11
12
13
14
15
16
17
M37534RSS
M37534M4-XXXSP
M37534E8SP
P14/CNTR0
P15
P16
P20/AN0
P21/AN1
NC
P22/AN2
P23/AN3
P24/AN4
P25/AN5
P26/AN6
P27/AN7
P40
P41
VREF
RESET
CNVSS
Vcc
XIN
XOUT
VSS
36
35
34
33
32
31
30
29
28
27
26
18
25
19
24
20
23
21
22
Outline 42S1M, PRDP0042BA-A
Fig. 3.10.3 M37534M4-XXXSP, M37534E8SP, M37534RSS pin configuration
Rev.3.00 Oct 23, 2006
REJ09B0178-0300
page 70 of 70
P13/SDATA
P12/SCLK
P11/TXD/D+
P10/RXD/DP07
P06
P05
P04
P03
P02
P01
P00
USBVREFOUT
P37/INT0
P36(LED6)/INT1
P35(LED5)
P34(LED4)
P33(LED3)
P32(LED2)
P31(LED1)
P30(LED0)
7534 Group User’s Manual
REVISION HISTORY
Rev.
Date
Description
Page
Summary
1.00 Nov 24, 2000
–
First edition
1.10 Sep 15, 2001
4
Preface: Home page address revised.
5
BEFORE USING THIS MANUAL: Home page address revised.
2.00
1-8
Table 1 Function description of VSS, VCC revised.
1-9
Fig. 7 “Under development” eliminated.
1-13
“Note on stack page” added.
1-19
1-42
Fig. 17 Ports P36, P37 revised.
NOTES ON PROGRAMMING “Note on Stack Page” added.
1-43
Table 8 32P6U-A added. Name of Programming Adapter revised.
Jun. 21, 2004 All pages
1-42
Words standardized: On-chip oscillator, A/D converter
Electric Characteristic Difference Among Mask ROM and One Time PROM
Version MCUs added.
1-43
Note on Power Source Voltage added.
DATA REQUIRED FOR MASK ORDERS revised.
3-26
3.3.12 Electric Characteristic Difference Among Mask ROM and One Time
PROM Version MCUs,
3.3.13 Note on Power Source Voltage added.
3-53
3.00
Oct. 23, 2006 All pages
32P6U-A revised.
Package names “36P2R-A” → “PRSP0036GA-A” revised
Package names “32P6U-A” → “PLQP0032GB-A” revised
Package names “42P4B” → “PRDP0042BA-A” revised
“USB Spec. Rev.1.1” → “Low-Speed USB2.0 specification” revised
Chapter 1
40
Clock Generating Circuit; “No external resistor is needed .... resistor exists onchip.” → “No external resistor is needed .... depending on conditions.)
Fig. 45; Pulled up added, NOTE added
41
Fig. 48; NOTE 2 added
42
NOTES ON PROGRAMMING; Watchdog Timer added
NOTES ON USE; USB Communication added
43
NOTES ON USE; Note on A/D Converter added
Chapter 2
50
2.4.1 Transfer type: “Hi-Speed function: H.S.” added
69
77
2.4.5; USB Communication added
2.5.4 (3) Method to stabilize A/D Converter added
(1/2)
7534 Group User’s Manual
REVISION HISTORY
Rev.
Date
Description
Page
3.00
Summary
Oct. 23, 2006 Chapter 3
19
3.3.3 (3) Method to stabilize A/D Converter
20
26
3.3.4 Notes on watchdog timer
3.3.15 USB Communication added
53
3.6 Package outline revised
(2/2)
RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER
USER’S MANUAL
7534 Group
Publication Data :
Published by :
Rev.1.00 Nov 24, 2000
Rev.3.00 Oct 23, 2006
Sales Strategic Planning Div.
Renesas Technology Corp.
© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
7534 Group
User’s Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan