RENESAS 3807_03

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 38000 SERIES
3807
Group
User’s Manual
keep safety first in your circuit designs !
● Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury,
fire or property damage. Remember to give due consideration to safety when
making your circuit designs, with appropriate measures such as (i) placement
of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.
Notes regarding these materials
● These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the customer’s
application; they do not convey any license under any intellectual property rights,
or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
● Mitsubishi Electric Corporation assumes no responsibility for any damage, or
infringement of any third-party’s rights, originating in the use of any product
data, diagrams, charts or circuit application examples contained in these materials.
● All information contained in these materials, including product data, diagrams
and charts, represent information on products at the time of publication of these
materials, and are subject to change by Mitsubishi Electric Corporation without
notice due to product improvements or other reasons. It is therefore recommended
that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for the latest product information before
purchasing a product listed herein.
● Mitsubishi Electric Corporation semiconductors are not designed or manufactured
for use in a device or system that is used under circumstances in which human
life is potentially at stake. Please contact Mitsubishi Electric Corporation or an
authorized Mitsubishi Semiconductor product distributor when considering the
use of a product contained herein for any specific purposes, such as apparatus
or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea
repeater use.
● The prior written approval of Mitsubishi Electric Corporation is necessary to
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● If these products or technologies are subject to the Japanese export control
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JAPAN and/or the country of destination is prohibited.
● Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or the
products contained therein.
Preface
This user’s manual describes Mitsubishi’s CMOS 8bit microcomputers 3807 Group.
After reading this manual, the user should have a
through knowledge of the functions and features of
the 3807 Group, and should be able to fully utilize
the product. The manual starts with specifications
and ends with application examples.
For details of software, refer to the “SERIES MELPS
740 <SOFTWARE> USER’S MANUAL.”
For details of development support tools, refer to the
“DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTERS” data book.
BEFORE USING THIS USER’S MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such
as hardware design or software development. Chapter 3 also includes necessary information for systems denelopment.
Be sure to refer to this chapter.
1. Organization
● CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
● CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on setting examples
of related registers.
● CHAPTER 3 APPENDIX
This chapter includes necessary information for systems development using the microcomputer, electric
characteristics, a list of registers, the masking confirmation (mask ROM version), and mark specifications which
are to be submitted when ordering.
2. Structure of register
The figure of each register structure describes its functions, contents at reset, and attributes as follows :
(Note 2)
Bit attributes
Bits
(Note 1)
Contents immediately after reset release
b7 b6 b5 b4 b3 b2 b1 b0
0
CPU mode register (CPUM) [Address : 3B16]
B
0
Name
Function
b1 b0
Processor mode bits
1
0 0 : Single-chip mode
01:
1 0 : Not available
11:
0 : 0 page
1 : 1 page
At reset
R W
0
0
2
Stack page selection bit
3
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
0
✕
0
✕
Fix this bit to “0.”
1
4
5
6
Main clock (XIN-XOUT) stop bit
7
Internal system clock selection bit
: Bit in which nothing is arranged
0 : Operating
1 : Stopped
0 : XIN-XOUT selected
1 : XCIN-XCOUT selected
0
✻
✻
: Bit that is not used for control of the corresponding function
Note 1. Contents immediately after reset release
0••••••“0” at reset release
1••••••“1” at reset release
Undefined••••••Undefined or reset release
✻ ••••••Contents determined by option at reset release
Note 2. Bit attributes••••••The attributes of control register bits are classified into 3 bytes : read-only, write-only
and read and write. In the figure, these attributes are represented as follows :
R••••••Read
••••••Read enabled
✕••••••Read disabled
W••••••Write
••••••Write enabled
✕ ••••••Write disabled
LIST OF GROUPS HAVING THE SIMILAR FUNCTIONS
3807 group, one of the CMOS 8-bit microcomputer 38000 series presented in this user’s manual is provided with
standard functions.
The basic functions of the 3800, 3802, 3806 and 3807 groups having the same functions are shown below. For the
detailed functions of each group, refer to the related data book and user’s manual.
List of groups having the same functions
Group
As of September 1996
3800 group
3802 group
3806 group
3807 group
Pin
(Package type)
64 pin
• 64P4B
• 64P6N-A
• 64P6D-A
64 pin
• 64P4B
• 64P6N-A
80 pin
• 80P6N-A
• 80P6S-A
• 80P6D-A
80 pin
• 80P6N-A
Clock generating circuit
1 circuit
1 circuit
1 circuit
2 circuits
Timer
<8-bit>
Prescaler : 3
Timer : 4
<8-bit>
Prescaler : 3
Timer : 4
<8-bit>
Prescaler : 3
Timer : 4
Timer : 3
<16-bit>
Timer X/Y : 2
Timer A/B : 2
UART or
Clock synchronous ✕ 1
UART or
Clock synchronous ✕ 1
UART or
Clock synchronous ✕ 1
UART or
Clock synchronous ✕ 1
—
Clock synchronous ✕ 1
Clock synchronous ✕ 1
Clock synchronous ✕ 1
A-D converter
—
8-bit ✕ 8-channel
8-bit ✕ 8-channel
8-bit ✕ 13-channel
D-A converter
—
8-bit ✕ 2-channel
8-bit ✕ 2-channel
8-bit ✕ 4-channel
Function
<8-bit>
Serial I/O
Mask
ROM
Memory
type
One Time
PROM
EPROM
RAM
8K 16K 24K 32K
(Note 1)
(Note 1)
✽
(Note 1)
8K
16K
(Note 1)
(Note 1)
24K
32K 12K 16K 24K 32K 48K
(Note 1)
32K
16K — 32K —
8K (Note
1)
—
—
—
— 16K —
—
—
—
32K
384
64
0
32
K
—
384 384 512 640 384 384
(Note 1)
(Note 1)
(Note 3)
(Note 3)
(Note 3)
—
— 24K — 48K
16K
—
—
48K
— (Note
2)
16K
1024 384 384 512 1024 1024
512
(Note 1)
(Note 2)
24
K
(Note 3)
PWM output
Remarks
Notes 1:
2:
3:
✽.
16K
Extended operating temperature version available
High-speed version available
Extended operating temperature version and High-speed version available
ROM expansion
Real time port output
Analog comparator
Watchdog timer
Table of contents
Table of contents
CHAPTER 1. HARDWARE
DESCRIPTION ................................................................................................................................ 1-2
FEATURES ...................................................................................................................................... 1-2
APPLICATION ................................................................................................................................. 1-2
PIN CONFIGURATION ................................................................................................................... 1-2
FUNCTIONAL BLOCK ................................................................................................................... 1-3
PIN DESCRIPTION ......................................................................................................................... 1-4
PART NUMBERING ....................................................................................................................... 1-6
GROUP EXPANSION ..................................................................................................................... 1-7
FUNCTIONAL DESCRIPTION ....................................................................................................... 1-8
Central Processing Unit (CPU) ............................................................................................... 1-8
Memory .................................................................................................................................... 1-12
I/O Ports .................................................................................................................................. 1-14
Interrupts .................................................................................................................................. 1-20
Timers ...................................................................................................................................... 1-23
Serial I/O.................................................................................................................................. 1-41
A-D Converter ......................................................................................................................... 1-47
D-A Converter ......................................................................................................................... 1-48
Analog Comparator ................................................................................................................. 1-49
Watchdog Timer ...................................................................................................................... 1-50
Clock output function ............................................................................................................. 1-51
Reset Circuit ............................................................................................................................ 1-52
Clock Generating Circuit ........................................................................................................ 1-54
Processor Mode ...................................................................................................................... 1-57
NOTES ON PROGRAMMING ..................................................................................................... 1-59
Processor Status Register ..................................................................................................... 1-59
Interrupts .................................................................................................................................. 1-59
Decimal Calculations .............................................................................................................. 1-59
Timers ...................................................................................................................................... 1-59
Multiplication and Division Instructions ................................................................................ 1-59
Ports ......................................................................................................................................... 1-59
Serial I/O.................................................................................................................................. 1-59
A-D Converter ......................................................................................................................... 1-59
D-A Converter ......................................................................................................................... 1-59
Instruction Execution Time .................................................................................................... 1-59
NOTES ON USAGE ..................................................................................................................... 1-60
Handling of Source Pins ........................................................................................................ 1-60
3807 GROUP USER'S MANUAL
i
Table of contents
P3 4 clock output function ....................................................................................................... 1-60
Timer X and timer Y .............................................................................................................. 1-60
EPROM version/One Time PROM version ..........................................................................1-60
DATA REQUIRED FOR MASK ORDERS .................................................................................1-61
ROM PROGRAMMING METHOD ............................................................................................... 1-61
FUNCTIONAL DESCRIPTION SUPPLEMENT ..........................................................................1-62
Interrupt .................................................................................................................................... 1-62
Timing After Interrupt ............................................................................................................. 1-63
A-D Converter ......................................................................................................................... 1-64
CHAPTER 2. APPLICATION
2.1 I/O port ..................................................................................................................................... 2-2
2.1.1 Memory map of I/O port ................................................................................................ 2-2
2.1.2 Related registers ............................................................................................................. 2-3
2.1.3 Handling of unused pins ................................................................................................ 2-5
2.2 Timer ......................................................................................................................................... 2-6
2.2.1 Memory map of timer ..................................................................................................... 2-6
2.2.2 Related registers ............................................................................................................. 2-7
2.2.3 Timer application examples ......................................................................................... 2-14
2.3 Serial I/O ................................................................................................................................ 2-29
2.3.1 Memory map of serial I/O ........................................................................................... 2-29
2.3.2 Related registers ........................................................................................................... 2-30
2.3.3 Serial I/O connection examples .................................................................................. 2-37
2.3.4 Setting of serial I/O transfer data format ................................................................. 2-39
2.3.5 Serial I/O application examples .................................................................................. 2-40
2.4 Real
2.4.1
2.4.2
2.4.3
time output port .......................................................................................................... 2-62
Memory map of real time output port ....................................................................... 2-62
Related registers ........................................................................................................... 2-62
Real time output port application examples ............................................................. 2-67
2.5 A-D converter ........................................................................................................................ 2-80
2.5.1 Memory map of A-D conversion .................................................................................2-80
2.5.2 Related registers ........................................................................................................... 2-81
2.5.3 A-D conversion application example ..........................................................................2-83
2.6 Reset ....................................................................................................................................... 2-87
2.6.1 Connection example of reset IC .................................................................................2-87
2.7 Application circuit example ............................................................................................... 2-88
ii
3807 GROUP USER'S MANUAL
Table of contents
CHAPTER 3. APPENDIX
3.1 Electrical characteristics ...................................................................................................... 3-2
3.1.1 Absolute maximum ratings ............................................................................................ 3-2
3.1.2 Recommended operating conditions............................................................................. 3-3
3.1.3 Electrical characteristics................................................................................................. 3-5
3.1.4 A-D converter characteristics ........................................................................................ 3-7
3.1.5 D-A converter characteristics ........................................................................................ 3-7
3.1.6 Analog comparator characteristics ................................................................................ 3-7
3.1.7 Timing requirements ....................................................................................................... 3-8
3.1.8 Switching characteristics ................................................................................................ 3-9
3.1.9 Timing requirements in memory expansion and microprocessor mode ............... 3-10
3.1.10 Switching characteristics in memory expansion and microprocessor mode ...... 3-10
3.2 Standard characteristics..................................................................................................... 3-17
3.2.1 Power source current characteristic examples ........................................................ 3-17
3.2.2 Port standard characteristic examples ...................................................................... 3-18
3.2.3 Input current standard characteristic examples ....................................................... 3-21
3.2.4 A-D conversion standard characteristics .................................................................. 3-22
3.2.5 D-A conversion standard characteristics .................................................................. 3-23
3.3 Notes on use......................................................................................................................... 3-24
3.3.1 Notes on interrupts ....................................................................................................... 3-24
3.3.2 Notes on the serial I/O1 .............................................................................................. 3-24
3.3.3 Notes on the A-D converter ........................................................................................ 3-25
3.3.4 Notes on the RESET pin ............................................................................................. 3-26
3.3.5 Notes on input and output pins .................................................................................. 3-26
3.3.6 Notes on memory expansion mode and microprocessor mode ............................ 3-27
3.3.7 Notes on built-in PROM ............................................................................................... 3-28
3.4 Countermeasures against noise ....................................................................................... 3-29
3.4.1 Shortest wiring length .................................................................................................. 3-29
3.4.2 Connection of a bypass capacitor across the Vss line and the Vcc line ............ 3-30
3.4.3 Wiring to analog input pins ......................................................................................... 3-31
3.4.4 Consideration for oscillator .......................................................................................... 3-31
3.4.5 Setup for I/O ports ....................................................................................................... 3-32
3.4.6 Providing of watchdog timer function by software .................................................. 3-32
3.5 List of registers .................................................................................................................... 3-34
3.6 Mask ROM ordering method .............................................................................................. 3-56
3.7 Mark specification form ...................................................................................................... 3-58
3.8 Package outline .................................................................................................................... 3-59
3.9 Machine Instructions ........................................................................................................... 3-60
3.10 List of instruction codes .................................................................................................. 3-70
3.11 SFR memory map .............................................................................................................. 3-71
3.12 Pin configuration ................................................................................................................ 3-72
3807 GROUP USER'S MANUAL
iii
List of figures
List of figures
CHAPTER 1 HARDWARE
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Fig.
1 Pin configuration of M38073M4-XXXFP ........................................................................... 1-2
2 Functional block diagram ................................................................................................... 1-3
3 Part numbering .................................................................................................................... 1-6
4 Memory expansion plan ..................................................................................................... 1-7
5 740 Family CPU register structure ................................................................................... 1-8
6 Register push and pop at interrupt generation and subroutine call ............................ 1-9
7 Structure of CPU mode register...................................................................................... 1-11
8 Memory map diagram ....................................................................................................... 1-12
9 Memory map of special function register (SFR) .......................................................... 1-13
10 Structure of Port P2P3 control register ....................................................................... 1-14
11 Structure of Pull-up control register .............................................................................1-14
12 Port block diagram (1) ................................................................................................... 1-17
13 Port block diagram (2) ................................................................................................... 1-18
14 Port block diagram (3) ................................................................................................... 1-19
15 Interrupt control ............................................................................................................... 1-22
16 Structure of interrupt-related registers ........................................................................ 1-22
17 Block diagram of Timer X and Timer Y ...................................................................... 1-27
18 Structure of Timer X mode register, Timer Y mode register, and Timer XY control register ............ 1-28
19 Timing chart of Timer • Event counter mode ............................................................. 1-29
20 Timing chart of Pulse output mode .............................................................................. 1-29
21 Timing chart of Pulse period measurement mode ..................................................... 1-30
22 Timing chart of Pulse width measurement mode ...................................................... 1-30
23 Timing chart of Programmable waveform generating mode ..................................... 1-31
24 Timing chart of Programmable one-shot generating mode ...................................... 1-31
25 Timing chart of PWM mode ........................................................................................... 1-32
26 Structure of Timer 123 mode register ..........................................................................1-33
27 Block diagram of Timer .................................................................................................. 1-33
28 Block diagram of Real time output port ...................................................................... 1-36
29 Structure of Real time output port related register (1) ............................................. 1-37
30 Structure of Real time output port related register (2) ............................................. 1-38
31 8 repeated load mode operation ................................................................................... 1-39
32 6 repeated load mode operation ................................................................................... 1-39
33 5 repeated load mode operation ................................................................................... 1-40
34 One-shot pulse generating mode operation ............................................................... 1-40
35 Block diagram of clock synchronous serial I/O1........................................................ 1-41
36 Operation of clock synchronous serial I/O1 function ................................................ 1-41
37 Block diagram of UART serial I/O1 .............................................................................. 1-42
38 Operation of UART serial I/O1 function ...................................................................... 1-42
39 Structure of Serial I/O1 related register...................................................................... 1-43
40 Structure of Serial I/O2 control register 1, 2 ............................................................. 1-44
41 Block diagram of Serial I/O2 ......................................................................................... 1-45
42 Timing of Serial I/O2 ...................................................................................................... 1-45
43 S CMP2 output operation ................................................................................................... 1-46
44 Structure of A-D control register ................................................................................... 1-47
45 Block diagram of A-D converter ....................................................................................1-47
3807 GROUP USER’S MANUAL
i
List of figures
Fig.
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46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Structure of D-A control register ...................................................................................1-48
Block diagram of D-A converter ....................................................................................1-48
Equivalent connection circuit of D-A converter .......................................................... 1-48
Block diagram of Analog comparator ........................................................................... 1-49
Block diagram of Watchdog timer .................................................................................1-50
Structure of Watchdog timer control register ............................................................. 1-50
Structure of Port P2P3 control register ....................................................................... 1-51
Block diagram of Clock output function ...................................................................... 1-51
Reset circuit example ..................................................................................................... 1-52
Reset sequence ............................................................................................................... 1-52
Internal status at reset ................................................................................................... 1-53
Ceramic resonator circuit ............................................................................................... 1-54
External clock input circuit .............................................................................................1-54
System clock generating circuit block diagram (Single-chip mode) .............................. 1-55
State transitions of system clock ................................................................................................. 1-56
Memory maps in various processor modes ................................................................ 1-57
Structure of CPU mode register ....................................................................................1-57
ONW function timing ....................................................................................................... 1-58
Programming and testing of One Time PROM version ............................................ 1-61
Timing chart after an interrupt occurs ..........................................................................1-63
Time up to execution of the interrupt processing routine ........................................ 1-63
A-D conversion equivalent circuit .................................................................................. 1-65
A-D conversion timing chart .......................................................................................... 1-65
CHAPTER 2 APPLICATION
ii
Fig.
Fig.
Fig.
Fig.
Fig.
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
Memory map of I/O port related registers .................................................................2-2
Structure of Port Pi (i=0, 1, 2, 3, 4, 5, 7, 8) ........................................................... 2-3
Structure of Port Pi direction register (i=0, 1, 2, 3, 4, 5, 7, 8) ............................ 2-3
Structure of Port P6 ..................................................................................................... 2-4
Structure of Port P6 direction register ....................................................................... 2-4
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Fig.
2.2.1 Memory map of timer related registers ......................................................................2-6
2.2.2 Structure of Timer XY control register ....................................................................... 2-7
2.2.3 Structure of Timer X Low-order, Timer X High-order, Timer Y Low-order, Timer Y High-order .... 2-7
2.2.4 Structure of Timer 1, Timer 3 ..................................................................................... 2-8
2.2.5 Structure of Timer 2 ..................................................................................................... 2-8
2.2.6 Structure of Timer X mode register ........................................................................... 2-9
2.2.7 Structure of Timer Y mode register ........................................................................... 2-9
2.2.8 Structure of Timer 123 mode register ..................................................................... 2-11
2.2.9 Structure of Interrupt edge selection register ........................................................ 2-11
2.2.10 Structure of Interrupt request register 1 ............................................................... 2-12
2.2.11 Structure of Interrupt request register 2 ............................................................... 2-12
2.2.12 Structure of Interrupt control register 1 ................................................................ 2-13
2.2.13 Structure of Interrupt control register 2 ................................................................ 2-13
2.2.14 Connection of timers and setting of division ratios [Clock function] ................ 2-15
2.2.15 Setting of related registers [Clock function] ......................................................... 2-16
2.2.16 Control procedure [Clock function] ........................................................................ 2-17
2.2.17 Example of a peripheral circuit ...............................................................................2-18
2.2.18 Connection of the timer and setting of the division ratio [Piezoelectric buzzer output] ........... 2-18
3807 GROUP USER’S MANUAL
List of figures
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2.2.19
2.2.20
2.2.21
2.2.22
2.2.23
2.2.24
2.2.25
2.2.26
2.2.27
2.2.28
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2.3.1 Memory map of serial I/O related registers ........................................................... 2-29
2.3.2 Structure of Transmit/Receive buffer register ........................................................ 2-30
2.3.3 Structure of Serial I/O1 status register ................................................................... 2-30
2.3.4 Structure of Serial I/O1 control register.................................................................. 2-31
2.3.5 Structure of UART control register ........................................................................... 2-31
2.3.6 Structure of Baud rate generator .............................................................................. 2-32
2.3.7 Structure of Serial I/O2 control register 1 .............................................................. 2-32
2.3.8 Structure of Serial I/O2 control register 2 .............................................................. 2-33
2.3.9 Structure of Serial I/O2 register................................................................................ 2-33
2.3.10 Structure of Interrupt edge selection register ...................................................... 2-34
2.3.11 Structure of Interrupt request register 1 ............................................................... 2-35
2.3.12 Structure of Interrupt request register 2 ............................................................... 2-35
2.3.13 Structure of Interrupt control register 1 ................................................................ 2-36
2.3.14 Structure of Interrupt control register 2 ................................................................ 2-36
2.3.15 Serial I/O connection examples (1) ....................................................................... 2-37
2.3.16 Serial I/O connection examples (2) ....................................................................... 2-38
2.3.17 Setting of Serial I/O transfer data format ............................................................. 2-39
2.3.18 Connection diagram [Communication using a clock synchronous serial I/O] .. 2-40
2.3.19 Timing chart [Communication using a clock synchronous serial I/O] ............... 2-40
2.3.20 Setting of related registers at a transmitting side
[Communication using a clock synchronous serial I/O] ................................ 2-41
2.3.21 Setting of related registers at a receiving side
[Communication using a clock synchronous serial I/O] ................................ 2-42
2.3.22 Control procedure at a transmitting side
[Communication using a clock synchronous serial I/O] .................................. 2-43
2.3.23 Control procedure at a receiving side
[Communication using a clock synchronous serial I/O] .................................. 2-44
2.3.24 Connection diagram [Output of serial data] ......................................................... 2-45
2.3.25 Timing chart [Output of serial data] ...................................................................... 2-45
2.3.26 Setting of serial I/O1 related registers [Output of serial data] .......................... 2-46
2.3.27 Setting of serial I/O1 transmission data [Output of serial data]........................ 2-47
2.3.28 Control procedure of serial I/O1 [Output of serial data] .................................... 2-48
2.3.29 Setting of serial I/O2 related registers [Output of serial data] .......................... 2-49
2.3.30 Setting of serial I/O2 transmission data [Output of serial data]........................ 2-50
2.3.31 Control procedure of serial I/O2 [Output of serial data] .................................... 2-51
2.3.32 Connection diagram
[Cyclic transmission or reception of block data between microcomputers].. 2-52
2.3.33 Timing chart
[Cyclic transmission or reception of block data between microcomputers].. 2-53
Fig.
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Fig.
Fig.
Setting of related registers [Piezoelectric buzzer output]................................... 2-19
Control procedure [Piezoelectric buzzer output] .................................................. 2-20
A method for judging if input pulse exists ........................................................... 2-21
Setting of related registers (1) [Measurement of frequency] ............................. 2-22
Setting of related registers (2) [Measurement of frequency] ............................. 2-23
Control procedure [Measurement of frequency]................................................... 2-24
Connection of the timer and setting of the division ratio [Measurement of pulse width] ........... 2-25
Setting of related registers [Measurement of pulse width] ................................ 2-26
Control procedure (1) [Measurement of pulse width] ......................................... 2-27
Control procedure (2) [Measurement of pulse width] ......................................... 2-28
3807 GROUP USER’S MANUAL
iii
List of figures
Fig. 2.3.34 Setting of related registers
[Cyclic transmission or reception of block data between microcomputers] .. 2-53
Fig. 2.3.35 Control in the master unit ....................................................................................... 2-54
Fig. 2.3.36 Control in the slave unit .......................................................................................... 2-55
Fig. 2.3.37 Connection diagram [Communication using UART] ............................................ 2-56
Fig. 2.3.38 Timing chart [Communication using UART] ......................................................... 2-56
Fig. 2.3.39 Setting of related registers at a transmitting side [Communication using UART] ........................ 2-58
Fig. 2.3.40 Setting of related registers at a receiving side [Communication using UART] ............................ 2-59
Fig. 2.3.41 Control procedure at a transmitting side [Communication using UART] .......... 2-60
Fig. 2.3.42 Control procedure at a receiving side [Communication using UART] .............. 2-61
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
2.4.1 Memory map of real time output port related registers ........................................ 2-62
2.4.2 Structure of Real time port register ........................................................................ 2-62
2.4.3 Structure of Real time port control register 0 ........................................................ 2-63
2.4.4 Structure of Real time port control register 1 ........................................................ 2-64
2.4.5 Structure of Real time port control register 2 ........................................................ 2-65
2.4.6 Structure of Real time port control register 3 ........................................................ 2-66
2.4.7 Structure of Timer A Low-order, Timer A High-order, Timer B Low-order, Timer B High-order .. 2-66
2.4.8 Connection diagram .................................................................................................... 2-67
2.4.9 Operation patterns of motor ......................................................................................2-67
2.4.10 Example of timer table for acceleration and deceleration.................................. 2-68
2.4.11 Example of operation pattern table ....................................................................... 2-69
2.4.12 Example of output data table .................................................................................. 2-69
2.4.13 Timing of Real time output ......................................................................................2-70
2.4.14 Setting method and output timing ..........................................................................2-71
2.4.15 Setting of related registers (1) ................................................................................ 2-72
2.4.16 Setting of related registers (2) ................................................................................ 2-73
2.4.17 Setting of related registers (3) ................................................................................ 2-74
2.4.18 Setting of related registers (4) ................................................................................ 2-75
2.4.19 Control procedure (1) ............................................................................................... 2-76
2.4.20 Control procedure (2) ............................................................................................... 2-77
2.4.21 Control procedure (3) ............................................................................................... 2-78
2.4.22 Control procedure (4) ............................................................................................... 2-79
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
2.5.1 Memory map of A-D conversion related registers ................................................. 2-80
2.5.2 Structure of A-D control register ...............................................................................2-81
2.5.3 Structure of A-D conversion register ....................................................................... 2-81
2.5.4 Structure of Interrupt request register 2 ................................................................. 2-82
2.5.5 Structure of Interrupt control register 2 .................................................................. 2-82
2.5.6 Connection diagram [Read for analog signal using an internal trigger] ............. 2-83
2.5.7 Setting of related registers [Read for analog signal using an internal trigger] . 2-83
2.5.8 Control procedure [Read for analog signal using an internal trigger] ................ 2-84
2.5.9 Connection diagram [Read for analog signal using an external trigger] ............ 2-85
2.5.10 Setting of related registers [Read for analog signal using an external trigger] ................. 2-85
2.5.11 Control procedure [Read for analog signal using an external trigger] ............. 2-86
Fig. 2.6.1 Example of Poweron reset circuit .............................................................................2-87
Fig. 2.6.2 RAM back-up system ................................................................................................. 2-87
Fig. 2.7.1 Hot water supply system application example ....................................................... 2-89
Fig. 2.7.2 CD changer (car audio) application example ......................................................... 2-90
Fig. 2.7.3 Hot water washing toilet seat application example ............................................... 2-91
iv
3807 GROUP USER’S MANUAL
List of figures
CHAPTER 3 APPENDIX
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
Circuit for measuring output switching characteristics (1) .................................... 3-11
Circuit for measuring output switching characteristics (2) .................................... 3-11
Timing diagram (1) (in single-chip mode) .............................................................. 3-12
Timing diagram (2) (in memory expansion mode and microprocessor mode) .. 3-13
Timing diagram (3) (in memory expansion mode and microprocessor mode) .. 3-14
Timing diagram (4) (in memory expansion mode and microprocessor mode) .. 3-15
Timing diagram (5) (in memory expansion mode and microprocessor mode) .. 3-16
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
3.2.1 Power source current characteristic example ........................................................ 3-17
3.2.2 Power source current characteristic example (in wait mode) .............................. 3-17
3.2.3 Standard characteristic example of CMOS output port at P-channel drive(1) .. 3-18
3.2.4 Standard characteristic example of CMOS output port at P-channel drive(2) .. 3-18
3.2.5 Standard characteristic example of CMOS output port at N-channel drive(1) .. 3-19
3.2.6 Standard characteristic example of CMOS output port at N-channel drive(2) .. 3-19
3.2.7 Standard characteristic example of CMOS output port at N-channel drive(3) .. 3-20
3.2.8 Standard characteristic example of CMOS output port at N-channel drive(4) .. 3-20
3.2.9 Standard characteristic example of input current at connecting pull-up transistor (1) .................. 3-21
3.2.10 Standard characteristic example of input current at connecting pull-up transistor (2) ................ 3-21
3.2.11 A-D conversion standard characteristics .............................................................. 3-22
3.2.12 D-A conversion standard characteristics .............................................................. 3-23
Fig. 3.3.1 Structure of interrupt control register 2 .................................................................. 3-24
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
Wiring for the RESET pin .......................................................................................... 3-29
Wiring for clock I/O pins ............................................................................................ 3-30
Wiring for the VPP pin of the One Time PROM and the EPROM version ........ 3-30
Bypass capacitor across the VSS line and the V CC line ...................................... 3-30
Analog signal line and a resistor and a capacitor ................................................ 3-31
Wiring for a large current signal line ...................................................................... 3-31
Wiring to a signal line where potential levels change frequently........................ 3-31
Setup for I/O ports ..................................................................................................... 3-32
Watchdog timer by software ...................................................................................... 3-32
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
3.5.1 Structure of Port Pi (i=0, 1, 2, 3, 4, 5, 7, 8) ......................................................... 3-34
3.5.2 Structure of Port Pi direction register (i=0, 1, 2, 3, 4, 5, 7, 8) .......................... 3-34
3.5.3 Structure of Port P6 ................................................................................................... 3-35
3.5.4 Structure of Port P6 direction register .................................................................... 3-35
3.5.5 Structure of Timer XY control register .................................................................... 3-36
3.5.6 Structure of Port P2P3 control register .................................................................. 3-36
3.5.7 Structure of Pull-up control register ........................................................................ 3-37
3.5.8 Structure of Watchdog timer control register ......................................................... 3-37
3.5.9 Structure of Transmit/Receive buffer register ........................................................ 3-38
3.5.10 Structure of Serial I/O1 status register ................................................................. 3-38
3.5.11 Structure of Serial I/O1 control register ............................................................... 3-39
3.5.12 Structure of UART control register ........................................................................ 3-39
3.5.13 Structure of Baud rate generator............................................................................ 3-40
3.5.14 Structure of Serial I/O2 control register 1 ............................................................ 3-40
3.5.15 Structure of Serial I/O2 control register 2 ............................................................ 3-41
3.5.16 Structure of Serial I/O2 register .............................................................................3-41
3.5.17 Structure of Timer X Low-order, Timer X High-order, Timer Y Low-order, Timer Y High-order 3-42
3807 GROUP USER’S MANUAL
v
List of figures
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
vi
3.5.18
3.5.19
3.5.20
3.5.21
3.5.22
3.5.23
3.5.24
3.5.25
3.5.26
3.5.27
3.5.28
3.5.29
3.5.30
3.5.31
3.5.32
3.5.33
3.5.34
3.5.35
3.5.35
3.5.36
3.5.36
Structure of Timer 1, Timer 3 .................................................................................3-42
Structure of Timer 2 ................................................................................................. 3-43
Structure of Timer X mode register ...................................................................... 3-44
Structure of Timer Y mode register ...................................................................... 3-44
Structure of Timer 123 mode register ................................................................... 3-46
Structure of Real time port register ...................................................................... 3-46
Structure of Real time port control register 0 ...................................................... 3-47
Structure of Real time port control register 1 ...................................................... 3-48
Structure of Real time port control register 2 ...................................................... 3-49
Structure of Real time port control register 3 ...................................................... 3-50
Structure of Timer A Low-order, Timer A High-order, Timer B Low-order, Timer B High-order 3-50
Structure of D-A control register ............................................................................3-51
Structure of A-D control register ............................................................................3-51
Structure of A-D conversion register..................................................................... 3-52
Structure of D-Ai conversion register (i = 1,2,3,4) .............................................. 3-52
Structure of Interrupt edge selection register ...................................................... 3-53
Structure of CPU mode register .............................................................................3-53
Structure of Interrupt request register 1 ............................................................... 3-54
Structure of Interrupt request register 2 ............................................................... 3-54
Structure of Interrupt control register 1 ................................................................ 3-55
Structure of Interrupt control register 2 ................................................................ 3-55
3807 GROUP USER’S MANUAL
List of tables
List of tables
CHAPTER 1 HARDWARE
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
1 Pin description (1)............................................................................................................ 1-4
2 Pin description (2)............................................................................................................ 1-5
3 List of supported products .............................................................................................. 1-7
4 Push and pop instructions of accumulator or processor status register ................. 1-9
5 Set and clear instructions of each bit of processor status register ....................... 1-10
6 List of I/O port functions (1) ......................................................................................... 1-15
7 List of I/O port functions (2) ......................................................................................... 1-16
8 Interrupt vector addresses and priority ...................................................................... 1-21
9 Port functions in memory expansion mode and microprocessor mode ................. 1-57
10 Special programming adapter ..................................................................................... 1-61
11 Interrupt sources, vector addresses and interrupt priority ..................................... 1-62
12 Change of A-D conversion register during A-D conversion .................................. 1-64
CHAPTER 2 APPLICATION
Table 2.1.1 Handling of unused pins (in single-chip mode) .................................................... 2-5
Table 2.1.2 Handling of unused pins (in memory expansion mode and microprocessor mode) ......... 2-5
Table 2.2.1 Function of CNTR0 /CNTR1 edge switch bit ........................................................ 2-10
Table 2.3.1 Setting examples of Baud rate generator values and transfer bit rate values ...................... 2-57
CHAPTER 3 APPENDIX
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
3.1.1 Absolute maximum ratings ....................................................................................... 3-2
3.1.2 Recommended operating conditions (1) ................................................................. 3-3
3.1.3 Recommended operating conditions (2) ................................................................. 3-3
3.1.4 Recommended operating conditions (3) ................................................................. 3-4
3.1.5 Electrical characteristics (1) ..................................................................................... 3-5
3.1.6 Electrical characteristics (2) ..................................................................................... 3-6
3.1.7 A-D converter characteristics ................................................................................... 3-7
3.1.8 D-A converter characteristics ................................................................................... 3-7
3.1.9 Analog comparator characteristics ........................................................................... 3-7
3.1.10 Timing requirements (1) .......................................................................................... 3-8
3.1.11 Timing requirements (2) .......................................................................................... 3-8
3.1.12 Switching characteristics (1)................................................................................... 3-9
3.1.13 Switching characteristics (2)................................................................................... 3-9
3.1.14 Timing requirements in memory expansion mode and microprocessor mode .......................... 3-10
3.1.15 Switching characteristics in memory expansion mode and microprocessor mode ................... 3-10
Table 3.3.1 Programming adapter .............................................................................................. 3-28
Table 3.3.2 Setting of programming adapter switch ............................................................... 3-28
Table 3.3.3 Setting of PROM programmer address ................................................................ 3-28
Table 3.5.1 Function of CNTR0 /CNTR1 edge switch bit ........................................................ 3-45
3807 GROUP USER’S MANUAL
i
CHAPTER 1
HARDWARE
DESCRIPTION
FEATURES
APPLICATIONS
PIN CONFIGURATION
FUNCTIONAL BLOCK
PIN DESCRIPTION
PART NUMBERING
GROUP EXPANSION
FUNCTIONAL DESCRIPTION
NOTES ON PROGRAMMING
DATA REQUIRED FOR MASK
ORDERS
ROM PROGRAMMING METHOD
FUNCTIONAL DESCRIPTION
SUPPLEMENT
HARDWARE
DESCRIPTION/FEATURES/APPLICATIONS/PIN CONFIGURATION
DESCRIPTION
•
•
•
•
•
•
•
The 3807 group is a 8-bit microcomputer based on the 740 family
core technology.
The 3807 group has two serial I/Os, an A-D converter, a D-A
converter, a real time output port function, a watchdog timer, and an
analog comparator, which are available for a system controller which
controls motors of office equipment and household appliances.
The various microcomputers in the 3807 group include variations of
internal memory size and packaging. For details, refer to the section
on part numbering.
For details on availability of microcomputers in the 3807 group, refer
to the section on group expansion.
•
FEATURES
•
•
•
•
•
•
•
•
•
•
Basic machine-language instructions ....................................... 71
The minimum instruction execution time ............................ 0.5 µs
(at 8 MHz oscillation frequency)
Memory size .................................................................................
ROM .................................................8 to 60 K bytes
RAM ............................................ 384 to 2048 bytes
Programmable input/output ports ............................................. 68
Software pull-up resistors (Ports P0 to P2) .............................. 24
Input ports (Ports P63 and P64) .................................................. 2
Interrupts .................................................. 20 sources, 16 vectors
Timers X, Y ................................................................... 16-bit ✕ 2
Timers A, B (for real time output port function) ............ 16-bit ✕ 2
Timers 1–3 ...................................................................... 8-bit ✕ 3
•
•
•
Serial I/O1 (UART or Clock-synchronized) ..................... 8-bit ✕ 1
Serial I/O2 (Clock-synchronized) .................................... 8-bit ✕ 1
A-D converter ................................................ 8-bit ✕ 13 channels
D-A converter .................................................. 8-bit ✕ 4 channels
Watchdog timer ............................................................. 16-bit ✕ 1
Analog comparator ....................................................... 1 channel
2 Clock generating circuit
Main clock (XIN–XOUT) ......................... Internal feedback resistor
Sub-clock (XCIN–XCOUT) ......... Without internal feedback resistor
(connect to external ceramic resonator or quartz-crystal oscillator)
Power source voltage
In high-speed mode ................................................... 4.0 to 5.5 V
(at 8 MHz oscillation frequency and high-speed selected)
In middle-speed mode ............................................... 2.7 to 5.5 V
(at 8 MHz oscillation frequency and middle-speed selected)
In low-speed mode .................................................... 2.7 to 5.5 V
(at 32 kHz oscillation frequency and low-speed selected)
Power dissipation
In high-speed mode ......................................................... 34 m W
(at 8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode ............................................................ 60 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
Memory expansion ......................................................... possible
Operating temperature range ................................... –20 to 85 °C
APPLICATION
LBP engine control, PPC, FAX, office equipment, household appliances, consumer electronics, etc.
42
41
43
44
45
46
47
48
49
50
51
52
53
55
54
56
57
58
60
59
61
62
65
40
66
39
67
38
68
37
69
36
70
35
71
34
33
72
M38073M4-XXXFP
73
74
32
31
75
30
76
29
77
28
78
27
79
80
26
21
22
23
24
13
14
15
16
17
18
19
20
11
12
10
P62/AN7
P61/AN6
P60/AN5
P77/AN4
P76/AN3
P75/AN2
P74/AN1
P73/SRDY2/ADT/AN0
P72/SCLK2
P71/SOUT2
P70/SIN2
P57/DA2
P56/DA1
P55/CNTR1
P54/CNTR0
P53/INT4
P52/INT3
P51/SCMP2/INT2
P50/TOUT
P47/SRDY1
P46/SCLK1
P45/TXD
P44/RXD
P43/INT1
5
6
7
8
9
25
1
2
3
4
P87/RTP5
P86/RTP4
P85/RTP3
P84/RTP2
P83/RTP1
P82/RTP0
P81/DA4/AN12
P80/DA3/AN11
VCC
ADVREF
AVSS
P65/DAVREF/AN10
P64/CMPREF /AN9
P63/CMPIN /AN8
CMPOUT
CMPVCC
63
64
P30/RTP6
P31/RTP7
P32/ONW
P33/RESETOUT
P34/CKOUT/φ
P35/SYNC
P36/WR
P37/RD
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/AD8
P11/AD9
P12/AD10
P13/AD11
P14/AD12
P15/AD13
P16/AD14
P17/AD15
PIN CONFIGURATION (TOP VIEW)
Package type : 80P6N-A
80-pin plastic-molded QFP
Fig. 1. Pin configuration of M38073M4-XXXFP
1-2
3807 GROUP USER’S MANUAL
P20/DB0
P21/DB1
P22/DB2
P23/DB3
P24/DB4
P25/DB5
P26/DB6
P27/DB7
VSS
XOUT
XIN
P40/XCOUT
P41/XCIN
RESET
CNVSS
P42/INT0
CMPOUT
CMPVCC
79
3807 GROUP USER’S MANUAL
RTP0 –
D-A
4 5 6 7 8 9 10 11
I/O port P 7
I/O port P 8
SCMP2
65 66 67 68 69 70 71 72
(8)
SI/O2(8)
74 75
DAVREF
(8)
ROM
AVSS
P6(8)
D-A
converter 2
(8)
I/O port P 6
1 2 3
CMPIN
CMPREF
76 77 78
A-D
converter
ADVREF
CMPREF
P7(8)
(8)
converter 4 converter 3
D-A
Analog
comparator
CMPIN
XCOUT
Clock generating circuit
XCIN
P8(8)
RTP5
80
RAM
SS
I/O port P 5
CC
PS
PC L
S
Y
X
A
TOUT
INT2 –
INT4
P4(8)
I/O port P 4
I/O port P 3
I/O port P 2
I/O port P 1
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
P1(8)
Timer B (16)
Timer A (16)
Timer Y (16)
P0(8)
TOUT
I/O port P 0
49 50 51 52 53 54 55 56
Timer 2 (8)
Timer 3 (8)
Timer X (16)
P2(8)
CNTR1
CNTR0
RTP0 – INT4
RTP5
RTP
57 58 59 60 61 62 63 64
P3(8)
INT1
INT0
26
27
Timer 1 (8)
CNVSS
RESET
Reset input
INT0, XCIN
INT1 XCOUT
20 21 22 23 24 25 28 29
SI/O1(8)
C P U
73
V
SCMP2
PC H
12 13 14 15 16 17 18 19
P5(8)
D-A
converter 1
(8)
32
31
30
Sub–clock Sub–clock
output
input
V
X OUT
X IN
Main clock Main clock
input
output
FUNCTIONAL BLOCK DIAGRAM (Package : 80P6N)
HARDWARE
FUNCTIONAL BLOCK
FUNCTIONAL BLOCK
Fig. 2. Functional block diagram
1-3
HARDWARE
PIN DESCRIPTION
PIN DESCRIPTION
Table. 1. Pin description (1)
Pin
VCC, VSS
CMPV CC
Name
Function
Function except a port function
Power source
• Apply voltage of 2.7–5.5 V to VCC, and 0 V to VSS .
Analog comparator • Power source input pin for an analog comparator
power source
CNVSS
CNVSS
ADVREF
Analog reference
• This pin controls the operation mode of the chip.
• Normally connected to VSS.
• If this pin is connected to VCC , the internal ROM is inhibited and external memory is accessed.
• Reference voltage input pin for A-D converter.
voltage
AV SS
CMPOUT
______
Analog power
• Analog power source input pin for A-D and D-A converter and an analog comparator
source
• Connect to V SS.
Analog comparator • Output pin for an analog comparator
output
RESET
XIN
Reset input
Clock input
XOUT
Clock output
P00–P07
P10–P17
P20–P27
I/O port P0
I/O port P1
I/O port P2
• Reset input pin for active “L”
• Input and output signals for the internal clock generating circuit.
• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency.
• If an external clock is used, connect the clock source to the XIN pin and leave the X OUT pin open.
• The clock is used as the oscillating source of system clock.
• 8-bit CMOS I/O port
• I/O direction register allows each pin to be individually programmed as either input or output.
• At reset this port is set to input mode.
• In modes other than single-chip, these pins are used as address, data bus I/O pins.
• CMOS compatible input level
• CMOS 3-state output structure
• Port P2 can be switched CMOS or TTL input level.
P30/RTP6, I/O port P3
P31/RTP7
P34/CKOUT ,
P32, P33,
• 8-bit CMOS I/O port
• Real time port function
• I/O direction register allows each pin to be individually programmed as either input or output.
pins
• At reset this port is set to input mode.
• Clock output function pin
• In modes other than single-chip, these pins are used as control bus I/O pins.
P35–P37
• CMOS compatible input level
• CMOS 3-state output structure
• Port P32 can be switched CMOS or TTL input level.
• 8-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
P40/XCOUT,
P41/XCIN
I/O port P4
P42/INT0,
P43/INT1
• CMOS 3-state output structures
• Interrupt input pins
• Timer X, Timer Y function pins
(INT0 , INT1 )
• Serial I/O1 function pins
• 8-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
• CMOS 3-state output structure
• Timer 2 output pin
• Interrupt input pin
• Serial I/O2 function pin
P44/RXD,
P45/TXD,
P46/SCLK1,
P47/SRDY1
P50/TOUT
P51/SCMP2/
INT2
I/O port P5
P52/INT3,
P53/INT4
P54/CNTR0,
P55/CNTR1
P56/DA1,
• Interrupt input pin
• Real time port function pin(INT4)
• Timer X, Timer Y function pins
• D-A conversion output
P57/DA2
1-4
• Sub-clock generating I/O
pins(connect a resonator)
pins
3807 GROUP USER’S MANUAL
HARDWARE
PIN DESCRIPTION
Table. 2. Pin description (2)
Pin
P60/AN5–
P62/AN7
Name
I/O port P6
Function
• 3-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
Function except a port function
• A-D conversion output
pins
• CMOS 3-state output structure
P63/CMPIN/ Input port P6
AN8
P64/CMPREF/
AN9
• 2-bit CMOS input port
• CMOS compatible input level
P65/DAVREF/ I/O port P6
AN10
• 1-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
• CMOS 3-state output structure
• 8-bit CMOS I/O port with the same function as port P0
P70/S IN2,
I/O port P7
P71/S OUT2,
• A-D conversion input pin
• D-A conversion power
source input pin
• A-D conversion input pin
• Serial I/O2 function pins
• CMOS compatible input level
• CMOS 3-state output structures
P72/SCLK2
P73/S RDY2/
ADT/AN0
P74/AN1–
P77/AN4
P80/DA3/
AN11,
P81/DA4/
• Analog comparator input pin
• A-D conversion input pin
• Reference voltage input pin
for analog comparator
• Serial I/O2 function pin
• A-D conversion input pin
• A-D trigger input pin
• A-D conversion input pin
I/O port P8
• 8-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
• CMOS 3-state output structures
• D-A conversion output
pin
• A-D conversion input pin
AN12,
P82/RTP0–
P87/RTP5
• Realtime port function
pins
3807 GROUP USER’S MANUAL
1-5
HARDWARE
PART NUMBERING
PART NUMBERING
Product M3807 3 M 4 - XXX FP
Package type
FP : 80P6N-A package
FS : 80D0 package
ROM number
Omitted in some types.
ROM/PROM size
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
9 : 36864 bytes
A : 40960 bytes
B : 45056 bytes
C : 49152 bytes
D : 53248 bytes
E : 57344 bytes
F : 61440 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used.
Memory type
M : Mask ROM version
E : EPROM or One Time PROM version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes
Fig. 3. Part numbering
1-6
3807 GROUP USER’S MANUAL
HARDWARE
GROUP EXPANSION
GROUP EXPANSION
Mitsubishi plans to expand the 3807 group as follows:
Memory Type
Support for Mask ROM, One Time PROM and EPROM versions.
Memory Size
ROM/PROM size .................................................... 8K to 60K bytes
RAM size ............................................................. 384 to 2048 bytes
Package
80P6N-A ..................................... 0.8 mm-pitch plastic molded QFP
80D0 ........................ 0.8 mm-pitch ceramic LCC (EPROM version)
ROM size (byte)
Being planned
External
ROM
M38078S
Under development
M38079EF
60K
Being planned
M38078MC
48K
Being planned
32K
M38077M8
28K
24K
20K
16K
Mass product
Mass
product
M38073M4
M38073E4
12K
8K
384
512
640
768
896
1024
1152
1280
1408
1536
2048
3072
4032
RAM size (byte)
Note : Products under development or planning : the development schedule and specifications may be revised without notice.
Fig. 4. Memory expansion plan
Currently supported products are listed below.
Table 3. List of supported products
Product
M38073M4-XXXFP
M38073E4-XXXFP
M38073E4FP
M38073E4FS
(P) ROM size (bytes)
ROM size for User ()
16384
As of May 1996
RAM size (bytes)
512
Package
Remarks
80P6N-A
Mask ROM version
One Time PROM version
80D0
One Time PROM version (blank)
EPROM version
(16254)
3807 GROUP USER’S MANUAL
1-7
HARDWARE
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
Stack pointer (S)
The stack pointer is an 8-bit register used during sub-routine calls
and interrupts. The stack is used to store the current address data
and processor status when branching to subroutines or interrupt routines.
The lower eight bits of the stack address are determined by the contents of the stack pointer. The upper eight bits of the stack address
are determined by the Stack Page Selection Bit. If the Stack Page
Selection Bit is “0”, then the RAM in the zero page is used as the
stack area. If the Stack Page Selection Bit is “1”, then RAM in page
1 is used as the stack area.
The Stack Page Selection Bit is located in the SFR area in the zero
page. Note that the initial value of the Stack Page Selection Bit varies with each microcomputer type. Also some microcomputer types
have no Stack Page Selection Bit and the upper eight bits of the
stack address are fixed. The operations of pushing register contents
onto the stack and popping them from the stack are shown in Fig.6.
The 3807 group uses the standard 740 family instruction set. Refer
to the table of 740 family addressing modes and machine instructions or the SERIES 740 <Software> User´s Manual for details on
the instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instructions cannot be used.
The MUL, DIV, WIT and STP instruction can be used.
The central processing unit (CPU) has the six registers.
Accumulator (A)
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
Index register X (X), Index register Y (Y)
Both index register X and index register Y are 8-bit registers. In the
index addressing modes, the value of the OPERAND is added to the
contents of register X or register Y and specifies the real address.
When the T flag in the processor status register is set to “1”, the
value contained in index register X becomes the address for the second OPERAND.
b7
Program counter (PC)
The program counter is a 16-bit counter consisting of two 8-bit registers
PCH and PCL. It is used to indicate the address of the next instruction to
be executed.
b0
Accumulator
A
b7
b0
Index Register X
X
b7
b0
Index Register Y
Y
b7
b0
Stack Pointer
S
b15
b7
PCH
b0
Program Counter
PCL
b7
b0
N V T B D I Z C Processor Status Register (PS)
Carry Flag
Zero Flag
Interrupt Disable Flag
Decimal Mode Flag
Break Flag
Index X Mode Flag
Overflow Flag
Negative Flag
Fig. 5. 740 Family CPU register structure
1-8
3807 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
On-going Routine
Interrupt request
(Note 1)
M (S)
(PCH)
(S)
(S – 1)
M (S)
(PCL)
(S)
(S – 1)
M (S)
(PS)
(S)
(S – 1)
Execute JSR
M (S)
Store Return Address
on Stack (Note 2)
(S)
M (S)
(S)
(PCH)
(S – 1)
(PCL)
(S – 1)
Subroutine
Interrupt
Service Routine
Execute RTS
Restore Return
Address
(S)
(PCL)
Execute RTI
(S + 1)
M (S)
(S)
(S + 1)
(PCH)
M (S)
(S)
(S + 1)
(PS)
M (S)
(S)
(S + 1)
(PCL)
M (S)
(S)
(S + 1)
(PCH)
M (S)
Store Return Address
on Stack (Note 2)
Store Contents of Processor
Status Register on Stack
I Flag “0” to “1”
Fetch the Jump Vector
Restore Contents of
Processor Status Register
Restore Return
Address
Note 1 : The condition to enable the interrupt
Interrupt enable bit is “1”
Interrupt disable flag is “0”
2 : When an interrupt occurs, the address of the next instruction to be executed is stored in
the stack area. When a subroutine is called, the address one before the next instruction
to be executed is stored in the stack area.
Fig. 6. Register push and pop at interrupt generation and subroutine call
Table. 4. Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
Push instruction to stack
Pop instruction from stack
PHA
PHP
PLA
PLP
3807 GROUP USER’S MANUAL
1-9
HARDWARE
FUNCTIONAL DESCRIPTION
Processor status register (PS)
The processor status register is an 8-bit register consisting of flags
which indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C)
flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid.
After reset, the Interrupt disable (I) flag is set to “1”, but all other flags
are undefined. Since the Index X mode (T) and Decimal mode (D)
flags directly affect arithmetic operations, they should be initialized in
the beginning of a program.
(1) Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
(2) Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
(3) Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
When an interrupt occurs, this flag is automatically set to “1” to
prevent other interrupts from interfering until the current interrupt
is serviced.
(4) Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
(5) Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”. The saved processor
status is the only place where the break flag is ever set.
(6) Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory, e.g. the results of an
operation between two memory locations is stored in the
accumulator. When the T flag is “1”, direct arithmetic operations
and direct data transfers are enabled between memory locations,
i.e. between memory and memory, memory and I/O, and I/O and
I/O. In this case, the result of an arithmetic operation performed
on data in memory location 1 and memory location 2 is stored in
memory location 1. The address of memory location 1 is
specified by index register X, and the address of memory
location 2 is specified by normal addressing modes.
(7) Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
(8) Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table. 5. Set and clear instructions of each bit of processor status register
C flag
Set instruction
Clear instruction
1-10
SEC
CLC
Z flag
_
_
I flag
D flag
SEI
CLI
SED
CLD
3807 GROUP USER’S MANUAL
B flag
_
_
T flag
SET
CLT
V flag
_
CLV
N flag
_
_
HARDWARE
FUNCTIONAL DESCRIPTION
CPU Mode Register
The CPU mode register contains the stack page selection bit and
processor mode bits. The CPU mode register is allocated at address
003B16 .
b7
b0
CPU mode register
(CPUM : address 003B16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Not available
Stack page selection bit
0 : 0 page
1 : 1 page
XCOUT drivability selection bit
0 : Low drive
1 : High drive
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN-XCOUT oscillating function
Main clock (XIN-XOUT) stop bit
0 : oscillating
1 : stopped
Main clock division ratio selection bits
b7 b6
0 0 : φ = f(XIN)/2 (high-speed mode)
0 1 : φ = f(XIN)/8 (middle-speed mode)
1 0 : φ = f(XCIN)/2 (low-speed mode)
1 1 : Not available
Fig. 7. Structure of CPU mode register
3807 GROUP USER’S MANUAL
1-11
HARDWARE
FUNCTIONAL DESCRIPTION
Memory
Special function register (SFR) area
Zero page
The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
Special page
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the reset is user area for storing programs.
Interrupt vector area
The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM capacity
(byte)
192
256
384
512
640
768
896
1024
1536
2048
Address
XXXX16
000016
SFR area
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
Zero page
004016
RAM
010016
XXXX16
Reserved area
084016
ROM area
ROM capacity
(byte)
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
Not used
Address
YYYY16
Address
ZZZZ16
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
ROM
YYYY16
Reserved ROM area
(128 byte)
ZZZZ16
FF0016
Interrupt vector area
FFFE16
FFFF16
Fig. 8. Memory map diagram
1-12
Special page
FFDC16
3807 GROUP USER’S MANUAL
Reserved ROM area
HARDWARE
FUNCTIONAL DESCRIPTION
000016
Port P0 (P0)
002016
Timer X (low-order) (TXL)
000116
Port P0 direction register (P0D)
002116
Timer X (high-order) (TXH)
000216
Port P1 (P1)
002216
Timer Y (low-order) (TYL)
000316
Port P1 direction register (P1D)
002316
Timer Y (high-order) (TYH)
000416
Port P2 (P2)
002416
Timer 1 (T1)
000516
Port P2 direction register (P2D)
002516
Timer 2 (T2)
000616
Port P3 (P3)
002616
Timer 3 (T3)
000716
Port P3 direction register (P3D)
002716
Timer X mode register (TXM)
000816
Port P4 (P4)
002816
Timer Y mode register (TYM)
000916
Port P4 direction register (P4D)
002916
Timer 123 mode register (T123M)
000A16
Port P5 (P5)
002A16
Real time port register (RTP)
000B16
Port P5 direction register (P5D)
002B16
Real time port control register 0 (RTPCON0)
000C16
Port P6 (P6)
002C16
Real time port control register 1 (RTPCON1)
000D16
Port P6 direction register (P6D)
002D16
Real time port control register 2 (RTPCON2)
000E16
Port P7 (P7)
002E16
Real time port control register 3 (RTPCON3)
000F16
Port P7 direction register (P7D)
002F16
Timer A (low-order) (TAL)
001016
Port P8 (P8)
003016
Timer A (high-order) (TAH)
001116
Port P8 direction register (P8D)
003116
Timer B (low-order) (TBL)
003216
Timer B (high-order) (TBH)
003316
D-A control register (DACON)
001216
001316
001416
Timer XY control register (TXYCON)
003416
A-D control register (ADCON)
001516
Port P2P3 control register (P2P3C)
003516
A-D conversion register (AD)
001616
Pull-up control register (PULL)
003616
D-A1 conversion register (DA1)
001716
Watchdog timer control register (WDTCON)
003716
D-A2 conversion register (DA2)
001816
Transmit/Receive buffer register (TB/RB)
003816
D-A3 conversion register (DA3)
001916
Serial I/O1 status register (SIO1STS)
003916
D-A4 conversion register (DA4)
001A16
Serial I/O1 control register (SIO1CON)
003A16
Interrupt edge selection register (INTEDGE)
001B16
UART control register (UARTCON)
003B16
CPU mode register (CPUM)
001C16
Baud rate generator (BRG)
003C16
Interrupt request register 1(IREQ1)
001D16
Serial I/O2 control register 1 (SIO2CON1)
003D16
Interrupt request register 2(IREQ2)
001E16
Serial I/O2 control register 2 (SIO2CON2)
003E16
Interrupt control register 1(ICON1)
001F16
Serial I/O2 register (SIO2)
003F16
Interrupt control register 2(ICON2)
Fig. 9. Memory map of special function register (SFR)
3807 GROUP USER’S MANUAL
1-13
HARDWARE
FUNCTIONAL DESCRIPTION
I/O Ports
[Direction Registers] PiD
The 3807 group has 68 programmable I/O pins arranged in nine individual I/O ports (P0—P5, P60—P6 2, P65 and P7—P8). The I/O ports
have direction registers which determine the input/output direction of
each individual pin. Each bit in a direction register corresponds to
one pin, each pin can be set to be input port or output port. When "0"
is written to the bit corresponding to a pin, that pin becomes an input
pin. When "1" is written to that pin, that pin becomes an output pin. If
data is read from a pin set to output, the value of the port output latch
is read, not the value of the pin itself. Pins set to input (the bit corresponding to that pin must be set to "0") are floating and the value of
that pin can be written to. If a pin set to input is written to, only the
port output latch is written to and the pin remains floating.
b7
b0
Port P2P3 control register
(P2P3C : address 001516)
P34 Clock output control bit
0: I/O port
1: Clock output
Output clock frequency selection bit
000: φ
001: f(XCIN)
010: “L” fixed output
011: “L” fixed output
(f(XCIN) in low-speed mode)
100: f(XIN)
101: f(XIN)/2 (f(XCIN)/2 in low-speed mode)
110: f(XIN)/4 (f(XCIN)/4 in low-speed mode)
111: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
[Pull-up Control Register] PULL
Ports P0, P1 and P2 have built-in programmable pull-up resistors.
The pull-up resistors are valid only in the case that the each control
bit is set to "1" and the corresponding port direction registers are set
to input mode.
(1) CMOS/TTL input level selection
Either CMOS input level or TTL input level can be selected as an
input level for ports P20 to P27 and P32. The input level is selected by
P2·P32 input level selection bit (b7) of the port P2P3 control register
(address 001516). When the bit is set to "0", CMOS input level is
selected. When the bit is set to "1", the TTL input level is selected.
After this bit is re-set, its initial value depends on the state of the
CNVss pin. When the CNVss pin is connected to Vss, the initial value
becomes "0". When the CNVss pin is connected to Vcc, the initial
value becomes "1".
Not used (return "0" when read)
P2 • P32 input level selection bit
0: CMOS level input
1: TTL level input
Fig. 10. Structure of Port P2P3 control register
b7
b0
Pull-up control register
(PULL : address 001616)
P00—P03 pull-up control bit
P04,P05 pull-up control bit
(2) Notes on STP instruction execution
Make sure that the input level at each pin is either 0V or to Vcc during
execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the
input-stage gate.
P06 pull-up control bit
P07 pull-up control bit
P10—P13 pull-up control bit
P14—P17 pull-up control bit
P20—P23 pull-up control bit
P24—P27 pull-up control bit
Fig. 11. Structure of Pull-up control register
1-14
3807 GROUP USER’S MANUAL
0: No pull-up
1: Pull-up
HARDWARE
FUNCTIONAL DESCRIPTION
Table. 6. List of I/O port functions (1)
Pin
Name
Input/Output
I/O Format
Non-Port Function
P00–P07
Port P0
Input/output,
CMOS compatible input level Address low-order byte output
P10–P17
P20–P27
Port P1
Port P2
individual bits
CMOS 3-state output
CMOS/TTL input level
CMOS 3-state output
P30/RTP 6,
P31/RTP 7
Port P3
P32
Address high-order byte output Pull-up control register
Data bus I/O
CPU mode register
Pull-up control register
Port P2P3 control register
CMOS compatible input level Real time port output
CPU mode register
CMOS 3-state output
Real time port control register
CMOS/TTL input level
Control signal input
CMOS 3-state output
CMOS compatible input level Control signal output
CMOS 3-state output
Clock output, φ output
P33
P34/CKOUT
Related SFRs
CPU mode register
Ref.No.
(1)
(2)
CPU mode register
Port P2P3 control register
CPU mode register
(3)
CPU mode register
(4)
Port P2P3 control register
P35–P37
Control signal I/O
CPU mode register
(3)
P40/X COUT, Port P4
P41/X CIN
P42/INT 0,
P43/INT 1
Sub-clock generating circuit
CPU mode register
(5)
(6)
(7)
P44/RXD,
P45/T XD,
P46/S CLK1,
P47/SRDY1
P50/T OUT
P51/S CMP2/
INT2
Serial I/O1 function I/O
Serial I/O1 control register
UART control register
Timer 2 output
External interrupt input
Serial I/O2 function I/O
Timer 123 mode register
Interrupt edge selection register
Serial I/O2 control register
External interrupt input
Real time port trigger input (INT4)
Timer X, Timer Y function I/O
Interrupt edge selection register
(7)
(13)
D-A conversion output
Timer X mode register
Timer Y mode register
D-A control register
A-D conversion input
A-D control register
(15)
A-D control register
(16)
A-D control register
(17)
Serial I/O2 function I/O
Serial I/O2 control register
Serial I/O2 function I/O
A-D trigger input
Serial I/O2 control register
A-D control register
(18)
(19)
(20)
(21)
External interrupt input
Interrupt edge selection register
Timer X, Timer Y function input
Port P5
P52/INT 3,
P53/INT 4
P54/CNTR0
P55/CNTR1
P56/DA1,
P57/DA2
P60/AN5— Port P6
P62/AN7
P63/CMP IN/
AN8
P64 /CMPREF/
AN9
Input
P65 /DAVREF/
AN10
Input/output,
individual bits
CMOS compatible input level Analog comparator input pin
A-D conversion input
Analog comparator reference
voltage input pin
A-D conversion input
CMOS compatible input level D-A converter power source
CMOS 3-state output
input
(8)
(9)
(10)
(11)
(12)
(22)
(14)
A-D conversion input
P70/S IN2,
P71/S OUT2,
P72/SCLK2
P73/S RDY2/
ADT/AN0
Port P7
A-D conversion input
P74/AN1—
P77/AN4
A-D conversion input
3807 GROUP USER’S MANUAL
A-D control register
(15)
1-15
HARDWARE
FUNCTIONAL DESCRIPTION
Table. 7. List of I/O port functions (2)
Pin
P80/DA3/
AN11
P81/DA4/
AN12
P82/RTP0—
P87/RTP5
Name
Port P8
Input/Output
I/O Format
Non-Port Function
Related SFRs
Input/output,
CMOS compatible input level D-A conversion output
D-A control register
individual bits
CMOS 3-state output
A-D conversion input
A-D control register
Real time port output
Real time port control
register
Ref.No.
(14)
(23)
Note1 : For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as function
I/O ports, refer to the applicable sections.
2 : Make sure that the input level at each pin is either 0 V or Vcc during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the input-stage gate.
1-16
3807 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
(1) Ports P0—P2
(2) Ports P30,P31
Real time port output selection bit
Pull-up control
Direction register
Data bus
Direction register
Data bus
Port latch
Port latch
Data for real time port
*1
(4) Port P34
(3) Ports P32,P33,P35—P37
Clock output control
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
*1
Clock output
(5) Port P40
(6) Port P41
Port XC switch bit
Port XC switch bit
Direction register
Data bus
Direction register
Port latch
Data bus
Port latch
Oscillator
Port P41
Sub-clock oscillating circuit input
Port XC switch bit
(7) Ports P42,P43,P52,P53
Direction register
Data bus
(8) Port P44
Serial I/O1 enable bit
Receive enable bit
Direction register
Port latch
Data bus
Port latch
Interrupt input
Timer X input (P42)
Timer Y input (P43)
RTP trigger input (P53)
serial I/O1 input
except P52
*1 Either CMOS input level or TTL input level can be selected as an input level for ports P20 to P27 and P32 by P2•P32 input level selection bit.
Fig. 12. Port block diagram (1)
3807 GROUP USER’S MANUAL
1-17
HARDWARE
FUNCTIONAL DESCRIPTION
(9) Port P45
(10) Port P46
P45/TXD P-channel output disable bit
Serial I/O1 enable bit
Transmit enable bit
Serial I/O1 synchronous
clock selection bit
Serial I/O1 enable bit
Serial I/O1mode selection bit
Serial I/O1enable bit
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Serial I/O1 output
Serial I/O1 clock output
Serial I/O1 external clock input
(11) Port P47
(12) Port P50
Serial I/O1 mode selection bit
Serial I/O1 enable bit
SRDY1 output enable bit
Direction register
Direction register
Data bus
Data bus
Port latch
Port latch
TOUT output control bit
Timer 2 output
Serial I/O1 ready output
(13) Ports P54,P55
(14) Ports P56,P57,P80,P81
Direction register
Data bus
Direction register
Port latch
Data bus
Timer X, Timer Y
operating mode bits
"001"
"100"
"101"
"110"
Port latch
D-A conversion output
DA1 output enable bit (P56)
DA2 output enable bit (P57)
DA3 output enable bit (P80)
DA4 output enable bit (P81)
Timer output
CNTR0, CNTR1 interrupt input
A-D conversion input
Analog input pin selection bit
except P56,P57
(15) Ports P60—P62,P74—P77
(16) Ports P63,P64
Direction register
Data bus
Port latch
Data bus
A-D conversion input
Analog input pin selection bit
A-D conversion input
Analog input pin selection bit
Fig. 13. Port block diagram (2)
1-18
3807 GROUP USER’S MANUAL
Analog comparator input
HARDWARE
FUNCTIONAL DESCRIPTION
(17) Port P65
(18) Port P70
Direction register
Data bus
Direction register
Port latch
Data bus
Port latch
D-A conversion power source input
Serial I/O2 input
A-D conversion input
Analog input pin selection bit
(20) Port P72
(19) Port P71
Direction register
Direction register
Data bus
P72/SCLK2 P-channel output
disable bit
Serial I/O2 synchronous
clock selection bit
Serial I/O2 port selection bit
P71/SOUT2 P-channel output disable bit
Serial I/O2 transmit completion signal
Serial I/O2 port selection bit
Port latch
Data bus
Port latch
Serial I/O2 clock output
Serial I/O2 clock output
Serial I/O2 external clock input
(21) Port P73
(22) Port P51
SRDY2 output enable bit
Serial I/O2 I/O comparison
signal control bit
Direction register
Direction register
Data bus
Data bus
Port latch
Port latch
Serial I/O2 I/O comparison
signal output
Serial I/O2 ready output
AD external trigger valid bit
Interrrupt input
A-D trigger interrupt input
A-D conversion input
Analog input pin selection bit
(23) Ports P82—P87
Real time port output selection bit
Direction register
Data bus
Port latch
Data for real time port
Fig. 14. Port block diagram (3)
3807 GROUP USER’S MANUAL
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HARDWARE
FUNCTIONAL DESCRIPTION
Interrupts
Interrupts occur by twenty sources: eight external, eleven internal,
and one software.
(1) Interrupt Control
Each interrupt except the BRK instruction interrupt have both an
interrupt request bit and an interrupt enable bit, and is controlled by
the interrupt disable flag. An interrupt occurs if the corresponding
interrupt request and enable bits are "1" and the interrupt disable flag
is "0". Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by
software. The BRK instruction interrupt and reset cannot be disabled
with any flag or bit. The I flag disables all interrupts except the BRK
instruction interrupt and reset. If several interrupts requests occurs
at the same time the interrupt with highest priority is accepted first.
(2) Interrupt Operation
Upon acceptance of an interrupt the following operations are automatically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status register are automatically pushed onto the stack
3. Concurrently with the push operation, the interrupt jump destination address is read from the vector table into the program
counter.
4. The interrupt disable flag is set and the corresponding interrupt request bit is cleared.
■Notes on Use
When the active edge of an external interrupt (INT0—INT4, CNTR0
or CNTR1) is set or the timer /INT interrupt source and the ADT/ A-D
conversion interrupt source are changed, the corresponding
interrupt request bit may also be set. Therefore, please take following sequence:
(1) Disable the external interrupt which is selected.
(2) Change the active edge in interrupt edge selection register
(in case of CNTR0: Timer X mode register ; in case of CNTR1:
Timer Y mode register).
(3) Clear the set interrupt request bit to "0."
(4) Enable the external interrupt which is selected.
1-20
3807 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
Table. 8. Interrupt vector addresses and priority
Interrupt Source Priority
Vector Addresses (Note 1)
High
Low
Interrupt Request
Remarks
Generating Conditions
Reset (Note 2)
INT0
1
2
FFFD16
FFFB16
FFFC16
FFFA16
At reset
At detection of either rising or falling edge of
INT0 input
Non-maskable
External interrupt
(active edge selectable)
INT1
3
FFF916
FFF816
Serial I/O1
receive
Serial I/O1
4
FFF716
FFF616
At detection of either rising or falling edge of
INT1 input
At completion of serial I/O1 data receive
External interrupt
(active edge selectable)
Valid when serial I/O1 is selected
5
FFF516
FFF416
At completion of serial I/O1 data transmit
Valid when serial I/O1 is selected
transmit
Timer X
Timer Y
INT3
shift or when transmit buffer is empty
6
7
8
FFF316
FFF116
FFEF16
FFF216
FFF016
FFEE16
Timer 2
INT4
9
FFED16
FFEC16
Timer 3
CNTR0
10
FFEB16
FFEA16
CNTR1
11
FFE916
FFE816
Serial I/O2
12
FFE716
FFE616
INT2
13
FFE516
FFE416
Timer 1
Timer A
Timer B
A-D conversion
ADT
14
15
16
FFE316
FFE116
FFDF16
FFE216
FFE016
FFDE16
BRK instruction
17
FFDD16
FFDC16
At timer X underflow
At timer Y underflow
At detection of either rising or falling edge of
INT3 input
External interrupt
(active edge selectable)
At timer 2 underflow
At detection of either rising or falling edge of
INT4 input
Valid when INT3 interrupt is selected
Valid when timer 2 interrupt is selected
External interrupt
(active edge selectable)
Valid when INT4 interrupt is selected
At timer 3 underflow
At detection of either rising or falling edge of
CNTR0 input
At detection of either rising or falling edge of
CNTR1 input
Valid when timer 3 interrupt is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
At completion of serial I/O2 data transmit
and receive
At detection of either rising or falling edge of
INT2 input
Valid when serial I/O2 is selected
External interrupt
(active edge selectable)
Valid when INT2 interrupt is selected
At timer 1 underflow
At timer A underflow
At timer B underflow
At completion of A-D conversion
At falling edge of ADT input
Valid when timer 1 interrupt is selected
Valid when A-D interrupt is selected
External interrupt(valid at falling)
At BRK instruction execution
Valid when ADT interrupt is selected and
when A-D external trigger is selected.
Non-maskable software interrupt
Note1 : Vector addresses contain interrupt jump destination addresses.
2 : Reset function in the same way as an interrupt with the highest priority.
3807 GROUP USER’S MANUAL
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HARDWARE
FUNCTIONAL DESCRIPTION
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
Interrupt request
Fig. 15. Interrupt control
b7
b0 Interrupt edge selection register
(INTEDGE : address 003A16)
INT0 interrupt edge selection bit
INT1 interrupt edge selection bit
INT2 interrupt edge selection bit
INT3 interrupt edge selection bit
INT4 interrupt edge selection bit
Timer 1/INT2 interrupt source bit
Timer 2/INT3 interrupt source bit
Timer 3/INT4 interrupt source bit
b7
0 : Falling edge active
1 : Rising edge active
0 : INT interrupt selected
1 : Timer interrupt selected
b0 Interrupt request register 1
(IREQ1 : address 003C16)
b7
b0 Interrupt request register 2
(IREQ2 : address 003D16)
CNTR0 interrupt request bit
CNTR1 interrupt request bit
Serial I/O2 interrupt request bit
Timer 1/INT2 interrupt request bit
Timer A interrupt request bit
Timer B interrupt request bit
ADT/AD conversion interrupt request bit
Not used (returns "0" when read)
INT0 interrupt request bit
INT1 interrupt request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 2/INT3 interrupt request bit
Timer 3/INT4 interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0 Interrupt control register 1
(ICON1 : address 003E16)
b7
INT0 interrupt enable bit
INT1 interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 2/INT3 interrupt enable bit
Timer 3/INT4 interrupt enable bit
b0 Interrupt control register 2
(ICON2 : address 003F16)
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
Serial I/O2 interrupt enable bit
Timer 1/INT2 interrupt enable bit
Timer A interrupt enable bit
Timer B interrupt enable bit
ADT/AD conversion interrupt enable bit
Not used (returns "0" when read)
(Do not write "1" to this bit)
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 16. Structure of Interrupt-related registers
1-22
3807 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
Timers
The 3807 group has seven timers : four 16-bit timers (Timer X, Timer
Y, Timer A, and Timer B) and three 8-bit timers (Timer 1, Timer 2,
and Timer 3).
All timers are down-counters. When the timer reaches either "00 16"
or "0000 16", an underflow occurs with the next count pulse. Then the
contents of the timer latch is reloaded into the timer and the timer
continues down-counting. When a timer underflows, the interrupt
request bit corresponding to that timer is set to "1."
Read and write operation on 16-bit timer must be performed for both
high- and low-order bytes. When reading a 16-bit timer, read from
the high-order byte first. When writing to 16-bit timer, write to the loworder byte first. The 16-bit timer cannot perform the correct operation
when reading during write operation, or when writing during read
operation.
Timers A and B are real time output port timers. For details, refer to
the section "Real time output port".
●Timer X, Timer Y
Timer X and Y are independent 16-bit timers which can select
enable seven different operation modes each by the setting of their
mode registers. The related registers of timer X and Y are listed
below. The following register abbreviations are used:
• Timer XY control register (TXYCON: address 0014 16)
• Port P4 direction register (P4D: address 000916 )
• Port P5 direction register (P5D: address 000B16)
• Timer X (low-order) (TXL: address 002016 )
• Timer X (high-order) (TXH: address 002116)
• Timer Y (low-order) (TYL: address 002216 )
• Timer Y (high-order) (TYH: address 002316)
• Timer X mode register (TXM: address 002716)
• Timer Y mode register (TYM: address 002816)
• Interrupt edge selection register (INTEDGE: address 003A16)
• Interrupt request register 1 (IREQ1: address 003C16 )
• Interrupt request register 2 (IREQ2: address 003D16 )
• Interrupt control register 1 (ICON1: address 003E16)
• Interrupt control register 2 (ICON2: address 003F16)
For details, refer to the structures of each register.
The following is an explanation of the seven modes:
(1) Timer • event counter mode
➀Timer mode
• Mode selection
This mode can be selected by setting "000" to the following bits.
Timer X operating mode bit (bits 2 to 0) of TXM
Timer Y operating mode bit (bits 2 to 0) of TYM
• Count source selection
In high- or middle-speed mode, f(XIN)/2, f(XIN)/16, or f(XCIN) can be
selected as the count source.
In low-speed mode the count source is f(XCIN).
A count source is selected by the following bit.
Timer X count source selection bit (bits 7 and 6) of TXM
Timer Y count source selection bit (bits 7 and 6) of TYM
• Interrupt
When an underflow is generated, the corresponding timer X
interrupt request bit (b4) or timer Y interrupt request bit (b5) of IREQ1
is set to "1".
• Explanation of operation
After reset release, timer X stop control bit (b0) and timer Y stop
control bit (b1) of TXYCON are set to "1"and the timer stops.
During timer stop, a timer value written to the timer X or timer Y
is set by writing data to the corresponding timer latch and
timer at the same time. The timer operation is started by setting the
bits 0 or 1 of TXYCON to "0". When the timer reaches "000016", an
underflow occurs with the next count pulse. Then the contents of
the timer latch is reloaded into the timer and the timer continues
down-counting. For changing a timer value during count operation,
a latch value must be changed by writing data only to the
corresponding latch first. Then the timer is reloaded with the new
latch value at the next underflow.
➁Event counter mode
• Mode selection
This mode can be selected by the following sequence.
1. Set "000" to the timer X operating mode bit (bits 2 to 0) of TXM,
or to the timer Y operating mode bit (bits 2 to 0) of TYM.
2. Select an input signal from the CNTR0 pin (in case of timer X ;
set "11" to bits 7 and 6 of TXM), or from the CNTR1 pin (in case
of timer Y ; set "11" to bits 7 and 6 of TYM) as a count source.
The valid edge for the count operation is selected by the CNTR0/
CNTR1 active edge switch bit (b5) of TXM or TYM: if set to "0",
counting starts with the rising edge or if set to "1", counting starts
with the falling edge.
• Interrupt
The interrupt generation at underflow is the same as already
explained for the timer mode.
• Explanation of operation
The operation is the same as already explained for the timer mode.
In this mode, the double-function port of CNTR0/CNTR 1 pin must
be set to input.
Figure 19 shows the timing chart for the timer • event counter mode.
(2) Pulse output mode
• Mode selection
This mode can be selected by setting "001" to the following bits.
Timer X operating mode bit (bits 2 to 0) of TXM
Timer Y operating mode bit (bits 2 to 0) of TYM
• Count source selection
In high- or middle-speed mode, f(XIN)/2, f(XIN)/16, or f(XCIN) can be
selected as the count source.
In low-speed mode the count source is f(XCIN).
• Interrupt
The interrupt generation at underflow is the same as already
explained for the timer mode.
• Explanation of operation
Counting operation is the same as in timer mode. Moreover the
pulse which is inverted each time the timer underflows is output
from CNTR 0/CNTR 1 pin. When the CNTR0/CNTR1 active edge
switch bit (b5) of TXM or TYM is "0", output starts with "H" level.
When set to "1", output starts with "L" level.
3807 GROUP USER’S MANUAL
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HARDWARE
FUNCTIONAL DESCRIPTION
■Precautions
Set the double-function port of CNTR0/CNTR 1 pin to output in this
mode.
[During timer operation stop]
The output from CNTR 0/CNTR1 pin is initialized to the level set
through CNTR0/CNTR1 active edge switch bit.
[During timer operation enabled]
When the value of the CNTR0/CNTR 1 active edge switch bit is written over, the output level of CNTR0/CNTR1 pin is inverted.
Figure 20 shows the timing chart of the pulse output mode.
(3) Pulse period measurement mode
• Mode selection
This mode can be selected by setting "010" to the following bits.
Timer X operating mode bit (bits 2 to 0) of TXM
Timer Y operating mode bit (bits 2 to 0) of TYM
• Count source selection
In high- or middle-speed mode, f(XIN)/2 or f(XIN)/16 can be selected
as the count source.
In low-speed mode the count source is f(XCIN).
• Interrupt
The interrupt generation at underflow is the same as already
explained for the timer mode. Bits 0 or 1 of IREQ2 is set to "1"
synchronously to pulse period measurement completion.
• Explanation of operation
[During timer operation stop]
Select the count source. Next, select the interval of the pulse
periods to be measured. When bit 5 of the TXM or TYM is set to
"0", the timer counts during the interval of one falling edge of CNTR0/
CNTR1 pin input until the next falling edge of input. If bits 5 are set
to "1", the timer counts during the interval of one rising edge until
the next rising edge.
[During timer operation enabled]
The pulse period measurement starts by setting bit 0 or 1 of
TXYCON to "0" and the timer counts down from the value that was
set to the timer before the start of measurement. When a valid edge
of measurement start/stop is detected, the 1's complement of the
timer value is written to the timer latch and "FFFF16" is set to the
timer. Furthermore when the timer underflows, a timer X/Y interrupt
request occurs and "FFFF 16" is set to the timer. The measured
value is held until the next measurement completion.
■Precautions
Set the double-function port of CNTR0/CNTR1 pin to input in this
mode.
A read-out of timer value is impossible in this mode. The timer is
written to only during timer stop (no measurement of pulse periods).
Since the timer latch in this mode is specialized for the read-out of
measured values, do not perform any write operations during
measurement.
The timer is set to "FFFF16 " when the timer either underflows or a
valid edge of pulse period measurement is detected. Due to that, the
timer value at the start of measurement depends on the timer value
before the start of measurement.
Figure 21 shows the timing chart of the pulse period measurement
mode.
1-24
(4) Pulse width measurement mode
• Mode selection
This mode can be selected by setting "011" to the following bits.
Timer X operating mode bit (bits 2 to 0) of TXM
Timer Y operating mode bit (bits 2 to 0) of TYM
• Count source selection
In high- or middle-speed mode, f(XIN)/2 or f(XIN)/16 can be selected
as the count source.
In low-speed mode the count source is f(XCIN).
• Interrupt
The interrupt generation at underflow is the same as already
explained for the timer mode. Bit 0 or 1 of IREQ2 is set to "1" synchronously to pulse width measurement completion.
• Explanation of operation
[During timer operation stop]
Select the count source. Next, select the interval of the pulse widths
to be measured. When bit 5 of TXM or TYM is set to "1", the timer
counts during the interval of one falling edge of CNTR0/CNTR1 pin
input until the next rising edge of input ("L" interval). If bit 5 is set to
"0", the timer counts during the interval of one rising edge until the
next falling edge ("H" interval).
[During timer operation enabled]
The pulse width measurement starts by setting bit 0 or 1 of TXYCON
to "0" and the timer counts down from the value that was set to the
timer before the start of measurement. When a valid edge of
measurement completion is detected, the 1's complement of the
timer value is written to the timer latch and "FFFF16" is set to the
timer. Furthermore when the timer underflows, a timer X/Y interrupt
request occurs and "FFFF16" is set to the timer. The measured
value is held until the next measurement completion.
■Precautions
Set the double-function port of CNTR 0/CNTR1 pin to input in this
mode.
A read-out of timer value is impossible in this mode. The timer is
written to only during timer stop (no measurement of pulse widths).
Since the timer latch in this mode is specialized for the read-out of
measured values, do not perform any write operations during measurement.
The timer value is set to "FFFF 16" when the timer either underflows
or a valid edge of pulse widths measurement is detected. Due to
that, the timer value at the start of measurement depends on the
timer value before the start of measurement.
Figure 22 shows the timing chart of the pulse width measurement
mode.
(5) Programmable waveform generation mode
• Mode selection
This mode can be selected by setting "100" to the following bits.
Timer X operating mode bit (bits 2 to 0) of TXM
Timer Y operating mode bit (bits 2 to 0) of TYM
• Count source selection
In high- or middle-speed mode, f(XIN)/2, f(XIN)/16, or f(XCIN) can be
selected as the count source.
In low-speed mode the count source is f(XCIN).
• Interrupt
The interrupt generation at underflow is the same as already
3807 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
explained for the timer mode.
• Explanation of operation
Counting operation is the same as in timer mode. Moreover the
timer outputs the data set in the corresponding output level latch
(bit 4 of TXM or TYM) to CNTR0/CNTR1 pin each time the timer
underflows. After the timer underflows, the generation of optional
waveform from CNTR0/CNTR1 pin is possible through a change of
values in the output level latch and timer latch.
■Precautions
Set the double-function port of CNTR0/CNTR 1 pin to output in this
mode.
Figure 23 shows the timing chart of the programmable waveform
generation mode.
(6) Programmable one-shot generating mode
• Mode selection
This mode can be selected by setting "101" to the following bits.
Timer X operating mode bit (bits 2 to 0) of TXM
Timer Y operating mode bit (bits 2 to 0) of TYM
• Count source selection
In high- or middle-speed mode, f(XIN)/2 or f(XIN)/16 can be selected
as the count source.
• Interrupt
The interrupt generation at underflow is the same as already
explained for the timer mode. The one-shot generating trigger
condition must be set to the INT0 interrupt edge selection bit (b0)
and INT1 interrupt edge selection bit (b1) of INTEDGE. Setting these
bits to "0" causes the interrupt request being
triggered by a falling edge, setting them to "1" causes the interrupt
request being triggered by a rising edge. The INT0 interrupt request
bit (b0) and INT1 interrupt request bit (b1) of IREQ1 are set to "1" by
detecting the active edge of the INT pin.
• Explanation of operation
For a "H" one-shot pulse, set bit 5 of TXM, TYM to "0".
[During timer operation stop]
The output level of CNTR0/CNTR1 pin is initialized to "L" at mode
selection. Set the one-shot pulse width to TXH, TXL, TYH, TYL. A
trigger generation during timer stop (input signal to INT0/INT 1 pin)
is invalid.
[During timer operation enabled]
When a trigger generation is detected, "H" is output, and at underflow
"L" is output from CNTR0/CNTR1 pin.
For a "L" one-shot pulse set bit 5 of TXM, TYM to "1".
[During timer operation stop]
The output level of CNTR0/CNTR1 pin is initialized to "H" at mode
selection. Set the one-shot pulse width to TXH, TXL, TYH, TYL. A
trigger generation during timer stop (input signal to INT0/INT 1 pin)
is invalid.
[During timer operation enabled]
When a trigger generation is detected, "L" is output, and at underflow
"H" is output from CNTR0/CNTR1 pin.
■Precautions
• Set the double-function port of CNTR0/CNTR1 pin to output and the
double-function port of INT0/INT1 pin to input in this mode.
• This mode is unused in low-speed mode.
• During one-shot generation permission or one-shot generation the
output level from CNTR 0/CNTR1 pin changes if the value of the
CNTR 0/CNTR1 active edge switch bit is inverted.
Figure 24 shows the timing chart of the programmable one-shot
generating mode.
(7) PWM mode
• Mode selection
This mode can be selected by setting "110" to the following bits.
Timer X operating mode bit (bits 2 to 0) of TXM
Timer Y operating mode bit (bits 2 to 0) of TYM
• Count source selection
In high- or middle-speed mode, f(XIN)/2 or f(X IN)/16 can be selected
as the count source.
• Interrupt
With a rising edge of CNTR0/CNTR 1 output, the timer X interrupt
request bit (b4) and timer Y interrupt request bit (b5) of IREQ1 are
set to "1".
• Explanation of operation
PWM waveform is output from CNTR 0 pin (in case of timer X) or
from CNTR1 pin (in case of timer Y).
The "H" interval of PWM waveform is determined by the setting
value m (m=0 to 255) of TXH and TYH and the "L" interval of PWM
waveform is determined by the setting value n (n=0 to 255) of TXL
and TYL.
The PWM cycles are:
PWM cycle time = (m+n)·ts
PWM duty = m/(m+n)
where: ts: period of timer X/timer Y count source
[During count operation stop]
When a timer value is set to TXL, TXH, TYL, TYH by writing data to
timer and timer latch at the same time. When setting this value, the
output of CNTR 0/CNTR1 pin is initialized to the "H" level.
[During count operation enabled]
By setting the bit 0 or 1 of TXYCON to "0", an "H" interval of TXH or
TYH is output first, and after that a "L" level interval of TXL or TYL
are output next. These operations are repeated continuously. The
PWM output is changed after the underflow by setting a timer value,
which is set by writing data to the timer latch only, to TXL, TXH,
TYL, TYH.
■Precautions
• Set the double-function port of CNTR0/CNTR1 pin to output in this
mode.
• This mode is unused in low-speed mode.
• When the PWM "H" interval is set to "0016", PWM output is "L".
• When the PWM "L" interval is set to "0016 ", PWM output is "H".
• When the PWM "H" interval and "L" interval are set to "0016", PWM
output is "L".
• When a PWM "H" interval or "L" interval is set to "0016 " at least for
a short time, timer X/timer Y interrupt request does not occur.
• When the value set to the timer latch is "0016 ", the value is undefined since the timer counts down by dummy count operation.
Figure 25 shows the timing chart of the PWM mode.
3807 GROUP USER’S MANUAL
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HARDWARE
FUNCTIONAL DESCRIPTION
■Precautions regarding all modes
• Timer X, timer Y writing control
One of the following operation is selected by bit 3 of TXM or TYM
for timer X or timer Y.
Writing data to the corresponding latch and timer at the same
time
Writing data to only corresponding latch
When the operation "writing data to only corresponding latch" is
selected, the value is set to the timer latch by writing a value to
timer X/Y address and a timer is renewed at the next underflow.
After releasing a reset, "writing the corresponding latch and timer
at the same time" is selected. When a value is written to timer X/Y
address, a value is set to a timer and a timer latch at the same time.
When "writing data to only corresponding latch" is selected, if writing to a reload latch and an underflow are performed at the same
timing, the timer value is undefined.
• Timer X, timer Y read control
In pulse period measurement mode and pulse width measurement
mode the timer value cannot be read-out. In all other modes readout operations without effect to count operations/stops are possible.
However, the timer latch value cannot be read-out.
• Precautions regarding the CNTR0/CNTR1 active edge switch bit
and the INT0/INT 1 interrupt edge selection bit:
The CNTR 0/CNTR 1 active edge switch bit and the INT 0/INT1
interrupt edge selection bit settings have an effect also on each
interrupt active edge.
1-26
3807 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
CNTR0 active edge
switch bit
Programmable one-shot
"1"
P42/INT0
Data bus
generating mode
Programmable one-shot
generating circuit
"0"
Programmable one-shot generating mode
PWM mode
PWM mode
PWM generating circuit
INT0 interrupt request
Programmable waveform
generating mode
Output level latch
D
Q
T
pulse output mode
S
Q
T
CNTR0 active edge
switch bit
"0"
Q
"1" Pulse output mode
"001"
"100"
"101"
"110"
Timer X operating
mode bits
Timer X latch (low-order)
P54 latch
Timer X latch (high-order)
Timer X (high-order)
Timer X (low-order)
Timer X interrupt request
P54 direction register
Pulse period measurement mode
Pulse width measurement mode
Edge detection circuit
CNTR0 interrupt request
"1"
P54/CNTR0
"0"
CNTR0 active
edge switch bit
f(XIN)/2
f(XIN)/16
f(XCIN)
Timer X stop control bit
Timer X count source
selection bits
CNTR1 active edge
switch bit
Programmable one-shot
"1"
generating mode
P43/INT1
Programmable one-shot
generating circuit
Programmable one-shot generating mode
"0"
PWM mode
PWM mode
PWM generating circuit
INT1 interrupt request
Programmable waveform
generating mode
Output level latch
D
T
Q
Pulse output mode
S
Q
T
CNTR1 active edge
switch bit
"0"
Q
"1"
"001"
"100"
"101"
"110"
Timer Y operating
mode bits
Timer Y latch (low-order)
Timer Y (low-order)
P55 latch
Pulse output mode
Timer Y latch (high-order)
Timer Y (high-order)
Timer Y interrupt request
P55 direction register
Pulse period measurement mode
Pulse width measurement mode
Edge detection circuit
CNTR1 interrupt request
"1"
P55/CNTR1
"0"
CNTR1 active
edge switch bit
f(XIN)/2
f(XIN)/16
f(XCIN)
Timer Y stop control bit
Timer Y count source
selection bits
Fig. 17. Block diagram of Timer X and Timer Y
3807 GROUP USER’S MANUAL
1-27
HARDWARE
FUNCTIONAL DESCRIPTION
b7
b7
b7
b0
b0
Timer X mode register
(TXM : address 002716)
Timer Y mode register
(TYM : address 002816)
Timer X operating mode bits
b2 b1 b0
0 0 0 : Timer • event counter mode
0 0 1 : Pulse output mode
0 1 0 : Pulse period measurement mode
0 1 1 : Pulse width measurement mode
1 0 0 : Programmable waveform generating mode
1 0 1 : Programmable one-shot generating mode
1 1 0 : PWM mode
1 1 1 : Not used
Timer Y operating mode bits
b2 b1 b0
0 0 0 : Timer•event counter mode
0 0 1 : Pulse output mode
0 1 0 : Pulse period measurement mode
0 1 1 : Pulse width measurement mode
1 0 0 : Programmable waveform generating mode
1 0 1 : Programmable one-shot generating mode
1 1 0 : PWM mode
1 1 1 : Not used
Timer X write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer Y write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Output level latch
0 : "L" output
1 : "H" output
Output level latch
0 : "L" output
1 : "H" output
CNTR0 active edge switch bit
0 : • Event counter mode ; counts rising edges
• Pulse output mode ; output starts with “H” level
• Pulse period measurement mode ;
measures between two falling edges
• Pulse width measurement mode ; measures “H” periodes
• Programmable one-shot generating mode ;
after start at “L” level, output a “H” pulse
(interrupt request is triggered on falling edge)
1 : • Eevent counter mode ; counts falling edges
• Pulse output mode ; output starts with “L” level
• Pulse period measurement mode ;
measures between two rising edges
• Pulse width measurement mode ; measures “L” periodes
• Programmable one-shot generating mode ;
after start at “H” level, output a “L” pulse
(interrupt request is triggered on rising edge)
CNTR1 active edge switch bit
0 : • Event counter mode ; counts rising edges
• Pulse output mode ; output starts with “H” level
• Pulse period measurement mode ;
measures between two falling edges
• Pulse width measurement mode ; measures “H” periodes
• Programmable one-shot generating mode ;
after start at “L” level, output a “H” pulse
(interrupt request is triggered on falling edge)
1 : • Eevent counter mode ; counts falling edges
• Pulse output mode ; output starts with “L” level
• Pulse period measurement mode ;
measures between two rising edges
• Pulse width measurement mode ; measures “L” periodes
• Programmable one-shot generating mode ;
after start at “H” level, output a “L” pulse
(interrupt request is triggered on rising edge)
Timer X count source selection bits
b7 b6
0 0 : f(XIN)/2
0 1 : f(XIN)/16
1 0 : f(XCIN)
1 1 : Input signal from CNTR0 pin
Timer Y count source selection bits
b7 b6
0 0 : f(XIN)/2
0 1 : f(XIN)/16
1 0 : f(XCIN)
1 1 : Input signal from CNTR1 pin
b0
Timer XY control register
(TXYCON : address 001416)
Timer X stop control bit
0 : start counting
1 : stop counting
Timer Y stop control bit
0 : start counting
1 : stop counting
Not used (returns “0” when read)
Fig. 18. Structure of Timer X mode register, Timer Y mode register, and Timer XY control register
1-28
3807 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
FFFF16
TL
000016
TR
TR
TR
TL: A value set to a timer latch
TR: Timer interrupt request
Fig. 19. Timing chart of Timer•Event counter mode
FFFF16
TL
000016
TR
Waveform output from
CNTR0/CNTR1 pin
CNTR
TR
TR
TR
CNTR
TL: A value set to a timer latch
TR: Timer interrupt request
CNTR: CNTR0/CNTR1 interrupt request
This example’s condition:
CNTR0/CNTR1 active edge switch bit “0”:
⇒ output starts with “H” level, interrupt at falling edge
Fig. 20. Timing chart of Pulse output mode
3807 GROUP USER’S MANUAL
1-29
HARDWARE
FUNCTIONAL DESCRIPTION
000016
T3
T2
T1
FFFF16
TR
TR
T2
FFFF16+T1
T3
FFFF16
Signal input from
CNTR0/CNTR1 pin
CNTR
CNTR
CNTR
CNTR
TR: Timer interrupt request
CNTR: CNTR0/CNTR1 interrupt request
This example’s condition:
CNTR0/CNTR1 active edge switch bit set to “1”
⇒ measure from rising edge to rising edge; interrupt at rising edge
Fig. 21. Timing chart of Pulse period measurement mode
000016
T3
T2
T1
FFFF16
TR
FFFF16+T2
TR
T1
T3
Signal input from
CNTR0/CNTR1 pin
CNTR
TR: Timer interrupt request
CNTR: CNTR0/CNTR1 interrupt request
This example’s condition:
CNTR0/CNTR1 active edge switch bit set to “1”
⇒ measure “L” width; interrupt at rising edge
Fig. 22. Timing chart of Pulse width measurement mode
1-30
3807 GROUP USER’S MANUAL
CNTR
CNTR
HARDWARE
FUNCTIONAL DESCRIPTION
FFFF16
T3
L
T2
T1
000016
Signal output from
CNTR0/CNTR1 pin
L
T3
T1
T2
TR
TR
TR
TR
CNTR
CNTR
L: Initial value of timer
TR: Timer interrupt request
CNTR: CNTR0/CNTR1 interrupt request
This example’s condition:
CNTR0/CNTR1 active edge switch bit set to “0”
⇒ output starts with “L” level; interrupt at falling edge
Fig. 23. Timing chart of Programmable waveform generating mode
FFFF16
L
TR
TR
TR
Signal input from
INT0/INT1 pin
Signal output from
CNTR0/CNTR1 pin
L
L
CNTR
L
CNTR
L: One-shot pulse width; timer latch value
TR: timer interrupt request
CNTR: CNTR0/CNTR1 interrupt request
This example’s condition:
CNTR0/CNTR1 active edge switch bit set to “0”
⇒ output a “H” pulse; interrupt at falling edge
Fig. 24. Timing chart of Programmable one-shot generating mode
3807 GROUP USER’S MANUAL
1-31
HARDWARE
FUNCTIONAL DESCRIPTION
ts
Timer X/Timer Y
count source
Timer X/Timer Y
PWM output signal
m ✕ ts
n ✕ ts
(m+n) ✕ ts
CNTR
TR
TR
CNTR: CNTR0/CNTR1 interrupt request
TR: Timer interrupt request
PWM waveform (duty : m/(m + n) and period: (m + n) ✕ ts) is output
m : the setting value of TXH/TYH (m = 0 to 255)
n: the setting value of TXL/TYL (n = 0 to 255)
ts: the period of timer X / timer Y count source
This example's condition:
CNTR0/CNTR1 active edge switch bit set to “0”
⇒ output starts with “H” level; interrupt at falling edge
Fig. 25. Timing chart of PWM mode
1-32
3807 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
●Timer 1, Timer 2, Timer 3
Timer 1 to 3 are 8-bit timers for which the count source can be selected through timer 123 mode register.
b7
b0
Timer 123 mode register
(T123M : address 002916)
(1) Timer 2 write control
Timer 2 write control bit (b2) of timer 123 mode register allows to
select whether a value written to timer 2 is written to timer latch and
timer synchronously or to the timer latch only.
If only the timer latch is written to, the value is set only to the reloadlatch by writing a value to the timer address at that time. The
content of timer is reloaded with the next underflow. Usually writing
operation to the timer latch and timer synchronously is selected. And
a value is written to the timer latch and timer synchronously when a
value is written to the timer address.
If only the timer latch is written to, it may occur that the value set to
the counter is not constant, when the timing with which the reloadlatch is written to and the underflow timing is nearly the same.
TOUT output active edge switch bit
0 : start with "H" output
1 : start with "L" output
TOUT output control bit
0 : TOUT output disabled
1 : TOUT output enabled
Timer 2 write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer 2 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode)
Timer 3 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode)
Timer 1 count source selection bits
00 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode)
01 : f(XIN)/2 (or f(XCIN)/2 in low-speed mode)
10 : f(XCIN)
11 : Not available
(2) Timer 2 output control
When timer 2 output (T OUT) is enabled, inverted signals are output
from T OUT pin each time timer 2 has underflow. For this reason, set
the double-function port of T OUT pin to output mode.
Not used (returns “0” when read)
■Precautions on timers 1 to 3
When the count source for timer 1 to 3 is switched, it may occur that
short pulses are generated in count signals and that the timer count
value shows big changes. When timer 1 output is selected as timer 2
or timer 3 count source, short pulses are generated to
signals output from timer 1 through writing timer 1. Due to that, the
count values for timer 2 and 3 may change very often.
Therefore, when the count sources for timer 1 to 3 are set, set the
values in order starting from timer 1.
Fig. 26. Structure of Timer 123 mode register
Data bus
f(XIN)/16
(f(XCIN)/16 in low-speed mode)
Timer 1 count source
selection bits
"00"
Timer 1 latch (8)
"01"
f(XIN)/2
Timer 1 (8)
(f(XCIN)/2 in low-speed mode)
"10"
f(XCIN)
Timer 2 count source
selection bit
Timer 2 latch (8)
"0"
Timer 2 (8)
"1"
f(XIN)/16
(f(XCIN)/16 in low-speed mode)
Timer 2 write
control bit
Timer 1
interrupt
request
Timer 2
interrupt
request
TOUT output
TOUT output active control bit
edge switch bit
"0"
Q S
P50/TOUT
P50 direction
register
P50 latch
"1"
T
Q
"0"
TOUT output control bit
f(XIN)/16
(f(XCIN)/16 in low-speed mode)
Timer 3 latch (8)
Timer 3 (8)
"1"
Timer 3 count source
selection bit
Timer 3
interrupt
request
Fig. 27. Block diagram of Timer
3807 GROUP USER’S MANUAL
1-33
HARDWARE
FUNCTIONAL DESCRIPTION
●Real time output port
The 3807 group has two on-chip sets of real time output ports (RTP).
The two sets of real time output ports consist of two 16-bit timers A
and B and eight 8-bit real time port registers. Synchronous to the
reloading of timers A and B, the real time port register values are
output from ports P82 to P87, P3 0 and P31. The real time port registers consist of 8-bit register 0 to 7. Each port with its corresponding
bits is shown in figure 26.
Timer A and timer B have each two 16-bit timer latches. Figure 28
shows the real time port block diagram and figure 29 and 30 show
the structure of the real time port control registers 0 to 3.
There are four operating modes for real time ports which are:
8 repeated load mode, 6 repeated load mode, 5 repeated load mode
and one-shot pulse generating mode. Each operating mode can be
set for timer A and timer B separately. However, switch modes during timer count stop.
(1) 8 repeated load mode
The output operation for each value of the real time port registers 7
to 0 is performed repeatedly in association with an alternate underflow
of the corresponding timer latch 1 or 0. The real time port output
pointer changes in sequence as a cycle of 8 repeated load operations as "7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, ...."
The initial value at the generation of a start trigger can be specified
by setting a value in the output pointer. Figure 31 shows a timing
chart of 8 repeated load mode.
(2) 6 repeated load mode
The output operation for each value of real time port registers 5 to 0
is performed repeatedly in association with an alternate underflow of
the corresponding timer latch 1 to 0. The real time port output pointer
changes in sequence as a cycle of 6 repeated load operations as "5,
4, 3, 2, 1, 0, 5, 4, 3, 2, 1, 0, 5, 4, ...."
The initial value at the generation of a start trigger can be specified
by setting a value in the output pointer. Figure 32 shows a timing
chart of the 6 repeated load mode.
(3) 5 repeated load mode
The output operation for each value of real time port registers 4 to 0
is performed repeatedly in association with an alternate underflow of
the corresponding timer latch 1 or 0. The real time port output pointer
changes in sequence as a cycle of 5 repeated load operations as "4,
3, 2, 1, 0, 4, 3, 2, 1, 0, 4, 3, 2, 1, ...." The initial value at the generation
of a start trigger can be specified by setting a value in the output
pointer. Figure 33 shows a timing chart of the 5 repeated load mode.
(4) One-shot pulse generation mode
The output operation for each value of real time port registers 2 to 0
is performed only once in association with trigger generation and an
underflow of timer latch 1 or 0. After a trigger is generated, the value
of real time port register 1 is output from the real time output port and
the output pointer value becomes "0002". At each underflow of the
timer, the each value of real time port registers 0 and 2 is output in
ascending sequence, then the operation is completed.
After completion of the operation, the value of real time port register
2 is continuously output from the real time output port and the output
pointer value continues to be "0012" until the next start trigger is
1-34
generated. In this condition, the real time port function is in the wait
status.
When this mode is selected, the pointer value is not changed by
writing a value into the output pointer. If external trigger is specified
as trigger selection when this mode is selected, a rising and falling
double edge trigger is generated regardless of the contents of the
INT4 interrupt source bit (b7) of the interrupt edge selection register.
Figure 34 shows a timing chart of the one-shot pulse generation mode.
(5) Selection of timer interrupt mode
The timer is a count-down system. The contents of the timer latch
are reloaded by the count pulse subsequent to the moment when the
contents of the counter becomes "000016". At the same time, the
interrupt request bit corresponding to each timer is set to "1." The
interrupt request corresponding to the value of the real time port
output pointer can also be controlled. For controlling the interrupt
request bit, refer to the item pertaining to the timer interrupt mode
selection bit of the real time port control register 1,2 shown in figure
29 and 30.
(6) Switch of timer count source
The timer A and the timer B can select the system clock φ divided by
2 or 16 as a count source with the timer A, B count source selection
bit (b0) of real time port control register 0.
[Timer latches]
Each of the timer A and the timer B has two 16-bit timer latches. Data
is written into the 8 low-order bits and the 8 high-order bits in this
order. When the high-order side has been written, the next latch is
automatically specified. The writing pointer changes in sequence as
"1, 0, 1, 0, 1, ...." The timer latch to be written first can be specified by
setting the timer writing pointer. Data is not written directly into the
timer A and the timer B. When reading the contents of the timer, the
count value at that point of time is read. Read the high-order side first
and then the low-order side. The low-order side value is read with
the same timing as that for the high-order side value and held at the
timer read latch. The data held state is released by reading the loworder side. At a reload operation of the timer A or the timer B. Timer
latch 1 is reloaded as the initial value after a trigger is generated.
After that, the timer latch is reloaded in sequence as "0, 1, 0, 1, ...."
The timer latch value cannot be read out.
[Start trigger]
The operation of the real time port is started by a start trigger. When
a start trigger is generated, the value of the real time port register
specified by the output pointer (the value of real time port register 1
in the one-shot pulse generation mode) is output from the real time
output port.
The value of timer latch 1 is reloaded into the timer A or the timer B
and the timer count A, B source stop bit is released, so that the timer
count is started.
After that, when the timer underflows, data is transferred from the
real port register to the real time output port.
As a start trigger, either internal trigger or external trigger can be
selected by the timer A start trigger selection bit (b2) or timer B start
trigger selection bit (b5) of real time port control register 0.
3807 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
When the internal trigger is selected, a start trigger is generated by
an input signal of the INT4 pin. The start trigger becomes a falling
edge when the INT4 interrupt edge selection bit is "0" and a rising
edge when this bit is "1".
When the external trigger is selected in the one-shot pulse generation mode, the start trigger becomes a rising/falling double edge trigger regardless of the contents of the INT 4 interrupt edge selection
bit.
[Real time port registers] RTP
The data to be output to real time ports is written into 8 real time port
registers 0 to 7. The correspondence between each bit of real time
port registers and each port output is as follows :
P31: bit 7 of real time port registers 7 to 0
P30: bit 6 of real time port registers 7 to 0
P87: bit 5 of real time port registers 7 to 0
P86: bit 4 of real time port registers 7 to 0
P85: bit 3 of real time port registers 7 to 0
P84: bit 2 of real time port registers 7 to 0
P83: bit 1 of real time port registers 7 to 0
P82: bit 0 of real time port registers 7 to 0
It can be selected for each bit by real time port control register 3
whether the output of each port is to be used as an ordinary I/O port
or a real time port output.
[Real time port data pointer]
It can be optionally specified by the real time port data pointers A or
B and the real time port data pointer A or B switching bit in which real
time port register the output data is to be set or form which real time
port register the data output is to be started.
When writing output data into the real time port register, set the real
time port data pointer A, B switch bit to "0" (select the R/W pointer)
and also write a value into the 3 bits of the real time port data
pointers A, B. With this, the real time port register for writing will be
specified. After that, when a value is written into the real time port
register (address 002A 16), the data is written into the specified real
time port register and also the R/W pointer value is automatically
decreased by 1. Then writing data is enabled into the next real time
port register.
A value of "0002" to "1112" can be set int the R/W pointer regardless
of the operating mode specified by the timer A, B operating mode
selection bit, and the R/W pointer value is automatically decreased
by 1 by writing data into the real time port register. However, when a
value becomes "0002", the R/W pointer value is decreased by 1 in
the numeral range of stages to be used in each operating mode unless the R/W pointer is set again at the subsequent write operation to
the real time port register. When "111 2 (=7)" is set in the R/W pointer,
the R/W pointer operation in each selected mode is as follows :
•During 8 repeated load mode 7➝6➝5➝4➝3➝2➝1➝0➝7➝6➝5...
•During 6 repeated load mode 7➝6➝5➝4➝3➝2➝1➝0➝5➝4➝3...
•During 5 repeated load mode 7➝6➝5➝4➝3➝2➝1➝0➝4➝3➝2....
•During one-shot pulse generation mode
7➝6➝5➝4➝3➝2➝1➝0➝2➝1➝0....
When reading the real time port register, set the real time port data
pointer A, B switch bit to "0" (select the R/W pointer) and also writing
a value into the 3 bits of the real time port data pointer A, B to specify
the real time port register for reading. After that, the value of the
specified real time port register can be read by reading the real time
port register (address 002A16). In this care, however, the R/W pointer
value is not counted down automatically. Accordingly, to read another real time port register, rewrite the R/W pointer beforehand.
To specify a read port register to be output to the real time output
port, set the real time port data pointer A, B switch bit to "1" (select an
output pointer) and also set a value in the 3 bits of the real time port
data pointer A or B.
When a start trigger is generated, data is output beginning with the
real time port register set in the output pointer and the output pointer
value is automatically decreased by 1.
At each underflow of the timer A or timer B, the output pointer value
is automatically decreased by 1. Regarding the case of the one-shot
pulse generation mode, however, refer to the item pertaining to the
one-shot pulse generation mode.
When the real time port data pointer A to B has been read, only the
output pointer can be read.
■Notes regarding all modes
•When the trigger is generated again during timer count operation,
the operation is started from the beginning. In this case, put an
interval of 3 cycles or more between the generation of a trigger and
the generation of the next trigger, If the generation of the next trigger occurs almost concurrently with the underflow timing of the timer,
the next real time output may not be performed normally.
•To stop the timer count after generation of a start trigger, write "1" in
the timer A, B count source stop bit of real time port control register
0 at an interval of 3 cycles or more of the timer count source.
•To change the contents of the real time port data pointer A, B switch
bit, the real time port data pointer must be specified simultaneously.
Therefore, use the LDM/STA instruction instead of the SEB/CLB
instruction.
•If the timer A, B count source stop bit is changed ("1"➝"0") by a start
trigger between the read operation and the write operation of a
read-modify-write instruction such as the SEB instruction which is
used in real time port control register 0, the timer count will stop,
having an effect on the real time output.
An maximum interval of 2 cycles of the count source is required
before the timer A, B count source stop bit is cleared to "0" which
indicates the count operation state after a start trigger is generated
regardless of whether the start trigger is an internal trigger or an
external trigger.
Accordingly, do not use the read-modify-write instruction for real
time port control register 0 in this period. If a write operation for real
time port control register 0 with any purpose other than stopping
the timer count is performed concurrently with the generation of a
start trigger, be sure to use such an instruction for writing "0" into
the timer A, B count source stop bit as the LDM/STA instruction.
Even if "0" is written into the timer A, B count source stop bit, the
timer count remains in the stop state without change.
•When the timing for writing to the high-order side reload latch is
almost equal to the underflow timing, an undesirable value may be
set in the timer A or timer B.
•If the real time output port is selected by real time port control register 3 after resetting, "L" is output from this pin until a start trigger is
generated.
3807 GROUP USER’S MANUAL
1-35
HARDWARE
FUNCTIONAL DESCRIPTION
Data bus
XCIN
"10"
1/2
Timer A write
pointer (1)
Timer A, B
count source
"0" selection bit
Main clock division
ratio selection bits
XIN
"00"
"01"
1/16
Timer A 1H latch (8)
Timer A 1L latch (8)
Timer A 0H latch (8)
Timer A 0L latch (8)
"1"
Timer A interrupt
request
Timer A (16)
P5
P301/RTP0
/RTP7
/PWM0
Timer A count
source stop bit
P31 latch
Timer A read-out latch (8)
PWM0èoóÕ
Real time output
Real time port output selection bit (P31)
Timer B write
pointer (1)
P31 direction register
P30/RTP6
Timer B 1H latch (8)
Timer B 1L latch (8)
Timer B 0H latch (8)
Timer B 0L latch (8)
P30 latch
PWM1èoóÕ
Real time output
Real time port output selection bit (P30)
Timer B count
source stop bit
Timer B read-out latch (8)
Real time port • port
allocation selection bit
P30 direction register
P87/RTP5
Timer B interrupt
request
Timer B (16)
Real time port R/W
pointer A (3)
"1"
Real time port R/W
pointer B (3)
"0"
P87 latch
0
7
Real time port
register 0 (8)
Real time port
register 1 (8)
Real time port
register 2 (8)
Real time port
register 3 (8)
Real time port
register 4 (8)
Real time port
register 5 (8)
Real time port
register 6 (8)
Real time port
register 7 (8)
Real time output
Real time port output selection bit (P87)
P87 direction register
P86/RTP4
P86 latch
Real time output
Real time port output selection bit (P86)
P86 direction register
P85/RTP3
Real time port • port
allocation selection bit
"1"
Real time port output
pointer A (3)
"0"
Real time port output
pointer B (3)
P85 latch
Real time output
Real time port output selection bit (P85)
Output latch (8)
P85 direction register
P84/RTP2
P84 latch
Real time output
Real time port output selection bit (P84)
P84 direction register
P83/RTP1
P83 latch
When a start trigger bit is set to "1"
(internal trigger is selected)
A timer latch value is loaded into the timer
When an external start trigger is generated
(external trigger is selected)
A timer latch value is loaded into the timer
Real time output
Real time port output selection bit (P83)
operation
0
1
stop
P83 direction register
P82/RTP0
at reset
P82 latch
Timer count source stop bit is set to "1".
Real time output
Real time port output selection bit (P82)
State transition of timer count source stop bit
P82 direction register
Fig. 28. Block diagram of Real time output port
1-36
3807 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
Real time port control register 0
(RTPCON0 : address 002B16)
Timer A, B count source selection bit
0: f(XIN)/2 or f(XCIN)/2
1: f(XIN)/16 or f(XCIN)/16
Real time port • port allocation selection bit
0: 4-4 port division
(P82 to P85 correspond to timer A; P86, P87, P30, P31 correspond to timer B)
1: 2-6 port division
(P82 to P87 correspond to timer A; P30, P31 correspond to timer B)
Timer A start trigger selection bit
0: Internal trigger (trigger is generated by setting bit 3 to “1”)
1: External trigger (trigger start by external input INT4)
(note)
Timer A start trigger bit (“0” at read-out)
0: Not triggered
1: Timer A start (when bit 2=”0”)
Timer A count source stop bit
0: Count operation (when a start trigger is generated, “0” is set automatically)
1: Count stop
Timer B start trigger selection bit
0: Internal trigger (trigger is generated by setting bit 6 to “1”)
1: External trigger (trigger start by external input INT4)
(note)
Timer B start trigger bit (“0” at read-out)
0: Not triggered
1: Timer B start (when bit 5=”0”)
Timer B count source stop bit
0: Count operation (when a start trigger is generated, “0” is set automatically)
1: Count stop
Note: Rising or falling edge of external input can be switched by the INT4 interrupt edge selection bit of interrupt edge selection register
(however, at one-shot pulse generating mode the timer is triggered at both rising and falling edge).
b7
b0
Real time port control register 1
(RTPCON1 : address 002C16)
Timer A operation mode selection bit
00: 8 repeated load mode
01: 6 repeated load mode
10: 5 repeated load mode
11: One-shot pulse generating mode
Real time port data pointer A switch bit (“1” at read-out )
0: R/W pointer
1: Output pointer
Timer A interrupt mode selection bit
0: Interrupt request occurs with RTP output pointer value “0002”
1: Interrupt request occurs regardless of RTP output pointer value
Real time port data pointer A (output pointer value at read-out)
000: indicates real time port register 0
001: indicates real time port register 1
010: indicates real time port register 2
011: indicates real time port register 3
100: indicates real time port register 4
101: indicates real time port register 5
110: indicates real time port register 6
111: indicates real time port register 7
Timer A write pointer
0: indicates timer A0 latch
1: indicates timer A1 latch
Fig. 29. Structure of Real time output port related register (1)
3807 GROUP USER’S MANUAL
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HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
Real time port control register 2
(RTPCON2 : address 002D16)
Timer B operating mode selection bit
00: 8 repeated load mode
01: 6 repeated load mode
10: 5 repeated load mode
11: One-shot pulse generating mode
Real time port data pointer B switch bit (“1” at read-out )
0: R/W pointer
1: Output pointer
Timer B interrupt mode selection bit
0: Interrupt request occurs with RTP output pointer value “0002”
1: Interrupt request occurs regardless of RTP output pointer value
Real time port data pointer B (output pointer value at read-out)
000: indicates real time port register 0
001: indicates real time port register 1
010: indicates real time port register 2
011: indicates real time port register 3
100: indicates real time port register 4
101: indicates real time port register 5
110: indicates real time port register 6
111: indicates real time port register 7
Timer B write pointer
0: indicates timer B0 latch
1: indicates timer B1 latch
b7
b0
Real time port control register 3
(RTPCON3 : address 002E16)
Real time port output selection bit (P82)
0: I/O port
1: Real time output port
Real time port output selection bit (P83)
0: I/O port
1: Real time output port
Real time port output selection bit (P84)
0: I/O port
1: Real time output port
Real time port output selection bit (P85)
0: I/O port
1: Real time output port
Real time port output selection bit (P86)
0: I/O port
1: Real time output port
Real time port output selection bit (P87)
0: I/O port
1: Real time output port
Real time port output selection bit (P30)
0: I/O port
1: Real time output port
Real time port output selection bit (P31)
0: I/O port
1: Real time output port
Fig. 30. Structure of Real time output port related register (2)
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HARDWARE
FUNCTIONAL DESCRIPTION
Timer A operating mode selection bit: in case of 8 repeated load mode
4-4 port division
Synchronous to the start trigger the timer latch value is
loaded into the timer and timer count operation starts.
Timer count source
stop bit
Timer A count value
Port P82 / RTP0
Port P83 / RTP1
Port P84 / RTP2
Port P85 / RTP3
Real time port output
pointer A
A1
A0
A1
A0
A1
A0
A1
A0
A1
A0
A1
#7
#6
#5
#4
#3
#2
#1
#0
#7
#6
#5
1
1
0
0
0
0
0
1
1
1
0
0
1
1
1
0
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
5
4
3
7
6
5
4
A0
A1
6
7
2
1
0
#7—0: Data of real time port registers 7 to 0
Fig. 31. 8 repeated load mode operation
Timer A operating mode selection bit: in case of 6 repeated load mode
4-4 port division (3 ports out of P82/RTP0 to P85/RTP3 are used)
Synchronous to the start trigger the timer latch value is
loaded into the timer and timer count operation starts.
Timer count
source stop bit
Timer A count value
Port P82 / RTP0
Port P83 / RTP1
Port P84 / RTP2
Real time port output
pointer A
5
A1
A0
A1
#5
#4
#3
1
1
0
A0
A1
A0
A1
A0
A1
#2
#1
#0
#5
#4
#3
#2
#1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
1
1
4
3
2
0
5
4
3
2
1
0
1
#5—0: Data of real time port registers 5 to 0
Fig. 32. 6 repeated load mode operation
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HARDWARE
FUNCTIONAL DESCRIPTION
Timer A operating mode selection bit: in case of 5 repeated load mode
2-6 division (5 ports out of P82/RTP0 to P87/RTP5 are used)
Synchronous to the start trigger the timer latch value is
loaded into the timer and timer count operation starts.
Timer count
source stop bit
Timer A count value
A1
A0
A1
A0
A1
A0
A1
A0
A1
A0
#4
#3
#2
#1
#0
#4
#3
#2
#1
#0
1
0
0
0
1
1
0
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
1
1
3
2
1
0
4
3
2
1
0
4
Port P82 / RTP0
Port P83 / RTP1
Port P84 / RTP2
Port P85 / RTP3
Port P86 / RTP4
Real time port output
pointer A
4
#4—0: Data of real time port registers 4 to 0
Fig. 33. 5 repeated load mode operation
Timer A operating mode selection bit: in case of one-shot pulse generating mode
Synchronous to the start trigger the timer latch value is
loaded into the timer and timer count operation starts.
External start trigger input
INT4
Timer count
source stop bit
Counting stops when timer
A0 latch has underflow
Counting stops when timer
A0 latch has underflow
Timer A count value
A1
A0
#1
#0
0
1
Port P83 / RTP1
1
Real time port output
pointer A
0
Port P82 / RTP0
A1
A0
#2
#1
#0
#2
0
0
1
0
1
0
1
1
0
2
1
0
2
1
#2—0: Data of real time port registers 2 to 0
Fig. 34. One-shot pulse generating mode operation
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3807 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
Serial I/O
●Serial I/O1
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O1 mode can be selected by setting the
serial I/O1 mode selection bit (b6) of the serial I/O1 control register
to "1." For clock synchronous serial I/O, the transmitter and the
receiver must use the same clock for serial I/O1 operation. If an
internal clock is used, transmit/receive is started by a write signal to
the Transmit/Receive buffer register (TB/RB) (address:0018 16).
Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation during Serial I/O1 operation.
Data bus
Serial I/O 1 control register
Address 001816
Receive buffer register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive shift register
P44/RXD
Address 001A16
Shift clock
Clock control circuit
P46/SCLK1
Serial I/O1 synchronous clock selection bit
Division ratio 1/(n+1)
BRG count source selection bit
f(X
IN)
XIN
Baud rate generator
1/4
(f(XCIN) in low-speed mode)
Address 001C16
1/4
P47/SRDY1
Clock control circuit
Falling edge detector
F/F
Transmit shift register shift
completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Shift clock
P45/TXD
Transmit shift register
Transmit buffer register
Address 001816
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Address 001916
Data bus
Fig. 35. Block diagram of clock synchronous serial I/O1
Transmit/Receive shift clock
(1/2—1/2048 of internal
clock or external clock)
Serial output TxD
D0
D1
D2
D3
D4
D5
D6
D7
Serial input RxD
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY1
Write-in signal to transmit/receive
buffer register (address 001816)
TBE = 0
RBF = 1
TSC = 1
Overrun error (OE)
detection
TBE = 1
TSC = 0
Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting transmit interrupt source selection bit (TIC) of the serial I/O1
control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 36. Operation of clock synchronous serial I/O1 function
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HARDWARE
FUNCTIONAL DESCRIPTION
The transmit and receive shift registers each have a buffer (the two
buffers have the same address in memory). Since the shift register
cannot be written to or read from directly, transmit data is written to
the transmit buffer, and receive data is read from the receive buffer.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer can hold a character while the next character is being received.
(2) Asynchronous Serial I/O (UART) Mode
Asynchronous serial I/O1 mode (UART) can be selected by clearing the Serial I/O1 mode selection bit (b6) of the Serial I/O1 control
register to "0." Eight serial data transfer formats can be selected
and the transfer formats used by a transmitter and receiver must
be identical.
Data bus
Address 001816
P44/RXD
Serial I/O1 control register Address 001A16
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive buffer register
OE
Character length selection bit
7 bit
STdetector
Receive shift register
1/16
8 bit
PE FE
UART control register
SP detector
Clock control circuit
Serial I/O1 synchronous clock
selection bit
P46/SCLK1
f(XIN)
Address 001B16
Division ratio 1/(n+1)
Baud rate generator
Address 001C16
BRG count source selection bit
(f(XCIN) in low-speed mode)
1/4
ST/SP/PA generator
Transmit shift register shift
completion flag (TSC)
1/16
P45/TXD
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit shift register
Character length selection bit
Transmit buffer register
Address 001816
Transmit buffer empty flag (TBE)
Serial I/O1 status register Address 001916
Data bus
Fig. 37. Block diagram of UART serial I/O1
Transmit or receive clock
Write-in signal to
transmit buffer register
TBE=0
TSC=0
TBE=1
TBE=0
TBE=1
TSC=1*
Serial output TXD
ST
D0
D1
SP
ST
D0
D1
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit
Read-out signal from
receive buffer register
SP
* Generated at 2nd bit in 2-stop bit mode
RBF=0
RBF=1
RBF=1
Serial input RXD
ST
D0
D1
SP
ST
D0
D1
SP
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception).
2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt
source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes "1".
4: After data is written to the transmit buffer register when TSC=1, 0.5 to 1,5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 38. Operation of UART serial I/O1 function
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3807 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
All bits of the serial I/O1 status register are initialized to "0" at reset,
but if the transmit enable bit (b4) of the serial I/O1 control register
has been set to "1", the transmit shift register shift completion flag
(b2) and the transmit buffer empty flag (b0) become "1."
[Transmit Buffer Register/Receive Buffer Register] TB/RB (001816)
The transmit buffer and the receive buffer are located in the same
address. The transmit buffer is write-only and the receive buffer is
read-only. If a character bit length is 7 bits, the MSB of data stored in
the receive buffer is "0".
[Serial I/O1 Control Register] SIO1CON (001A16 )
The serial I/O1 control register contains eight control bits for serial
I/O1 functions.
[Serial I/O 1 Status Register] SIO1STS (001916)
The read-only serial I/O1 status register consists of seven flags (b0
to b6) which indicate the operating status of the serial I/O1 function
and various errors. Three of the flags (b4 to b6) are only valid in
UART mode. The receive buffer full flag (b1) is cleared to "0" when
the receive buffer is read.
The error detection is performed at the same time data is transferred
from the receive shift register to the receive buffer register, and the
receive buffer full flag is set. A writing to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (b3 to b6, respectively). Writing "0" to the serial I/O1 enable bit (SIOE : b7 of the serial
I/O1 control register) also clears all the status flags, including the
error flags.
b7
b0
b0
Serial I/O1 control register
(SIO1CON : address 001A16)
BRG count source selection bit (CSS)
(f(XCIN) in low-peed mode)
0: f(XIN)
1: f(XIN)/4 ((XCIN)/4 in low-speed mode)
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG/ 4
(when clock synchronous serial I/O is selected)
BRG/16 (UART is selected)
1: External clock input
(when clock synchronous serial I/O is selected)
External clock input/16 (UART is selected)
SRDY1 output enable bit (SRDY)
0: P47 pin operates as ordinaly I/O pin
1: P47 pin operates as SRDY1 output pin
Overrun error flag (OE)
0: No error
1: Overrun error
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Serial I/O1 mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Not used (returns "1" when read)
b0
[Baud Rate Generator] BRG (001C16)
The baud rate generator determines the baud rate for serial transfer.
With the 8-bit counter having a reload register the baud rate generator divides the frequency of the count source by 1/(n+1), where n is
the value written to the baud rate generator.
b7
Serial I/O1 status register
(SIO1STS : address 001916)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
b7
[UART Control Register] UARTCON (001B16 )
The UART control register consists of four control bits (b0 to b3)
which are valid when asynchronous serial I/O is selected and set the
data format of an data transfer. One bit in this register (b4) is
always valid and sets the output structure of the P45/TxD pin.
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P44 to P47 operate as ordinary I/O pins)
1: Serial I/O1 enabled
(pins P44 to P47 operate as serial I/O pins)
UART control register
(UARTCON : address 001B16)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity cheching disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P45/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
Not used (return "1" when read)
Fig. 39. Structure of serial I/O1 related register
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HARDWARE
FUNCTIONAL DESCRIPTION
●Serial I/O2
The serial I/O2 can be operated only as the clock synchronous
type. As a synchronous clock for serial transfer, either internal clock
or external clock can be selected by the serial I/O2 synchronous
clock selection bit (b6) of serial I/O2 control register 1.
The internal clock incorporates a dedicated divider and permits
selecting 6 types of clock by the internal synchronous clock selection bit (b2, b1, b0) of serial I/O2 control register 1.
Regarding SOUT2 and SCLK2 being output pins, either CMOS output
format or N-channel open-drain output format can be selected by
the P7 1/SOUT2, P72/SCLK2 P-channel output disable bit (b7) of
serial I/O2 control register 1.
When the internal clock has been selected, a transfer starts by a
write signal to the serial I/O2 register (address 001F16). After completion of data transfer, the level of the SOUT2 pin goes to high impedance automatically but bit 7 of the serial I/O2 control register 2 is
not set to "1" automatically.
When the external clock has been selected, the contents of the
serial I/O2 register is continuously sifted while transfer clocks are
input. Accordingly, control the clock externally. Note that the SOUT2
pin does not go to high impedance after completion of data transfer.
To cause the SOUT2 pin to go to high impedance in the case where
the external clock is selected, set bit 7 of the serial I/O2 control
register 2 to "1" when SCLK2 is "H" after completion of data transfer.
After the next data transfer is started (the transfer clock falls), bit 7
of the serial I/O2 control register 2 is set to "0" and the SOUT2 pin is
put into the active state.
Regardless of the internal clock to external clock, the interrupt request bit is set after the number of bits (1 to 8 bits) selected by the
optional transfer bit is transferred. In case of a fractional number of
bits less than 8 bits as the last data, the received data to be stored
in the serial I/O2 register becomes a fractional number of bits close
to MSB if the transfer direction selection bit of serial I/O2 control
register 1 is LSB first, or a fractional number of bits close to LSB if
the said bit is MSB first. For the remaining bits, the previously received data is shifted.
At transmit operation using the clock synchronous serial I/O, the
SCMP2 signal can be output by comparing the state of the transmit
pin SOUT2 with the state of the receive pin SIN2 in synchronization
with a rise of the transfer clock. If the output level of the SOUT2 pin is
equal to the input level to the SIN2 pin, "L" is output from the SCMP2
pin. If not, "H" is output. At this time, an INT2 interrupt request can
also be generated. Select a valid edge by bit 2 of the interrupt edge
selection register (address 003A 16).
b7
Serial I/O2 control register 1
(SIO2CON1 : address 001D16)
Internal synchronous clock selection bit
b2 b1 b0
0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode)
0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode)
0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode)
1 1 0: f(XIN)/128 f(XCIN)/128 in low-speed mode)
1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode)
Serial I/O2 port selection bit
0: I/O port
1: SOUT2,SCLK2 output pin
SRDY2 output enable bit
0: P73 pin is normal I/O pin
1: P73 pin is SRDY2 output pin
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O2 synchronous clock selection bit
0: External clock
1: Internal clock
P71/SOUT2 ,P72/SCLK2 P-channel output disable bit
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode )
b7
b0
Serial I/O2 control register 2
(SIO2CON2 : address 001E16)
Optional transfer bits
b2 b1 b0
0 0 0: 1 bit
0 0 1: 2 bit
0 1 0: 3 bit
0 1 1: 4 bit
1 0 0: 5 bit
1 0 1: 6 bit
1 1 0: 7 bit
1 1 1: 8 bit
Not used ( returns "0" when read)
Serial I/O2 I/O comparison signal control bit
0: P51 I/O
1: SCMP2 output
SOUT2 pin control bit (P71)
0: Output active
1: Output high-impedance
Fig. 40. Structure of Serial I/O2 control registers 1, 2
[Serial I/O2 Control Registers 1, 2] SIO2CON1 / SIO2CON2
The serial I/O2 control registers 1 and 2 are containing various selection bits for serial I/O2 control as shown in Figure 40.
1-44
b0
3807 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
Internal synchronous
clock selection bit
1/8
XCIN
1/16
"10"
"00"
"01"
XIN
1/64
1/128
1/256
P73 latch
Serial I/O2 synchronous
clock selection bit
"0"
P73/SRDY2
Data bus
1/32
Divider
Main clock division ratio
selection bits (Note)
"1"
SCLK2
SRDY2
Synchronous circuit
"1"
SRDY2 output enable bit
"0"
External clock
P72 latch
Optional transfer bits (3)
"0"
P72/SCLK2
Serial I/O2
interrupt request
Serial I/O counter 2 (3)
"1"
Serial I/O2 port selection bit
P71 latch
"0"
P71/SOUT2
"1"
Serial I/O2 port selection bit
Serial I/O2 register (8)
P70/SIN2
P51 latch
"0"
P51/SCMP2/INT2
D
Q
"1"
Serial I/O2 I/O comparison
signal control bit
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register.
Fig. 41. Block diagram of Serial I/O2
Transfer clock (Note 1)
Write-in signal to
serial I/O2 register
(Note 2)
Serial I/O2 output SOUT2
D0
D1
.
D2
D3
D4
D5
D6
D7
Serial I/O2 input SIN2
Receive enable signal SRDY2
Serial I/O2 interrupt request bit set
Notes 1: When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode) can be selected
by setting bits 0 to 2 of serial I/O2 control register 1.
2: When the internal clock is selected as a transfer clock, the SCOUT2 pin has high impedance after transfer completion.
Fig. 42. Timing chart of Serial I/O2
3807 GROUP USER’S MANUAL
1-45
HARDWARE
FUNCTIONAL DESCRIPTION
SCMP2
SCLK2
SOUT2
SIN2
Judgement of I/O data comparison
Fig. 43. SCMP2 output operation
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3807 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
A-D Converter
f(XIN) to at least 500kHz during A-D conversion. Use a CPU system
clock dividing the main clock XIN as the internal clock φ .
[A-D Conversion Register] AD (address 003516 )
The A-D conversion register is a read-only register that contains the
result of an A-D conversion. When reading this register during an
A-D conversion, the previous conversion result is read.
■Note
When the A-D external trigger is invalidated by the AD external
trigger valid bit, any interrupt request is not generated at a fall of the
ADT input. When the AD external trigger valid bit is set to "1" beforehand, A-D conversion is not started by writing "0" into the AD conversion completion bit and "0" is not written into the AD conversion
completion bit. Do not set "0" in the AD conversion completion bit
concurrently with the timing at which the AD external trigger valid bit
is rewritten. Put an interval of at least 50 cycles to more of the
internal clock φ between a start of A-D conversion and the next start
of A-D conversion.
[A-D Control Register] ADCON
The A-D control register controls the A-D conversion process. Bits 0
to 3 of this register select specific analog input pins. Bit 4 signals the
completion of an A-D conversion. The value of this bit remains at "0"
during an A-D conversion, then changes to "1" when the A-D conversion is completed. Writing "0" to this bit starts the A-D conversion.
When bit 6, which is the AD external trigger valid bit, is set to "1", this
bit enables A-D conversion at a falling edge of an ADT input. Set
ports which is also used as ADT pins to input when using an A-D
external trigger. Bit 5 is the ADVREF input switch bit. Writing "1" to
this bit, this bit always causes ADVREF connection. Writing "0" to this
bit causes ADV REF connection only during A-D conversion and cut
off when A-D conversion is completed.
b7
b0
A-D control register
(ADCON : address 003416)
Analog input pin selection bit
0000: P73/SRDY2/ADT/AN0
0001: P74/AN1
0010: P75/AN2
0011: P76/AN3
0100: P77/AN4
0101: P60/AN5
0110: P61/AN6
0111: P62/AN7
1000: P63/CMPIN/AN8
1001: P64/CMPREF/AN9
1010: P65/DAVREF/AN10
1011: P80/DA3/AN11
1100: P81/DA4/AN12
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between AV SS
and ADVREF by 256, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports AN 12 to AN0 and
inputs it to the comparator.
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
ADVREF input switch bit
0: OFF
1: ON
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input
voltage with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
conversion interrupt request bit to "1."
Note that the comparator is constructed linked to a capacitor, so set
AD external trigger valid bit
0: A-D external trigger invalid
1: A-D external trigger valid
Interrupt source selection bit
0: Interrupt request at A-D
conversion completed
1: Interrupt request at ADT
input falling
Fig. 44. Structure of A-D control register
Data bus
b7
b0
A-D control register
4
A-D control circuit
Channel selector
P73/SRDY2/ADT/AN0
P74/AN1
P75/AN2
P76/AN3
P77/AN4
P60/AN5
P61/AN6
P62/AN7
P63/CMPIN/AN8
P64/CMPREF/AN9
P65/DAVREF/AN10
P80/DA3/AN11
P81/DA4/AN12
Comparator
ADT/A-D interrupt request
A-D conversion register
8
Resistor ladder
AVSS ADVREF
Fig. 45. Block diagram of A-D converter
3807 GROUP USER’S MANUAL
1-47
HARDWARE
FUNCTIONAL DESCRIPTION
D-A Converter
The 3807 group has an on-chip D-A converter with 8-bit resolution
and 4 channels (DAi (i=1—4)). The D-A converter is performed by
setting the value in the D-A conversion register. The result of D-A
converter is output from DAi pin by setting the DAi output enable bits
to "1." When using the D-A converter, the corresponding port direction register bit (P65/DAVREF/AN10, P56/DA1, P57/DA2, P80/DA3/AN11 ,
P81/DA4/AN12) should be set to "0" (input status).
The output analog voltage V is determined by the value n (base 10)
in the D-A conversion register as follows:
b0
b7
D-A control register
(DACON : address 003316)
DA1 output enable bit
DA2 output enable bit
DA3 output enable bit
DA4 output enable bit
Not used (return "0" when read)
V=DAVREF x n/256 (n=0 to 255)
Where DAVREF is the reference voltage.
0 : Output disabled
1 : Output enabled
At reset, the D-A conversion registers are cleared to "0016", the DAi
output enable bits are cleared to "0", and DAi pin is set to input (high
impedance). The DA output is not buffered, so connect an external
buffer when driving a low-impedance load.
Fig. 46. Structure of D-A control register
Data bus
D-A1 conversion register (003616)
D-A2 conversion register (003716)
D-A3 conversion register (003816)
D-A4 conversion register (003916)
D-A i conversion register (8)
R-2R resistor ladder
DA i output enable bit
P56/DA1
P57/DA2
P80/DA3/AN11
P81/DA4/AN12
Fig. 47. Block diagram of D-A converter
DA i output enable bit (Note)
P56/DA1
P57/DA2
P80/DA3/AN11
P81/DA4/AN12
"0"
R
"1"
2R
R
2R
R
2R
R
2R
"0"
"1"
AVSS
P65/DAVREF/AN10
Note: i=1 to 4
Fig. 48. Equivalent connection circuit of D-A converter
1-48
2R
R
2R
R
2R
2R
2R
LSB
MSB
D-A i conversion
register (Note)
R
3807 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
Analog Comparator
An analog comparator circuit which is independent of peripheral circuits in the microcomputer is incorporated (Note).
An analog comparator outputs the result of comparison with an input
voltage of CMP REF pin which is specified as a reference voltage and
an input voltage of CMP IN pin to CMPOUT pin. The result is "1" when
the input voltage to port CMP IN is higher than the voltage applied to
port CMPREF and "0" when the voltage is lower.
Because the analog comparator consists of an analog MOS circuit,
set the input voltage to the CMPIN pin and the CMPREF pin within the
following range :
■Note
The analog comparator circuit is separated from the MCU internal
peripheral circuit in the microcomputer. Accordingly, even if the microcomputer runs away, the analog comparator is still in operation.
For this reason, the analog comparator can be used for safety circuit
design.
VSS +1.2 V to CMPVCC–0.5V
CMPVCC
P63/CMPIN /AN8
+
–
P64/CMPREF /AN9
CMPOUT
AVSS
Fig. 49. Block diagram of Analog comparator
3807 GROUP USER’S MANUAL
1-49
HARDWARE
FUNCTIONAL DESCRIPTION
Watchdog Timer
(2) Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 0017 16) permits
selecting a watchdog timer H count source. When this bit is set to
"0", the count source becomes the underflow signal of watchdog timer
L. The detection time is set then to f(XIN )=131.072 ms at 8 MHz
frequency and f(X CIN)=32.768 s at 32 kHz frequency.
When this bit is set to "1", the count source becomes the signal
divided by 16 for f(XIN) (or f(XCIN)). The detection time in this case is
set to f(XIN)=512 µs at 8 MHz frequency and f(XCIN)=128 ms at 32
KHz frequency. This bit is cleared to "0" after resetting.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because
of a software run-away). The watchdog timer consists of an 8-bit
watchdog timer L and a 8-bit watchdog timer H.
●Standard operation of watchdog timer
When any data is not written into the watchdog timer control register
(address 001716) after resetting, the watchdog timer is in the stop
state. The watchdog timer starts to count down by writing an optional
value into the watchdog timer control register (address 001716) and
an internal resetting takes place at an underflow of the watchdog
timer H.
Accordingly, programming is usually performed so that writing to the
watchdog timer control register (address 001716) may be started
before an underflow. When the watchdog timer control register
(address 001716 ) is read, the values of the 6 high-order bits of the
watchdog timer H, STP instruction disable bit, and watchdog timer H
count source selection bit are read.
(3) Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 0017 16) permits
disabling the STP instruction when the watchdog timer is in operation.
When this bit is "0", the STP instruction is enabled.
When this bit is "1", the STP instruction is disabled.
Once the STP instruction is executed, an internal resetting takes place.
When this bit is set to "1", it cannot be rewritten to "0" by program.
This bit is cleared to "0" after resetting.
(1) Initial value of watchdog timer
At reset or writing to the watchdog timer control register (address
001716 ), each watchdog timer H and L is set to "FF16 ."
“FF16” is set when
watchdog timer
control register is
written to.
XCIN
XIN
“FF16” is set when
watchdog timer
control register is
written to.
"0"
"10"
Main clock division
ratio selection bits
(Note)
Data bus
Watchdog timer L (8)
1/16
"1"
"00"
"01"
Watchdog timer H (8)
Watchdog timer H count
source selection bit
STP instruction disable bit
STP instruction
Reset
circuit
RESET
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of CPU mode register.
Fig. 50. Block diagram of Watchdog timer
b0
b7
Watchdog timer control register
(WDTCON : address 001716)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/16 or f(XCIN)/16
Fig. 51. Structure of Watchdog timer control register
1-50
3807 GROUP USER’S MANUAL
Internal reset
HARDWARE
FUNCTIONAL DESCRIPTION
Clock output function
The internal clock φ can be output from I/O port P34. Control of I/O
ports and clock output function can be performed by port P2P3
control register (address 001516).
b7
b0
Port P2P3 control register
(P2P3C : address 001516)
(1) I/O ports or clock output function selection
The P3 4 clock output control bit (b0) of port P2P3 control register
selects the I/O port or clock output function. When clock output
function is selected, the clock is output regardless of the port P3 4
direction register settings.
Directly after bit 0 is written to, the port or clock output is switched
synchronous to a falling edge of clock frequency selected by the
output clock frequency selection bit. When memory expansion mode
or microprocessor mode is selected in CPU mode register (b1, b0),
clock output is selected on regardless of P34 clock output control bit
settings or port P34 direction register settings.
P34 clock output control bit
0: I/O port
1: Clock output
Output clock frequency selection bits
000: φ
001: f(XCIN)
010: "L" fixed for output
011: "L" fixed for output
100: f(XIN)
(f(XCIN) in low-speed mode)
101: f(XIN)/2 (f(XCIN)/2 in low-speed mode)
110: f(XIN)/4 (f(XCIN)/4 in low-speed mode)
111: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
Not used (return "0" when read)
P2•P32 input level selection bit
0: CMOS level input
1: TTL level input
(2) Selection of output clock frequency
The output clock frequency selection bits (b3, b2, b1) of port P2P3
control register select the output clock frequency.
The output waveform when f(X IN) or f(XCIN) is selected, depends on
X IN or X CIN input waveform however; all other output waveform
settings have a duty cycle of 50%.
Fig. 52. Structure of Port P2P3 control register
P34 direction register
P34 clock output control bit
Microprocessor mode/memory expansion mode
P34 port latch
Output clock frequency
selection bits
"000"
"001"
XCIN
Main clock division ratio
selection bits (Note)
P34/CKOUT/ø
Low-speed mode
"100"
High-speed or
middle-speed
mode
1/2
1/4
1/16
XIN
"101"
"110"
"111"
"010"
"011"
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of CPU mode register.
Fig. 53. Block diagram of Clock output function
3807 GROUP USER’S MANUAL
1-51
HARDWARE
FUNCTIONAL DESCRIPTION
Reset Circuit
______
Poweron
To reset the microcomputer, RESET
pin should be held at an "L"
______
level for 2 µs or more. Then the RESET pin is returned to an "H" level
(the power source voltage should be between 2.7 V and 5.5 V, and
the oscillation should be stable), reset is released. After the reset is
completed, the program starts from the address contained in address
FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make
sure that the reset input voltage is less than 0.54 V for VCC of 2.7 V.
RESET
Power source
voltage
0V
VCC
Reset input
voltage
0V
(Note)
0.2VCC
Note : Reset release voltage ; Vcc=2.7 V
RESET
VCC
Power source
voltage detection
circuit
Fig. 54. Reset circuit example
XIN
φ
RESET
Internal
reset
?
?
Address
?
?
FFFC
FFFD
ADH,L
Reset address from the vector table.
?
Data
?
?
?
ADL
ADH
SYNC
XIN: 10.5 to 18.5 clock cycles
Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN)=8 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 55. Reset sequence
1-52
3807 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
Address Register contents
Address Register contents
(1) Port P0
000016
0016
(34) Timer 3
002616
FF16
(2) Port P0 direction register
000116
0016
(35) Timer X mode register
002716
0016
(3) Port P1
000216
0016
(36) Timer Y mode register
002816
0016
(4) Port P1 direction register
000316
0016
(37) Timer 123 mode register
002916
0016
(5) Port P2
000416
0016
(38) Real time port register 0—7
002A16
0016
(6) Port P2 direction register
000516
0016
(39) Real time port control register 0
002B16 1 0 0 1 0 0 0 0
(7) Port P3
000616
0016
(40) Real time port control register 1
002C16 1
(8) Port P3 direction register
000716
0016
R/W pointer
1 1 1
(9) Port P4
000816
0016
Output pointer
1 1 1
(10) Port P4 direction register
000916
0016
(41) Real time port control register 2
(11) Port P5
000A16
0016
R/W pointer
1 1 1
(12) Port P5 direction register
000B16
0016
Output pointer
1 1 1
(13) Port P6
000C16
0016
(42) Real time port control register 3
002E16
0016
(14) Port P6 direction register
000D16
0016
(43) Timer A (low-order)
002F16
FF16
(15) Port P7
000E16
0016
(44) Timer A (high-order)
003016
FF16
(16) Port P7 direction register
000F16
0016
(45) Timer B (low-order)
003116
FF16
(17) Port P8
001016
0016
(46) Timer B (high-order)
003216
FF16
(18) Port P8 direction register
001116
0016
(47) D-A control register
003316
0016
(19) Timer XY control register
001416 0 0 0 0 0 0 1 1
(48) A-D control register
003416 0 0 0 1 0 0 0 0
(20) Port P2P3 control register
001516 * 0 0 0 0 0 0 0
(49) D-A1 conversion register
003616
0016
(21) Pull-up control register
001616
(50) D-A2 conversion register
003716
0016
(22) Watchdog timer control register
001716 0 0 1 1 1 1 1 1
(51) D-A3 conversion register
003816
0016
(23) Serial I/O1 status register
001916 1 0 0 0 0 0 0 0
(52) D-A4 conversion register
003916
0016
(24) Serial I/O1 control register
001A16
(53) Interrupt edge selection register
003A16
0016
(25) UART control register
001B16 1 1 1 0 0 0 0 0
(54) CPU mode register
003B16 0 1 0 0 1 0 * 0
(26) Serial I/O2 control register 1
001D16
(55) Interrupt request register 1
003C16
0016
(27) Serial I/O2 control register 2
001E16 0 0 0 0 0 1 1 1
(56) Interrupt request register 2
003D16
0016
(28) Timer X (low-order)
002016
FF16
(57) Interrupt control register 1
003E16
0016
(29) Timer X (high-order)
002116
FF16
(58) Interrupt control register 2
003F16
0016
(30) Timer Y (low-order)
002216
FF16
(59) Processor status register
(31) Timer Y (high-order)
002316
FF16
(60) Program counter
(32) Timer 1
002416
FF16
(33) Timer 2
002516
0116
0016
0016
0016
0 0 0 0
002D16 1
(PS) 
0 0 0 0




1 
(PCH)
FFFD16 contents
(PCL)
FFFC16 contents

* The initial values depend on level of port CNVSS.
X: Not fixed
Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.
Fig. 56. Internal status at reset
3807 GROUP USER’S MANUAL
1-53
HARDWARE
FUNCTIONAL DESCRIPTION
Clock Generating Circuit
The 3807 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance with
the resonator manufacturer's recommended values. No
external resistor is needed between XIN and XOUT since a feed-back
resistor exists on-chip. However, an external feed-back resistor is
needed between XCIN and XCOUT.
Immediately after poweron, only the XIN oscillation circuit starts
oscillating, and XCIN and X COUT pins function as I/O ports.
●Frequency control
(1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8. After reset,
this mode is selected.
plied to the CPU (remains at "H") until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize. The internal clock
φ is supplied for the first time, when timer 2 underflows. Therefore
make sure not to set the timer 2/INT 3 interrupt request bit to "1" before the STP instruction stops the oscillator.
When the
______
oscillator is restarted by reset apply "L" level to port RESET until the
oscillation is stable since a wait time will not be generated.
(2) Wait mode
If the WIT instruction is executed, the internal clock φ stops at an "H"
level. The states of XIN and XCIN are the same as the state before
executing the WIT instruction. The internal clock restarts at reset or
when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted.
(2) High-speed mode
The internal clock φ is half the frequency of XIN.
(3) Low-speed mode
The internal clock φ is half the frequency of XCIN.
XCIN
■Note
If you switch the mode between middle/high-speed and low-speed,
stabilize both XIN and XCIN oscillations. The sufficient time is required
for the sub clock to stabilize, especially immediately after poweron
and at returning from stop mode. When switching the mode between
middle/high-speed and low-speed, set the frequency on condition
that f(XIN) > 3f(XCIN).
(4) Low power consumption mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set bit
5 of the CPU mode register to "1." When the main clock XIN is restarted (by setting the main clock stop bit to "0"), set enough time for
oscillation to stabilize.
By clearing furthermore the XCOUT drivability selection bit (b3) of CPU
mode register to "0", low power consumption operation of less than
55 µA (V CC=3 V, XCIN =32 kHz) can be realized by reducing the
drivability between XCIN and XCOUT . At reset or during STP instruction execution this bit is set to "1" and a reduced drivability that has
an easy oscillation start is set. The sub-clock XCIN-XCOUT oscillating
circuit can not directly input clocks that are generated externally. Accordingly, make sure to cause an external resonator to oscillate.
Rf
CCIN
1-54
XIN
XOUT
Rd
CCOUT
CIN
COUT
Fig. 57. Ceramic resonator circuit
XCIN
XCOUT
Rf
CCIN
●Oscillation control
(1) Stop mode
If the STP instruction is executed, the internal clock φ stops at an "H"
level, and XIN and XCIN oscillators stop. Timer 1 is set to "FF16" and
timer 2 is set to "0116."
Either XIN or X CIN divided by 16 is input to timer 1 as count source,
and the output of timer 1 is connected to timer 2. The bits of the timer
123 mode register except timer 3 count source selection bit (b4) are
cleared to "0". Set the timer 2/INT3 interrupt source bit to "1" and
timer 1/INT2 as well as timer 2/INT3 interrupt enable bit to disabled
("0") before executing the STP instruction. Oscillator restarts when
an external interrupt is received, but the internal clock φ is not sup-
XCOUT
XIN
Rd
open
External oscillation circuit
CCOUT
VCC
VSS
Fig. 58. External clock input circuit
3807 GROUP USER’S MANUAL
XOUT
HARDWARE
FUNCTIONAL DESCRIPTION
XCOUT
XCIN
"0"
"1"
Port XC
switch bit
Timer 1 count source
selection bits
XOUT
XIN
Main clock division ratio
selection bits (note)
"10"
"01"
Timer 1
Low-speed mode
1/2
Timer 2 count source
selection bit
1/4
1/2
"0"
Timer 2
"00"
High-speed or
middle-speed
mode
"1"
Main clock division ratio
selection bits (note)
Middle-speed mode
Timing φ (internal clock)
High-speed or
low-speed mode
Main clock stop bit
Q
S
R
S Q
STP instruction
WIT instruction
R
Q S
R
STP instruction
Reset
Interrupt disable flag l
Interrupt request
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of CPU mode register.
When low-speed mode is selected, set port Xc switch bit (b4) to “1”.
Fig. 59. System clock generating circuit block diagram (Single-chip mode)
3807 GROUP USER’S MANUAL
1-55
HARDWARE
FUNCTIONAL DESCRIPTION
Reset
Middle-speed mode
(f(φ)=1MHz)
CM7=0
CM6=1
CM5=0(8MHz oscillating)
CM4=1(32kHz oscillating)
"
"0
"0"
"0
"
CM4
"1"
CM4
"1"
4
"0"
C
"0 M 4
"
C
"1 M 6
"1
"
"
CM "
"1 M 6
C "
"1
High-speed mode
(f(φ)=4MHz)
CM7=0
CM6=0
CM5=0(8MHz oscillating)
CM4=0(32kHz stopped)
"0
"
CM6
"1"
"0"
CM
"0 7
"
CM
"1 6
"1
"
"
"0
"
High-speed mode
(f(φ)=4MHz)
CM7=0
CM6=0
CM5=0(8MHz oscillating)
CM4=1(32kHz oscillating)
"0"
"0"
CM6
"1"
CM7
"1"
Middle-speed mode
(f(φ)=1MHz)
CM7=0
CM6=1
CM5=0(8MHz oscillating)
CM4=0(32kHz stopped)
b7
CM5
"1"
"0"
Low-speed mode
(f(φ)=16kHz)
CM7=1
CM6=0
CM5=0(8MHz oscillating)
CM4=1(32kHz oscillating)
Low-speed mode
(f(φ)=16kHz)
CM7=1
CM6=0
CM5=1(8MHz stopped)
CM4=1(32kHz oscillating)
b4
CPU mode register
(CPUM : address 003B16)
CM4 : Port Xc switch bit
0 : I/O port function (stop oscillating)
1 : XCIN-XCOUT oscillating function
CM5 : Main clock (XIN- XOUT ) stop bit
0 : Operating
1 : Stopped
CM7 CM6: Main clock division ratio selection bit
b7 b6
0 0 : φ = f(XIN)/2 (High-speed mode)
0 1 : φ = f(XIN)/8 (Middle-speed mode)
1 0 : φ = f(XCIN)/2 (Low-speed mode)
1 1 : Not available
Note 1:Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2:The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait
mode is ended.
3:Timer operates in the wait mode.
4:When the stop mode is ended, a delay of approximately 1 ms occurs by Timer 1 and Timer 2 in middle/high-speen mode.
5:When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 and Timer 2 in low-speed mode.
6:Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/highspeed mode.
7:The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Fig. 60. State transitions of system clock
1-56
3807 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
AAAAA
AAAAA
Processor Mode
Single-chip mode, memory expansion mode, and microprocessor
mode can be selected by changing the contents of the processor
mode bits (CM 0 and CM1 : b1 and b0 of address 003B16 ). In memory
expansion mode and microprocessor mode, memory can be expanded externally through ports P0 to P3. In these modes, ports P0
to P3 lose their I/O port functions and become bus pins.
000816
Port P1
Port P2
Port P3
Outputs 8-bits high-order byte of address.
Operates as I/O pins for data D 7 to D0
(including instruction code)
P30 and P31 function only as output pins
(except that____
the port latch cannot be read).
P32 is the ONW input pin.
P33 is the RESTOUT output pin. (Note)
P34 is the φ output pin.
P35 is the ___
SYNC output pin.
___
P36 is the WR output pin, and P37 is the RD output
pin.
000816
SFR area
SFR area
004016
004016
internal RAM
reserved area
Table. 9. Port functions in memory expansion mode and microprocessor mode
Port Name
Function
Port P0
Outputs 8-bits low-order byte of address.
AAAAA
AAAAA
AAAAA
000016
000016
internal RAM
reserved area
AAAAA
AAAAA
AAAAA
AAAAA
*
YYYY16
internal ROM
FFFF16
FFFF16
Memory expansion mode
Note : If CNVSS is connected to VSS, the microcomputer goes to
single-chip mode after a reset, so this pin cannot be used as
the RESETOUT output pin.
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
084016
084016
Microprocessor mode
The shaded area are external memory area.
*: YYYY16 indicates the first address of internal ROM.
Fig. 61. Memory maps in various processor modes
(1) Single-chip mode
Select this mode by resetting the microcomputer with CNV SS
connected to VSS.
(2) Memory expansion mode
Select this mode by setting the processor mode bits (b1, b0) to "01"
in software with CNV SS connected to V SS. This mode enables
external memory expansion while maintaining the validity of the
internal ROM. However, some I/O devices will not support the memory
expansion mode. Internal ROM will take precedence over external
memory if addresses conflict.
b7
b0
CPU mode register
(CPUM : address 003B16)
Processor mode bits (CM1, CM0)
b1 b0
0
0
1
1
(3) Microprocessor mode
Select this mode by resetting the microcomputer with CNV SS connected to VCC, or by setting the processor mode bits to "10" in software with CNV SS connected to VSS . In microprocessor mode, the
internal ROM is no longer valid and external memory must be used.
0: Single-chip mode
1: Memory expansion mode
0: Microprocessor mode
1: Not available
Stack page selection bit
0: 0 page
1: 1 page
Fig. 62. Structure of CPU mode register
3807 GROUP USER’S MANUAL
1-57
HARDWARE
FUNCTIONAL DESCRIPTION
Bus control at memory expansion
_____
The 3807 group has a built-in ONW function to facilitate access to
external (expanded) memory and I/O devices in memory expansion
mode or microprocessor mode.
_____
If an "L" level signal is input to port P32/ONW when the CPU is in a
read or write state, the corresponding read or write cycle
is___
extended
___
by one cycle of φ . During this extended period, the RD or WR signal
remains at "L". This extension function is valid only for writing to and
reading from addresses 000016 to 000716 and 084016 to FFFF16, and
only read and write cycles are extended.
Read cycle
Dummy cycle Write cycle
Read cycle Dummy cycle
Write cycle
φ
AD15—AD0
RD
WR
ONW
*
*
*
* Period during which ONW input signal is received
During this period, the ONW signal must be fixed at either "H" or "L". At all other times, the input level of the ONW
signal has no affect on operations. The bus cycles is not extended for an address in the area 000816 to 083F16,
regardless of whether the ONW signal is received.
_____
Fig. 63. ONW function timing
1-58
3807 GROUP USER’S MANUAL
HARDWARE
NOTES ON PROGRAMMING
NOTES ON PROGRAMMING
Processor Status Register
A-D Converter
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is "1." After a
reset, initialize flags which affect program execution. In particular, it
is essential to initialize the index X mode (T) and the decimal mode
(D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change immediately
after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or
BBS instruction.
Decimal Calculations
•To calculate in decimal notation, set the decimal mode flag (D) to
"1", then execute an ADC or SBC instruction. Only the ADC and
SBC instructions yield proper decimal results. After executing an
ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction.
•In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
Multiplication and Division Instructions
The comparator uses internal capacitors whose charge will be lost if
the clock frequency is too low.
Therefore, make sure that
f(XIN) is at least on 500 kHz during an A-D
_____
conversion. (When the ONW pin has been set to "L", the A-D conversion will take twice as long to match the longer bus cycle, and so
f(X IN) must be at least 1 MHz.)
Do not execute the STP or WIT instruction during an A-D conversion.
D-A Converter
The accuracy of the D-A converter becomes rapidly poor under the
VCC = 4.0 V or less condition; a supply voltage of VCC ≥ 4.0 V is
recommended. When a D-A converter is not used, set all values of
D-Ai conversion registers (i=1 to 4) to "00 16."
Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency
of the internal clock φ by the number of cycles needed to execute an
instruction.
The number of cycles required to execute an instruction is shown in
the list of machine instructions.
The frequency of the internal clock φ is half of the X IN frequency in
high-speed_____
mode.
When the ONW function is used in modes other than single-chip
mode, the frequency of the internal clock φ may be one fourth of the
XIN frequency.
•The index X mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
•The execution of these instructions does not change the contents of
the processor status register.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
•The data transfer instruction (LDA, etc.)
•The operation instruction when the index X mode flag (T) is "1"
•The addressing mode which uses the value of a direction register
as an index
•The bit-test instruction (BBC or BBS, etc.) to a direction register
•The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a
direction register.
Use instructions such as LDM and STA, etc., to set the port direction
registers.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an
external clock and it is to output the SRDY1 signal, set the transmit
enable bit, the receive enable bit, and the SRDY1 output enable bit to
"1."
Serial I/O1 continues to output the final bit from the TXD pin after
transmission is completed. SOUT2 pin for serial I/O2 goes to high impedance after transfer is completed.
When in serial I/O1 (clock-synchronous mode) or in serial I/O2 an
external clock is used as synchronous clock, write transmission data
to both the transmit buffer register and serial I/O2 register, during
transfer clock is “H.”
3807 GROUP USER’S MANUAL
1-59
HARDWARE
NOTES ON USAGE
NOTES ON USAGE
Handling of Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suitable
for high frequencies as bypass capacitor between power source pin
(VCC pin) and GND pin (Vss pin) and between power source pin (VCC
pin) and analog power source input pin (AVSS pin). Besides, connect
the capacitor to as close as possible. For bypass capacitor which
should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 µF—0.1 µF is recommended.
P34 clock output function
In the case of using an I/O port P34 as a clock output function, note
the following : when an output clock frequency is changed during
outputting a clock, the port may feed a noise having a shorter pulse
width than the standard at the switch timing. Besides, it also may
happen at the timing for switching the low-speed mode to the middle/
high-speed mode.
Timer X and timer Y
In the pulse period measurement mode or the pulse width measurement mode for timers X and Y, set the "L" or "H" pulse width of input
signal from CNTR0/CNTR 1 pin to 2 cycles or more of a timer count
source.
EPROM version/One Time PROM version
The CNVSS pin is connected to the internal memory circuit block by a
low-ohmic resistance, since it has the multiplexed function to be a
programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVSS pin
and VSS pin or VCC pin with 1 to 10 kΩ resistance.
The mask ROM version track of port CNVSS has no operational interference even if it is connected via a resistor.
1-60
3807 GROUP USER’S MANUAL
HARDWARE
DATA REQUIRED FOR MASK ORDERS/ROM PROGRAMMING METHOD
DATA REQUIRED FOR MASK ORDERS
ROM PROGRAMMING METHOD
The following are necessary when ordering a mask ROM production:
(1) Mask ROM Order Confirmation Form
(2) Mark Specification Form
(3) Data to be written to ROM, in EPROM form (three identical copies)
The built-in PROM of the blank One Time PROM version and built-in
EPROM version can be read or programmed with a general purpose
PROM programmer using a special programming adapter. Set the
address of PROM programmer in the user ROM area.
Table. 10. Special programming adapter
Package
80P6N-A
80D0
Name of Programming Adapter
PCA4738F-80A
PCA4738L-80A
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in
Figure 64 is recommended to verify programming.
Programming with PROM
programmer
Screening (Caution)
(150°C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
Caution : The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Fig. 64. Programming and testing of One Time PROM version
3807 GROUP USER’S MANUAL
1-61
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
FUNCTIONAL DESCRIPTION SUPPLEMENT
Interrupt
3807 group permits interrupts on the basis of 16
sources. It is vector interrupts with a fixed priority
system. Accordingly, when two or more interrupt
requests occur during the same sampling, the higherpriority interrupt is accepted first. This priority is
determined by hardware, but variety of priority
processing can be performed by software, using an
interrupt enable bit and an interrupt disable flag.
For interrupt sources, vector addresses and interrupt priority, refer to “Table 11.”
Table 11. Interrupt sources, vector addresses and interrupt priority
Vector addresses
Priority
Interrupt sources
Remarks
High-order Low-order
1
2
Reset (Note)
INT0 interrupt
FFFD16
FFFB16
FFFC 16
FFFA16
3
INT1 interrupt
FFF9 16
FFF8 16
4
5
6
7
8
Serial I/O1 receive interrupt
Serial I/O1 transmit interrupt
Timer X interrupt
Timer Y interrupt
INT3 interrupt
FFF7 16
FFF5 16
FFF3 16
FFF1 16
FFEF16
FFF6 16
FFF4 16
FFF2 16
FFF0 16
FFEE 16
9
Timer 2 interrupt
INT4 interrupt
FFED16
FFEC16
10
Timer 3 interrupt
CNTR 0 interrupt
FFEB16
FFEA 16
11
CNTR 1 interrupt
FFE916
FFE816
12
13
Serial I/O2 interrupt
INT2 interrupt
FFE716
FFE516
FFE616
FFE416
14
15
16
Timer 1 interrupt
Timer A interrupt
Timer B interrupt
A-D conversion interrupt
ADT interrupt
FFE316
FFE116
FFDF16
FFE216
FFE016
FFDE16
17
BRK instruction interrupt
FFDD 16
FFDC 16
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
External interrupt(active edge selectable)
Valid when INT3 interrupt is selected
Valid when timer 2 interrupt is selected
External interrupt(active edge selectable)
Valid when INT4 interrupt is selected
Valid when timer 3 interrupt is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O2 is selected
External interrupt(active edge selectable)
Valid when INT2 interrupt is selected
Valid when timer 1 interrupt is selected
Valid when A-D interrupt is selected
External interrupt(only at falling edge)
Valid when ADT interrupt and A-D external
trigger valid are selected
Non-maskable software interrupt
Note: Reset functions in the same way as an interrupt with the highest priority.
1-62
3807 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Timing After Interrupt
Figure 65 shows a timing chart after an interrupt
occurs, and Figure 66 shows the time up to execution of the interrupt processing routine.
The interrupt processing routine begins with the
machine cycle following the completion of the instruction that is currently in execution.
SYNC
RD
WR
Address bus
PC
Not used
Data bus
SYNC
BL, BH
AL, AH
SPS
S, SPS
S-1, SPS S-2, SPS
PCH PCL
BL
PS
BH
AL
AL, AH
AH
: CPU operation code fetch cycle
: Vector address of each interrupt
: Jump destination address of each interrupt
: “0016” or “0116”
Fig. 65 Timing chart after an interrupt occurs
Start of interrupt processing
Generation of interrupt request
Main routine
0 to 16 ✻ cycles
Waiting time for
post-processing
of pipeline
Stack push and
Vector fetch
2 cycles
Interrupt processing routine
5 cycles
7 to 23 cycles
(At performing 8.0 MHz, 1.75 µ s to 5.75 µ s)
✻ : at execution of DIV instruction (16 cycles)
Fig. 66 Time up to execution of the interrupt processing routine
3807 GROUP USER’S MANUAL
1-63
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
A-D Converter
By repeating the above operations up to the lowestorder bit of the A-D conversion register, an analog
value converts into a digital value.
A-D conversion completes at 50 clock cycles (12.5
µ s at f(X IN) = 8.0 MHz) after it is started, and the
result of the conversion is stored into the A-D conversion register.
Concurrently with the completion of A-D conversion,
A-D conversion interrupt request occurs, so that the
AD conversion interrupt request bit is set to “1.”
A-D conversion is started by setting AD conversion
completion bit to “0.” During A-D conversion, internal operations are performed as follows.
1. After the start of A-D conversion, A-D conversion
register goes to “00 16.”
2. The highest-order bit of A-D conversion register
is set to “1,” and the comparison voltage Vref is
input to the comparator. Then, Vref is compared
with analog input voltage V IN.
3. As a result of comparison, when Vref < V IN, the
highest-order bit of A-D conversion register be
comes “1.” When Vref > V IN, the highest-order
bit becomes “0.”
Relative formula for a reference voltage V REF of A-D converter and Vref
When n = 0
Vref = 0
Vref = VREF ✕ (n – 0.5)
256
n : the value of A-D converter (decimal numeral)
When n = 1 to 255
Table 12. Change of A-D conversion register during A-D conversion
Change of A-D conversion register
At start of conversion
0
0
0
0
0
0
0
0
First comparison
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
Second comparison
Third comparison
After completion of eighth
comparison
✽1:
✽3:
✽5:
✽7:
1-64
A
A
A
A
result
result
result
result
of
of
of
of
the
the
the
the
✽
✽
1
1
✽
2
Value of comparison voltage (Vref)
0
V REF
2
VREF
2
VREF
2
–
V REF
512
±
V REF
±
V REF
4
4
A result of A-D conversion
✽
1
✽
2
✽
first comparison
third comparison
fifth comparison
seventh comparison
3
✽
4
✽
✽2:
✽4:
✽6:
✽8:
5
A
A
A
A
✽
6
✽
result
result
result
result
7
✽
of
of
of
of
8
the
the
the
the
second comparison
fourth comparison
sixth comparison
eighth comparison
3807 GROUP USER’S MANUAL
–
V REF
512
V REF
±
8
–
V REF
512
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Figures 67 shows A-D conversion equivalent circuit, and Figure 68 shows A-D conversion timing
chart.
VCC
VSS
VCC AVSS
VIN
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
Sampling
clock
C
Chopper amplifier
A-D conversion register
b5
b3 b2 b1 b0
ADT/A-D conversion interrupt
request
A-D control register
Vref
ADVREF
Build-in
D-A converter
Reference
clock
AVSS
Fig. 67 A-D conversion equivalent circuit
Write signal for A-D control register
50 cycles
AD conversion completion
bit
Sampling clock
Fig. 68 A-D conversion timing chart
3807 GROUP USER’S MANUAL
1-65
CHAPTER 2
APPLICATION
2.1
2.2
2.3
2.4
2.5
2.6
2.7
I/O port
Timer
Serial I/O
Real time output port
A-D converter
Reset
Application circuit example
APPLICATION
2.1 I/O port
2.1 I/O port
2.1.1 Memory map of I/O port
000016
Port P0 (P0)
000116
Port P0 direction register (P0D)
000216
Port P1 (P1)
000316
Port P1 direction register (P1D)
000416
Port P2 (P2)
000516
Port P2 direction register (P2D)
000616
Port P3 (P3)
000716
Port P3 direction register (P3D)
000816
Port P4 (P4)
000916
Port P4 direction register (P4D)
000A16
Port P5 (P5)
000B16
Port P5 direction register (P5D)
000C16
Port P6 (P6)
000D16
Port P6 direction register (P6D)
000E16
Port P7 (P7)
000F16
Port P7 direction register (P7D)
001016
Port P8 (P8)
001116
Port P8 direction register (P8D)
Fig. 2.1.1 Memory map of I/O port related registers
2-2
3807 GROUP USER’S MANUAL
APPLICATION
2.1 I/O port
2.1.2 Related registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 7, 8)
[Address : 0016, 0216, 0416, 0616, 0816, 0A16, 0E16, 1016]
B
Name
Function
0 Port Pi0
●
In output mode
Write
Port latch
Read
●
In input mode
Write : Port latch
Read : Value of pins
1 Port Pi1
2 Port Pi2
At reset
R W
0
0
0
3 Port Pi3
0
4 Port Pi4
0
5 Port Pi5
0
6 Port Pi6
0
7 Port Pi7
0
Fig. 2.1.2 Structure of Port Pi (i = 0, 1, 2, 3, 4, 5, 7, 8)
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4, 5, 7, 8)
[Address : 0116, 0316, 0516, 0716, 0916, 0B16, 0F16, 1116]
B
Function
Name
At reset
R W
0 Port Pi direction register
0 : Port Pi0 input mode
1 : Port Pi0 output mode
0
✕
1
0 : Port Pi1 input mode
1 : Port Pi1 output mode
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0 : Port Pi3 input mode
1 : Port Pi3 output mode
0 : Port Pi4 input mode
1 : Port Pi4 output mode
0
✕
0
✕
0
✕
0
✕
0 : Port Pi5 input mode
1 : Port Pi5 output mode
0 : Port Pi6 input mode
1 : Port Pi6 output mode
0 : Port Pi7 input mode
1 : Port Pi7 output mode
0
✕
0
✕
0
✕
2
3
4
5
6
7
Fig. 2.1.3 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4, 5, 7, 8)
3807 GROUP USER’S MANUAL
2-3
APPLICATION
2.1 I/O port
Port P6
b7 b6 b5 b4 b3 b2 b1 b0
Port P6 (P6) [Address : 0C16]
Name
B
Function
0 Port P60
●
In output mode
Write
Port latch
Read
●
In input mode
Write : Port latch
Read : Value of pins
1 Port P61
2 Port P62
3 Port P63
4 Port P64
At reset
R W
0
0
0
(Note)
0
✕
(Note)
0
✕
5 Port P65
0
6 Nothing is allocated for these bits. These are write disabled bits.
7 When these bits are read out, the values are “0”.
0
0
✕
✕
Note : These bits are used only for input port.
Fig. 2.1.4 Structure of Port P6
Port P6 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P6 direction register (P6D) [Address : 0D16]
Function
Name
B
0 Port P60—P62 direction
registers
1
2
R W
0
✕
0 : Port P61 input mode
1 : Port P61 output mode
0 : Port P62 input mode
1 : Port P62 output mode
0
✕
0
✕
3 Ports P63 and P64 are input ports.
0
✕
Accordingly, these bits do not have a direction register.
4 Nothing is allocated for these bits.
0
✕
0 : Port P65 input mode
1 : Port P65 output mode
6 Nothing is allocated for these bits. These are write disabled bits.
7 When these bits are read out, the values are “0”.
5 Port P65 direction register
Fig. 2.1.5 Structure of Port P6 direction register
2-4
At reset
0 : Port P60 input mode
1 : Port P60 output mode
3807 GROUP USER’S MANUAL
0
0
0
✕
✕
✕
APPLICATION
2.1 I/O port
2.1.3 Handling of unused pins
Table 2.1.1 Handling of unused pins (in single-chip mode)
Name of Pins/Ports
P0, P1, P2, P3, P4, P5, P6, P7, P8
ADV REF
AV SS
CMPVCC
CMPOUT
X OUT
Handling
• Set to the input mode and connect to V CC or V SS through a
resistor of 1 k
to 10 k .
• Set to the output mode and open at “L” or “H.”
Connect to V SS (GND) or open.
Connect to V SS(GND).
Connect to V SS(GND).
Open
Open (only when using external clock).
Table 2.1.2 Handling of unused pins (in memory expansion mode and microprocessor mode)
Name of Pins/Ports
P3 0, P3 1
P4, P5, P6, P7, P8
ADV REF
____
ONW
_________
RESET OUT
SYNC
AV SS
CMPVCC
CMPOUT
X OUT
Handling
Open
• Set to the input mode and connect to V CC or V SS through a
resistor of 1 k
to 10 k .
• Set to the output mode and open at “L” or “H.”
Connect to V SS (GND) or open.
Connect to V CC through a resistor of 1 k to 10 k .
Open
Open
Open
Connect to V SS(GND).
Connect to V SS(GND).
Open
Open (only when using external clock).
3807 GROUP USER’S MANUAL
2-5
APPLICATION
2.2 Timer
2.2 Timer
2.2.1 Memory map of timer
001416
Timer XY control register (TXYCON)
002016
Timer X Low-order (TXL)
002116
Timer X High-order (TXH)
002216
Timer Y Low-order (TYL)
002316
Timer Y High-order (TYH)
002416
Timer 1 (T1)
002516
Timer 2 (T2)
002616
Timer 3 (T3)
002716
Timer X mode register (TXM)
002816
Timer Y mode register (TYM)
002916
Timer 123 mode register (T123M)
003A16
Interrupt edge selection register (INTEDGE)
003C16
Interrupt request register 1 (IREQ1)
003D16
Interrupt request register 2 (IREQ2)
003E16
Interrupt control register 1 (ICON1)
003F16
Interrupt control register 2 (ICON2)
Fig. 2.2.1 Memory map of timer related registers
2-6
3807 GROUP USER’S MANUAL
APPLICATION
2.2 Timer
2.2.2 Related registers
Timer XY control register
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAA
AA
AA
A
AAAAAAA
AAAAAAA
AAAAAAAAAAAAAA
AA
AA
A
AAAAAAAAAAAAAA
AA
AA
A
AAAAAAAAAAAAAA
AA
AA
A
AAAAAAAAAAAAAA
AA
AA
A
Timer XY control register (TXYCON) [Address : 1416]
B
0
Name
Timer X stop control bit
Function
0 : Start counting
1 : Stop counting
Timer Y stop control bit
0 : Start counting
1 : Stop counting
2 Nothing is allocated for these bits. These are write disabled bits.
3 When these bits are read out, the values are “0.”
1
4
5
6
7
At reset
R W
1
1
0
0
0
0
0
0
✕
✕
✕
✕
✕
✕
Fig. 2.2.2 Structure of Timer XY control register
Timer X Low-order, Timer X High-order, Timer Y Low-order, Timer Y High-order
b7 b6 b5 b4 b3 b2 b1 b0
Timer X Low-order (TXL), Timer X High-order (TXH) [Address : 2016 , 2116]
Timer Y Low-order (TYL), Timer Y High-order (TYH) [Address : 2216 , 2316]
AAAAAAAAAAAAAA
AA
AA
A
AAAAAAAAAAAAAA
AAAAAAAAAAAAA
AA
AA
A
AAAAAAAAAAAAAA
AA
AA
A
AAAAAAAAAAAAAA
AA
AA
A
A
AA
AA
A
AAAAAAAAAAAAAA
AAAAAAAAAAAAA
AA
AA
A
A
AA
AA
A
AAAAAAAAAAAAAA
AAAAAAAAAAAAA
AA
AA
A
A
AA
AA
A
B
0
Function
●
●
1
2
●
3
4
A count value of each timer is set.
At writing
● A value set in this register is written to both a Timer and a
corresponding Timer latch at the same time, or to only a
Timer latch.
● A value is written to low-order first.
At reading
● When this register is read out, a value (count value) of a
corresponding Timer is read out.
●
A measurement value is read out in pulse period measurement mode and pulse width measurement mode.
●
A value is read out from high-order first.
At reset
R W
1
1
1
1
1
5
1
6
1
7
1
Fig. 2.2.3 Structure of Timer X Low-order, Timer X High-order, Timer Y Low-order, Timer Y High-order
3807 GROUP USER’S MANUAL
2-7
APPLICATION
2.2 Timer
Timer 1, Timer 3
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAA
A
AA
AA
A
AAAAAAAAAAAAA
A
AA
AA
A
AAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AA
AA
A
AA
AA
A
AAAAAAAAAAAAAA
AA
AA
A
Timer 1 (T1), Timer 3 (T3) [Address : 2416, 2616]
B
0
1
2
3
4
5
6
7
Function
●
●
●
A count value of each Timer is set.
A value set in this register is written to both each Timer
and a corresponding Timer latch at the same time.
When this register is read out, a value (count value) of a
corresponding Timer is read out.
At reset
R W
1
1
1
1
1
1
1
1
Fig. 2.2.4 Structure of Timer 1, Timer 3
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAA
A
AA
AA
A
AAAAAAAAAAAAA
A
AA
AA
A
AAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AA
AA
A
AA
AA
A
AAAAAAAAAAAAAA
AA
AA
A
Timer 2 (T2) [Address : 2516]
B
0
1
2
3
4
5
6
7
Function
●
●
●
A count value of Timer 2 is set.
A value set in this register is written to both Timer 2 and a
corresponding Timer 2 latch at the same time, or to only
Timer 2 latch.
When this register is read out, a value (count value) of a
corresponding Timer 2 is read out.
Fig. 2.2.5 Structure of Timer 2
2-8
3807 GROUP USER’S MANUAL
At reset
1
0
0
0
0
0
0
0
R W
APPLICATION
2.2 Timer
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAA
AA
AA
A
AAAAAAA
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AA
AA
A
AAAAAAA
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
Timer X mode register (TXM) [Address : 2716]
B
Name
Timer X operating mode bits
0
1
2
3
4
5
Timer X write control bit
Output level latch
CNTR0 active edge switch bit
Function
At reset
R W
b2 b1 b0
0
0
0
0
1
0 : Timer • Event counter mode
1 : Pulse output mode
0 : Pulse period measurement mode
1 : Pulse width measurement mode
0 : Programmable waveform
generation mode
1 0 1 : Programmable one-shot
generation mode
1 1 0 : PWM mode
1 1 1 : Not available
0 : To a latch and a timer at the same time
1 : To only latch
0 : “L” output
1 : “H” output
It depends on the operating mode
of the Timer X (refer to Table 2.2.1).
b7
Timer X count source selection 0
0
1
7
1
6 bits
0
0
1
1
0
b6
0:
1:
0:
1:
f(XIN)/2
f(XIN)/16
f(XCIN)
Input signal from CNTR0 pin
0
0
0
0
0
0
0
0
Fig. 2.2.6 Structure of Timer X mode register
Timer Y mode register
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAA
AAAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
A
AAAAAAA
AAAAAAA
AA
AA
A
Timer Y mode register (TYM) [Address : 2816]
B
Name
Timer Y operating mode bits
0
1
2
3
4
5
Timer Y write control bit
Output level latch
CNTR1 active edge switch bit
Function
0
0
0
0
1
0 : Timer • Event counter mode
1 : Pulse output mode
0 : Pulse period measurement mode
1 : Pulse width measurement mode
0 : Programmable waveform
generation mode
1 0 1 : Programmable one-shot
generation mode
1 1 0 : PWM mode
1 1 1 : Not available
0
0
1
1
0
0 : To a latch and a timer at the same time
1 : To only latch
0 : “L” output
1 : “H” output
It depends on the operating mode
of the Timer Y (refer to Table 2.2.1).
b7
Timer Y count source selection 0
0
1
7
1
6 bits
At reset
R W
b2 b1 b0
b6
0:
1:
0:
1:
f(XIN)/2
f(XIN)/16
f(XCIN)
Input signal from CNTR1 pin
0
0
0
0
0
0
0
0
Fig. 2.2.7 Structure of Timer Y mode register
3807 GROUP USER’S MANUAL
2-9
APPLICATION
2.2 Timer
Table. 2.2.1 Function of CNTR 0/CNTR 1 active edge switch bit
Operating mode of
Timer X/Timer Y
Timer mode
“0”
“1”
Event counter mode
“0”
“1”
Pulse output mode
“0”
“1”
Pulse period measurement mode
•
•
•
•
•
•
•
•
•
•
•
“0”
•
•
“1”
Pulse width measurement mode
“0”
“1”
Programmable one-shot generation
mode
•
•
•
•
•
•
“0”
•
•
“1”
•
2-10
Function of CNTR 0/CNTR 1 edge switch bit
(bit 5 of each address 27 16 and 28 16 )
Generation of CNTR0 /CNTR1 interrupt request : Falling edge
(No effect on timer count)
Generation of CNTR 0/CNTR 1 interrupt request : Rising edge
(No effect on timer count)
Timer X/Timer Y : Count at rising edge
Generation of CNTR0 /CNTR1 interrupt request : Falling edge
Timer X/Timer Y : Count at falling edge
Generation of CNTR0/CNTR 1 interrupt request : Rising edge
Start of pulse output : From “H” level
Generation of CNTR0 /CNTR1 interrupt request : Falling edge
Start of pulse output : From “L” level
Generation of CNTR 0/CNTR 1 interrupt request : Rising edge
Timer X/Timer Y : Measurement of a period between a falling
edge and the next falling edge
Generation of CNTR0 /CNTR1 interrupt request : Falling edge
Timer X/Timer Y : Measurement of a period between a rising
edge and the next rising edge
Generation of CNTR 0/CNTR 1 interrupt request : Rising edge
Timer X/Timer Y : Measurement of “H” level width
Generation of CNTR0 /CNTR1 interrupt request : Falling edge
Timer X/Timer Y : Measurement of “L” level width
Generation of CNTR 0/CNTR 1 interrupt request : Rising edge
Timer X/Timer Y : Start of a pulse output at “L” level, and
output of an one-shot “H” level pulse
Generation of CNTR0 /CNTR1 interrupt request : Falling edge
Timer X/Timer Y : Start of a pulse output at “H” level, and
output of an one-shot “L” level pulse
Generation of CNTR 0/CNTR 1 interrupt request : Rising edge
3807 GROUP USER’S MANUAL
APPLICATION
2.2 Timer
Timer 123 mode register
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
A
AA
AA
A
Timer 123 mode register (T123M) [Address : 2916]
B
Name
Function
TOUT output active edge switch 0 : Start at outputting “H” signal
0 bit
1 : Start at outputting “L” signal
TOUT output control bit
At reset
0
0 : Disabled TOUT output
1 : Enabled TOUT output
Timer 2 write control bit
0 : To a latch and a timer at the same time
2
1 : To only latch
0
Timer 2 count source selection : Output signal from Timer 1
3 bit
1 : f(XIN)/16
(Note 1)
0
Timer 3 count source selection 0 : Output signal from Timer 1
1 : f(XIN)/16
(Note 1)
b6 b5
Timer 1 count source selection 0
0 : f(XIN)/16
(Note 1)
5 bit
0 1 : f(XIN)/2
(Note 2)
0
1 0 : f(XCIN)
1 1 : Not available
Nothing is allocated for this bit. It is a write disabled bit.
7 When this bit is read out, the value is “0.”
Note 1 : In low-speed mode f(XCIN)/16 is selected.
2 : In low-speed mode f(XCIN)/2 is selected.
0
1
4 bit
6
R W
0
0
0
0
✕
Fig. 2.2.8 Structure of Timer 123 mode register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A16]
B
Name
INT0 interrupt edge selection
0 bit
INT1 interrupt edge selection
1 bit
INT2 interrupt edge selection
2 bit
Function
0 : Falling edge active
1 : Rising edge active
At reset
0
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
0
0 : Falling edge active
1 : Rising edge active
Timer 1/INT2 interrupt sources 0 : INT2 interrupt
5 bit
1 : Timer 1 interrupt
Timer 2/INT3 interrupt sources 0 : INT3 interrupt
6 bit
1 : Timer 2 interrupt
0
Timer 3/INT4 interrupt sources 0 : INT4 interrupt
1 : Timer 3 interrupt
0
INT3 interrupt edge selection
3 bit
R W
0
0
AAAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
INT4 interrupt edge selection
4 bit
7 bit
0
0
Fig. 2.2.9 Structure of Interrupt edge selection register
3807 GROUP USER’S MANUAL
2-11
APPLICATION
2.2 Timer
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address : 3C16]
B
Name
Function
0
INT0 interrupt request bit
0 : No interrupt request
1 : Interrupt request
1
INT1 interrupt request bit
At reset
R W
0
✻
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0
✻
0
✻
0
✻
0 : No interrupt request
1 : Interrupt request
Timer Y interrupt request bit
0 : No interrupt request
5
1 : Interrupt request
Timer 2/INT3 interrupt request 0 : No interrupt request
6 bit
1 : Interrupt request
0
✻
0
✻
0
✻
Timer 3/INT4 interrupt request 0 : No interrupt request
1 : Interrupt request
0
✻
Serial I/O1 receive interrupt
2 request bit
AAAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
Serial I/O1 transmit interrupt
3 request bit
4
Timer X interrupt request bit
7 bit
✻ “0” is set by software, but not “1.”
Fig. 2.2.10 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
A
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
Interrupt request register 2 (IREQ2) [Address : 3D16]
B
0
Name
CNTR0 interrupt request bit
Function
0 : No interrupt request
1 : Interrupt request
CNTR1 interrupt request bit
0 : No interrupt request
1 : Interrupt request
Serial I/O2 interrupt request
0 : No interrupt request
2 bit
1 : Interrupt request
Timer 1/INT2 interrupt request 0 : No interrupt request
3
1 : Interrupt request
bit
1
Timer A interrupt request bit
0 : No interrupt request
1 : Interrupt request
Timer B interrupt request bit
0 : No interrupt request
5
1 : Interrupt request
ADT/AD conversion interrupt 0 : No interrupt request
6 request bit
1 : Interrupt request
Nothing is allocated for this bit. It is a write disabled bit.
7 When this bit is read out, the value is “0.”
4
At reset
R W
0
✻
0
✻
0
✻
0
✻
0
✻
0
✻
0
✻
0
✕
AAAAAAAAAAAAAA
AA
AA
A
A
AAAAAAAAAAAAA
AA
AA
A
✻ “0” is set by software, but not “1.”
Fig. 2.2.11 Structure of Interrupt request register 2
2-12
3807 GROUP USER’S MANUAL
APPLICATION
2.2 Timer
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E16]
B
Name
Function
At reset
0
INT0 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
1
INT1 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0
Serial I/O1 receive interrupt
2 enable bit
R W
0
0
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
Serial I/O1 transmit interrupt
3 enable bit
4
5
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 2/INT3 interrupt enable
6 bit
Timer 3/INT4 interrupt enable
7 bit
0
0
0
Fig. 2.2.12 Structure of Interrupt control register 1
Interrupt control register 2
A
b7 b6 b5 b4 b3 b2 b1 b0
0
A
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
Interrupt control register 2 (ICON2) [Address : 3F16]
B
Name
Function
At reset
0
CNTR0 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
1
CNTR1 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
Serial I/O2 interrupt enable
2 bit
3
4
5
Timer 1/INT2 interrupt enable
bit
Timer A interrupt enable bit
Timer B interrupt enable bit
R W
0
0
0
0
AAAAAAAAAAAAAA
AA
AA
A
A
AAAAAAAAAAAAA
AA
AA
A
ADT/AD conversion interrupt
6 enable bit
7
Fix this bit to “0.”
0
0
Fig. 2.2.13 Structure of Interrupt control register 2
3807 GROUP USER’S MANUAL
2-13
APPLICATION
2.2 Timer
2.2.3 Timer application examples
(1) Basic functions and uses
[Function 1] Control of Event interval (Timer X, Timer Y, Timer 1, Timer 2, Timer 3)
The Timer count stop bit is set to “0” after setting a count value to a timer. Then a timer interrupt
request occurs after a certain period.
[Use] • Generation of an output signal timing
• Generation of a waiting time
[Function 2] Control of Cyclic operation (Timer X, Timer Y, Timer 1, Timer 2, Timer 3)
The value of a timer latch is automatically written to a corresponding timer every time a timer
underflows, and each cyclic timer interrupt request occurs.
[Use] • Generation of cyclic interrupts
• Clock function (measurement of 25m second)
• Control of a main routine cycle
Application example 1
[Function 3] Output of Rectangular waveform (Timer X, Timer Y, Timer 2)
The output level of the CNTR pin is inverted every time a timer underflows (Pulse output mode).
[Use] • A piezoelectric buzzer output
Application example 2
• Generation of the remote-control carrier waveforms
[Function 4] Count of External pulse (Timer X, Timer Y)
External pulses input to the CNTR pin are selected as a timer count source (Event counter
mode).
[Use] • Measurement of frequency
Application example 3
• Division of external pulses.
• Generation of interrupts in a cycle based on an external pulse.
(count of a reel pulse)
[Function 5] Measurement of External pulse width (Timer X, Timer Y)
The “H” or “L” level width of external pulses input to CNTR pin is measured (Pulse width
measurement mode).
[Use] • Measurement of external pulse frequency (Measurement of pulse width of FG pulse ✽ generated by motor)
Application example 4
• Measurement of external pulse duty (when the frequency is fixed)
✽FG pulse : Pulse used for detecting the motor speed to control the motor speed.
2-14
3807 GROUP USER’S MANUAL
APPLICATION
2.2 Timer
(2) Timer application example 1 : Clock function (measurement of 25 ms)
Outline : The input clock is divided by a timer so that the clock counts up every 25 ms.
Specifications : • The clock f(XIN) = 8 MHz is divided by a timer.
• The clock is counted at intervals of 25 ms by the Timer 3 interrupt.
Figure 2.2.14 shows a connection of timers and a setting of division ratios, Figures 2.2.15 show a
setting of related registers, and Figure 2.2.16 shows a control procedure.
f(XIN) = 8 MHz
Fixed
Timer 1
1/16
1/250
Timer 3
Timer 3 interrupt request bit
The clock is divided by 40 by software.
1/50
0 or 1
1/40
25 ms
1 second
0 : No interrupt request
1 : Interrupt request
Fig. 2.2.14 Connection of timers and setting of division ratios [Clock function]
3807 GROUP USER’S MANUAL
2-15
APPLICATION
2.2 Timer
Timer 123 mode register (Address : 2916)
b7
b0
0 0 0
T123M
Timer 3 count source selection bit : Output signal from
Timer 1
Timer 1 count source selection bits : f(XIN)/16
Timer 1 (Address : 2416)
b7
T1
b0
249
Timer 3 (Address : 2616)
b7
T3
b0
Set “division ratio – 1”
49
Interrupt edge selection register (Address : 3A16)
b7
INTEDGE
b0
1
Timer 3/INT4 interrupt sources bit : Timer 3 interrupt
Interrupt control register 1 (Address : 3E16)
b7
ICON1
b0
1
Timer 3/INT4 interrupt enable bit : Interrupt enabled
Interrupt request register 1 (Address : 3C16)
b7
IREQ1
b0
0
Timer 3/INT4 interrupt request bit
(becomes “1” every 25 ms)
Fig. 2.2.15 Setting of related registers [Clock function]
2-16
3807 GROUP USER’S MANUAL
APPLICATION
2.2 Timer
Control procedure :
Figure 2.2.16 shows a control procedure.
●
RESET
X : This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
Initialization
SEI
●
All interrupts : Disabled
....
T123M (Address : 2916)
X000XXXX2
INTEDGE (Address : 3A16), bit7
1
ICON1 (Address : 3E16), bit7
1
●
T1
T3
●
●
Select each count source of the Timer 1 and Timer 3.
Timer 3 interrupt : Enabled
....
....
(Address : 2416)
(Address : 2616)
250 – 1
50 – 1
CLI
●
Set “division ratio – 1” to the Timer 1 and Timer 3.
Interrupts : Enabled
Main processing
....
[Processing for completion of setting clock]
(Note 1)
(Address : 2416)
T1
(Address : 2616)
T3
IREQ1 (Address : 3C16), bit7
●
250 – 1
50 – 1
0
●
When restarting the clock from zero second after
completing to set the clock, reset timers.
Set the Timer 3 interrupt request bit to “0.”
Note 1: This processing is performed only
at completing to set the clock.
Timer 3 interrupt processing routine
Note 2: When using the Index X mode flag (T).
Note 3: When using the Decimal mode flag (D).
CLT (Note 2)
CLD (Note 3)
Push register to stack
●
Y
Clock stop?
Push the register used in the interrupt
processing routine into the stack.
●
Check if the clock has already been set.
●
Count up the clock.
●
Pop registers which is pushed to stack
N
Clock count up (1/40 second-year)
Pop registers
RTI
Fig. 2.2.16 Control procedure [Clock function]
3807 GROUP USER’S MANUAL
2-17
APPLICATION
2.2 Timer
(3) Timer application example 2 : Piezoelectric buzzer output
Outline : The rectangular waveform output function of a timer is applied for a piezoelectric buzzer
output.
Specifications : • The rectangular waveform resulting from dividing clock f(X IN) = 8 MHz into about
2 kHz (2049 Hz) is output from the P54 /CNTR0 pin.
• The level of the P5 4/CNTR 0 pin fixes to “H” while a piezoelectric buzzer output is
stopped.
Figure 2.2.17 shows an example of a peripheral circuit, and Figure 2.2.18 shows a connection of the
timer and setting of the division ratio.
The “H” level is output while a piezoelectric buzzer output is stopped.
CNTR0 output
3807 group
P54/CNTR0
PiPiPi....
244 µs
244 µ s
Set a division ratio so that the underflow output cycle of the Timer X becomes this value.
Fig. 2.2.17 Example of a peripheral circuit
Timer X count source
selection bit
f(XIN) = 8 MHz
1/16
Timer X
1/122
CNTR0
Fig. 2.2.18 Connection of the timer and setting of the division ratio [Piezoelectric buzzer output]
2-18
3807 GROUP USER’S MANUAL
APPLICATION
2.2 Timer
AA
AA
Timer X mode register (Address : 2716)
b7
TXM
0 1 0
b0
0 0 0 1
Timer X operating mode bits : Pulse output mode
Timer X write control bit : Write to a latch and a timer
at the same time.
CNTR0 active edge switch bit : Output from the “H” level
Timer X count source selection bits : f(XIN)/16
Timer XY control register (Address : 1416)
b7
b0
1
TXYCON
Timer X stop control bit : Stop counting
(set this bit to “0” at starting counting.)
Timer X High-order (Address : 2116)
b7
b0
TXH
0
Timer X Low-order (Address : 2016)
b7
TXL
b0
Set “division ratio – 1”
122—1
Port P5 direction register (Address : 0B16)
b7
b0
1
P5D
P54/CNTR0 : Output mode
Port P5 (Address : 0A16)
b7
P5
b0
1
“H” is output at stopping a piezoelectric
buzzer output.
Fig. 2.2.19 Setting of related registers [Piezoelectric buzzer output]
3807 GROUP USER’S MANUAL
2-19
APPLICATION
2.2 Timer
Control procedure :
Figure 2.2.20 shows a control procedure.
RESET
●X
Initialization
....
P5
P5D
....
1
(Address : 0A16), bit4
(Address : 0B16)
XXX1XXXX2
●
0
ICON1 (Address : 3E16), bit4
1
TXYCON(Address : 1416), bit0
TXM (Address : 2716)
010X00012
TXL (Address : 2016)
122 – 1
TXH (Address : 2116)
0
●
●
●
●
: This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
Set the port state at stopping a piezoelectric buzzer
output. (“H” level output)
Timer X interrupts : Disabled
Timer X count : Stopped
(stop outputting a piezoelectric buzzer).
Timer X : Pulse output mode
Set “division ratio – 1” to the Timer X.
Main processing
Output unit
●
A piezoelectric buzzer
is requested?
Y
The piezoelectric buzzer request occured in the
main processing is processed in the output unit.
N
TXYCON (Address : 1416), bit0
During stopping outputting a piezoelectric buzzer
1
TXYCON (Address : 1416), bit0
During outputting a piezoelectric buzzer
Fig. 2.2.20 Control procedure [Piezoelectric buzzer output]
2-20
0
3807 GROUP USER’S MANUAL
APPLICATION
2.2 Timer
(4) Timer application example 3 : Measurement of frequency
Outline : The following two values are compared for judging if the frequency is within a certain range.
• A value counted a pulse which is input to P5 5/CNTR 1 pin by a timer.
• A referance value
Specifications : • The pulse is input to the P55 /CNTR1 pin and counted by the Timer Y.
• A count value is read out at the interval of about 2 ms (Timer X interrupt interval).
When the count value is 28 to 40, it is regarded the input pulse as a valid.
• Because the timer is a down-counter, the count value is compared with 227 to
215 ₎ .
₎ 227 to 215 = 255 (initialized value of counter) – 28 to 40 (the number of valid
value).
Figure 2.2.21 shows a method for judging if input pulse exists, and Figure 2.2.22 and Figure 2.2.23
show a setting of related registers.
Input pulse
••••
71.4 µ s or more
(14 kHz or less)
••••
71.4 µ s
(14 kHz)
Invalid
••••
50 µs
(20 kHz)
Valid
2 ms
= 28 counts
71.4 µ s
50 µ s or less
(20 kHz or more)
Invalid
2 ms
50 µ s
= 40 counts
Fig 2.2.21 A method for judging if input pulse exists
3807 GROUP USER’S MANUAL
2-21
APPLICATION
2.2 Timer
AA
AA
Timer Y mode register (Address : 2816)
b7
TYM
1 1 1
b0
0 0 0 0
Timer Y operating mode bits : Timer•Event counter mode
Timer Y write control bit : Write to a latch and a timer
at the same time.
CNTR1 active edge switch bit : Count at falling edge
Timer Y count source selection bits : Input signal from
CNTR1 pin
AA
Timer X mode register (Address : 2716)
b7
TXM
0 1
b0
0 0 0 0
Timer X operating mode bits : Timer•Event counter mode
Timer X write control bit : Write to a latch and a timer
at the same time.
Timer X count source selection bits : f(XIN)/16
Timer XY control register (Address : 1416)
b7
b0
1 1
TXYCON
Timer X stop control bit : Stop counting
(set this bit to “0” at starting counting.)
Timer Y stop control bit : Stop counting
(set this bit to “0” at starting counting.)
Timer Y High-order (Address : 2316)
b7
TYH
b0
0016
Timer Y Low-order (Address : 2216)
b7
TYL
b0
Set to “FF16” before counting a pulse.
(After a certain time, a number of inputted
pulse is decremented from this value.)
FF16
Timer X High-order (Address : 2116)
b7
TXH
b0
0316
Timer X Low-order (Address : 2016)
b7
TXL
b0
Set “division ratio – 1” for making underflow every
2 ms input at inputting f(XIN)=8MHz.
E716
Fig. 2.2.22 Setting of related registers (1) [Measurement of frequency]
2-22
3807 GROUP USER’S MANUAL
APPLICATION
2.2 Timer
Interrupt control register 1 (Address : 3E16)
b7
b0
0 1
ICON1
Timer X interrupt enable bit : Interrupt enabled
Timer Y interrupt enable bit : Interrupt disabled
Interrupt request register 1 (Address : 3C16)
b7
b0
IREQ1
0
Timer X interrupt request bit
(becomes “1” every 2 ms)
Port P5 direction register (Address : 0B16)
b7
P5D
b0
0
P55/CNTR1 : Input mode
Fig. 2.2.23 Setting of related registers (2) [Measurement of frequency]
3807 GROUP USER’S MANUAL
2-23
APPLICATION
2.2 Timer
Control procedure :
Figure 2.2.24 shows a control procedure.
● X : This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
RESET
Initialization
●
All interrupts : Disabled
....
SEI
(Address : 2816)
111X00002
TYM
(Address : 0B16)
XX0XXXXX2
P5D
XXXXXX112
TXYCON(Address : 1416)
(Address : 2216)
FF16
TYL
(Address : 2316)
0016
TYH
(Address : 2716)
01XX00002
TXM
(Address : 2016)
E716
TXL
(Address : 2116)
0316
TXH
0
ICON1 (Address : 3E16), bit5
1
ICON1 (Address : 3E16), bit4
0
IREQ1 (Address : 3C16), bit4
....
TXYCON(Address : 1416)
●
●
●
●
●
●
●
●
XXXXXX002
●
Timer X count and Timer Y count :Started counting
●
Interrupts : Enabled
....
CLI
Timer Y : Timer•Event counter mode
(Count at falling edge of pulse input from CNTR1 pin)
Timer X count and Timer Y count :Stopped counting
Timer X : Timer mode
Timer X count source selection bit : f(XIN)/16
Set the division ratio so that the Timer X interrupt
occurs every 2 ms.
Timer Y interrupt : Disabled
Timer X interrupt : Enabled
Set the Timer X interrupt request bit to “0.”
~
~
Timer X interrupt processing routine
Note 1: When using the Index X mode flag (T).
Note 2: When using the Decimal mode flag (D).
CLT (Note 1)
CLD (Note 2)
Push register to stack
≠ 0016
●
●
TYH (Address : 2316)?
Push the register used in the interrupt
processing routine into the stack
When the count value is 256 or more, the
processing is performed as out of range.
=0016
●
(A)
TYL (Address : 2216)
D616
●
Read the count value.
Store the count value in the accumulator (A).
In range
< (A) < E416?
●
●
Out of range
Fpulse
TYL
TYH
Fpulse
0
(Address : 2216)
(Address : 2316)
FF16
0016
●
Compare the count value read with the
reference value.
Store the comparison result in flag Fpulse.
1
Initialize the count value
Processing for a result of judgment
Pop registers
●
Pop registers which is pushed to stack.
RTI
Fig. 2.2.24 Control procedure [Measurement of frequency]
2-24
3807 GROUP USER’S MANUAL
APPLICATION
2.2 Timer
(5) Timer application example 4 : Measurement of pulse width of FG pulse generated by motor
Outline : The “H” level width of a pulse input to the P5 4 /CNTR 0 pin is counted by Timer X. An
underflow is detected by Timer X interrupt and an end of the input pulse “H” level is
detected by CNTR 0 interrupt.
Specifications : • The “H” level width of FG pulse input to the P54 /CNTR0 pin is counted by Timer
X.
(Example : When the clock frequency is 8 MHz, the count source would be 2 µ s
that is obtained by dividing the clock frequency by 16. Measurement
can be made up to 131.072 ms in the range of FFFF 16 to 0000 16 .)
Figure 2.2.25 shows a connection of the timer and setting of the division ratio, and Figure 2.2.26
shows a setting of related registers.
Timer X count source
selection bit
f(XIN) = 8 MHz
1/16
Timer X
1/65536
Timer X interrupt
request bit
0 or 1
131.072 ms
0 : No interrupt request
1 : Interrupt request
Fig. 2.2.25 Connection of the timer and setting of the division ratio [Measurement of pulse width]
3807 GROUP USER’S MANUAL
2-25
APPLICATION
2.2 Timer
AA
AA
Timer X mode register (Address : 2716)
b7
TXM
0 1 0
b0
0 0 1 1
Timer X operating mode bits : Pulse width measurement mode
Timer X write control bit : Write to a latch and a timer
at the same time.
CNTR0 active edge switch bit : Measure the “H” level width
Timer X count source selection bits : f(XIN)/16
Timer XY control register (Address : 1416)
b7
b0
1
TXYCON
Timer X stop control bit : Stop counting
(set this bit to “0” at starting counting.)
Timer X High-order (Address : 2116)
b7
TXH
b0
FF16
Timer X Low-order (Address : 2016)
b7
TXL
b0
Set “FFFF16” before starting measuring a pulse width.
FF16
Interrupt control register 1 (Address : 3E16)
b7
b0
1
ICON1
Timer X interrupt enable bit : Interrupt enabled
Interrupt request register 1 (Address : 3C16)
b7
IREQ1
b0
0
Timer X interrupt request bit
(This bit is set to “1” at underflow of Timer X.)
Interrupt control register 2 (Address : 3F16)
b7
b0
1
ICON2
CNTR0 interrupt enable bit : Interrupt enabled
Interrupt request register 2 (Address : 3D16)
b7
b0
0
IREQ2
CNTR0 interrupt request bit
(This bit is set to “1” at completion of inputting
“H” level signal.)
Port P5 direction register (Address : 0B16)
b7
P5D
b0
0
P54/CNTR0 : Input mode
Fig. 2.2.26 Setting of related registers [Measurement of pulse width]
2-26
3807 GROUP USER’S MANUAL
APPLICATION
2.2 Timer
Figure 2.2.27 and Figure 2.2.28 show a control procedure.
RESET
● X : This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
Initialization
SEI
●
All interrupts : Disabled
....
010X00112
TXM
(Address : 2716)
P5D
(Address : 0B16)
XXX0XXXX2
TXYCON (Address : 1416), bit0
1
(Address : 2016)
TXL
255
(Address : 2116)
TXH
255
ICON1 (Address : 3E16), bit4
1
IREQ1 (Address : 3C16), bit4
0
ICON2 (Address : 3F16), bit0
1
IREQ2 (Address : 3D16), bit0
0
TXYCON (Address : 1416), bit0
0
●
●
●
●
Timer X interrupt : Enabled
●
CNTR0 interrupt : Enabled
●
Timer X count : Start
●
Interrupts : Enabled
●
Error occurs
....
CLI
Timer X : Pulse width measurement mode
(Count “H” level width of pulse input from CNTR0 pin.)
Timer X count : Stopped counting
Set the initial value of the Timer X.
~
~
Timer X interrupt processing routine (Note)
Processing for error
RTI
Note : The Timer X interrupt occurs at a level except a measurement level (when it
is “L” level in this applicaion example). Process by software in accordance
with the necessity like as a processing for errors is performed only at a
measurement level (The CNTR0 input level is judged by reading a content
of the Port P54 register).
Fig. 2.2.27 Control procedure (1) [Measurement of pulse width]
3807 GROUP USER’S MANUAL
2-27
APPLICATION
2.2 Timer
CNTR0 interrupt processing routine (Note 1)
CLT (Note 2)
CLD (Note 3)
Push register to stack
(A)
Result of pulse width measurement
high–order 8-bit
(A)
Result of pulse width measurement
low–order 8-bit
●
TXH
●
Note 2: When using the Index X mode flag (T).
Note 3: When using the Decimal mode flag (D).
Push the register used in the interrupt
processing routine into the stack.
A count value is read out and stored to RAM.
(A)
TXL
(A)
Pop registers
●
Pop registers which is pushed to stack.
RTI
Note 1: The first measurement value happen to be invalid at a start
timing of the Timer X count as shown a following figure.
Process it by software in accordance with the necessity.
Example
1. Be started the Timer X count at “L” level of the CNTR0 input signal.
(A level of the CNTR0 input signal is judged by reading a content of the Port
P54 register.)
2. Be invalid the first CNTR0 interrupt after starting the Timer X count.
[When the Timer X count is started at “L” level of the CNTR0 input signal]
000016
T2
T1
FFFF16
A value of T1 : Valid
A value of T2 : Valid
CNTR0 input
CNTR0 interrupt
CNTR0 interrupt
At starting counting the Timer X
[When the Timer X count is started at “H” level of the CNTR0 input signal]
000016
T1
T2
FFFF16
A value of T1 : Invalid
A value of T2 : Valid
CNTR0 input
CNTR0 interrupt
At starting counting the Timer X
CNTR0 interrupt
Fig. 2.2.28 Control procedure (2) [Measurement of pulse width]
2-28
3807 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
2.3 Serial I/O
2.3.1 Memory map of serial I/O
001816
Transmit/Receive buffer register (TB/RB)
001916
Serial I/O1 status register (SIO1STS)
001A16
Serial I/O1 control register (SIO1CON)
001B16
UART control register (UARTCON)
001C16 Baud rate generator (BRG)
001D16 Serial I/O2 control register 1 (SIO2CON1)
001E16
Serial I/O2 control register 2 (SIO2CON2)
001F16
Serial I/O2 register (SIO2)
003A16
Interrupt edge selection register (INTEDGE)
003C16
Interrupt request register 1 (IREQ1)
003D16
Interrupt request register 2 (IREQ2)
003E16
Interrupt control register 1 (ICON1)
003F16
Interrupt control register 2 (ICON2)
Fig. 2.3.1 Memory map of serial I/O related registers
3807 GROUP USER’S MANUAL
2-29
APPLICATION
2.3 Serial I/O
2.3.2 Related registers
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB) [Address : 1816]
Function
B
0
1
At reset
A transmission data is written to or a receive data is read out
from this buffer register.
• At writing : a data is written to the Transmit buffer register.
• At reading : a content of the Receive buffer register is read out.
R W
?
?
2
?
3
?
4
?
5
?
6
?
7
?
Note : A content of the Transmit buffer register cannot be read out.
A data cannot be written to the Receive buffer register.
Fig. 2.3.2 Structure of Transmit/Receive buffer register
Serial I/O1 status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 status reigster (SIO1STS) [Address : 1916]
Name
B
Transmit
buffer
empty flag
0
(TBE)
1 Receive buffer full flag (RBF)
2 Transmit shift register shift
completion flag (TSC)
3 Overrun error flag (OE)
4 Parity error flag (PE)
5 Framing error flag (FE)
6 Summing error flag (SE)
Function
0 : Buffer full
1 : Buffer empty
0 : Buffer empty
1 : Buffer full
0 : Transmit shift in progress
1 : Transmit shift completed
0
R W
✕
0
✕
0
✕
0 : No error
1 : Overrun error
0 : No error
1 : Parity error
0
✕
0
✕
0 : No error
1 : Framing error
0 : (OE) (PE) (FE) = 0
1 : (OE) (PE) (FE) = 1
0
✕
0
✕
1
✕
7 Nothing is allocated for this bit. It is a write disabled bit.
When this bit is read out, the value is “0.”
Fig. 2.3.3 Structure of Serial I/O1 status register
2-30
3807 GROUP USER’S MANUAL
At reset
APPLICATION
2.3 Serial I/O
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register (SIO1CON) [Address : 1A16]
B
0
1
Name
BRG count source
selection bit (CSS)
Serial I/O1
synchronous clock
selection bit (SCS)
Function
At reset
(Note 1)
(Note 2)
0 : f(XIN)
1 : f(XIN)/4
At selecting clock synchronous serial I/O
0 : BRG output divided by 4
1 : External clock input
R W
0
0
At selecting UART
0 : BRG output divided by 16
1 : External clock input divided by 16
2
SRDY1 output enable bit
3
(SRDY)
Transmit interrupt
source selection bit
(TIC)
4
Transmit enable bit (TE)
5
Receive enable bit (RE)
6
Serial I/O1 mode
selection bit (SIOM)
7
Serial I/O1 enable bit
(SIOE)
0 : I/O port (P47)
1 : SRDY1 output pin
0 : Transmit buffer empty
1 : Transmit shift operating
completion
0 : Transmit disabled
1 : Transmit enabled
0 : Receive disabled
1 : Receive enabled
0 : UART
1 : Clock synchronous serial I/O
0
0 : Serial I/O1 disabled
(P44–P47 : I/O port)
1 : Serial I/O1 enabled
(P44–P47 : Serial I/O function pin)
0
0
0
0
0
Note 1 : In low-speed mode f(XCIN) is selected.
2 : In low-speed mode f(XCIN)/4 is selected.
Fig. 2.3.4 Structure of Serial I/O1 control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register (UARTCON) [Address : 1B16]
Name
B
Character
length
0
selection bit (CHAS)
1 Parity enable bit
2
3
4
5
6
7
Function
0 : 8 bits
1 : 7 bits
0 : Parity checking disabled
1 : Parity checking enabled
0 : Even parity
1 : Odd parity
0 : 1 stop bit
1 : 2 stop bits
In output mode
0 : CMOS output
1 : N-channel open-drain
output
(PARE)
Parity selection bit
(PARS)
Stop bit length selection
bit (STPS)
P45/TxD P-channel
output disable bit
(POFF)
Nothing is allocated for these bits. These are write
disabled bits. When these bits are read out, the
values are “1.”
At reset
R W
0
0
0
0
0
1
1
1
✕
✕
✕
Fig. 2.3.5 Structure of UART control register
3807 GROUP USER’S MANUAL
2-31
APPLICATION
2.3 Serial I/O
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator (BRG) [Address : 1C16]
Function
B
At reset
0 A count value of Baud rate generator is set.
?
1
?
2
?
3
?
4
?
5
?
6
?
7
?
R W
Fig. 2.3.6 Structure of Baud rate generator
Serial I/O2 control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register 1 (SIO2CON1) [Address : 1D16]
Name
B
0 Internal synchronous
clock selection bits
1
2
Function
b2 b1 b0
0
0
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
(Note)
:
:
:
:
:
:
f(XIN)/8
f(XIN)/16
f(XIN)/32
f(XIN)/64
f(XIN)/128
f(XIN)/256
(f(XCIN)/8)
(f(XCIN)/16)
(f(XCIN)/32)
(f(XCIN)/64)
(f(XCIN)/128)
(f(XCIN)/256)
0 : I/O port (P71, P72)
1 : SOUT2, SCLK2 output pin
0 : I/O port (P73)
SRDY2 output enable bit
1 : SRDY2 output pin
0 : LSB first
Transfer direction
1 : MSB first
selection bit
Serial I/O2 synchronous clock 0 : External clock
1 : Internal clock
selection bit
In output mode
P71/ SOUT2, P72/ SCLK2
0 : CMOS output
P-channel output disable bit
1 : N-channel open-drain output
0
0
0
3 Serial I/O2 port selection bit
0
4
0
5
6
7
Note : In low-speed mode ( ) is selected.
Fig. 2.3.7 Structure of Serial I/O2 control register 1
2-32
At reset
3807 GROUP USER’S MANUAL
0
0
0
R W
APPLICATION
2.3 Serial I/O
Serial I/O2 control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register 2 (SIO2CON2) [Address : 1E16]
Name
B
0 Optional transfer bits
1
2
Function
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : 1 bit
1 : 2 bit
0 : 3 bit
1 : 4 bit
0 : 5 bit
1 : 6 bit
0 : 7 bit
1 : 8 bit
3 Nothing is allocated for these bits. These are write disabled bits.
4 When these bits are read out, the values are “0.”
5
6 Serial I/O2 I/O comparative 0 : P51 I/O
signal control bit
S
7 OUT2 pin control bit (P71)
1 : SCMP2 output
0 : Output active
1 : Output high impedance
At reset
R W
1
1
1
0
0
0
0
✕
✕
✕
0
Fig. 2.3.8 Structure of Serial I/O2 control register 2
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 register (SIO2) [Address : 1F16]
Function
B
At reset
0 A shift register for serial transmission and reception.
?
At transmitting : Set a transmission data.
● At receiving : Store a reception data.
1
?
2
?
3
?
4
?
5
?
6
?
7
?
R W
●
Fig. 2.3.9 Structure of Serial I/O2 register
3807 GROUP USER’S MANUAL
2-33
APPLICATION
2.3 Serial I/O
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A16]
Name
B
INT
0
interrupt
edge
0
selection bit
1 INT1 interrupt edge
selection bit
2 INT2 interrupt edge
selection bit
3 INT3 interrupt edge
selection bit
4 INT4 interrupt edge
selection bit
5 Timer 1/INT2 interrupt
source bit
Timer
2/INT3 interrupt
6
source bit
7 Timer 3/INT4 interrupt
source bit
Function
0
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
0 : INT2 interrupt
1 : Timer 1 interrupt
0
0 : INT3 interrupt
1 : Timer 2 interrupt
0
0 : INT4 interrupt
1 : Timer 3 interrupt
0
Fig. 2.3.10 Structure of Interrupt edge selection register
2-34
At reset
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
3807 GROUP USER’S MANUAL
0
0
0
0
R W
APPLICATION
2.3 Serial I/O
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 1 (IREQ1) [Address : 3C16]
Function
Name
B
At reset
R W
0 INT0 interrupt request bit
0 : No interrupt request
1 : Interrupt request
0
✻
1 INT1 interrupt request bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0
✻
0
✻
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0
✻
0
✻
0 : No interrupt request
1 : Interrupt request
Timer
2/INT
3 interrupt request 0 : No interrupt request
6
bit
1 : Interrupt request
0 : No interrupt request
Timer
3/INT
4
interrupt
request
7
1 : Interrupt request
bit
0
✻
0
✻
0
✻
2 Serial I/O1 receive interrupt
request bit
3 Serial I/O1 transmit interrupt
request bit
4 Timer X interrupt request bit
bit
5 Timer Y interrupt request bit
✻ “0” is set by software, but not “1.
Fig. 2.3.11 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 2 (IREQ2) [Address : 3D16]
Name
B
0 CNTR0 interrupt request bit
1
2
3
4
5
6
7
Function
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
CNTR1 interrupt request bit
1 : Interrupt request
0
Serial I/O2 interrupt request bit : No interrupt request
1 : Interrupt request
0 : No interrupt request
Timer 1/INT2 interrupt
1 : Interrupt request
request bit
0 : No interrupt request
Timer A interrupt request bit
1 : Interrupt request
0 : No interrupt request
Timer B interrupt request bit
1 : Interrupt request
0 : No interrupt request
ADT/AD conversion
1 :Interrupt request
interrupt request bit
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0.”
At reset
R W
0
✻
0
✻
0
✻
0
✻
0
✻
0
✻
0
✻
0
✕
✻ “0” is set by software, but not “1.”
Fig. 2.3.12 Structure of Interrupt request register 2
3807 GROUP USER’S MANUAL
2-35
APPLICATION
2.3 Serial I/O
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E16]
B
Function
Name
0 INT0 interrupt enable bit
1 INT1 interrupt enable bit
2 Serial I/O1 receive interrupt
enable bit
Serial
I/O1 transmit interrupt
3
enable bit
4 Timer X interrupt enable bit
5 Timer Y interrupt enable bit
6 Timer 2/INT3 interrupt enable
bit
Timer
3/INT4 interrupt enable
7
bit
At reset
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
R W
0
0
0
0
0
0
Fig. 2.3.13 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address : 3F16]
Name
B
0 CNTR0 interrupt enable bit
Function
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
3 Timer 1/INT2 interrupt enable
bit
4 Timer A interrupt enable bit
5 Timer B interrupt enable bit
6 ADT/AD conversion interrupt
enable bit
7 Fix this bit to “0.”
Fig. 2.3.14 Structure of Interrupt control register 2
2-36
At reset
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 CNTR1 interrupt enable bit
1 : Interrupt enabled
0
: Interrupt disabled
Serial
I/O2
interrupt
enable
bit
2
1 : Interrupt enabled
3807 GROUP USER’S MANUAL
0
0
0
0
0
0
R W
APPLICATION
2.3 Serial I/O
2.3.3 Serial I/O connection examples
(1) Control of peripheral IC equipped with CS pin
There are connection examples using a clock synchronous serial I/O mode.
Figure 2.3.15 shows connection examples of a peripheral IC equipped with the CS pin.
(1) Only transmission
(using the RXD pin as an I/O port)
Port
CS
SCLK
CLK
TXD
DATA
3807 group
Peripheral IC
(OSD controller etc.)
(3) Transmission and reception
(Pins RXD and TXD are connected)
(Pins IN and OUT in peripheral IC
are connected)
(2) Transmission and reception
Port
CS
SCLK
CLK
TXD
RXD
IN
3807 group
OUT
Peripheral IC
(E 2 PROM etc.)
(4) Connecting ICs
Port
CS
Port
CS
SCLK
CLK
SCLK
CLK
TXD
RXD
IN
TXD
IN
OUT
R XD
OUT
3807 group ✻1 Peripheral IC ✻2
2
(E PROM etc.)
Port
Peripheral IC 1
3807 group
✻1:
Select an N-channel open-drain output control of TXD pin.
2: Use such OUT pin of peripheral IC as an N-channel opendrain output in high impedance during receiving data.
Notes1: “Port” is an output port controlled by software.
2: Use SOUT2 and SIN2 instead of TXD and RXD in the
serial I/O2.
CS
CLK
IN
OUT
Peripheral IC 2
Fig. 2.3.15 Serial I/O connection examples (1)
3807 GROUP USER’S MANUAL
2-37
APPLICATION
2.3 Serial I/O
(2) Connection with microcomputer
Figure 2.3.16 shows connection examples of the other microcomputers.
(2) Selecting an external clock
(1) Selecting an internal clock
SCLK
CLK
TXD
RXD
3807 group
SCLK
CLK
IN
TXD
IN
OUT
RXD
OUT
Microcomputer
(3) Using the SRDY siganl output function
(Selecting an external clock)
3807 group
(4) Using UART✻
SRDY
RDY
SCLK
CLK
TXD
RXD
TXD
IN
RXD
TXD
RXD
OUT
3807 group
Microcomputer
3807 group
✻ : UART can not be used in the serial I/O2.
Note : Use SOUT2 and SIN2 instead of TXD and RXD in the serial I/O2.
Fig. 2.3.16 Serial I/O connection examples (2)
2-38
Microcomputer
3807 GROUP USER’S MANUAL
Microcomputer
APPLICATION
2.3 Serial I/O
2.3.4 Setting of serial I/O transfer data format
A clock synchronous or clock asynchronous (UART) is selected as a data format of the serial I/O1. The
serial I/O2 operates in a clock synchronous.
Figure 2.3.17 shows a setting of serial I/O transfer data format.
1ST-8DATA-1SP
ST
LSB
MSB
SP
1ST-7DATA-1SP
ST
LSB
MSB
SP
1ST-8DATA-1PAR-1SP
ST
LSB
MSB
PAR
PAR
SP
MSB
2SP
SP
1ST-7DATA-1PAR-1SP
ST
UART
LSB
MSB
1ST-8DATA-2SP
ST
LSB
1ST-7DATA-2SP
ST
Serial
I/O1
LSB
MSB
2SP
1ST-8DATA-1PAR-2SP
ST
LSB
MSB
PAR
PAR
2SP
2SP
1ST-7DATA-1PAR-2SP
ST
Clock synchronous
Serial I/O
Serial
I/O2
Clock synchronous
Serial I/O
LSB
MSB
LSB first
LSB first (1 to 8 bit optional transfer)
MSB first (1 to 8 bit optional transfer)
ST :Start bit
SP :Stop bit
PAR :Parity bit
Fig. 2.3.17 Setting of Serial I/O transfer data format
3807 GROUP USER’S MANUAL
2-39
APPLICATION
2.3 Serial I/O
2.3.5 Serial I/O application examples
(1) Communication using a clock synchronous serial I/O (transmit/receive)
Outline : 2-byte data is transmitted and received through the clock synchronous serial I/O. The
signal is used for communication control.
_____
SRDY1
Figure 2.3.18 shows a connection diagram, and Figure 2.3.19 shows a timing chart.
Transmitting side
Receiving side
P42/INT0
SRDY1
SCLK1
SCLK1
TXD
R XD
3807 group
3807 group
Fig. 2.3.18 Connection diagram [Communication using a clock synchronous serial I/O]
Specifications : •
•
•
•
The Serial I/O1 is used (clock synchronous serial I/O is selected)
Synchronous clock frequency : 125 kHz (f(XIN) = 8 MHz is divided by 64)
The S RDY1 (receivable signal) is used.
The receiving side outputs the S RDY1 signal at intervals of 2 ms (generated by
timer), and 2-byte data is transferred from the transmitting side to the receiving
side.
_____
_____
••••
SRDY1
SCLK1
TXD
••••
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
2 ms
Fig. 2.3.19 Timing chart [Communication using a clock synchronous serial I/O]
2-40
3807 GROUP USER’S MANUAL
D0 D1
••••
APPLICATION
2.3 Serial I/O
Transmitting side
Serial I/O1 status register (Address : 1916)
b7
b0
SIO1STS
Transmit buffer empty flag
• Check to be transferred data from the Transmit buffer register to
Transmit shift register.
• Writable the next transmission data to the Transmit buffer register
at being set to “1.”
Transmit shift register shift completion flag
Check a completion of transmitting 1-byte data with this flag
“1” : Transmit shift completed
Serial I/O1 control register (Address : 1A16)
b7
SIO1CON
b0
1 1 0 1
0 0
BRG counter source selection bit : f(XIN)
Serial I/O1 synchronous clock selection bit : BRG/4
Transmit enable bit : Transmit enabled
Receive enable bit : Receive disabled
Serial I/O1 mode selection bit : Clock synchronous serial I/O
Serial I/O1 enable bit : Serial I/O1 enabled
Baud rate generator (Address : 1C16)
b7
BRG
b0
15
Set “division radio – 1”
Interrupt edge selection register (Address : 3A16)
b7
INTEDGE
b0
0
INT0 active edge selection bit : Select INT0 falling edge
Fig. 2.3.20 Setting of related registers at a transmitting side [Communication using a clock
synchronous serial I/O]
3807 GROUP USER’S MANUAL
2-41
APPLICATION
2.3 Serial I/O
Receiving side
Serial I/O1 status register (Address : 1916)
b7
b0
SIO1STS
Receive buffer full flag
Check a completion of receiving 1-byte data with this flag.
“1” : At completing to receive
“0” : At reading out a receive buffer
Overrun error flag
“1” : when data are ready to be transferred to the
Receive shift register in the state of storing data
into the Receive buffer register.
Serial I/O1 control register (Address : 1A16)
b7
SIO1CON
1 1 1 1
b0
1 1
Serial I/O1 synchronous clock selection bit : External clock
SRDY1 output enable bit : Use the SRDY1 output
Transmit enable bit : Transmit enabled
Set this bit to “1,” using SRDY1 output.
Receive enable bit : Receive enabled
Serial I/O1 mode selection bit : Clock synchronous serial I/O
Serial I/O1 enable bit : Serial I/O1 enabled
Fig. 2.3.21 Setting of related registers at a receiving side [Communication using a clock
synchronous serial I/O]
2-42
3807 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
Control procedure : Figure 2.3.22 shows a control procedure at a transmitting side, and Figure
2.3.23 shows a control procedure at a receiving side.
●X : This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
RESET
Initialization
.....
1101XX002
SIO1CON (Address : 1A16)
(Address : 1C16)
BRG
16—1
INTEDGE (Address : 3A16), bit0
0
0
IREQ1 (Address:3C16), bit0?
• Detect INT0 falling edge
1
IREQ1 (Address : 3C16), bit0
TB/RB (Address : 1816)
0
• Write a transmission data
The Transmit buffer empty flag is set to “0”
by this writing.
The first byte of a
transmission data
SIO1STS (Address : 1916), bit0?
0
1
TB/RB (Address : 1816)
• Write a transmission data
The Transmit buffer empty flag is set to “0”
by this writing.
The second byte of
a transmission data
SIO1STS (Address : 1916), bit0?
0
• Check to be transfered data from the Transmit
buffer register to the Transmit shift register.
(Transmit buffer empty flag)
0
• Check a shift completion of the Transmit shift register
(Transmit shift register shift completion flag)
1
SIO1STS (Address : 1916), bit2?
• Check to be transfered data from the Transmit
buffer register to the Transmit shift register.
(Transmit buffer empty flag)
1
Fig. 2.3.22 Control procedure at a transmitting side [Communication using a clock synchronous
serial I/O]
3807 GROUP USER’S MANUAL
2-43
APPLICATION
2.3 Serial I/O
●X : This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
RESET
Initialization
.....
SIO1CON (Address : 1A16)
1111X11X2
N
Pass 2 ms?
• An interval of 2 ms is generated by a timer.
Y
TB/RB (Address : 1816)
• SRDY1 output
SRDY1 signal is output by writing data to
the TB/RB.
Using the SRDY1 , the transmit enabled bit (bit4)
of the SIO1CON(address:1A16) is set to “1.”
Dummy data
SIO1STS (Address : 1916), bit1?
0
• Check a completion of receiving
(Receive buffer full flag)
1
• Receive the first byte data.
A Receive buffer full flag is set to “0” by reading data.
Read out reception data from
TB/RB (Address : 1816)
SIO1STS (Address : 1916), bit1?
0
• Check a completion of receiving
(Receive buffer full flag)
1
Read out reception data from
TB/RB (Address : 1816)
• Receive the second byte data.
A Receive buffer full flag is set to “0” by reading data.
Fig. 2.3.23 Control procedure at a receiving side [Communication using a clock synchronous
serial I/O]
2-44
3807 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
(2) Output of serial data (control of a peripheral IC)
Outline : 4-byte data is transmitted and received through the clock synchronous serial I/O. The CS
signal is output to a peripheral IC through the port P5 3 .
P53
SCLK1
TXD
3807 group
CS
CLK
DATA
P53
CS
CS
CLK
SCLK2
CLK
DATA
SOUT2
DATA
Peripheral IC
(1) Example for using Serial I/O1
3807 group
CS
CLK
DATA
Peripheral IC
(2) Example for using Serial I/O2
Fig. 2.3.24 Connection diagram [Output of serial data]
Specifications : •
•
•
•
•
The Serial I/O is used. (clock synchronous serial I/O is selected)
Synchronous clock frequency : 125 kHz (f(XIN ) = 8 MHz is divided by 64)
Transfer direction : LSB first
The Serial I/O interrupt is not used. ___
The Port P53 is connected to the CS pin (“L” active) of the peripheral IC for a
transmission control (the output level of the port P5 3 is controlled by software).
Figre 2.3.25 shows an output timing chart of serial data.
CS
CLK
DATA
DO0
DO1
DO2
DO3
Note: The SOUT2 pin is in high impedance after completing to transfer data, using the serial I/O2
as an internal clock.
Fig. 2.3.25 Timing chart [Output of serial data]
3807 GROUP USER’S MANUAL
2-45
APPLICATION
2.3 Serial I/O
Figure 2.3.26 shows a setting of serial I/O1 related registers, and Figure 2.3.27 shows a setting of
serial I/O1 transmission data.
Serial I/O1 control register (Address : 1A16)
b7
SIO1CON
b0
1 1 0 1 1 0 0 0
BRG count source selection bit : f(XIN)
Serial I/O1 synchronous clock selection bit : BRG/4
SRDY1 output enable bit : Not use the SRDY1 signal output function
Transmit interrupt source selection bit : Transmit shift operating completion
Transmit enable bit : Transmit enabled
Receive enable bit : Receive disabled
Serial I/O1 mode selection bit : Clock synchronous serial I/O
Serial I/O1 enable bit : Serial I/O1 enabled
UART control register (Address : 1B16)
b7
b0
0
UARTCON
P45/TXD P-channel output disable bit : CMOS output
Baud rate generator (Address : 1C16)
b7
b0
15
BRG
Set “division ratio – 1”
Interrupt control register 1 (Address : 3E16)
b7
ICON1
b0
0
Serial I/O1 transmit interrupt enable bit : Interrupt disabled
Interrupt request register 1 (Address : 3C16)
b7
IREQ1
b0
0
Serial I/O1 transmit interrupt request bit
Using this bit, check the completion of
transmitting 1-byte base data.
“1” : Transmit shift completion
Port P5 (Address :0A16)
b7
P5
b0
1
Set to “0” before starting to transmit.
Port P5 direction register (Address :0B16)
b7
P5D
b0
1
P53/INT4 : Output mode
Fig. 2.3.26 Setting of serial I/O1 related registers [Output of serial data]
2-46
3807 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
Transmit/Receive buffer register (Address : 1816)
b7
TB/RB
b0
Set a transmission data.
Check that transmission of the previous data is
completed before writing data (bit 3 of the
Interrupt request register 1 is set to “1”).
Fig. 2.3.27 Setting of serial I/O1 transmission data [Output of serial data]
3807 GROUP USER’S MANUAL
2-47
APPLICATION
2.3 Serial I/O
Control procedure : When the registers are set as shown in Fig. 2.3.26, the Serial I/O1 can transmit
1-byte data simply by writing data to the Transmit buffer register.
Thus, after setting the CS signal to “L,” write the transmission data to the
Receive buffer register on a 1-byte base, and return the CS signal to “H” when
the desired number of bytes have been transmitted.
Figure 2.3.28 shows a control procedure of serial I/O1.
●X : This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
RESET
....
Initialization
SIO1CON (Address : 1A16)
110110002
UARTCON (Address : 1B16), bit4
0
16–1
BRG (Address : 1C16)
0
ICON1 (Address : 3E16), bit3
1
(Address : 0A16), bit3
P5
XXXX1XXX2
P5D (Address : 0B16)
●
●
Serial I/O1 transmit interrupt : Disabled
Set the CS signal output port.
(“H” level output)
●
Set the CS signal output level to “L.”
●
....
P5 (Address : 0A16), bit3
0
IREQ1 (Address : 3C16), bit3
TB/RB (Address : 1816)
●
0
a transmission
data
●
0
IREQ1 (Address : 3C16), bit3?
Set the Serial I/O1.
●
Set the Serial I/O1 transmit interrupt
request bit to “0.”
Write a transmission data.
(start to transmit 1-byte data)
Check the completion of transmitting 1byte data.
1
N
●
Complete to transmit data?
●
Y
●
P5 (Address : 0A16), bit3
1
Use any of RAM area as a counter for
counting the number of transmitted bytes.
Check that transmission of the target
number of bytes has been completed.
Return the CS signal output level to “H”
when transmission of the target number of
bytes is completed.
Fig. 2.3.28 Control procedure of serial I/O1 [Output of serial data]
2-48
3807 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
Figure 2.3.29 shows a setting of serial I/O2 related registers, and Figure 2.3.30 shows a setting of
serial I/O2 transmission data.
Serial I/O2 control register 1 (Address : 1D16)
b7
b0
SIO2CON1 0 1 0 0 1 0 1 1
Internal synchronous clock selection bits : f(XIN)/64
Serial I/O2 port selection bit : Use the Serial I/O2
SRDY2 output enable bit : Not use the SRDY2 signal output function
Transfer direction selection bit : LSB first
Serial I/O2 synchronous clock selection bit : Internal clock
P71/SOUT2, P72/SCLK2 P-channel output disable bit : CMOS output
Serial I/O2 control register 2 (Address : 1E16)
b7
SIO2CON2
b0
0
1 1 1
Optional transfer bits : 8 bit transfer
Serial I/O2 I/O comparative signal control bit : Not use SCMP2 output
Interrupt control register 2 (Address : 3F16)
b7
b0
ICON2
0
Serial I/O2 interrupt enable bit : Interrupt disabled
Interrupt request register 2 (Address : 3D16)
b7
b0
IREQ2
0
Serial I/O2 interrupt request bit
Using this bit, check the completion of
transmitting 1-byte base data.
“1” : Transmit completion
Port P5 (Address : 0A16)
b7
P5
b0
1
Set to “0” before starting to transmit.
Port P5 direction register (Address : 0B16)
b7
P5D
b0
1
P53/INT4 : Output mode
Fig. 2.3.29 Setting of serial I/O2 related registers [Output of serial data]
3807 GROUP USER’S MANUAL
2-49
APPLICATION
2.3 Serial I/O
Serial I/O2 register (Address : 1F16)
b7
SIO2
b0
Set a transmission data.
Check that transmission of the previous data is
completed before writing data (bit 2 of the Interrupt
request register 2 is set to “1”).
Fig. 2.3.30 Setting of serial I/O2 transmission data [Output of serial data]
2-50
3807 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
Control procedure : When the registers are set as shown in Fig. 2.3.29, the Serial I/O2 can transmit
1-byte data simply by writing data to the Serial I/O2 register.
Thus, after setting the CS signal to “L,” write the transmission data to the Serial
I/O1 register on a 1-byte base, and return the CS signal to “H” when the desired
number of bytes have been transmitted.
Figure 2.3.31 shows a control procedure of serial I/O2.
●X : This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
RESET
Initialization
...
.
SIO2CON1 (Address : 1D16) 010010112
SIO2CON2 (Address : 1E16)
X0XXX1112
ICON2 (Address : 3F16), bit2
0
P5
(Address : 0A16), bit3
1
P5D
(Address : 0B16)
XXXX1XXX2
●
●
●
●
Set the Serial I/O2 control register 1.
Set the Serial I/O2 control register 2.
Serial I/O2 interrupt : Disabled
Set the CS signal output port.
(“H” level output)
...
.
P5 (Address : 0A16), bit3
0
IREQ2 (Address : 3D16), bit2
Set the CS signal output level to “L.”
●
Set the Serial I/O2 interrupt request bit to “0.”
0
a transmission
data
SIO2 (Address : 1F16)
●
IREQ2 (Address : 3D16), bit2?
0
●
Write a transmission data.
(start to transmit 1-byte data)
●
Check the completion of transmitting 1byte data.
●
Use any of RAM area as a counter for
counting the number of transmitted bytes.
Check that transmission of the target
number of bytes has been completed.
1
N
Complete to transmit data?
●
Y
●
P5 (Address : 0A16), bit3
1
Return the CS signal output level to “H” when
transmission of the target number of bytes is
completed.
Fig. 2.3.31 Control procedure of serial I/O2 [Output of serial data]
3807 GROUP USER’S MANUAL
2-51
APPLICATION
2.3 Serial I/O
(3) Cyclic transmission or reception of block data (data of a specified number of bytes)
between microcomputers
[without using an automatic transfer]
Outline : When a clock synchronous serial I/O is used for communication, synchronization of the clock
and the data between the transmitting and receiving sides may be lost because of noise
included in the synchronizing clock. Thus, it is necessary to be corrected constantly. This
“heading adjustment” is carried out by using the interval between blocks in this example.
SCLK
SCLK
RXD
TXD
T XD
R XD
Master unit
Slave unit
Note : Use SOUT2 and SIN2 instead of TXD and RXD in the serial I/O2.
Fig. 2.3.32 Connection diagram [Cyclic transmission or reception of block data between
microcomputers]
Specifications : •
•
•
•
•
•
•
•
The serial I/O1 is used (clock synchronous serial I/O is selected).
Synchronous clock frequency : 125 kHz (f(XIN) = 8 MHz is divided by 64)
Byte cycle : 488 µ s
Number of bytes for transmission or reception : 8 byte/block
Block transfer cycle : 16 ms
Block transfer period : 3.5 ms
Interval between blocks : 12.5 ms
Heading adjustive time : 8 ms
Limitations of the specifications
1. Reading of the reception data and setting of the next transmission data must be completed
within the time obtained from “byte cycle – time for transferring 1-byte data” (in this example,
the time taken from generating of the Serial I/O1 receive interrupt request to generating of the
next synchronizing clock is 428 µ s).
2. “Heading adjustive time < interval between blocks” must be satisfied.
2-52
3807 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
The communication is performed according to the timing shown below. In the slave unit, when a
synchronizing clock is not input within a certain time (heading adjustive time), the next clock input is
processed as the beginning (heading) of a block.
When a clock is input again after one block (8 byte) is received, the clock is ignored.
Figure 2.3.34 shows a setting of related registers.
D0
D1
D2
D7
D0
Byte cycle
Block transfer period
Interval between blocks
Block transfer cycle
Heading adjustive time
Master side : Read a receive data
Write a transmit data
Slave side : Read a receive data
Write a transmit data
Processing for heading adjustment
Fig. 2.3.33 Timing chart [Cyclic transmission or reception of block data between microcomputers]
Master unit
Slave unit
Serial I/O1 control register (Address : 1A16)
b7
b0
Serial I/O1 control register (Address : 1A16)
b7
b0
SIO1CON 1 1 1 1 1 0 0 0
SIO1CON 1 1 1 1
0 1
BRG count source : f(XIN)
Synchronous
clock : BRG/4
Not use the SRDY1 output
Transmit interrupt source :
Transmit shift operating completion
Transmit enabled
Receive enabled
Transmit enabled
Receive enabled
Clock synchronous serial I/O
Clock synchronous serial I/O
Serial I/O1 enabled
Serial I/O1 enabled
Not be effected by
external clock
Synchronous clock : External clock
Not use the SRDY1 output
Not use the serial I/O1 transmit interrupt
Both of units
UART control register (Address : 1B16)
b7
b0
UARTCON
0
P45/TXD pin : CMOS output
Baud rate generator (Address : 1C16)
b7
b0
BRG
15
Set “division ratio – 1”
Fig. 2.3.34 Setting of related registers [Cyclic transmission or reception of block data between
microcomputers]
3807 GROUP USER’S MANUAL
2-53
APPLICATION
2.3 Serial I/O
Control procedure :
➀ Control in the master unit
After a setting of the related registers is completed as shown in Figure 2.3.34, in the master unit
transmission or reception of 1-byte data is started simply by writing transmission data to the
Transmit buffer register.
To perform the communication in the timing shown in Figure 2.3.33, therefore, take the timing into
account and write transmission data. Read out the reception data when the Serial I/O1 transmit
interrupt request bit is set to “1,” or before the next transmission data is written to the Transmit
buffer register.
A processing example in the master unit using timer interrupts is shown below.
Interrupt processing routine
executed every 488 µs
CLT (Note 1)
CLD (Note 2)
Push register to stack
Within a block transfer period?
●
Note 1: When using the Index X mode flag (T).
Note 2: When using the Decimal mode flag (D).
Push the register used in the interrupt
processing routine into the stack.
N
●
Y
Generate a certain block interval by
using a timer or other functions.
●
Count a block interval counter
Read a reception data
Complete to transfer a block?
Y
Start a block transfer?
Y
N
Write the first transmission data
(first byte) in a block
Write a transmission data
Pop registers
●
Pop registers which is pushed to stack.
RTI
Fig. 2.3.35 Control in the master unit
2-54
N
3807 GROUP USER’S MANUAL
Check the block interval counter and
determine to start of a block transfer.
APPLICATION
2.3 Serial I/O
➁
Control in the slave unit
After a setting of the related registers is completed as shown in Figure 2.3.34, the slave unit becomes the
state which is received a synchronizing clock at all times, and the Serial I/O1 receive interrupt request bit
is set to “1” every time an 8-bit synchronous clock is received.
By the serial I/O1 receive interrupt processing routine, the data to be transmitted next is written to the
Transmit buffer register after received data is read out.
However, if no serial I/O1 receive interrupt occurs for more than a certain time (head adjustive time), the
following processing will be performed.
1. The first 1 byte data of the transmission data in the block is written into the Transmission buffer register.
2. The data to be received next is processed as the first 1 byte of the received data in the block.
Figure 2.3.36 shows the control in the slave unit using a serial I/O1 receive interrupt and any timer interrupt
(for head adjustive).
Serial I/O1 receive interrupt
processing routine
Timer interrupt processing
routine
CLT (Note 1)
CLD (Note 2)
Push register to stack
●
●
N
Within a block transfer period?
CLT (Note 1)
CLD (Note 2)
Push register to stack
Push the register used in
the interrupt processing
routine into the stack.
Check the received byte
counter to judge if a block
has been transfered.
Y
●
Heading adjustive counter – 1
N
Heading adjustive
counter = 0?
Read a reception data
Push the register used in
the interrupt processing
routine into the stack.
Y
Write the first transmission data
(first byte) in a block
A received byte counter +1
A received byte counter ≥ 8?
A received byte counter
Y
0
N
Pop registers
Write any data (FF16)
Write a transmission data
●
Pop registers which is
pushed to stack.
RTI
Heading adjustive
counter
Initialized
value (Note 3)
Pop registers
●
Pop registers which is
pushed to stack.
RTI
Notes 1: When using the Index X mode flag (T).
2: When using the Decimal mode flag (D).
3: In this example, set the value which is equal to the
heading adjustive time divided by the timer interrupt
cycle as the initialized value of the heading adjustive
counter.
For example: When the heading adjustive time is 8 ms
and the timer interrupt cycle is 1 ms, set
8 as the initialized value.
Fig. 2.3.36 Control in the slave unit
3807 GROUP USER’S MANUAL
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APPLICATION
2.3 Serial I/O
(4) Communication (transmit/receive) using an asynchronous serial I/O (UART)
Point : 2-byte data is transmitted and received through an asynchronous serial I/O.
The port P4 2 is used for communication control.
Figure 2.3.37 shows a connection diagram, and Figure 2.3.38 shows a timing chart.
Receiving side
Transmitting side
P42
P42
TXD
R XD
3807 group
3807 group
Fig. 2.3.37 Connection diagram [Communication using UART]
Specifications : • The Serial I/O1 is used (UART is selected).
• Transfer bit rate : 9600 bps (f(XIN) = 4.9152 MHz is divided by 512)
• Communication control using port P4 2
(The output level of the port P42 is controlled by softoware.)
• 2-byte data is transferred from the transmitting side to the receiving side at intervals of 10 ms (generated by timer).
P42
TXD
....
ST D0
D1 D2 D3 D4 D5 D6
D7 SP(2) ST D0 D1 D2 D3
D4 D5 D6 D7 SP(2)
10 ms
Fig. 2.3.38 Timing chart [Communication using UART]
2-56
3807 GROUP USER’S MANUAL
ST D0
....
APPLICATION
2.3 Serial I/O
Table 2.3.1 shows setting examples of Baud rate generator (BRG) values and transfer bit rate values,
Figure 2.3.39 shows a setting of related registers at a transmitting side, and Figure 2.3.40 shows a
setting of related registers at a receiving side.
Table 2.3.1 Setting examples of Baud rate generator values and transfer bit rate values
Transfer bit BRG count
at f(X IN) = 4.9152 MHZ
at f(X IN) = 7.3728 MHZ
at f(XIN) = 8 MHZ
rate(bps)
source
(Note 1)
(Note 2) BRG setting value Actual time (bps) BRG setting value Actual time (bps) BRG setting value Actual time (bps)
600
f(X IN)/4
127(7F16 )
600.00
191(BF16)
600.00
207(CF16)
600.96
1200
f(X IN)/4
63(3F16 )
1200.00
95(5F 16)
1200.00
103(67 16)
1201.92
2400
f(X IN)/4
31(1F16 )
2400.00
47(2F 16)
2400.00
51(33 16)
2403.85
4800
f(X IN)/4
15(0F16 )
4800.00
23(17 16)
4800.00
25(19 16)
4807.69
9600
f(X IN)/4
7(0716 )
9600.00
11(0B 16)
9600.00
12(0C 16)
9615.38
19200
f(X IN)/4
3(0316 )
19200.00
5(05 16)
19200.00
5(05 16)
20833.33
38400
f(X IN)/4
1(0116 )
38400.00
2(02 16)
38400.00
2(02 16)
41666.67
76800
f(XIN)
3(0316 )
76800.00
5(05 16)
76800.00
5(05 16)
83333.33
31250
f(XIN)
15(0F 16)
31250.00
62500
f(XIN)
7(07 16)
62500.00
Notes 1: Equation of transfer bit rate
Transfer bit rate (bps) =
f(XIN)
(BRG setting value + 1) ✕ 16 ✕ m
m: when bit 0 of the Serial I/O1 control register (Address : 1A16 ) is set to “0,” a value
of m is 1.
when bit 0 of the Serial I/O1 control register (Address : 1A 16 ) is set to “1,” a value
of m is 4.
2: A BRG count source is selected by bit 0 of the Serial I/O1 control register (Address : 1A16 ).
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APPLICATION
2.3 Serial I/O
Transmitting side
Serial I/O1 status register (Address : 1916)
b7
b0
SIO1STS
Transmit buffer empty flag
• Check to be transferred data from the Transmit buffer
register to the Transmit shift register.
• Writable the next transmission data to the Transmit buffer
register at being set to “1.”
Transmit shift register shift completion flag
Check a completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Serial I/O1 control register (Address : 1A16)
b7
SIO1CON
b0
1 0 0 1
0 0 1
BRG count source selection bit : f(XIN)/4
Serial I/O1 synchronous clock selection bit : BRG/16
SRDY1 output enable bit : Not use SRDY1 output
Transmit enable bit : Transmit enabled
Receive enable bit : Receive disabled
Serial I/O1 mode selection bit : Asynchronous serial I/O(UART)
Serial I/O1 enable bit : Serial I/O1 enabled
UART control register (Address : 1B16)
b7
b0
0 1
UARTCON
0 0
Character length selection bit : 8 bits
Parity enable bit : Parity checking disabled
Stop bit length selection bit : 2 stop bits
P45/TXD P-channel output disable bit : CMOS output
Baud rate generator (Address : 1C16)
b7
b0
7
BRG
Set
f(XIN)
Transfer bit rate ✕ 16 ✕ m ✻
1
✻ when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to
“0,” a value of m is 1.
when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to
“1,” a value of m is 4.
Port P4 direction register (Address : 0916)
b7
b0
1
P4D
P42/INT0 : Output mode
Port P4 (Address : 0816)
b7
P4
b0
0
P42/INT0 : Set to “1” at starting to communicate.
Fig. 2.3.39 Setting of related registers at a transmitting side [Communication using UART]
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3807 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
Receiving side
Serial I/O1 status register (Address : 1916)
b7
b0
SIO1STS
Receive buffer full flag
Check a completion of receiving 1-byte data with this flag.
“1” : at completing to receive
“0” : at reading out a content of the Receive buffer register
Overrun error flag
“1” : when data are ready to be transferred to the
Receive shift register in the state of storing data
into the Receive buffer register.
Parity error flag
“1” : when parity error occurs at enabled parity.
Framing error flag
“1” : when data can not be received at the timing of
setting a stop bit.
Summing error flag
“1” : when even one of the following errors occurs.
• Overrun error
• Parity error
• Framing error
Serial I/O1 control register (Address : 1A16)
b7
SIO1CON
b0
1 0 1 0
0 0 1
BRG count source selection bit : f(XIN)/4
Serial I/O1 synchronous clock selection bit : BRG/16
SRDY1 output enable bit : Not use SRDY1 out
Transmit enable bit : Transmit disabled
Receive enable bit : Receive enabled
Serial I/O1 mode selection bit : Asynchronous serial I/O(UART)
Serial I/O1 enable bit : Serial I/O1 enabled
UART control register (Address : 1B16)
b7
b0
1
UARTCON
0 0
Character length selection bit : 8 bits
Parity enable bit : Parity checking disabled
Stop bit length selection bit : 2 stop bits
Baud rate generator (Address : 1C16)
b7
b0
7
BRG
Set
f(XIN)
Transfer bit rate ✕ 16 ✕ m ✻
1
✻ when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to
“0,” a value of m is 1.
when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to
“1,” a value of m is 4.
Port P4 direction register (Address : 0916)
b7
P4D
b0
0
P42/INT0 : Input mode
Fig. 2.3.40 Setting of related registers at a receiving side [Communication using UART]
3807 GROUP USER’S MANUAL
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APPLICATION
2.3 Serial I/O
Control procedure : Figure 2.3.41 shows a control procedure at a transmitting side, and Figure 2.3.42
shows a control procedure at a receiving side.
 X : This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
RESET
Initialization
....
.
SIO1CON (Address : 1A16) 1001X0012
UARTCON(Address : 1B16) XXX01X002
BRG
(Address : 1C16) 8 —1
P4
(Address : 0816), bit2 0
P4D
(Address : 0916) XXXXX1XX2
• Set port P42 for a communication control.
N
Pass 10 ms?
• An interval of 10 ms is generated by a timer.
Y
P4 (Address : 0816), bit2
1
• Start of communication.
• Write a transmission data
The Transmit buffer empty flag is set to “0”
by this writing.
The first byte of a
transmission data
TB/RB (Address : 1816)
SIO1STS (Address : 1916), bit0?
0
• Check to be transferred data from the Transmit
buffer register to the Transmit shift register.
(Transmit buffer empty flag)
1
• Write a transmission data
The Transmit buffer empty flag is set to “0”
by this writing.
The second byte of
a transmission data
TB/RB (Address : 1816)
0
• Check to be transferred data from the Transmit
buffer register to the Transmit shift register.
(Transmit buffer empty flag)
0
• Check a shift completion of the Transmit shift register.
(Transmit shift register shift completion flag)
SIO1STS (Address : 1916), bit0?
1
SIO1STS (Address : 1916), bit2?
1
P4 (Address : 0816), bit2
0
• End of communication
Fig. 2.3.41 Control procedure at a transmitting side [Communication using UART]
2-60
3807 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
 X : This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
RESET
Initialization
.....
SIO1CON (Address : 1A16)
UARTCON(Address : 1B16)
(Address : 1C16)
BRG
(Address : 0916)
P4D
1010X0012
XXXX1X002
8 1
XXXXX0XX2
SIO1STS (Address : 1916), bit1?
0
• Check a completion of receiving.
(Receive buffer full flag)
1
• Receive the first 1 byte data
A Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from RB (Address : 1816)
SIO1STS (Address : 1916), bit6?
1
• Check an error flag.
0
• Check a completion of receiving.
(Receive buffer full flag)
0
SIO1STS (Address : 1916), bit1?
1
• Receive the second byte data
A Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from RB (Address : 1816)
SIO1STS (Address : 1916), bit6?
1
• Check an error flag.
Processing for error
0
1
P4 (Address : 0816), bit2?
0
SIO1CON (Address : 1A16)
SIO1CON (Address : 1A16)
0000X0012
1010X0012
• Countermeasure for a bit slippage
Fig. 2.3.42 Control procedure at a receiving side [Communication using UART]
3807 GROUP USER’S MANUAL
2-61
APPLICATION
2.4 Real time output port
2.4 Real time output port (RTP)
2.4.1 Memory map of real time output port
002A16
Real time port register (RTP)
002B16
Real time port control register 0 (RTPCON0)
002C16
Real time port control register 1 (RTPCON1)
002D16
Real time port control register 2 (RTPCON2)
002E16
Real time port control register 3 (RTPCON3)
002F16
Timer A Low-order (TAL)
003016
Timer A High-order (TAH)
003116
Timer B Low-order (TBL)
003216
Timer B High-order (TBH)
Fig. 2.4.1 Memory map of real time output port related registers
2.4.2 Related registers
Real time port register
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAA
A
AA
AA
A
AAAAAAAAAAAAA
A
AA
AA
A
AAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AA
AA
A
AA
AA
A
AAAAAAAAAAAAAA
AA
AA
A
Real time port register (RTP) [Address : 2A16]
B
0
1
2
3
4
5
6
7
●
●
●
Function
At reset
Sets the data to be output to the Real time port.
Makes it possible to write data into any of Real time port
registers 0 to 7 by specifying the Real time port data pointer
(R/W pointer) and writing data into this register.
Makes it possible to read any data of Real time port registers 0
to 7 by specifying the Real time port data pointer (R/W pointer)
and reading data from this register.
0
0
0
0
0
0
0
0
Fig. 2.4.2 Structure of Real time port register
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3807 GROUP USER’S MANUAL
R W
APPLICATION
2.4 Real time output port
Real time port control register 0
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAA
AA
AA
A
AAAAAAAA
AA
AA
A
AAAAAAA
AAAAAAAA
AA
AA
A
AAAAAAA
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAA
AA
AA
A
AAAAAAA
AAAAAAA
AAAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
A
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
Real time port control register 0 (RTPCON0) [Address : 2B16]
B
Name
Function
(Note 1)
Timer A, Timer B count source 0 : f(XIN)/2
0 selection bit
1 : f(XIN)/16
(Note 2)
Real time port • port allocation 0 : 4-4 division
(Corresponding ports to the Timer A :
selection bit
P82-P85
Corresponding ports to the Timer B :
P86, P87, P30, P31)
1
1 : 2-6 division
(Corresponding ports to the Timer A :
P82-P87
Corresponding ports to the Timer B :
P30, P31)
Timer A start trigger selection
bit
2
Timer A start trigger bit
3
Timer A count source stop bit
4
Timer B start trigger selection
bit
5
Timer B start trigger bit
6
Timer B count source stop bit
7
At reset
0
0
0 : Internal trigger
(occurs by writing “1” to bit 3.)
1 : External trigger
(occurs by inputting trigger to the INT4
pin.)
(Note 3)
0
0 : No operating by writing “0”
1 : Timer A starts counting by
writing “1”
(when bit 2 is set to “0”)
0
0 : Operating
(is set to “0” automatically at generating a start trigger.)
1 : Stop
0 : Internal trigger
(occurs by writing “1” to bit 6.)
1 : External trigger
(occurs by inputting trigger to the INT4
pin.)
(Note 3)
R W
(Note 4)
1
0
0 : No operating by writing “0”
1 : Timer B starts counting by
writing “1”
(when bit 5 is set to “0”)
0
0 : Operating
(is set to “0” automatically at generating a start trigger.)
1 : Stop
1
(Note 4)
Note 1: In low-speed mode f(XCIN)/2 is selected.
2: In low-speed mode f(XCIN)/16 is selected.
3: The rising edge or falling edge of the external trigger is switched by the INT4
interrupt edge selection bit (bit 4) of the interrupt edge selection register
(Address : 3A16.) (However, when the One-shot pulse generation mode is
selected, a rising/falling double edge trigger is generated in spite of the
contents of the INT4 interrupt edge selection bit.)
4: At a read operation, “0” is always read out.
Fig. 2.4.3 Structure of Real time port control register 0
3807 GROUP USER’S MANUAL
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APPLICATION
2.4 Real time output port
Real time port control register 1
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
AAAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAA
AA
AA
A
AAAAAAA
AAAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAA
AAAAAAAA
AA
AA
A
A
AAAAAAA
AAAAAAA
AA
AA
A
Real time port control register 1 (RTPCON1) [Address : 2C16]
B
Name
Timer A operating mode
0 selection bits
1
2
3
4
5
6
7
Function
0 0 : 8-repeated load mode
0 1 : 6-repeated load mode
1 0 : 5-repeated load mode
1 1 : One-shot pulse generation mode
Real time port data pointer A
0 : R/W pointer
switch bit
(Note 1) 1 : Output pointer
0 : Interrupts occur when a Real
Timer A interrupt mode
time port output pointer value
selection bit
becomes “0002.”
1 : Interrupt request occurs in
spite of a Real time port
output pointer value.
Real time port data pointer A b6 b5 b4
0 0 0 : Real time port register 0
0 0 1 : Real time port register 1
0 1 0 : Real time port register 2
0 1 1 : Real time port register 3
1 0 0 : Real time port register 4
1 0 1 : Real time port register 5
1 1 0 : Real time port register 6
(Note 2) 1 1 1 : Real time port register 7
Timer A write pointer
At reset
R W
b1 b0
0 : Specify the Timer A0 latch
1 : Specify the Timer A1 latch
0
0
0
0
1
1
1
1
Note 1: Use LDM or STA instruction for specifying the Real time port data pointer A
when this bit is switched. When this bit is read, “1” is always read out.
2: When these bits are read, an output pointer is read out.
Fig. 2.4.4 Structure of Real time port control register 1
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3807 GROUP USER’S MANUAL
APPLICATION
2.4 Real time output port
Real time port control register 2
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
AAAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAA
AA
AA
A
AAAAAAA
AAAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAA
AAAAAAAA
AA
AA
A
A
AAAAAAA
AAAAAAA
AA
AA
A
Real time port control register 2 (RTPCON2) [Address : 2D16]
B
Name
Timer B operating mode
0 selection bits
1
2
3
4
5
6
7
Function
0 0 : 8-repeated load mode
0 1 : 6-repeated load mode
1 0 : 5-repeated load mode
1 1 : One-shot pulse generation mode
Real time port data pointer B
0 : R/W pointer
switch bit
(Note 1) 1 : Output pointer
0 : Interrupts occur when a Real
Timer B interrupt mode
time port output pointer value
selection bit
becomes “0002.”
1 : Interrupt request occurs in
spite of a Real time port
output pointer value.
Real time port data pointer B b6 b5 b4
0 0 0 : Real time port register 0
0 0 1 : Real time port register 1
0 1 0 : Real time port register 2
0 1 1 : Real time port register 3
1 0 0 : Real time port register 4
1 0 1 : Real time port register 5
1 1 0 : Real time port register 6
(Note 2) 1 1 1 : Real time port register 7
Timer B write pointer
At reset
R W
b1 b0
0 : Specify the Timer B0 latch
1 : Specify the Timer B1 latch
0
0
0
0
1
1
1
1
Note 1: Use LDM or STA instruction for specifying the Real time port data pointer B
when this bit is switched. When this bit is read, “1” is always read out.
2: When these bits are read, an output pointer is read out.
Fig. 2.4.5 Structure of Real time port control register 2
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APPLICATION
2.4 Real time output port
Real time port control register 3
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
Real time port control register 3 (RTPCON3) [Address : 2E16]
B
Name
Function
Real time port output selection 0 : I/O port
0 bit (P82)
1 : Real time output port
Real time port output selection
1 bit (P83)
Real time port output selection
2 bit (P84)
At reset
0
0
0
Real time port output selection
0
Real time port output selection
0
3 bit (P85)
4 bit (P86)
Real time port output selection
5 bit (P87)
Real time port output selection
6 bit (P30)
Real time port output selection
7 bit (P31)
R W
0
0
0
Fig. 2.4.6 Structure of Real time port control register 3
Timer A Low-order, Timer A High-order, Timer B Low-order, Timer B High-order
b7 b6 b5 b4 b3 b2 b1 b0
Timer A Low-order (TAL), Timer A High-order (TAH) [Address : 2F16 , 3016]
Timer B Low-order (TBL), Timer B High-order (TBH) [Address : 3116 , 3216]
AAAAAAAAAAAAA
A
AA
AA
A
AAAAAAAAAAAAA
A
AA
AA
A
AAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AA
AA
A
AA
AA
A
AAAAAAAAAAAAAA
AA
AA
A
B
0
1
2
3
4
5
6
7
Function
●
●
●
Sets the real time output cycle.
Writing is performed in the order of low-order and high-order.
There are 2 reload latches. When the high-order side is written,
the next latch is automatically specified. The latch to be written
first can be specified by the Timer A or B write pointer (bit 7
of address 2C16 or 2D16).
Reading is performed in the order of high-order and low-order.
At a read operation, the value being counted is read out.
At reset
1
1
1
1
1
1
1
1
Fig. 2.4.7 Structure of Timer A Low-order, Timer A High-order, Timer B Low-order, Timer B High-order
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R W
APPLICATION
2.4 Real time output port
2.4.3 Real time output port application examples
Control of stepping motor
Outline : The rotation of the stepping motor is controlled by using Real time output ports.
Figure 2.4.8 shows a connection diagram.
P82/RTP0
P83/RTP1
P84/RTP2
P85/RTP3
Motor 1
P86/RTP4
P87/RTP5
P30/RTP6
P31/RTP7
Motor 2
3807 group
Fig. 2.4.8 Connection diagram
Specifications : • Each of two motors is controlled by using four Real time output ports.
• Clock f(X IN) = 8 MHz
• The same data table is used for acceleration and deceleration.
(20 steps, 500 pps max.)
• The value of the Timer A and B are updated by each interrupt processing routine.
• When the Timer A and/or B stops, the “L” level is output.
Figure 2.4.9 shows the operation patterns of the motor to be controlled in this application example.
The Timer A and the Timer B can control the motor independently with different operation patterns.
Pattern 1
Pattern 2
Pattern 3
200 steps at a constant
motor speed
Forward
rotation
240
20
220
260
410
430 450
Step
Reverse
rotation
150 steps at a constant
motor speed
Speed
Fig. 2.4.9 Operation patterns of motor
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APPLICATION
2.4 Real time output port
The motor is accelerated and decelerated by updating the timer value in the Timer interrupt processing
routine. Figure 2.4.10 shows an example of timer table for acceleration and deceleration. A table
common to both Timer A and Timer B is used in this application example.
As shown in the following figure, the motor speed is controlled by setting a value in the low-order side
of the table first at acceleration and by setting a value the high-order side of the table first at deceleration.
At a constant motor speed, the motor operation is continued with the last timer value of acceleration.
Setting example for acceleration
Timer value set in
Timer table (Speed)
F42316
A2C216
485616
28B016
1AC116
12F616
0E4116
0B4A16
094116
07CF16
06C216
05F916
056116
04EB16
049B16
045216
042116
040016
03EE16
03E716
( 8pps)
( 12pps)
( 27pps)
( 48pps)
( 73pps)
(103pps)
(137pps)
(173pps)
(211pps)
(250pps)
(289pps)
(327pps)
(363pps)
(397pps)
(427pps)
(452pps)
(473pps)
(488pps)
(497pps)
(500pps)
Setting example for deceleration
Setting of Timer A for
changing speed
Setting of Timer A for
changing speed
Timer A Low-order (Address:2F16)
TAL
2316
Timer A Low-order (Address:2F16)
TAL
Timer A High-order (Address:3016)
TAH
F416
E716
Timer A High-order (Address:3016)
TAH
0316
500pps
8pps
Timer A Low-order (Address:2F16)
TAL
C216
Timer A Low-order (Address:2F16)
TAL
Timer A High-order (Address:3016)
TAH
A216
EE16
Timer A High-order (Address:3016)
TAH
0316
12pps
497pps
Timer A Low-order (Address:2F16)
TAL
5616
Timer A Low-order (Address:2F16)
TAL
Timer A High-order (Address:3016)
TAH
4816
0016
Timer A High-order (Address:3016)
TAH
27pps
Fig. 2.4.10 Example of timer table for acceleration and deceleration
2-68
3807 GROUP USER’S MANUAL
0416
488pps
APPLICATION
2.4 Real time output port
Figure 2.4.11 shows an example of operation pattern table to operate the motor by the operation
patterns shown in Figure 2.4.9. The total number of operation patterns, the direction of motor rotation
and number of steps at a constant motor speed are set in this table.
The motor can be rotated by an arbitrary distance by changing this number of steps. (In this application
example, up to 255 steps can be set.)
An operation pattern table is set for each of the Timer A and the Timer B.
Total number of operation patterns
Forward rotation
200 steps at a constant motor speed
Reverse rotation
150 steps at a constant motor speed
Forward rotation
100 steps at a constant motor speed
Reverse rotation
250 steps at a constant motor speed
0416
0016
C816
FF16
9616
0016
6416
FF16
FA16
Operation pattern 1
Operation pattern 2
Operation pattern 3
Operation pattern 4
Note : “0016” is defined as a forward rotation in this example.
“FF16” is defined as a reverse rotation in this example.
Fig. 2.4.11 Example of operation pattern table
Figure 2.4.12 shows an example of output data table. Output data is selected in the 4 types of tables
shown in Figure 2.4.12 according to the information on forward rotation and reverse rotation referenced
in the operation pattern table shown in Figure 2.4.11, and then set in Real time port registers 0 to 7.
For example, in case the Timer B continues to control the motor in the forward direction when the data
of operation pattern 2 is set after the Timer A has output operation pattern 1, the data of table 3 is
set in Real time port registers 0 to 7.
Table 1
Table 2
Table 3
Table 4
RTP7–RTP4 : Forward rotation RTP7–RTP4 : Reverse rotation RTP7–RTP4 : Forward rotation RTP7–RTP4 : Reverse rotation
RTP3–RTP0 : Forward rotation RTP3–RTP0 : Forward rotation RTP3–RTP0 : Reverse rotation RTP3–RTP0 : Reverse rotation
b7
Real time port register 7
Real time port register 6
Real time port register 5
Real time port register 4
Real time port register 3
Real time port register 2
Real time port register 1
Real time port register 0
b0
b7
b0
b7
b0
b7
b0
00 01 00 0 1
10 01 00 0 1
00011001
1 001 1 00 1
b7
b7
b7
b7
b0
b0
b0
b0
00 11 00 11
100000 11
00111000
1 0001 000
b7
b7
b7
b7
b0
b0
b0
b0
00 10 0010
11000 010
0010110 0
11 00 1 100
b7
b7
b7
b7
b0
b0
b0
b0
0110 0110
0 1000 110
0 1100 10 0
0 100 01 00
b7
b7
b7
b7
b0
b0
b0
b0
01000100
0 1100 100
0 1 00 0 11 0
01 10 01 10
b7
b7
b7
b7
b0
b0
b0
b0
1 1001 100
00101 100
11 000 01 0
00 10 0 0 10
b7
b7
b7
b7
b0
b0
b0
b0
10 0 01 0 0 0
00111000
10 000 01 1
0011 0 0 11
b7
b7
b7
b7
b0
10011001
b0
0 0 01 10 0 1
b0
10010001
b0
0 001 0 0 01
Fig. 2.4.12 Example of output data table
3807 GROUP USER’S MANUAL
2-69
APPLICATION
2.4 Real time output port
Figure 2.4.13 shows the waveforms which are output from RTP 0 to RTP7 as a result that the Timer
A and the Timer B are operated by using the data of Figure 2.4.10 to Figure 2.4.12. This timing chart
is for the case where the Timer A controls operation pattern 1 and the Timer B controls operation
pattern 3.
Acceleration(20 steps)
A constant motor speed
(200 steps)
Deceleration(20 steps)
RTP0
RTP1
RTP2
RTP3
Acceleration(20 steps)
A constant motor speed
(100 steps)
RTP4
RTP5
RTP6
RTP7
Fig. 2.4.13 Timing of Real time output
2-70
3807 GROUP USER’S MANUAL
Deceleration(20 steps)
APPLICATION
2.4 Real time output port
Figure 2.4.14 shows the setting method and output timing for the Timer A. The same setting method
is used even for the Timer B. Before the count of the Timer A is started, initial values (t1, t2) are set
in the Timer A1 latch and the Timer A0 latch. After the count of the Timer A is started, the timer value
(t3, ...) is updated in the Timer A interrupt processing routine.
The next latch is automatically specified each time a value is set in the timer, so it is not necessary
to specify a write latch in bit 7 of RTPCON1 when the timer value is updated.
In this application example, the real time output port is switched over to the programmable I/O port
after termination of the last output because the “L” level is output from RTP 0 to RTP 7 when the timer
stops as a matter of specification. However, when the count of the Timer A is stopped and the real
time output port is switched over to the programmable I/O port after termination of the last output, the
next RTP data is output in a short period from an underflow of the Timer A till a count stop of the
Timer A. To avoid outputting the next RTP data in the short period, the count of the Timer A is stopped
at a start of the last output (though the last output data is output) and the last output period is counted
by using different timers (Timer X for the Timer A and timer Y for the Timer B in this case). After that
counting, when the Timer X underflows, the real time output port is switched over to the programmable
I/O port and the “L” level is output.
To continue to output the last output data after the timer stops, just stop the count of the Timer A after
termination of the last output.
Figure 2.4.14 shows the setting method and output timing and Figure 2.4.15 to Figure 2.4.18 show
the control procedures for related registers.
A constant motor speed
(200 steps)
Acceleration
(20 steps)
RTP0–RTP3
Deceleration
(20 steps)
7
6
4
3
4
3
1
6
5
3
2
3
2
0
t20 t20
t20 t20
t2
t20 t20 t20
t20 t19 t18
0
(Note 1)
(Note 3)
Output pointer value
7
7
(Note 2)
Timer A count source
stop bit
(Note 4)
Timer A count value
(Note 4)
t1
t2
Timer A interrupt request
Timer A setting value
t3
t4
A
B
A : Timer A count Stop, Timer X count Start
B : Timer X count Stop, RTP output Port output
Use the same setting method for RTP4–RTP7(Timer B).
Note 1:
2:
3:
4:
Numbers 0 to 7 indicate Real time port registers 0 to 7.
The output pointer value (bits 6 to 4 of real time port control register 1) is decreased by 1 at each underflow of the
Timer A. Thus, the current output pointer value which is read out indicates the next Real time port register to be
output.
The “L” level is output after the timer stops. Thus, the last output is executed by creating time by software (Timer
X) after the stop of the timer and switching over the real time output port to the programmable I/O port. (For the
reason that if the Timer A is stopped during or after an interrupt caused at the termination of the last output, the
next data (data of Real time port register 7) is output in a short period from the underflow of the Timer A to the
count stop of the Timer A.) To continue to output the last output data after the timer stops, just stop the count of
the timer after termination of the last output.
Set the timer values t1 and t2 before an RTP output.
Fig. 2.4.14 Setting method and output timing
3807 GROUP USER’S MANUAL
2-71
APPLICATION
2.4 Real time output port
Real time port register (Address : 2A16)
b7
b0
RTP
Sets the data for controlling motor 1.
(This data is output at each underflow of the Timer A.)
Sets the data for controlling motor 2.
(This data is output at each underflow of the Timer B.)
Real time port control register 0 (Address : 2B16)
b7
RTPCON0
b0
1 0 0 1 0 0 0 1
Timer A, Timer B count source selection bit : f(XIN)/16
Real time port•port allocation selection bit : 4-4 division
Timer A start trigger selection bit : Internal trigger
Timer A start trigger bit : Timer A is started by writing “1”
Timer A count source stop bit : Timer A is stopped by writing “1”
Timer B start trigger selection bit : Internal trigger
Timer B start trigger bit : Timer B is started by writing “1”
Timer B count source stop bit : Timer B is stopped by writing “1”
Real time port control register 1 (Address : 2C16)
b7
RTPCON1
b0
1 1 1 1 1 0 0 0
Timer A operating mode selection bits : 8-repeated load mode
Real time port data pointer A switch bit
“0”: For reading the contents of the Real time port register
or setting a value in the Real time port register
“1”: For specifying the output pointer.
Timer A interrupt mode selection bit : Causes interrupt request
at Timer A underflow
Real time port data pointer A : Specify Real time port register 7
Timer A write pointer : Specify the Timer A1 latch
Real time port control register 2 (Address : 2D16)
b7
RTPCON2
b0
1 1 1 1 1 0 0 0
Timer B operating mode selection bits : 8-repeated load mode
Real time port data pointer B switch bit
“0”: For reading the contents of the Real time port register
or setting a value in the Real time port register
“1”: For specifying the output pointer.
Timer B interrupt mode selection bit : Causes interrupt request
at Timer B underflow
Real time port data pointer B : Specify Real time port register 7
Timer B write pointer : Specify the Timer B1 latch
Fig. 2.4.15 Setting of related registers (1)
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3807 GROUP USER’S MANUAL
APPLICATION
2.4 Real time output port
Real time port control register 3 (Address : 2E16)
b7
b0
RTPCON3
Real time port output selection bit (P82/RTP0)
Real time port output selection bit (P83/RTP1)
Real time port output selection bit (P84/RTP2)
Real time port output selection bit (P85/RTP3)
Real time port output selection bit (P86/RTP4)
Real time port output selection bit (P87/RTP5)
Real time port output selection bit (P30/RTP6)
“0” : I/O port
(At stopping Timer A)
“1” : Real time output port
(At operating Timer A)
“0” : I/O port
(At stopping Timer B)
“1” : Real time output port
(At operating Timer B)
Real time port output selection bit (P31/RTP7)
Timer A High-order (Address : 3016)
b7
b0
TAH
Timer A Low-order (Address : 2F16)
b7
b0
A value is updated at each underflow of the Timer A.
(At acceleration or deceleration)
TAL
Timer B High-order (Address : 3216)
b7
b0
TBH
Timer B Low-order (Address : 3116)
b7
b0
A value is updated at each underflow of the Timer B.
(At acceleration or deceleration)
TBL
Timer X mode register (Address : 2716)
b7
TXM
0 1
b0
0 0 0 0
Timer X operating mode bits : Timer•Event counter mode
Timer X write control bit : write to a latch and a timer at the
same time
Timer X count source selection bits : f(XIN)/16
Timer Y mode register (Address : 2816)
b7
TYM
0 1
b0
0 0 0 0
Timer Y operating mode bits : Timer•Event counter mode
Timer Y write control bit : write to a latch and a timer at the
same time
Timer Y count source selection bits : f(XIN)/16
Fig. 2.4.16 Setting of related registers (2)
3807 GROUP USER’S MANUAL
2-73
APPLICATION
2.4 Real time output port
Timer XY control register (Address : 1416)
b7
b0
1 1
TXYCON
Timer X stop control bit : Stop counting (Set “0” at starting counting)
Timer Y stop control bit : Stop counting (Set “0” at starting counting)
Timer X High-order (Address : 2116)
b7
TXH
b0
F416
Timer X Low-order (Address : 2016)
b7
b0
Set a value which need for counting the last
output period (62500-1:8pps) of RTP0–RTP3.
2316
TXL
Timer Y High-order (Address : 2316)
b7
TYH
b0
F416
Timer Y Low-order (Address : 2216)
b7
b0
Set a value which need for counting the last
output period (62500-1:8pps) of RTP4–RTP7.
2316
TYL
Interrupt control register 1 (Address : 3E16)
b7
b0
0 0
ICON1
Timer X interrupt enable bit : Interrupt disabled
Timer Y interrupt enable bit : Interrupt disabled
Interrupt request register 1 (Address : 3C16)
b7
IREQ1
b0
0 0
Timer X interrupt request bit
(Judge a termination of the last output period
of RTP0–RTP3)
Timer Y interrupt request bit
(Judge a termination of the last output period
of RTP4–RTP7)
Fig. 2.4.17 Setting of related registers (3)
2-74
3807 GROUP USER’S MANUAL
APPLICATION
2.4 Real time output port
Interrupt control register 2 (Address : 3F16)
b7
b0
1 1
ICON2
Timer A interrupt enable bit : Interrupt enabled
Timer B interrupt enable bit : Interrupt enabled
Interrupt request register 2 (Address : 3D16)
b7
b0
0 0
IREQ2
Timer A interrupt request bit
Timer B interrupt request bit
Port P3 (Address : 0616)
b7
b0
0 0
P3
P30/RTP6, P31/RTP7 :
Output “L” level at stopping Timer B
Port P3 direction register (Address : 0716)
b7
b0
1 1
P3D
P30/RTP6, P31/RTP7 : Output mode
Port P8 (Address : 1016)
b7
P8
b0
0 0 0 0 0 0
P82/RTP0–P85/RTP3 :
Output “L” level at stopping Timer A
P86/RTP4, P87/RTP5 :
Output “L” level at stopping Timer B
Port P8 direction register (Address : 1116)
b7
P8D
b0
1 1 1 1 1 1
P82/RTP0–P87/RTP5 : Output mode
Fig. 2.4.18 Setting of related registers (4)
3807 GROUP USER’S MANUAL
2-75
APPLICATION
2.4 Real time output port
Control procedure :
Figure 2.4.19–Figure 2.4.22 show control procedures.
●
RESET
X : This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
Initialization
SEI
....
RTPCON0 (Address : 2B16)
RTPCON1 (Address : 2C16)
9116
F816
RTPCON2 (Address : 2D16)
F816
●
RTPCON3 (Address : 2E16)
0016
●
....
TXM
TYM
P3
P3D
P8
P8D
(Address : 2716)
(Address : 2816)
(Address : 0616)
(Address : 0716)
(Address : 1016)
(Address : 1116)
●
●
....
01XX00002
01XX00002
XXXXXX002
XXXXXX112
000000XX2
111111XX2
●
●
●
●
RTP (Address : 2A16)
N
Initial value
Timer A and Timer B counts are stopped.
Timer A : Selecting “8-repeated load mode”, “setting R/W pointer
to Real time port register 7”, and “specification of Timer
A1 latch.”
Timer B : Selecting “8-repeated load mode”, “setting R/W pointer
to Real time port register 7”, and “specification of Timer
B1 latch.”
P82/RTP0–P87/RTP5, P30/RTP6, P31/RTP7 : I/O port
Timer X : Timer·Event counter mode
Timer Y : Timer·Event counter mode
Initialization for ports
(“L” is output at stopping a stepping motor)
Each value of the table is set to the Real time port
registers 0–7.
(A value of R/W pointer is automatically decreased by 1.)
A setting of Real time port
registers 0–7 is completed ?
Y
TAL
TAH
TAL
TAH
TBL
TBH
TBL
TBH
(Address : 2F16)
(Address : 3016)
(Address : 2F16)
(Address : 3016)
(Address : 3116)
(Address : 3216)
(Address : 3116)
(Address : 3216)
ICON2
IREQ2
ICON2
IREQ2
(Address : 3F16) , bit4
(Address : 3D16), bit4
(Address : 3F16) , bit5
(Address : 3D16), bit5
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
RTPCON1 (Address : 2C16)
RTPCON2 (Address : 2D16)
RTPCON0 (Address : 2B16), bit3
RTPCON0 (Address : 2B16), bit6
RTPCON3 (Address : 2E16)
1
0
1
0
●
Set an initial value to the Timer A1 latch.
●
Set an initial value to the Timer A0 latch.
●
Set an initial value to the Timer B1 latch.
●
●
●
●
●
FC16
FC16
1
1
FF16
●
●
●
●
●
Set an initial value to the Timer B0 latch.
The next latch is specified
automatically.
Timer A interrupt : Interrupt enabled
The Timer A interrupt request bit is set to “0”.
Timer B interrupt : Interrupt enabled
The Timer B interrupt request bit is set to “0”.
Timer A : An output pointer is set to the Real time port register 7.
Timer B : An output pointer is set to the Real time port register 7.
Timer A : Start counting
Timer B : Start counting
The port output is switched to the RTP output.
A
Fig. 2.4.19 Control procedure (1)
2-76
The next latch is specified
automatically.
3807 GROUP USER’S MANUAL
APPLICATION
2.4 Real time output port
A
Y
All patterns for the Real time port
registers 0–3 are completed to output?
N
Timer A is stopped completely?
Y
Processing for updating
data of RTP0–RTP3 output
N
Y
All patterns for the Real time port
registers 4–7 are completed to output?
N
Timer B is stopped completely?
N
Y
Processing for updating
data of RTP4–RTP7 output
Fig. 2.4.20 Control procedure (2)
3807 GROUP USER’S MANUAL
2-77
APPLICATION
2.4 Real time output port
Note : Execute the same processing for RTP4–RTP7
(Timer B.)
Processing for updating data of RTP0–RTP3 output
RTPCON0
TXL
TXH
TXYCON
(Address : 2B16), bit4
(Address : 2016)
(Address : 2116)
(Address : 1416), bit0
1
2316
F416
0
●
●
●
Timer X count is started.
●
Is the last output completed?
0
IREQ1 (Address : 3C16), bit4
Timer A count is stopped.
Set the last output period
1
1
TXYCON (Address : 1416), bit0
(A)
RTPCON3 (Address : 2E16)
(A)
(A)&F016
(A)
RTPCON3 (Address : 2E16)
•Store the last output data to RAM
(A)
RTPCON1 (Address : 2C16)
CLC
(A)
(A)+1016
(A)
(A)&7816
(A)
RTPCON1 (Address : 2C16)
RTP (Address : 2A16)
(A)
(A)&F016
(A)
●
●
●
●
●
The last data
(A)
Timer X count is stopped.
RTP0–RTP3 output is switched to a port output.
A RTP data pointer value is set back the previous
value ( the last output pointer.)
Read out the last output data.
4 low-order bits of the last output data are stored to
RAM.
N
All patterns are completed?
Y
●
Data for the Real time port register is updated.
RTPCON1(Address : 2C16)
....
TAL
TAH
TAL
TAH
TBL
TBH
TBL
TBH
(Address : 2F16)
(Address : 3016)
(Address : 2F16)
(Address : 3016)
(Address : 3116)
(Address : 3216)
(Address : 3116)
(Address : 3216)
Output pointer
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
....
IREQ2 (Address : 3D16), bit4
0
●
●
Judges whether real time port registers 0 to 3 output
the data for forward rotation or the data for reverse
rotation next in order to determine which output data
table is to be used.
Sets the output pointer so that the output may be
started with the last output data of the previous pattern.
Set an initial value to the Timer A1 latch.
The next latch is specified
automatically.
●
Set an initial value to the Timer A0 latch.
●
Set an initial value to the Timer B1 latch.
●
Set an initial value to the Timer B0 latch
●
Set the Timer A interrupt request bit to “0.”
The next latch is specified
automatically.
....
RTPCON0(Address : 2B16), bit3
1
(A)
RTPCON3 (Address : 2E16)
(A)
(A) or 0F16
RTPCON3(Address : 2E16)
(A)
●
●
Timer A : Start counting
The port output is switched to the RTP output.
Set the all patterns
completion flag
RTS
Fig. 2.4.21 Control procedure (3)
2-78
3807 GROUP USER’S MANUAL
APPLICATION
2.4 Real time output port
Timer A interrupt processing
routine (Note)
Note : Execute the same processing for Timer B.
Y (A constant motor speed processing)
During a constant
motor speed?
N
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
Counter + 1
During accelerating?
Y
(An acceleration processing)
All number of constant
motor speed steps are
completed to output?
Counter + 1
N
N
Y
All number of acceleration steps
are completed to output?
N
Set the deceleration flag
(A deceleration processing is
executed next time)
(A deceleration processing)
Y
A number of steps
(number of deceleration
steps – 1) is completed
to output?
Y
(Stop completely)
N
Set the constant motor speed flag
Counter
0016
(A constant motor speed processing is
executed next time)
Counter
0016
Counter + 1
Set the completion stop flag
Counter
0016
Set a value of a timer table
for deceleration in order
low-order to high-order of
Timer A.
RTI
Fig. 2.4.22 Control procedure (4)
3807 GROUP USER’S MANUAL
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APPLICATION
2.5 A-D converter
2.5 A-D converter
2.5.1 Memory map of A-D conversion
003416
A-D control register (ADCON)
003516
A-D conversion register (AD)
003D16
Interrupt request register 2 (IREQ2)
003F16
Interrupt control register 2 (ICON2)
Fig. 2.5.1 Memory map of A-D conversion related registers
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3807 GROUP USER’S MANUAL
APPLICATION
2.5 A-D converter
2.5.2 Related registers
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register (ADCON) [Address : 3416]
B
Name
Function
b3 b2 b1 b0
0 Analog input pin selection bits 0 0 0 0 : P73/SRDY2/ADT/AN0
0 0 0 1 : P74/AN1
0 0 1 0 : P75/AN2
0 0 1 1 : P76/AN3
0 1 0 0 : P77/AN4
0 1 0 1 : P60/AN5
0 1 1 0 : P61/AN6
0 1 1 1 : P62/AN7
1 0 0 0 : P63/CMPIN/AN8
1 0 0 1 : P64/CMPREF/AN9
1 0 1 0 : P65/DAVREF/AN10
1 0 1 1 : P80/DA3/AN11
1 1 0 0 : P81/DA4/AN12
1
2
3
4 AD conversion completion bit
5 ADVREF input switch bit
When A-D trigger is invalid
0 : Start conversion by writing to “0”
1 : Conversion completed
When A-D trigger is valid
0 : Conversion in progress
1 : Conversion completed
0 : Connect only at A-D conversion
1 : Connect all time
At reset
R W
0
0
0
0
1
0
6 AD external trigger valid bit
0 : A-D external tirgger invalid
1 : A-D external tirgger valid
0
7 Interrupt source selection bit
0 : At conversion completed
1 : At ADT falling input
0
Fig. 2.5.2 Structure of A-D control register
A-D conversion register
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (AD) [Address : 3516]
B
Function
0 The read-only register which A-D conversion results are stored.
1
2
3
4
5
6
7
At reset
?
?
?
?
?
?
?
?
R W
✕
✕
✕
✕
✕
✕
✕
✕
Fig. 2.5.3 Structure of A-D conversion register
3807 GROUP USER’S MANUAL
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APPLICATION
2.5 A-D converter
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 2 (IREQ2) [Address : 3D16]
B
Name
CNTR
0
interrupt
request bit
0
Function
At reset
R W
0 : No interrupt request
1 : Interrupt request
0
✻
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
2 Serial I/O2 interrupt request
bit
1 : Interrupt request
3 Timer 1/INT2 interrupt request 0 : No interrupt request
bit
1 : Interrupt request
0 : No interrupt request
4 Timer A interrupt request bit
1 : Interrupt request
0
✻
0
✻
0
✻
0
✻
5 Timer B interrupt request bit
0
✻
0
✻
0
✕
1 CNTR1 interrupt request bit
0 : No interrupt request
1 : Interrupt request
6 ADT/AD conversion interrupt 0 : No interrupt request
request bit
1 : Interrupt request
7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0.”
✻ “0” is set by software, but not “1.”
Fig. 2.5.4 Structure of Interrupt request register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address : 3F16]
Name
B
0 CNTR0 interrupt enable bit
1 CNTR1 interrupt enable bit
2 Serial I/O2 interrupt enable
bit
3 Timer 1/INT2 interrupt enable
bit
4 Timer A interrupt enable bit
Function
At reset
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
R W
0
0
0
AA
AAAAAA
AAAAAAA
AA
AA
AA
AAAAAAAA
AAAAAAA
AA
AA
AA
5 Timer B interrupt enable bit
6 ADT/AD conversion interrupt
enable bit
7 Fix this bit to “0.”
Fig. 2.5.5 Structure of Interrupt control register 2
2-82
3807 GROUP USER’S MANUAL
0
0
0
APPLICATION
2.5 A-D converter
2.5.3 A-D conversion application example
Conversion of Analog input voltage
Outline : The analog input voltage input from the sensor is converted into digital values.
Refer to the following examples for using an internal trigger or an external trigger.
(1) Read for analog signal using an internal trigger
Figure 2.5.6 shows a connection diagram, and Figure 2.5.7 shows a setting of related registers.
Reference voltage
ADVREF
Sensor
P74/AN1
AVSS
VSS
3807 group
Fig. 2.5.6 Connection diagram [Read for analog signal using an internal trigger]
Specifications : • The analog input voltage input from the sensor is converted into digital values.
(Note)
• The P7 4/AN 1 pin is used as an analog input pin.
• A-D conversion start with an internal trigger (by setting bit 4 of A-D control
register to “0” ).
Note : Example
When a reference voltage, 5.12 V is input to the ADV REF pin and a voltage,
4 V to the P74 /AN1 pin, an input voltage is converted to a following value.
(256 / 5.12 V) ✕ 4 V = 200 (C8 16)
AA
AA
A
AA
AAAAAA
A
A-D control register (Address : 3416)
ADCON
0
1 0 0 0 1
Analog input pin selection bits : Select the P74/AN1 pin
AD conversion completion bit : Conversion completed
(set to “0” at starting)
AD external trigger valid bit : Invalid (internal trigger)
A-D conversion register (Address : 3516)
AD
(read-only)
Store a result of A-D conversion (Note)
Note: Read out a result of A-D conversion after bit 4 of the A-D control register (ADCON) is set to “1.”
Port P7 direction register (Address : 0F16)
P7D
0
P74/AN1 pin : Input mode
Fig. 2.5.7 Setting of related registers [Read for analog signal using an internal trigger]
3807 GROUP USER’S MANUAL
2-83
APPLICATION
2.5 A-D converter
Control procedure : By setting the related registers as shown in Figure 2.5.8, the analog input
voltage input from the sensor are converted into digital values.
●X : This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
• Select the P74/AN1 pin as an analog input pin.
ADCON (Address : 3416)
X0X100012
P7D
(Address : 0F16)
XXX0XXXX2
ADCON (Address : 3416), bit4
0
ADCON (Address : 3416), bit4?
External trigger is invalid.
• P74/AN1 pin:Input mode
• Start A-D conversion.
0
• Check the completion of A-D conversion.
1
Read out AD (Address : 3516)
• Read out the conversion result.
Fig. 2.5.8 Control procedure [Read for analog signal using an internal trigger]
2-84
3807 GROUP USER’S MANUAL
APPLICATION
2.5 A-D converter
(2) Read for analog signal using an external trigger
Figure 2.5.9 shows a connection diagram, and Figure 2.5.10 shows a setting of related registers.
Reference voltage
ADVREF
Sensor
P74/AN1
External trigger
P73/SRDY2/ADT/AN0
AVSS
VSS
3807 group
Fig. 2.5.9 Connection diagram [Read for analog signal using an external trigger]
Specifications : • The analog input voltage input from the sensor is converted into digital values.
(Note)
• The P7 4/AN 1 pin is used as an analog input pin.
• A-D _____
conversion start with an external trigger (by inputting a falling edge to the
P7 3/SRDY2 /ADT/AN0 pin ).
Note : Example
When a reference voltage, 5.12 V is input to the ADV REF pin and a voltage,
4 V to the P74 /AN1 pin, an input voltage is converted to a following value.
(256 / 5.12 V) ✕ 4 V = 200 (C8 16)
AA
AA
A
AA
AAAAAA
A
A-D control register (Address : 3416)
ADCON
1
1 0 0 0 1
Analog input pin selection bits : Select the P74/AN1 pin
AD conversion completion bit : Conversion completed
(Note 1)
AD external trigger valid bit :Valid
A-D conversion register (Address : 3516)
AD
(read-only)
Store a result of A-D conversion (Note 2)
Port P7 direction register (Address : 0F16)
P7D
0 0
P73/SRDY2/ADT/AN0 pin : Input mode
P74/AN1 pin : Input mode
Note 1: An external trigger becomes valid by setting this bit to “1.”
When bit 6 is set to “1” and bit 4 to “0” at the same time, A-D comversion may start at that time.
2: Read out a result of A-D conversion after bit 4 of the A-D control register (ADCON) is set to “1.”
Fig. 2.5.10 Setting of related registers [Read for analog signal using an external trigger]
3807 GROUP USER’S MANUAL
2-85
APPLICATION
2.5 A-D converter
Control procedure : By setting the related registers as shown in Figure 2.5.11, the analog input
voltage input from the sensor are converted into digital values.
●X : This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
~
~
ADCON (Address : 3416)
P7D
(Address : 0F16)
• Select the P74/AN1 pin as an analog input pin.
X1X100012
XXX00XXX2
ADCON (Address : 3416), bit4?
External trigger is valid.
• P73/SRDY2/ADT/AN0 pin : Input mode
1
• Check the start of A-D conversion.
0
ADCON (Address : 3416), bit4?
0
• Check the completion of A-D conversion.
1
Read out AD (Address : 3516)
• Read out the conversion result.
~
~
Fig. 2.5.11 Control procedure [Read for analog signal using an external trigger]
2-86
3807 GROUP USER’S MANUAL
APPLICATION
2.6 Reset
2.6 Reset
2.6.1 Connection example of reset IC
VCC
1
Power source
M62022L
5
Output
RESET
Delay capacity
4
GND
0.1
F
VSS
3
3807 group
Fig. 2.6.1 Example of Poweron reset circuit
Figure 2.6.2 shows the system example which switch to the RAM backup mode by detecting a drop of the
system power source voltage with the INT interrupt.
System power
source voltage
+5
VCC
+
7
VCC1
RESET
2
1
5
INT
3
V1 GND Cd
6
VCC2
4
RESET
INT
VSS
3807 group
M62009L, M62009P, M62009FP
Fig. 2.6.2 RAM back-up system
3807 GROUP USER’S MANUAL
2-87
APPLICATION
2.7 Application circuit example
2.7 Application circuit example
Refer to the following applicaion circuit examples using the 3807 group microcomputer.
• Hot water supply system application example ........................................................... Figure 2.7.1
• CD changer (car audio) application example ............................................................. Figure 2.7.2
• Hot water washing toilet seat applicaiton example ................................................... Figure 2.7.3
2-88
3807 GROUP USER’S MANUAL
3807 GROUP USER’S MANUAL
AN1
AN2
AN3
AN4
Water level sensor
Water temperature thermistor
Hot water supply thermistor
Hot water pour thermistor
For controlling
AN5
AN0
Mode setting
VR
P04
Flame sensor
Timer A (16-bit)
XIN
WDT
8MHZ
XOUT
RESET
P20
TXD
Timer 2 (8-bit)
Timer 3 (8-bit)
RXD
CNTR1
CNTR0
RTP1
AN6
RTP0
P11
P10
Timer 1 (8-bit)
(Event counter mode)
Timer Y (16-bit)
(Pulse period measurement mode)
Timer X (16-bit)
(Real time port output)
Timer B (16-bit)
(Real time port output)
P00–P02
P03
3
Igniter
E2PROM
3807 group
Hot water supply system application example
Driver
Reset IC
WDT
Flux sensor
Fan motor
Remote-controller 2
Remote-controller 1
Hot water supply
comparison valve
Electromagnetic valve 2
Electromagnetic valve 1
APPLICATION
2.7 Application circuit example
Fig. 2.7.1 Hot water supply system application example
2-89
2-90
Fig. 2.7.2 CD changer (car audio) application example
3807 GROUP USER’S MANUAL
Eject
Clock for middle-/high-speed mode
Clock for low-speed mode
Sensor from CD changer mechanism unit
Power source monitor
LAM controller
for cars
AD
AD
PORT
INT1
SI/O1
INT2
SI/O2
PORT
PORT
System controller
microcomputer
3807 group
Car audio CD changer application example
F_OK
••••
CD•DSP
CD changer mechanism unit
Eject/CD SELECT1–6
APPLICATION
2.7 Application circuit example
AN0
AN1
AN2
Nozzle position detection
Water temperature detection 1
Water temperature detection 2
3807 GROUP USER’S MANUAL
AN5
AN6
AN7
AN8
Toilet seat temperature detection
Room temperature detection
Power source voltage detection
Warm water flux detection
SW input
Remote-controller
AN4
Water temperature detection 4
TxD
RTP
RTP
Timer Y (16-bit)
Pulse output mode
Timer X (16-bit)
8 repeated load mode
resolution = 250 ns
Timer B (16-bit)
8 repeated load mode
resolution = 250 ns
Timer A (16-bit)
Timer 3 (8-bit)
phase control
Timer 2 (8-bit)
Timer 1 (8-bit)
8MHZ
XOUT
Runaway detection
WDTH (8-bit)
WDTL (8-bit)
Pulse period measurement mode
resolution = 250 ns
XIN
CNTR1
AN3
Water temperature detection 3
10
INT0
Commercial power source input
3807 group
Warm water washing toilet seat application example
4
4
Pump output
Deodorization contorl output
Hot air fan output
LED output
Electromagnetic valve control output
Buzzer output
Stepping motor
control 2
Stepping motor
control 1
Toilet seat heater output
Hot air heater output
Warm water heater output
APPLICATION
2.7 Application circuit example
Fig. 2.7.3 Hot water washing toilet seat applicaiton example
2-91
CHAPTER 3
APPENDIX
3.1 Electrical characteristics
3.2 Standard characteristics
3.3 Notes on use
3.4 Countermeasures against noise
3.5 List of registers
3.6 Mask ROM ordering method
3.7 Mark specification form
3.8 Package outline
3.9 Machine instructions
3.10 List of instruction codes
3.11 SFR memory map
3.12 Pin configuration
APPENDIX
3.1 Electrical characteristics
3.1 Electrical characteristics
3.1.1 Absolute maximum ratings
Table 3.1.1 Absolute maximum ratings
Parameter
Symbol
Conditions
VCC
Power source voltage
CMPVCC
Analog comparator power source voltage
VI
Input voltage
VI
Input voltage
RESET, XIN
VI
Input voltage
CNVSS (ROM version)
VI
Input voltage
CNVSS (PROM version)
P00–P07, P1 0–P17 , P20–P2 7,
P30–P37, P4 0–P47, P5 0–P57 ,
P60–P65, P7 0–P77, P8 0–P87 ,
ADVREF
Ratings
Unit
–0.3 to 7.0
V
–0.3 to 7.0
V
–0.3 to VCC +0.3
V
–0.3 to VCC +0.3
V
–0.3 to 7
V
–0.3 to 13
V
____________
All voltages are
based on VSS.
Output transistors
are cut off.
VI
In-phase input voltage
CMPIN, CMPREF
–0.3 to CMPVCC +0.3
V
VID
Differential input voltage
|CMPIN–CMPREF|
CMPVCC
V
VO
Output voltage
P00–P07, P1 0–P17 , P20–P2 7,
P30–P37, P4 0–P47, P5 0–P57 ,
P60–P62, P6 5, P70–P7 7,
P80–P87, XOUT
–0.3 to VCC +0.3
V
VO
Output voltage
CMP OUT
Pd
Power dissipation
Topr
Operating temperature
Tstg
Storage temperature
3-2
Ta = 25°C
3807 GROUP USER’S MANUAL
–0.3 to CMPVCC +0.3
V
500
mW
–20 to 85
°C
–40 to 125
°C
APPENDIX
3.1 Electrical characteristics
3.1.2 Recommended operating conditions
Table 3.1.2 Recommended operating conditions (1)
(Vcc = 2.7 to 5.5 V, Ta = – 20 to 85 °C, unless otherwise noted)
Symbol
Limits
Parameter
Unit
Min.
Typ.
Max.
2.7
5.0
5.5
V
4.0
5.0
5.5
V
VCC
Power source voltage
VSS
Power source voltage
ADVREF
A-D comparator reference voltage
2.0
VCC
V
DAVREF
D-A comparator reference voltage
2.7
VCC
V
CMPV CC
Analog comparator power source voltage
AV SS
Analog power source voltage
VIA
A-D comparator input voltage
AN 0—AN12
VIH
“H” input voltage
P0 0—P07, P10—P17, P3 0, P31,
P33—P37, P40—P47, P5 0—P57,
P60—P65, P70—P77, P80—P87
VIH
“H” input voltage (CMOS input level selected) P2 0—P27, P32
VIH
“H” input voltage (TTL input level selected)
f(XIN)
4.1MHz
f(XIN) = 8MHz
0
V
VCC
V
0
V
AVSS
VCC
V
0.8VCC
VCC
V
0.8VCC
VCC
V
P2 0—P27, P32 (Note)
2.0
VCC
V
0.8VCC
VCC
V
0
0.2VCC
V
______
VIH
“H” input voltage
RESET, XIN, CNVSS
VIL
“L” input voltage
P00—P07, P10—P17, P3 0, P31,
P33—P37, P40—P47, P5 0—P57,
P60—P65, P70—P77, P80—P87
VIL
“L” input voltage (CMOS input level selected) P2 0—P27, P32
0
0.2VCC
V
VIL
“L” input voltage (TTL input level selected)
P2 0—P27, P32 (Note)
0
0.8
V
VIL
“L” input voltage
RESET, CNVSS
0
0.2VCC
V
VIL
“L” input voltage
XIN
0
0.16VCC
V
______
Note: When Vcc is 4.0 to 5.5 V.
Table 3.1.3 Recommended operating conditions (2)
(Vcc = 2.7 to 5.5 V, Ta = – 20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
Typ.
Max.
Unit
∑IOH(peak)
“H” total peak output current (Note)
P00–P0 7, P10 –P17, P2 0–P27,
P30–P3 7, P80–P8 7
–80
mA
∑IOH(peak)
“H” total peak output current (Note)
P40–P4 7, P50 –P57, P6 0–P62, P6 5,
CMPOUT, P7 0–P77
–80
mA
∑IOL(peak)
“L” total peak output current (Note)
P00–P0 7, P10 –P17, P2 0–P23,
P30–P3 7, P80–P8 7
80
mA
∑IOL(peak)
“L” total peak output current (Note)
P24–P2 7
in single chip mode
80
mA
in memory expansion mode and
microprocessor mode
80
mA
∑IOL(peak)
“L” total peak output current (Note)
P40–P4 7, P50 –P57, P6 0–P62, P6 5,
CMPOUT, P7 0–P77
80
mA
∑IOH(avg)
“H” total average output current (Note)
P00–P0 7, P10 –P17, P2 0–P27,
P30–P3 7, P80–P8 7
–40
mA
∑IOH(avg)
“H” total average output current (Note)
P40–P4 7, P50 –P57, P6 0–P62, P6 5,
CMPOUT, P7 0–P77
–40
mA
∑IOL(avg)
“L” total average output current (Note)
P00–P0 7, P10 –P17, P2 0–P23,
P30–P3 7, P80–P8 7
40
mA
∑IOL(avg)
“L” total average output current (Note)
P24–P2 7
in single chip mode
40
mA
in memory expansion mode and
microprocessor mode
40
mA
P40–P4 7, P50 –P57, P6 0–P62, P6 5,
CMPOUT, P7 0–P77
40
mA
∑IOL(avg)
“L” total average output current (Note)
Note: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average
value measured over 100ms. The total peak current is the peak value of all the currents.
3807 GROUP USER’S MANUAL
3-3
APPENDIX
3.1 Electrical characteristics
Table 3.1.4 Recommended operating conditions (3)
(Vcc = 2.7 to 5.5 V, Ta = – 20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
Typ.
Max.
Unit
IOH(peak)
“H” peak output current (Note 1)
P00 –P07, P1 0–P17, P2 0–P27 ,
P30–P3 7, P4 0–P47, P5 0–P57,
P60–P6 2, P65 , CMPOUT, P7 0–P77,
P80–P8 7
–10
mA
IOL(peak)
“L” peak output current (Note 1)
P00 –P07, P1 0–P17, P2 0–P23 ,
P30–P3 7, P4 0–P47, P5 0–P57,
P60–P6 2, P65 , CMPOUT, P7 0–P77,
P80–P8 7
10
mA
IOL(peak)
“L” peak output current (Note 1)
P24–P27
in single chip mode
20
mA
in memory expansion mode and
microprocessor mode
10
mA
IOH(avg)
“H” average output current (Note 2)
P00 –P07, P1 0–P17, P2 0–P27 ,
P30–P3 7, P4 0–P47, P5 0–P57,
P60–P6 2, P65 , CMPOUT, P7 0–P77,
P80–P8 7
–5
mA
IOL(avg)
“L” average output current (Note 2)
P00 –P07, P1 0–P17, P2 0–P23 ,
P30–P3 7, P4 0–P47, P5 0–P57,
P60–P6 2, P65 , CMPOUT, P7 0–P77,
P80–P8 7
5
mA
IOL(avg)
“L” average output current (Note 2)
P24–P27
in single chip mode
15
mA
in memory expansion mode and
microprocessor mode
5
mA
Main clock input oscillation
frequency (Note 3)
High-speed mode
4.0V VCC 5.5V
8
MHz
High-speed mode
2.7V VCC 4.0V
3VCC–4
MHz
Middle-speed mode
4.0V VCC 5.5V
8
MHz
Middle-speed mode (Note 5)
2.7V VCC 4.0V
8
MHz
Middle-speed mode (Note 5)
2.7V VCC 4.0V
3VCC–4
MHz
50
kHz
f(XIN)
f(XCIN)
Sub-clock input oscillation frequency (Note 3, 4)
Note1:
2:
3:
4:
32.768
The peak output current is the peak current flowing in each port.
The average output current IOL (avg), IOH (avg) in an average value measured over 100ms.
When the oscillation frequency has a duty cyde of 50%.
When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) f(X IN)/
3.
5: When using the timer X/Y, timer A/B (real time output port), timer 1/2/3, serial I/O1, serial I/O2, and A-D converter, set the main
clock input oscillation frequency to the max. 3 Vcc–4 (MHz).
3-4
3807 GROUP USER’S MANUAL
APPENDIX
3.1 Electrical characteristics
3.1.3 Electrical characteristics
Table 3.1.5 Electrical characteristics (1)
(Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = – 20 to 85 °C, unless otherwise noted)
Symbol
VOH
VOL
VT+–VT–
Parameter
Test conditions
Limits
Min.
Typ.
Max.
Unit
“H” output voltage P00–P0 7, P10–P1 7, P20 –P27,
P30–P3 7, P40–P4 7, P50 –P57,
P60–P6 2, P65, P7 0–P77 ,
P80–P8 7, CMPOUT (Note 1)
IOH = –10mA
VCC = 4.0 to 5.5V
VCC –2.0
V
IOH = –1.0mA
VCC = 2.7 to 5.5V
VCC –1.0
V
“L” output voltage P00–P0 7, P10–P1 7, P20 –P27,
P30–P3 7, P40–P4 7, P50 –P57,
P60–P6 2, P65, P7 0–P77 ,
P80–P8 7, CMPOUT
IOL = 10mA
VCC = 4.0 to 5.5V
2.0
V
IOL = 1.6mA
VCC = 2.7 to 5.5V
0.4
V
Hysteresis
P42, P4 3, P51–P5 5, P7 3 (Note 2),
CNTR0, CNTR1 , INT0–INT4, ADT
0.4
V
VT+–VT–
Hysteresis
RXD, SCLK1, SIN2, SCLK2
0.5
V
VT+–VT–
Hysteresis
RESET
I IH
“H” input current
P00–P0 7, P10–P1 7, P20 –P27,
P30–P3 7, P40–P4 7, P50 –P57,
P60–P6 5, P70–P7 7, P8 0–P87
I IH
“H” input current
RESET, CNVSS
VI = VCC
I IH
“H” input current
XIN
VI = VCC
I IL
“L” input current
P00–P0 7, P10–P1 7, P20 –P27,
P30–P3 7, P40–P4 7, P50 –P57,
P60–P6 5, P70–P7 7, P8 0–P87
VI = VSS
(Pin floating. Pull-up
transistors “off”)
I IL
“L” input current
RESET, CNVSS
VI = VSS
I IL
“L” input current
XIN
VI = VSS
I IL
“L” input current
P00–P0 7, P10–P1 7, P2 0–P27
Pull-up transistors “on”
VI = VSS
VRAM
RAM hold voltage
____________
0.5
VI = VCC
(Pin floating. Pull-up
transistors “off”)
V
5.0
µA
5.0
µA
____________
µA
4
–5.0
µA
–5.0
µA
____________
When clock stopped
2.0
–4
µA
–0.2
mA
5.5
V
Note1: P45 is measured when the P45 /TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16 ) is “0”.
P71, and P12 are measured when the P71/SOUT2 and P72/SCLK2 P-channel output disable bit of the serial I/O2 control register 1
(bit 7 of address 001D16).
2: P73 is measured when the AD external trigger valid bit of the A–D control register (bit 6 of address 003416 ) is “1”.
3807 GROUP USER’S MANUAL
3-5
APPENDIX
3.1 Electrical characteristics
Table 3.1.6 Electrical characteristics (2)
(Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = – 20 to 85 °C, unless otherwise noted)
Symbol
ICC
CMPICC
3-6
Parameter
Power source current
Limits
Test conditions
Min.
Unit
Typ.
Max.
High-speed mode
f(X IN) = 8MHz
f(X CIN) = 32.768kHz
Output transistors “off”
6.8
13
High-speed mode
f(X IN) = 8MHz (in WIT state)
f(X CIN) = 32.768kHz
Output transistors “off”
1.6
Low-speed mode
f(X IN) = stopped
f(X CIN) = 32.768kHz
Low-power dissipation mode (CM 3 = 0)
Output transistors “off”
60
200
µA
Low-speed mode
f(X IN) = stopped
f(X CIN) = 32.768kHz (in WIT state)
Low-power dissipation mode (CM 3 = 0)
Output transistors “off”
20
40
µA
Low-speed mode (V CC = 3V)
f(X IN) = stopped
f(X CIN) = 32.768kHz
Low-power dissipation mode (CM 3 = 0)
Output transistors “off”
20
55
µA
Low-speed mode (V CC = 3V)
f(X IN) = stopped
f(X CIN) = 32.768kHz (in WIT state)
Low-power dissipation mode (CM 3 = 0)
Output transistors “off”
5.0
10.0
µA
Middle-speed mode
f(X IN) = 8MHz
f(X CIN) = stopped
Output transistors “off”
4.0
7.0
mA
Middle-speed mode
f(X IN) = 8MHz (in WIT state)
f(X CIN) = stopped
Output transistors “off”
1.5
mA
Increment when A-D conversion is executed
f(X IN) = 8MHz
800
µA
All oscillation stopped (in STP state)
Output transistors “off”
0.1
Ta = 25°C
Ta = 85°C
200
Analog comparator
Power source current
3807 GROUP USER’S MANUAL
mA
mA
1.0
µA
10
µA
500
µA
APPENDIX
3.1 Electrical characteristics
3.1.4 A-D converter characteristics
Table 3.1.7 A-D converter characteristics
(Vcc = 2.7 to 5.5 V, Vss = AVss = 0 V, ADVREF = 2.0 V to Vcc, Ta = – 20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
—
Resolution
—
Absolute accuracy (excluding quantization error)
t CONV
Conversion time
RLADDER
Ladder resistor
I ADVREF
Reference power
source input current
I I(AD)
A-D port input current
ADVREF
“on”
ADVREF
“off”
Limits
Min.
Typ.
VCC = ADV REF = 5.0V
ADVREF = 5.0V
Max.
Unit
8
Bits
±2
LSB
50
tc(φ)
12
35
100
kΩ
50
150
200
µA
5
µA
5.0
µA
3.1.5 D-A converter characteristics
Table 3.1.8 D-A converter characteristics
(Vcc = 2.7 to 5.5 V, Vss = AVss = 0 V, DAVREF = 2.7 V to Vcc, Ta = – 20 to 85 °C, unless otherwise noted)
Symbol
Parameter
—
Resolution
—
Absolute accuracy
Test conditions
Min.
Limits
Typ.
Max.
Unit
8
Bits
VCC = 4.0 to 5.5V
1.0
%
VCC = 2.7 to 4.0V
2.5
%
3
µs
t su
Setting time
Ro
Output resistor
I DAVREF
Reference power source input current (Note)
1
2.5
4
kΩ
3.2
mA
Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”.
3.1.6 Analog comparator characteristics
Table 3.1.9 Analog comparator characteristics
(Vcc = 2.7 to 5.5 V, Vss = AVss = 0 V, CMPVcc = 2.7 V to Vcc, Ta = – 20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Min.
Max.
3
50
mV
VIO
Input offset voltage
IB
Input bias current
5
µA
I IO
Input offset current
5
µA
CMPVCC
–0.5
V
2500
ns
VICM
In-phase input voltage range
AV
Voltage gain
t PD
Response time
CMPVCC = 5.0V
CMPREF = 2.5V, Rs = 0Ω
Unit
Typ.
1.2
∞
CMPVCC = 5.0V
CMPREF = 2.5V
3807 GROUP USER’S MANUAL
60
3-7
APPENDIX
3.1 Electrical characteristics
3.1.7 Timing requirements
Table 3.1.10 Timing requirements (1)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = – 20 to 85 °C, unless otherwise noted)
Symbol
Parameter
____________
Limits
Min.
Typ.
Max.
Unit
tW(RESET)
Reset input “L” pulse width
2
µs
tC(XIN)
External clock input cycle time
125
ns
tWH(XIN)
External clock input “H” pulse width
50
ns
tWL(XIN)
External clock input “L” pulse width
50
ns
tC(CNTR)
CNTR 0, CNTR 1 input cycle time
200
ns
tWH(CNTR)
CNTR 0, CNTR 1 input “H” pulse width
80
ns
tWL(CNTR)
CNTR 0, CNTR 1 input “L” pulse width
80
ns
tWH(INT)
INT0 to INT4 input “H” pulse width
80
ns
tWL(INT)
INT0 to INT4 input “L” pulse width
80
ns
tC(SCLK1)
Serial I/O1 clock input cycle time (Note)
800
ns
tWH(SCLK1)
Serial I/O1 clock input “H” pulse width (Note)
370
ns
tWL(SCLK1)
Serial I/O1 clock input “L” pulse width (Note)
370
ns
tsu (RXD–SCLK1)
Serial I/O1 clock input set up time
220
ns
th(SCLK1–R XD)
Serial I/O1 clock input hold time
100
ns
tC(SCLK2)
Serial I/O2 clock input cycle time
1000
ns
tWH(SCLK2)
Serial I/O2 clock input “H” pulse width
400
ns
tWL(SCLK2)
Serial I/O2 clock input “L” pulse width
400
ns
tsu (SIN2–SCLK2)
Serial I/O2 clock input set up time
200
ns
200
ns
th(SCLK2–SIN2)
Serial I/O2 clock input hold time
Note: When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
Table 3.1.11 Timing requirements (2)
(Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = – 20 to 85 °C, unless otherwise noted)
Symbol
Parameter
____________
Limits
Min.
Typ.
Max.
Unit
tW(RESET)
Reset input “L” pulse width
2
µs
tC(XIN)
External clock input cycle time
243
ns
tWH(XIN)
External clock input “H” pulse width
100
ns
tWL(XIN)
External clock input “L” pulse width
100
ns
tC(CNTR)
CNTR 0, CNTR 1 input cycle time
500
ns
tWH(CNTR)
CNTR 0, CNTR 1 input “H” pulse width
230
ns
tWL(CNTR)
CNTR 0, CNTR 1 input “L” pulse width
230
ns
tWH(INT)
INT0 to INT4 input “H” pulse width
230
ns
tWL(INT)
INT0 to INT4 input “L” pulse width
230
ns
tC(SCLK1)
Serial I/O1 clock input cycle time (Note)
2000
ns
tWH(SCLK1)
Serial I/O1 clock input “H” pulse width (Note)
950
ns
tWL(SCLK1)
Serial I/O1 clock input “L” pulse width (Note)
950
ns
tsu (RXD–SCLK1)
Serial I/O1 clock input set up time
400
ns
th(SCLK1–R XD)
Serial I/O1 clock input hold time
200
ns
tC(SCLK2)
Serial I/O2 clock input cycle time
2000
ns
tWH(SCLK2)
Serial I/O2 clock input “H” pulse width
950
ns
tWL(SCLK2)
Serial I/O2 clock input “L” pulse width
950
ns
tsu (SIN2–SCLK2)
Serial I/O2 clock input set up time
400
ns
300
ns
th(SCLK2–SIN2)
Serial I/O2 clock input hold time
Note: When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
3-8
3807 GROUP USER’S MANUAL
APPENDIX
3.1 Electrical characteristics
3.1.8 Switching characteristics
Table 3.1.12 Switching characteristics (1)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = – 20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
t WH(SCLK1)
Serial I/O1 clock output “H” pulse width
t WL(SCLK1)
Serial I/O1 clock output “L” pulse width
t d(SCLK1–TXD)
Serial I/O1 output delay time (Note 1)
t v(SCLK1–TXD)
Serial I/O1 output valid time (Note 1)
t r(SCLK1)
Serial I/O1 clock output rising time
t f(SCLK1)
Serial I/O1 clock output falling time
t WH(SCLK2)
Serial I/O2 clock output “H” pulse width
t WL(SCLK2)
Serial I/O2 clock output “L” pulse width
t d(SCLK2–SOUT2 )
Serial I/O2 output delay time (Note 2)
t v(SCLK2–SOUT2)
Serial I/O2 output valid time (Note 2)
t f(SCLK2)
Serial I/O2 clock output falling time
t r(CMOS)
CMOS output rising time (Note 3)
t f(CMOS)
CMOS output falling time (Note 3)
Fig. 3.1.1
Limits
Min.
Typ.
Max.
Unit
t C(SCLK1)/2–30
ns
t C(SCLK1)/2–30
ns
140
ns
–30
Fig. 3.1.1
ns
30
ns
30
ns
tC(SCLK2)/2–160
ns
tC(SCLK2)/2–160
ns
200
ns
0
ns
Fig. 3.1.1
30
ns
10
30
ns
10
30
ns
Note 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: When the P71/SOUT2, P7 2/SCLK2 P-channel output disable bit of the serial I/O2 control register1 (bit 7 of address 001D16) is “0”.
3: XOUT pin is excluded.
Table 3.1.13 Switching characteristics (2)
(Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = – 20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
t WH(SCLK1)
Serial I/O1 clock output “H” pulse width
t WL(SCLK1)
Serial I/O1 clock output “L” pulse width
t d(SCLK1–TXD)
Serial I/O1 output delay time (Note 1)
t v(SCLK1–TXD)
Serial I/O1 output valid time (Note 1)
t r(SCLK1)
Serial I/O1 clock output rising time
t f(SCLK1)
Serial I/O1 clock output falling time
t WH(SCLK2)
Serial I/O2 clock output “H” pulse width
t WL(SCLK2)
Serial I/O2 clock output “L” pulse width
t d(SCLK2–SOUT2 )
Serial I/O2 output delay time (Note 2)
t v(SCLK2–SOUT2)
Serial I/O2 output valid time (Note 2)
t f(SCLK2)
Serial I/O2 clock output falling time
t r(CMOS)
CMOS output rising time (Note 3)
t f(CMOS)
CMOS output falling time (Note 3)
Fig. 3.1.1
Limits
Min.
Typ.
Max.
Unit
t C(SCLK1)/2–50
ns
t C(SCLK1)/2–50
ns
350
–30
Fig. 3.1.1
ns
50
ns
50
ns
tC(SCLK2)/2–240
ns
tC(SCLK2)/2–240
ns
400
0
Fig. 3.1.1
ns
ns
ns
50
ns
20
50
ns
20
50
ns
Note 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: When the P71/SOUT2, P7 2/SCLK2 P-channel output disable bit of the serial I/O2 control register1 (bit 7 of address 001D16) is “0”.
3: XOUT pin is excluded.
3807 GROUP USER’S MANUAL
3-9
APPENDIX
3.1 Electrical characteristics
3.1.9 Timing requirements in memory expansion mode and microprocessor mode
Table 3.1.14 Timing requirements in memory expansion and microprocessor mode
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = – 20 to 85 °C, in high-speed mode, unless otherwise noted)
Symbol
Limits
Parameter
Min.
_________
____
tsu(ONW–φ)
ONW input set up time
Typ.
Max.
Unit
–20
ns
_________
____
th(φ–ONW)
ONW input hold time
–20
ns
tsu(DB–φ)
Data bus set up time
50
ns
th(φ–DB)
Data bus hold time
0
ns
–20
ns
ONW input hold time
–20
ns
Data bus set up time
50
ns
Data bus hold time
0
ns
____ __
____ __
tsu(ONW–RD), t su(ONW–WR)
__ ____
__ ____
th(RD–ONW), th(WR–ONW)
__
tsu(DB–RD)
__
th(RD–DB)
________
ONW input set up time
_________
3.1.10 Switching characteristics in memory expansion mode and microprocessor mode
Table 3.1.15 Switching characteristics in memory expansion and microprocessor mode
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = – 20 to 85 °C, in high-speed mode, unless otherwise noted)
Symbol
Limits
Test conditions
Parameter
Min.
tc(φ)
φ
clock cycle time
tWH(φ)
φ
clock “H” pulse width
tC(XIN)–10
tWL (φ)
φ
clock “L” pulse width
tC(XIN)–10
td(φ–AH)
AD15 –AD8 delay time
Fig. 3.1.1
Typ.
Max.
2t C(XIN)
Unit
ns
ns
ns
16
35
ns
20
40
ns
td(φ–AL)
AD7 –AD0 delay time
tv(φ–AH)
AD15 –AD8 valid time
2
5
ns
tv(φ–AL)
AD7 –AD0 valid time
2
5
ns
td(φ–SYNC)
SYNC delay time
16
ns
tv(φ–SYNC)
SYNC valid time
5
td(φ–DB)
Data bus delay time
15
tv(φ–DB)
Data bus valid time
__
__
__
tWL (RD), tWL(WR)
__
__
__
__
td(AL–RD), td(AL–WR)
__
__
__
__
tv(RD–AH), t v(WR–AH)
tv(RD–AL), t v(WR–AL)
__
td(WR–DB)
ns
3tC (XIN)–10
ns
___
AD15 –AD8 delay time
tC(XIN)–35
t C(XIN)–16
ns
AD7 –AD0 delay time
tC(XIN)–40
t C(XIN)–20
ns
AD15 –AD8 valid time
2
5
ns
AD7 –AD0 valid time
2
5
ns
Data bus delay time
__
tv(WR–DB)
_____
ns
tC(XIN)–10
___
RD pulse width, WR pulse width
(When one-wait is valid)
td(AH–RD), td(AH–WR)
15
Data bus valid time
____________
td(RESET–RESETOUT)
____________
tv(φ–RESETOUT)
30
10
ns
ns
_______________
RESET OUT output delay time
200
ns
100
ns
_______________
RESET OUT output valid time (Note)
0
Note: ____________
The RESETOUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after the
RESET input goes “H”.
3-10
ns
10
RD pulse width, WR pulse width
__
ns
30
3807 GROUP USER’S MANUAL
APPENDIX
3.1 Electrical characteristics
1k
Measurement output pin
100pF
Measurement output pin
100pF
CMOS output
N-channel open-drain output
Fig. 3.1.1 Circuit for measuring output switching
characteristics (1)
Fig. 3.1. 2 Circuit for measuring output switching
characteristics (2)
3807 GROUP USER’S MANUAL
3-11
APPENDIX
3.1 Electrical characteristics
Timing Diagram
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
0.8VCC
CNTR 0, CNTR 1
0.2VCC
tWL(INT)
tWH(INT)
0.8VCC
INT 0 INT 4
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
X IN
tf
S CLK1
S CLK2
0.2VCC
tC(SCLK1), tC(SCLK2)
tr
tWL(SCLK1), tWL(SCLK2)
0.8VCC
0.2VCC
tsu(RXD-SCLK1),
tsu(SIN2-SCLK2)
R XD
S IN2
th(SCLK1-RXD),
th(SCLK2-SIN2),
0.8VCC
0.2VCC
td(SCLK1-TXD),td(SCLK2-SOUT2)
TXD
S OUT2
Fig. 3.1.3 Timing diagram (1) (in single-chip mode)
3-12
tWH(SCLK1), tWH(SCLK2)
3807 GROUP USER’S MANUAL
tv(SCLK1-TXD),
tv(SCLK2-SOUT2)
APPENDIX
3.1 Electrical characteristics
Timing Diagram in Memory Expansion Mode and Microprocessor Mode(CMOS level input)
tC(
tWH(
)
tWL(
)
)
0.5VCC
td(
-AH)
AD15 AD8
tv(
-AH)
tv(
-AL)
tv(
-SYNC)
tv(
-WR)
0.5VCC
td(
-AL)
AD7 AD0
0.5VCC
td(
-SYNC)
0.5VCC
SYNC
td(
RD,WR
-WR)
0.5VCC
tSU(ONW-
th(
)
-ONW)
0.8VCC
0.2VCC
ONW
tSU(DB-
)
th(
-DB)
tv(
-DB)
0.8VCC
0.2VCC
DB0 DB7
(At CPU reading)
td(
-DB)
DB0 DB7
(At CPU writing)
0.5VCC
Timing Diagram in Microprocessor Mode
RESET
0.8VCC
0.2VCC
0.5VCC
td(RESET- RESETOUT)
RESETOUT
tv(
-RESETOUT)
0.5VCC
Fig. 3.1.4 Timing diagram (2) (in memory expansion mode and microprocessor mode)
3807 GROUP USER’S MANUAL
3-13
APPENDIX
3.1 Electrical characteristics
Timing Diagram in Memory Expansion Mode and Microprocessor Mode(CMOS level input)
tWL(RD)
tWL(WR)
RD,WR
0.5V C C
td(AH-RD)
td(AH-WR)
AD15 AD8
tv(RD-AH)
tv(WR-AH)
0.5VCC
td(AL-RD)
td(AL-WR)
AD7 AD0
tv(RD-AL)
tv(WR-AL)
0.5VCC
th(RD-ONW)
th(WR-ONW)
tsu(ONW-RD)
tsu(ONW-WR)
ONW
0.8VCC
0.2VCC
(At CPU reading)
RD
0.5VCC
tSU(DB-RD)
th(RD-DB)
0.8VCC
0.2VCC
DB0 DB7
(At CPU writing)
WR
0.5VCC
tv(WR-DB)
td(WR-DB)
DB0 DB7
0.5VCC
Fig. 3.1.5 Timing diagram (3) (in memory expansion mode and microprocessor mode)
3-14
3807 GROUP USER’S MANUAL
APPENDIX
3.1 Electrical characteristics
Timing Diagram in Memory Expansion Mode and Microprocessor Mode(TTL level input)
tC(
tWH(
)
tWL(
)
)
2.0V
0.8V
td(
-AH)
tv(
-AH)
tv(
-AL)
tv(
-SYNC)
tv(
-WR)
th(
-ONW)
th(
-DB)
tv(
-DB)
2.0V
0.8V
AD15 AD8
td(
-AL)
2.0V
0.8V
AD7 AD0
td(
-SYNC)
2.0V
0.8V
SYNC
td(
-WR)
2.0V
0.8V
RD,WR
tSU(ONW-
)
2.0V
0.45V
ONW
tSU(DB-
)
2.0V
0.45V
DB0 DB7
(At CPU reading)
td(
-DB)
DB0 DB7
(At CPU writing)
2.0V
0.8V
Timing Diagram in Microprocessor Mode
RESET
0.8VCC
0.2VCC
2.0V
0.8V
td(RESET-RESETOUT)
RESETOUT
tv(
-RESETOUT)
2.0V
0.8V
Fig. 3.1.6 Timing diagram (4) (in memory expansion mode and microprocessor mode)
3807 GROUP USER’S MANUAL
3-15
APPENDIX
3.1 Electrical characteristics
Timing Diagram in Memory Expansion Mode and Microprocessor Mode(TTL level input)
tWL(RD)
tWL(WR)
RD,WR
AD15 AD8
AD7 AD0
2.0V
0.8V
td(AH-RD)
td(AH-WR)
tv(RD-AH)
tv(WR-AH)
td(AL-RD)
td(AL-WR)
tv(RD-AL)
tv(WR-AL)
2.0V
0.8V
2.0V
0.8V
th(RD-ONW)
th(WR-ONW)
tsu(ONW-RD)
tsu(ONW-WR)
ONW
2.4V
0.45V
(At CPU reading)
RD
2.0V
0.8V
tSU(DB-RD)
th(RD-DB)
2.4V
0.45V
DB0 DB7
(At CPU writing)
WR
2.0V
0.8V
tv(WR-DB)
td(WR-DB)
2.0V
0.8V
DB0 DB7
Fig. 3.1.7 Timing diagram (5) (in memory expansion mode and microprocessor mode)
3-16
3807 GROUP USER’S MANUAL
APPENDIX
3.2 Standard characteristics
3.2 Standard characteristics
3.2.1 Power source current characteristic examples
Figures 3.2.1 and Figure 3.2.2 show power source current characteristic examples.
[Measuring condition : 25 °C, f(XCIN) = 32kHz, A-D conversion operatting, in high-speed mode]
Rectangular waveform
Power source current
(mA)
10
Vcc=5.0V, Ta=25°C
9
8
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10
Frequency f(XIN)(MHz)
Fig. 3.2.1 Power source current characteristic example
[Measuring condition : 25 °C, f(XCIN ) = 32kHz, A-D conversion operatting, in high-speed mode]
Rectangular waveform
Power source current 1.0
(mA)
Vcc=5.0V, Ta=25°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
8
9
10
Frequency f(XIN)(MHz)
Fig. 3.2.2 Power source current characteristic example (in wait mode)
3807 GROUP USER’S MANUAL
3-17
APPENDIX
3.2 Standard characteristics
3.2.2 Port standard characteristic examples
Figures 3.2.3, Figure 3.2.4, Figure 3.2.5, and Figure 3.2.6 show port standard characteristic examples.
[Port P87 I OH–V OH characteristic (P-channel drive)]
(Pins with same characteristic : P0, P1, P2, P3, P4, P5, P60—P6 2, P6 5, P7, P8, CMP OUT)
IO H
(mA)
–100
–90
–80
–70
–60
–50
–40
Vcc=5.5V,Ta=90°C
–30
–20
Vcc=5.0V,Ta=90°C
–10
0
0
Vcc=3.0V,Ta=90°C
1
2
3
4
5
6
VOH (V)
Fig. 3.2.3 Standard characteristic example of CMOS output port at P-channel drive (1)
[Port P87 I OH–V OH characteristic (P-channel drive)]
(Pins with same characteristic : P0, P1, P2, P3, P4, P5, P60—P6 2, P6 5, P7, P8, CMP OUT)
IO H
(mA)
–100
–90
–80
–70
–60
–50
–40
Vcc=5.5V,Ta=25°C
–30
Vcc=5.0V,Ta=25°C
–20
–10
Vcc=3.0V,Ta=25°C
0
0
1
2
3
4
5
6
VOH (V)
Fig. 3.2.4 Standard characteristic example of CMOS output port at P-channel drive (2)
3-18
3807 GROUP USER’S MANUAL
APPENDIX
3.2 Standard characteristics
[Port P8 7 IOL–V OL characteristic (N-channel drive)]
(Pins with same characteristic : P0, P1, P2 0—P2 3, P3, P4, P5, P6 0—P6 2, P6 5, P7, P8,
CMPOUT, P2 4—P2 7 except in single-chip mode)
IOL
(mA)
–100
–90
–80
–70
–60
Vcc=5.5V,Ta=90°C
–50
Vcc=5.0V,Ta=90°C
–40
–30
Vcc=3.0V,Ta=90°C
–20
–10
0
0
1
2
3
4
5
6
VOL (V)
Fig. 3.2.5 Standard characteristic example of CMOS output port at N-channel drive (1)
[Port P8 7 IOL–V OL characteristic (N-channel drive)]
(Pins with same characteristic : P0, P1, P2 0—P2 3, P3, P4, P5, P6 0—P6 2, P6 5, P7, P8,
CMPOUT, P2 4—P2 7 except in single-chip mode)
IOL
(mA)
–100
–90
–80
–70
Vcc=5.5V,Ta=25°C
–60
Vcc=5.0V,Ta=25°C
–50
–40
–30
Vcc=3.0V,Ta=25°C
–20
–10
0
0
1
2
3
4
5
6
VO L (V)
Fig. 3.2.6 Standard characteristic example of CMOS output port at N-channel drive (2)
3807 GROUP USER’S MANUAL
3-19
APPENDIX
3.2 Standard characteristics
[Port P27 IOL –VOL characteristic (N-channel drive)]
(Pins with same characteristic : P24 —P27 in single-chip mode)
IOL
(mA)
–100
Vcc=5.5V,Ta=90°C
–90
Vcc=5.0V,Ta=90°C
–80
–70
–60
–50
–40
Vcc=3.0V,Ta=90°C
–30
–20
–10
0
0
1
2
3
4
5
6
VOL (V)
Fig. 3.2.7 Standard characteristic example of CMOS output port at N-channel drive (4)
[Port P27 IOL –VOL characteristic (N-channel drive)]
(Pins with same characteristic : P24 —P27 in single-chip mode)
IOL
(mA)
Vcc=5.5V,Ta=25°C
–100
Vcc=5.0V,Ta=25°C
–90
–80
–70
–60
–50
Vcc=3.0V,Ta=25°C
–40
–30
–20
–10
0
0
1
2
3
4
5
6
VOL (V)
Fig. 3.2.8 Standard characteristic example of CMOS output port at N-channel drive (5)
3-20
3807 GROUP USER’S MANUAL
APPENDIX
3.2 Standard characteristics
3.2.3 Input current standard characteristic examples
Figure 3.2.9 and Figure 3.2.10 show input current standard characteristic examples.
[Port P2 7 I IL characteristic (at pull-up)] (Pins with same characteristic : P0, P1, P2)
IIL
(mA)
–250
–225
–200
Vcc=5.5V,Ta=90°C
–175
–150
Vcc=5.0V,Ta=90°C
–125
–100
–75
–50
–25
Vcc=3.0V,Ta=90°C
0
0
1
2
3
4
5
6
VI (V)
Fig. 3.2.9 Standard characteristic example of input current at connecting pull-up transistor (1)
[Port P2 7 I IL characteristic (at pull-up)] (Pins with same characteristic : P0, P1, P2)
IIL
(mA)
–250
–225
Vcc=5.5V,Ta=25°C
–200
–175
–150
Vcc=5.0V,Ta=25°C
–125
–100
–75
–50
Vcc=3.0V,Ta=25°C
–25
0
0
1
2
3
4
5
6
VI (V)
Fig. 3.2.10 Standard characteristic example of input current at connecting pull-up transistor (2)
3807 GROUP USER’S MANUAL
3-21
APPENDIX
3.2 Standard characteristics
3.2.4 A-D conversion standard characteristics
Figure 3.2.11 shows the A-D conversion standard characteristics.
The lower-side line on the graph indicates the absolute precision error. It represents the deviation from the
ideal value. For example, the conversion of output code from 0 to 1 occurs ideally at the point of AN0 =
10 mV, but the measured value is 0 mV. Accordingly, the measured point of conversion is represented as
“10 – 0 = 10 mV.”
The upper-side line on the graph indicates the width of input voltages equivalent to output codes. For
example, the measured width of the input voltage for output code 13 is 22 mV, so the differential nonlinear
error is represented as “22 – 20 = 2 mV” (0.1 LSB).
A-D CONVERTER STEP WIDTH MEASUREMENT
Measured when a power source voltage is stable in the single-chip mode and the high-speed mode
Fig. 3.2.11 A-D conversion standard characteristics
3-22
3807 GROUP USER’S MANUAL
APPENDIX
3.2 Standard characteristics
3.2.5 D-A conversion standard characteristics
Figure 3.2.12 shows the D-A conversion standard characteristics. The lower-side line on the graph indicates the absolute precision error. In this case, it represents the difference between the ideal analog output
value for an input code and the measured value.
The upper-side line on the graph indicates the change width of output analog value to a one-bit change
of input code.
D-A CONVERTER STEP WIDTH MEASUREMENT
Measured when a power source voltage is stable in the single-chip mode and the high-speed mode
Fig. 3.2.12 D-A conversion standard characteristics
3807 GROUP USER’S MANUAL
3-23
APPENDIX
3.3 Notes on use
3.3 Notes on use
3.3.1 Notes on interrupts
(1) Sequence for switching an external interrupt
detection edge
When the external interrupt detection edge must be
switched, make sure the following sequence.
Reason
The interrupt circuit recognizes the switching of the
detection edge as the change of external input
signals. This may cause an unnecessary interrupt.
(2) Bit 7 of the interrupt control register 2
Fix the bit 7 of the interrupt control register 2
(Address:003F16 ) to “0”.
Clear an interrupt enable bit to “0” (interrupt disabled)
Switch the detection edge
Clear an interrupt request bit to “0” (no interrupt request issued)
Set the interrupt enable bit to “1” ( interrupt enabled )
b7
0
b0
Interrupt control register 2
Address 003F16
Figure 3.3.1 shows the structure of the interrupt
control register 2.
Interrupt enable bits
Not used
Fix this bit to “0”
Fig. 3.3.1 Structure of interrupt control register 2
3.3.2 Notes on the serial I/O1
(1) Stop of data transmission
As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear
the transmit enable bit to “0” (transmit disabled), and clear the serial I/O enable bit to “0” (serial I/O1 disabled)in
the following cases :
● when stopping data transmission during transmitting data in the clock synchronous serial I/O mode
● when stopping data transmission during transmitting data in the UART mode
● when stopping only data transmission during transmitting and receiving data in the UART mode
Reason
Since transmission is not stopped and the transmission circuit is not initialized even if the serial I/O1 enable bit
is cleared
to “0” (serial I/O1 disabled), the internal transmission is running (in this case, since pins TxD, RxD, SCLK1,
______
and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer
register in this state, the data is transferred to the transmit shift register and start to be shifted. When the serial
I/O1 enable bit is set to “1” at this time, the data during internally shifting is output to the TxD pin and it may cause
an operation failure to a microcomputer.
(2) Stop of data reception
As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear
the receive enable bit to “0” (receive disabled), or clear the serial I/O enable bit to “0” (serial I/O disabled) in the
following case :
● when stopping data reception during receiving data in the clock synchronous serial I/O mode
Clear the receive enable bit to “0” (receive disabled) in the following cases :
● when stopping data reception during receiving data in the UART mode
● when stopping only data reception during transmitting and receiving data in the UART mode
3-24
3807 GROUP USER’S MANUAL
APPENDIX
3.3 Notes on use
(3) Stop of data transmission and reception in a clock synchronous serial I/O mode
As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear
both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled) at the same time in the
following case:
● when stopping data transmission and reception during transmitting and receiving data in the clock synchronous
mode (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of
transmission and reception is disabled, a bit error occurs because transmission and reception cannot be
synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the
transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the
transmission circuit is not initialized by clearing the serial I/O1 enable bit to “0” (serial I/O1 disabled) (refer to (1)).
_____
(4) The SRDY pin on a receiving side _____
When signals are output from the S RDY pin on the reception_____
side by using an external clock in the clock
synchronous serial I/O mode, set all of the receive enable bit, the SRDY output enable bit, and the transmit enable
bit to “1” (transmit enabled).
(5) Stop of data reception in a clock synchronous
serial I/O mode
Set the serial I/O1 control register again after the
transmission and the reception circuits are reset by
clearing both the transmit enable bit and the receive
enable bit to “0.”
Clear both the transmit
enable bit (TE) and the
receive enable bit (RE) to “0”
Set the bits 0 to 3 and bit 6 of
the serial I/O1 control
register
Set both the transmit enable
bit (TE) and the receive
enable bit (RE) to “1”
Can be set with the
LDM instruction at
the same time
(6) Control of data transmission using the transmit shift completion flag
The transmit shift completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When checking
the transmit shift completion flag after writing a data to the transmit buffer register for controlling a data
transmission, note this delay.
(7) Control of data transmission using an external clock
When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to “1”
at “H” level of the SCLK input signal. Also, write data to the transmit buffer register at “H” level of the SCLK input
signal.
3.3.3 Notes on the A-D converter
(1) Input of signals from signal source with high impedance to an analog input pin
Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor
of 0.01 µF to 1 µF. Further, make sure to check the operation of application products on the user side.
Reason
The A-D converter builds in the capacitor for analog voltage comparison. Accordingly, when signals from signal
source with high impedance are input to an analog input pin, a charge and discharge noise generates. This may
cause the A-D conversion precision to be worse.
3807 GROUP USER’S MANUAL
3-25
APPENDIX
3.3 Notes on use
(2) AVSS pin
Connect a power source for the A-D converter, AVSS pin to the VSS line of the analog circuit.
(3) A clock frequency during an A-D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is
too low. Thus, make sure the following during an A-D conversion.
● f(XIN) is 500 kHz or more .
(When the ONW pin is "L", f(XIN) is 1 MHz or more.)
● Do not execute the STP instruction and WIT instruction.
3.3.4 Notes on the RESET pin
When a rising time of the reset signal is long, connect a ceramic capacitor or others across the RESET pin and
the VSS pin. And use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, make
sure the following :
●Make the length of the wiring which is connected to a capacitor the shortest possible.
●Make sure to check the operation of application products on the user side.
Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, a microcomputer may
malfunction.
3.3.5 Notes on input and output pins
(1) Fix of a port input level in stand-by state
Fix input levels of an input and an I/O port for getting effect of low-power dissipation in stand-by state, especially
for the I/O ports of the N-channel open-drain.
Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor.
When determining a resistance value, make sure the following:
●External circuit
●Variation of output levels during the ordinary operation
* stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
Reason
Even when setting as an output port with its direction register, in the following state :
●N-channel......when the content of the port latch is “1”
the transistor becomes the OFF state, which causes the ports to be the high-impedance state. Make sure that the
level becomes “undefined” depending on external circuits.
Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input
levels of an input and an I/O port are “undefined.” This may cause power source current.
(2) Modify of the content of I/O port latch
When the content of the port latch of an I/O port is modified with the bit managing instruction*, the value of the
unspecified bit may be changed.
Reason
The bit managing instruction is read-modify-write instruction for reading and writing data by a byte unit.
Accordingly, when this instruction is executed on one bit of the port latch of an I/O port, the following is executed
to all bits of the port latch.
●As for a bit which is set as an input port : The pin state is read in the CPU, and is written to this bit after bit
managing.
●As for a bit which is set as an output port : The bit value is read in the CPU, and is written to this bit after bit
managing.
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3807 GROUP USER’S MANUAL
APPENDIX
3.3 Notes on use
Make sure the following :
●Even when a port which is set as an output port is changed for an input port, its port latch holds the output data.
●Even when a bit of a port latch which is set as an input port is not speccified with a bit managing instruction,
its value may be changed in case where content of the pin differs from a content of the port latch.
* bit managing instructions : SEB, and CLB instruction
(3) The AVSS pin when not using the A-D converter
When not using the A-D converter, handle a power source pin for the A-D converter, AVSS pin as follows :
● AVSS : Connect to the VSS pin
Reason
If the AV SS pin is opened, the microcomputer may malfunction by effect of noise or others.
3.3.6 Notes on memory expansion mode and microprocessor mode
(1) Writing data to the port latch of port P3
In the memory expansion or the microprocessor mode, ports P3 0 and P31 can be used as the output port. Use the
LDM or STA instruction for writing data to the port latch (address 000616) of port P3.
When using a read-modify-write instruction (the SEB or the CLB instruction), allocate the read and the write
enabled memory at address 000616.
Reason
In the memory expansion or microprocessor mode, address 000616 is allocated in the external area.
Accordingly,
● Data is read from the external memory.
● Data is written to both the port latch of the port P3 and the external memory.
Accordingly, when executing a read-modify-write instruction for address 0006 16, external memory data is read and
modified, and the result is written in both the port latch of the port P3 and the external memory. If the read enabled
memory is not allocated at address 000616, the read data is undefined. The undefined data is modified and written
to the port latch of the port P3. The port latch data of port P3 becomes “undefined.”
(2) Overlap of an internal memory and an external memory
When the internal and the external memory are overlapped in the memory expansion mode, the internal memory
is valid in this overlapped area. When the CPU writes or reads to this area, the following is performed :
● When reading data
Only the data in the internal memory is read into the CPU and the data in the external memory is not read into
the CPU. However, as the read signal and address are still valid, the external memory data of the
corresponding address is output to the external data bus.
● When writing data
Data is written in both the internal and the external memory.
3807 GROUP USER’S MANUAL
3-27
APPENDIX
3.3 Notes on use
3.3.7 Notes on built-in PROM
(1) Programming adapter
To write or read data into/from the internal PROM, use the dedicated programming adapter and general-purpose
PROM programmer as shown in Table 3.3.1.
Table 3.3.1 Programming adapter
Microcomputer
Programming adapter
M38073E4FS
PCA4738L-80A
M38073E4FP
PCA4738F-80A
(one-time blank)
(2) Write and read
In PROM mode, operation is the same as that of the M5M27C256AK, but programming conditions of PROM
programmer are not set automatically because there are no internal device ID codes.
Accurately set the following conditions for data write/read. Take care not to apply 21 V to Vpp pin (is also used as
the CNVSS pin), or the product may be permanently damaged.
● Programming voltage : 12.5 V
● Setting of programming adapter switch : refer to table 3.3.2
● Setting of PROM programmer address : refer to table 3.3.3
Table 3.3.2 Setting of programming adapter switch
Programming adapter
SW 1
SW 2
SW 3
CMOS
CMOS
OFF
PCA4738F-80A
PCA4738L-80A
Table 3.3.3 Setting of PROM programmer address
Microcomputer
PROM programmer start address
PROM programmer completion address
Address : 408016 (Note 1)
Address : 7FFD16 (Note 1)
M38073E4FS
M38073E4FP
Note : Addresses C08016 to FFFD16 in the internal PROM correspond to addresses 408016 to 7FFD 16 in the
ROM programmer.
(3) Erasing
Contents of the windowed EPROM are erased through an ultraviolet light source of the wavelength 2537Angstrom . At least 15 W-sec/cm 2 are required to erase EPROM contents.
3-28
3807 GROUP USER’S MANUAL
APPENDIX
3.4 Countermeasures against noise
3.4 Countermeasures against noise
Countermeasures against noise are described below. The following countermeasures are effective against noise in
theory, however, it is necessary not only to take measures as follows but to evaluate before actual use.
3.4.1 Shortest wiring length
The wiring on a printed circuit board can be as an antenna which feeds noise into the microcomputer.
The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer.
(1) Wiring for the RESET pin
Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor
across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm).
Reason
The reset works to initialize a microcomputer.
The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having
a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state
of the microcomputer is completely initialized. This may cause a program runaway.
Noise
Reset
circuit
RESET
VSS
N.G.
Reset
circuit
RESET
VSS
VSS
VSS
3807 group
O.K.
3807 group
Fig. 3.4.1 Wiring for the RESET pin
(2) Wiring for clock input/output pins
●Make the length of wiring which is connected to clock I/O pins as short as possible.
●Make the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected to an
oscillator and the VSS pin of a microcomputer as short as possible.
●Separate the VSS pattern only for oscillation from other VSS patterns.
Reason
A microcomputer's operation synchronizes with a clock generated by the oscillator (circuit). If noise enters clock
I/O pins, clock waveforms may be deformed. This may cause a malfunction or program runaway.
Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level
of an oscillator, the correct clock will not be input in the microcomputer.
3807 GROUP USER’S MANUAL
3-29
APPENDIX
3.4 Countermeasures against noise
An example of VSS patterns on the
underside of a printed circuit board
Noise
,,,
,,,
,,,
,
,,,,
Oscillator wiring
pattern example
XIN
XOUT
VSS
N.G.
XIN
XOUT
VSS
O.K.
XIN
XOUT
VSS
Separate the VSS line for oscillation from other VSS lines
Fig. 3.4.2 Wiring for clock I/O pins
(3) Wiring for the VPP pin of the One Time PROM
version and the EPROM version
(In this microcomputer the VPP pin is also used
as the CNVSS pin)
Connect an approximately 5 kΩ resistor to theV P P
pin the shortest possible in series and also to the VSS
pin. When not connecting the resistor, make the
length of wiring between the VPP pin and the VSS pin
the shortest possible.
Approximately
5kΩ
CNVSS/VPP
VSS
Note:Even when a circuit which included an approximately 5 kΩ resistor is used in the Mask ROM
version, the maicrocomputer operates correctly.
Reason
The VPP pin of the One Time PROM and the EPROM
version is the power source input pin for the built-in
PROM. When programming in the built-in PROM,
the impedance of the VPP pin is low to allow the
electric current for wiring flow into the PROM. Because of this, noise can enter easily. If noise enters
the VPP pin, abnormal instruction codes or data are
read from the built-in PROM, which may cause a
program runaway.
3.4.2 Connection of a bypass capacitor across the
Vss line and the Vcc line
Connect an approximately 0.1 µF bypass capacitor
across the VSS line and the VCC line as follows:
●Connect a bypass capacitor across the VSS pin
and the VCC pin at equal length .
●Connect a bypass capacitor across the VSS pin
and the VCC pin with the shortest possible wiring.
●Use lines with a larger diameter than other signal
lines for VSS line and VCC line.
3807 group
Make it the shortest possible
Fig. 3.4.3 Wiring for the VPP pin of the One Time PROM
and the EPROM version
,,
,,
,,
,,
,, ,,,,
VCC
Chip
VCC
VSS
VSS
Fig. 3.4.4 Bypass capacitor across the VSS line and
the VCC line
3-30
3807 GROUP USER’S MANUAL
APPENDIX
3.4 Countermeasures against noise
3.4.3 Wiring to analog input pins
●Connect an approximately 100 Ω to 1 kΩ resistor to an
analog signal line which is connected to an analog
input pin in series. Besides, connect the resistor to
the microcomputer as close as possible.
●Connect an approximately 1000 pF capacitor across
the V SS pin and the analog input pin. Besides,
connect the capacitor to the V SS pin as close as
possible. Also, connect the capacitor across the
analog input pin and the V SS pin at equal length.
Reason
Signals which is input in an analog input pin (such as
an A-D converter input pin) are usually output signals
from sensor. The sensor which detects a change of
event is installed far from the printed circuit board
with a microcomputer, the wiring to an analog input
pin is longer necessarily. This long wiring functions
as an antenna which feeds noise into the
microcomputer, which causes noise to an analog
input pin.
If a capacitor between an analog input pin and the
Vss pin is grounded at a position far away from the
Vss pin, noise on the GND line may enter a microcomputer through the capacitor.
3.4.4. Consideration for oscillator
Take care to prevent an oscillator that generates
clocks for a microcomputer operation from being
affected by other signals.
Noise
(Note)
N.G.
O.K.
VSS
Note:The resistor is used for dividing
resistance with a thermistor.
Fig.3.4.5 Analog signal line and a resistor and a
capacitor
Microcomputer
Mutual inductance
M
XIN
XOUT
VSS
Large
current
GND
Fig.3.4.6 Wiring for a large current signal line
(2) Keeping an oscillator away from signal lines
where potential levels change frequently
Install an oscillator and a connecting pattern of an
osillator away from signal lines where potential levels
change frequently. Also, do not cross such signal
lines over the clock lines or the signal lines which are
sensitive to noise.
Reason
Signal lines where potential levels change frequently
(such as the CNTR pin line) may affect other lines at signal
rising or falling edge. If such lines cross over a clock
line, clock waveforms may be deformed, which causes
a microcomputer failure or a program runaway.
Analog
input pin
Thermistor
(1) Keeping an oscillator away from large current
signal lines
Install a microcomputer (and especially an oscillator)
as far as possible from signal lines where a current
larger than the tolerance of current value flows.
Reason
In the system using a microcomputer, there are
signal lines for controlling motors, LEDs, and thermal
heads or others. When a large current flows through
those signal lines, strong noise occurs because of
mutual inductance.
Microcomputer
N.G.
Do not cross
CNTR
XIN
XOUT
VSS
Fig.3.4.7 Wiring to a signal line where potential levels
change frequently
3807 GROUP USER’S MANUAL
3-31
APPENDIX
3.4 Countermeasures against noise
3.4.5 Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
●Connect a resistor of 100 Ω or more to an I/O port
inseries.
<Software>
●As for an input port, read data several times by a
program for checking whether input levels are
equal or not.
●As for an output port, since the output data may
reverse because of noise, rewrite data to its port
latch at fixed periods.
●Rewirte data to direction registers and pull-up
control registers (only the product having it) at fixed
periods.
O.K.
Noise
Data bus
Noise
Direction register
N.G.
Port latch
I/O port
pins
Fig. 3.4.8 Setup for I/O ports
When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse may be
output from this port. If this is undesirable, connect a capacitor to this port to remove the noise pulse.
3.4.6 Providing of watchdog timer function by
software
If a microcomputer runs away because of noise or
others, it can be detected by a software watchdog
timer and the microcomputer can be reset to normal
operation. This is equal to or more effective than
program runaway detection by a hardware watchdog
timer. The following shows an example of a watchdog
timer provided by software.
In the following example, to reset a microcomputer to
normal operation, the main routine detects errors of
the interrupt processing routine and the interrupt
processing routine detects errors of the main routine.
This example assumes that interrupt processing is
repeated multiple times in a single main routine
processing.
Main routine
Interrupt processing routine
(SWDT)← N
(SWDT) ← (SWDT)—1
CLI
Interrupt processing
Main processing
(SWDT)
≤0?
N
(SWDT)
=N?
≤0
RTI
Return
=N
Interrupt processing
>0
Main routine
routine errors
errors
<The main routine>
●Assigns a single byte of RAM to a software watchdog
timer (SWDT) and writes the initial value N in the
SWDT once at each execution of the main routine.
Fig. 3.4.9 Watchdog timer by software
The initial value N should satisfy the following
condition:
N+1 ≥ (Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others, the initial value N
should have a margin.
●Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of
interrupt processing count after the initial value N has been set.
●Detects that the interrupt processing routine has failed and determines to branch to the program initialization
routine for recovery processing in the following cases:
If the SWDT contents do not change after interrupt processing
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3807 GROUP USER’S MANUAL
APPENDIX
3.4 Countermeasures against noise
<The interrupt processing routine>
●Decrements the SWDT contents by 1 at each interrupt processing.
●Determins that the main routine operates normally when the SWDT contents are reset to the initial value N at
almost fixed cycles (at the fixed interrupt processing count).
●Detects that the main routine has failed and determines to branch to the program initialization routine for recovery
processing in the following case:
When the contents of the SWDT reach 0 or less by continuative decrement without initializing to the initial value
N.
3807 GROUP USER’S MANUAL
3-33
APPENDIX
3.5 List of registers
3.5 List of registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 7, 8)
[Address : 0016, 0216, 0416, 0616, 0816, 0A16, 0E16, 1016]
B
Name
0 Port Pi0
Function
●
In output mode
Write
Port latch
Read
●
In input mode
Write : Port latch
Read : Value of pins
1 Port Pi1
2 Port Pi2
At reset
R W
0
0
0
3 Port Pi3
0
4 Port Pi4
0
5 Port Pi5
0
6 Port Pi6
0
7 Port Pi7
0
Fig. 3.5.1 Structure of Port Pi (i = 0, 1, 2, 3, 4, 5, 7, 8)
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4, 5, 7, 8)
[Address : 0116, 0316, 0516, 0716, 0916, 0B16, 0F16, 1116]
B
Function
Name
R W
0 Port Pi direction register
0
✕
1
0 : Port Pi1 input mode
1 : Port Pi1 output mode
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0 : Port Pi3 input mode
1 : Port Pi3 output mode
0 : Port Pi4 input mode
1 : Port Pi4 output mode
0
✕
0
✕
0
✕
0
✕
0 : Port Pi5 input mode
1 : Port Pi5 output mode
0 : Port Pi6 input mode
1 : Port Pi6 output mode
0 : Port Pi7 input mode
1 : Port Pi7 output mode
0
✕
0
✕
0
✕
2
3
4
5
6
7
Fig. 3.5.2 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4, 5, 7, 8)
3-34
At reset
0 : Port Pi0 input mode
1 : Port Pi0 output mode
3807 GROUP USER’S MANUAL
APPENDIX
3.5 List of registers
Port P6
b7 b6 b5 b4 b3 b2 b1 b0
Port P6 (P6) [Address : 0C16]
Function
Name
B
0 Port P60
●
In output mode
Write
Port latch
Read
●
In input mode
Write : Port latch
Read : Value of pins
1 Port P61
2 Port P62
3 Port P63
4 Port P64
At reset
R W
0
0
0
(Note)
0
✕
(Note)
0
✕
5 Port P65
0
6 Nothing is allocated for these bits. These are write disabled bits.
7 When these bits are read out, the values are “0”.
0
0
✕
✕
Note : These bits are used only for input port.
Fig. 3.5.3 Structure of Port P6
Port P6 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P6 direction register (P6D) [Address : 0D16]
Function
Name
B
0 Port P60—P62 direction
registers
1
2
At reset
R W
0 : Port P60 input mode
1 : Port P60 output mode
0
✕
0 : Port P61 input mode
1 : Port P61 output mode
0 : Port P62 input mode
1 : Port P62 output mode
0
✕
0
✕
3 Ports P63 and P64 are input ports.
0
✕
Accordingly, these bits do not have a direction register.
4 Nothing is allocated for these bits.
0
✕
0 : Port P65 input mode
1 : Port P65 output mode
6 Nothing is allocated for these bits. These are write disabled bits.
7 When these bits are read out, the values are “0”.
5 Port P65 direction register
0
0
0
✕
✕
✕
Fig. 3.5.4 Structure of Port P6 direction register
3807 GROUP USER’S MANUAL
3-35
APPENDIX
3.5 List of registers
Timer XY control register
b7 b6 b5 b4 b3 b2 b1 b0
Timer XY control register (TXYCON) [Address : 1416]
B
0
Name
Timer X stop control bit
Function
0 : Start counting
1 : Stop counting
Timer Y stop control bit
0 : Start counting
1 : Stop counting
2 Nothing is allocated for these bits. These are write disabled bits.
3 When these bits are read out, the values are “0.”
1
4
5
6
7
At reset
R W
1
1
0
0
0
0
0
0
✕
✕
✕
✕
✕
✕
Fig. 3.5.5 Structure of Timer XY control reigster
Port P2P3 control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P2P32 control register (P2P3C) [Address : 1516]
Name
B
0 P34 clock output control bit
1 Output clock frequency
selection bits
2
3
Function
At reset
0 : I/O port (P34)
1 : Clock output (CKOUT output pin)
0
b3 b2 b1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0:φ
1 : f(XIN)
0 : “L” fixed output
1 : “L” fixed output
0 : f(XIN)
(f(XCIN))
1 : f(XIN)/2 (f(XCIN)/2)
0 : f(XIN)/4 (f(XCIN)/4)
1 : f(XIN)/16 (f(XCIN)/16) (Note 1)
4 Nothing is allocated for these bits. These are write disabled bits.
5 When these bits are read out, the values are “0.”
6
7 P2•P3 input level selection bit 0 : CMOS level
1 : TTL level
Note 1 : In low-speed mode ( ) is selected.
2 : When CNVss pin is connected to Vss, the value is “0”.
When CNVss pin is connected to Vcc, the value is “1”.
Fig. 3.5.6 Structure of Port P2P3 control register
3-36
3807 GROUP USER’S MANUAL
R W
0
0
0
0
0
(Note 2)
✕
✕
✕
APPENDIX
3.5 List of registers
Pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register (PULL) [Address : 1616]
Name
B
0 P00—P03 pull-up control bit
1 P04, P05 pull-up control bit
2 P06 pull-up control bit
3 P07 pull-up control bit
4 P10—P13 pull-up control bit
5 P14—P17 pull-up control bit
6 P20—P23 pull-up control bit
7 P24—P27 pull-up control bit
Function
At reset
0 : No pull-up
1 : Pull-up
(Note)
0 : No pull-up
1 : Pull-up
(Note)
0 : No pull-up
1 : Pull-up
(Note)
0
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
0
R W
0
0
(Note)
0
(Note)
0
(Note)
0
(Note)
0 : No pull-up
1 : Pull-up
(Note)
0
Note : Valid only in input mode.
Fig. 3.5.7 Structure of Pull-up control register
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog timer control register (WDTCON) [Address : 1716]
B
Name
0 Watchdog timer H
1
2
3
4
5
Function
At reset
● After re-set a watchdog timer
operates by writting any values
in this register
1
1
1
1
1
1
● After
re-set these bits are re-set
to “0000002” by writting any
values in this register.
0
:
STP instruction enabled
STP instruction disable bit
6
(Note) 1 : STP instruction disabled
Watchdog timer H count
0 : Watchdog timer L underflow
7 source selection bit
1 : f(XIN)/16 or f(XCIN)/16
R W
✕
✕
✕
✕
✕
✕
0
0
Note : When this bit is set to “1”, it is not rewritten to “0” by software.
Fig. 3.5.8 Structure of Watchdog timer control register
3807 GROUP USER’S MANUAL
3-37
APPENDIX
3.5 List of registers
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB) [Address : 1816]
Function
B
0 A transmission data is written to or a receive data is read out
1
from this buffer register.
• At writing : a data is written to the Transmit buffer register.
• At reading : a content of the Receive buffer register is read out.
R W
At reset
?
?
2
?
3
?
4
?
5
?
6
?
7
?
Note : A content of the Transmit buffer register cannot be read out.
A data cannot be written to the Receive buffer register.
Fig. 3.5.9 Structure of Transmit/Receive buffer register
Serial I/O1 status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 status reigster (SIO1STS) [Address : 1916]
Name
B
Transmit
buffer
empty flag
0
(TBE)
1 Receive buffer full flag (RBF)
2 Transmit shift register shift
completion flag (TSC)
3 Overrun error flag (OE)
4 Parity error flag (PE)
5 Framing error flag (FE)
6 Summing error flag (SE)
Function
0 : Buffer full
1 : Buffer empty
0 : Buffer empty
1 : Buffer full
0 : Transmit shift in progress
1 : Transmit shift completed
0
R W
✕
0
✕
0
✕
0 : No error
1 : Overrun error
0 : No error
1 : Parity error
0
✕
0
✕
0 : No error
1 : Framing error
0 : (OE) (PE) (FE) = 0
1 : (OE) (PE) (FE) = 1
0
✕
0
✕
1
✕
7 Nothing is allocated for this bit. It is a write disabled bit.
When this bit is read out, the value is “0.”
Fig. 3.5.10 Structure of Serial I/O1 status register
3-38
3807 GROUP USER’S MANUAL
At reset
APPENDIX
3.5 List of registers
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register (SIO1CON) [Address : 1A16]
B
0
1
Name
BRG count source
selection bit (CSS)
Serial I/O1
synchronous clock
selection bit (SCS)
Function
At reset
(Note 1)
(Note 2)
0 : f(XIN)
1 : f(XIN)/4
At selecting clock synchronous serial I/O
0 : BRG output divided by 4
1 : External clock input
R W
0
0
At selecting UART
0 : BRG output divided by 16
1 : External clock input divided by 16
2
SRDY1 output enable bit
3
(SRDY)
Transmit interrupt
source selection bit
(TIC)
4
Transmit enable bit (TE)
5
Receive enable bit (RE)
6
Serial I/O1 mode
selection bit (SIOM)
7
Serial I/O1 enable bit
(SIOE)
0 : I/O port (P47)
1 : SRDY1 output pin
0 : Transmit buffer empty
1 : Transmit shift operating
completion
0 : Transmit disabled
1 : Transmit enabled
0 : Receive disabled
1 : Receive enabled
0 : UART
1 : Clock synchronous serial I/O
0
0 : Serial I/O1 disabled
(P44–P47 : I/O port)
1 : Serial I/O1 enabled
(P44–P47 : Serial I/O function pin)
0
0
0
0
0
Note 1 : In low-speed mode f(XCIN) is selected.
2 : In low-speed mode f(XCIN)/4 is selected.
Fig. 3.5.11 Structure of Serial I/O1 control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register (UARTCON) [Address : 1B16]
Name
B
Character
length
0
1
2
3
4
5
6
7
Function
0 : 8 bits
1 : 7 bits
0 : Parity checking disabled
1 : Parity checking enabled
0 : Even parity
1 : Odd parity
0 : 1 stop bit
1 : 2 stop bits
In output mode
0 : CMOS output
1 : N-channel open-drain
output
selection bit (CHAS)
Parity enable bit
(PARE)
Parity selection bit
(PARS)
Stop bit length selection
bit (STPS)
P45/TxD P-channel
output disable bit
(POFF)
Nothing is allocated for these bits. These are write
disabled bits. When these bits are read out, the
values are “1.”
At reset
R W
0
0
0
0
0
1
1
1
✕
✕
✕
Fig. 3.5.12 Structure of UART control register
3807 GROUP USER’S MANUAL
3-39
APPENDIX
3.5 List of registers
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator (BRG) [Address : 1C16]
Function
B
At reset
0 A count value of Baud rate generator is set.
?
1
?
2
?
3
?
4
?
5
?
6
?
7
?
R W
Fig. 3.5.13 Structure of Baud rate generator
Serial I/O2 control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register 1 (SIO2CON1) [Address : 1D16]
Name
B
Internal
synchronous
0
clock selection bits
1
2
Function
b2 b1 b0
0
0
0
0
1
1
0
0
1
1
1
1
0 : f(XIN)/8
1 : f(XIN)/16
0 : f(XIN)/32
1 : f(XIN)/64
0 : f(XIN)/128
1 : f(XIN)/256
(f(XCIN)/8)
(f(XCIN)/16)
(f(XCIN)/32)
(f(XCIN)/64)
(f(XCIN)/128)
(f(XCIN)/256)
0 : I/O port (P71, P72)
1 : SOUT2, SCLK2 output pin
0 : I/O port (P73)
SRDY2 output enable bit
1 : SRDY2 output pin
0
Transfer direction selection bit : LSB first
1 : MSB first
Serial I/O2 synchronous clock 0 : External clock
1 : Internal clock
selection bit
In output mode
P71/ SOUT2, P72/ SCLK2
0 : CMOS output
P-channel output disable bit
1 : N-channel open-drain output
0
0
0
3 Serial I/O2 port selection bit
0
4
0
5
6
7
Note : In low-speed mode ( ) is selected.
Fig. 3.5.14 Structure of Serial I/O2 control register 1
3-40
At reset
(Note)
3807 GROUP USER’S MANUAL
0
0
0
R W
APPENDIX
3.5 List of registers
Serial I/O2 control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register 2 (SIO2CON2) [Address : 1E16]
Name
B
Optional
transfer
bits
0
1
2
Function
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : 1 bit
1 : 2 bit
0 : 3 bit
1 : 4 bit
0 : 5 bit
1 : 6 bit
0 : 7 bit
1 : 8 bit
3 Nothing is allocated for these bits. These are write disabled bits.
4 When these bits are read out, the values are “0.”
5
0 : P51 I/O
6 Serial I/O2 I/O comparative
signal control bit
S
7 OUT2 pin control bit (P71)
1 : SCMP2 output
0 : Output active
1 : Output high impedance
At reset
R W
1
1
1
0
0
0
0
✕
✕
✕
0
Fig. 3.5.15 Structure of Serial I/O2 control register 2
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 register (SIO2) [Address : 1F16]
Function
B
At reset
0 A shift register for serial transmission and reception.
?
At transmitting : Set a transmission data.
● At receiving : Store a reception data.
1
?
2
?
3
?
4
?
5
?
6
?
7
?
R W
●
Fig. 3.5.16 Structure of Serial I/O2 register
3807 GROUP USER’S MANUAL
3-41
APPENDIX
3.5 List of registers
Timer X Low-order, Timer X High-order, Timer Y Low-order, Timer Y High-order
b7 b6 b5 b4 b3 b2 b1 b0
Timer X Low-order (TXL), Timer X High-order (TXH) [Address : 2016 , 2116]
Timer Y Low-order (TYL), Timer Y High-order (TYH) [Address : 2216 , 2316]
AAAAAAAAAAAAA
A
AA
AA
A
AAAAAAAAAAAAA
A
AA
AA
A
AAAAAAAAAAAAA
A
AA
AA
A
AAAAAAAAAAAAA
A
AA
AA
A
AAAAAAAAAAAAA
A
AA
AA
A
AAAAAAAAAAAAA
A
AA
AA
A
AAAAAAAAAAAAA
AAAAAAAAAAAAAA
AA
AA
A
AAAAAAAAAAAAAA
AA
AA
A
A
AA
AA
A
B
Function
●
0
●
1
2
●
3
4
A count value of each timer is set.
At writing
● A value set in this register is written to both a Timer and a
corresponding Timer latch at the same time, or to only a
Timer latch.
● A value is written to low-order first.
At reading
● When this register is read out, a value (count value) of a
corresponding Timer is read out.
●
A measurement value is read out in pulse period measurement mode and pulse width measurement mode.
●
A value is read out from high-order first.
At reset
R W
1
1
1
1
1
5
1
6
1
7
1
Fig. 3.5.17 Structure of Timer X Low-order, Timer X High-order, Timer Y Low-order, Timer Y High-order
Timer 1, Timer 3
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAA
A
AA
AA
A
AAAAAAAAAAAAA
A
AA
AA
A
AAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AA
AA
A
AA
AA
A
AAAAAAAAAAAAAA
AA
AA
A
Timer 1 (T1), Timer 3 (T3) [Address : 2416, 2616]
B
0
1
2
3
4
5
6
7
Function
●
●
●
A count value of each Timer is set.
A value set in this register is written to both each Timer
and a corresponding Timer latch at the same time.
When this register is read out, a value (count value) of a
corresponding Timer is read out.
Fig. 3.5.18 Structure of Timer 1, Timer 3
3-42
3807 GROUP USER’S MANUAL
At reset
1
1
1
1
1
1
1
1
R W
APPENDIX
3.5 List of registers
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAAAA
AAAAAAAAAAAAA
AA
AA
A
AA
AA
A
AAAAAAAAAAAAAA
AA
AA
A
AAAAAAAAAAAAAA
AA
AA
A
AAAAAAAAAAAAAA
AA
AA
A
Timer 2 (T2) [Address : 2516]
B
0
1
2
3
4
5
6
7
Function
●
●
●
A count value of Timer 2 is set.
A value set in this register is written to both Timer 2 and a
corresponding Timer 2 latch at the same time, or to only
Timer 2 latch.
When this register is read out, a value (count value) of a
corresponding Timer 2 is read out.
At reset
R W
1
0
0
0
0
0
0
0
Fig. 3.5.19 Structure of Timer 2
3807 GROUP USER’S MANUAL
3-43
APPENDIX
3.5 List of registers
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAA
AA
AA
A
AAAAAAA
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AA
AA
A
AAAAAAA
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAA
AA
AA
A
A
AAAAAAA
AAAAAAA
AA
AA
A
Timer X mode register (TXM) [Address : 2716]
B
Name
Timer X operating mode bits
0
1
2
Timer X write control bit
3
Output level latch
4
CNTR0 active edge switch bit
5
Function
At reset
R W
b2 b1 b0
0
0
0
0
1
0
0
1
1
0
0 : Timer • Event counter mode
1 : Pulse output mode
0 : Pulse period measurement mode
1 : Pulse width measurement mode
0 : Programmable waveform
generation mode
1 0 1 : Programmable one-shot
generation mode
1 1 0 : PWM mode
1 1 1 : Not available
0 : To a latch and a timer at the same time
1 : To only latch
0 : “L” output
1 : “H” output
It depends on the operating mode
of the Timer X (refer to Table 3.5.1).
b7 b6
Timer X count source selection 0
0
1
7
1
6 bits
0:
1:
0:
1:
f(XIN)/2
f(XIN)/16
f(XCIN)
Input signal from CNTR0 pin
0
0
0
0
0
0
0
0
Fig. 3.5.20 Structure of Timer X mode register
Timer Y mode register
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAA
AAAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
A
AAAAAAA
AAAAAAA
AA
AA
A
Timer Y mode register (TYM) [Address : 2816]
B
Name
Timer Y operating mode bits
0
1
2
3
4
5
Timer Y write control bit
Output level latch
CNTR1 active edge switch bit
Function
0
0
0
0
1
0
0
1
1
0
0 : Timer • Event counter mode
1 : Pulse output mode
0 : Pulse period measurement mode
1 : Pulse width measurement mode
0 : Programmable waveform
generation mode
1 0 1 : Programmable one-shot
generation mode
1 1 0 : PWM mode
1 1 1 : Not available
0 : To a latch and a timer at the same time
1 : To only latch
0 : “L” output
1 : “H” output
It depends on the operating mode
of the Timer Y (refer to Table 3.5.1).
b7 b6
Timer Y count source selection 0
0
1
7
1
6 bits
0:
1:
0:
1:
Fig. 3.5.21 Structure of Timer Y mode register
3-44
At reset
b2 b1 b0
3807 GROUP USER’S MANUAL
f(XIN)/2
f(XIN)/16
f(XCIN)
Input signal from CNTR1 pin
0
0
0
0
0
0
0
0
R W
APPENDIX
3.5 List of registers
Table. 3.5.1 Function of CNTR 0/CNTR 1 edge switch bit
Operating mode of
Timer X/Timer Y
Timer mode
“0”
“1”
Event counter mode
“0”
“1”
Pulse output mode
“0”
“1”
Pulse period measurement mode
•
•
•
•
•
•
•
•
•
•
•
“0”
•
•
“1”
Pulse width measurement mode
“0”
“1”
Programmable one-shot generation
mode
•
•
•
•
•
•
“0”
•
•
“1”
•
Function of CNTR 0/CNTR 1 edge switch bit
(bit 5 of each address 2716 and 28 16)
Generation of CNTR0 /CNTR1 interrupt request : Falling edge
(No effect on timer count)
Generation of CNTR 0/CNTR 1 interrupt request : Rising edge
(No effect on timer count)
Timer X/Timer Y : Count at rising edge
Generation of CNTR0 /CNTR1 interrupt request : Falling edge
Timer X/Timer Y : Count at falling edge
Generation of CNTR0/CNTR1 interrupt request : Rising edge
Start of pulse output : From “H” level
Generation of CNTR0 /CNTR1 interrupt request : Falling edge
Start of pulse output : From “L” level
Generation of CNTR 0/CNTR 1 interrupt request : Rising edge
Timer X/Timer Y : Measurement of a period between a falling
edge and the next falling edge
Generation of CNTR0 /CNTR1 interrupt request : Falling edge
Timer X/Timer Y : Measurement of a period between a rising
edge and the next rising edge
Generation of CNTR 0/CNTR 1 interrupt request : Rising edge
Timer X/Timer Y : Measurement of “H” level width
Generation of CNTR0 /CNTR1 interrupt request : Falling edge
Timer X/Timer Y : Measurement of “L” level width
Generation of CNTR 0/CNTR 1 interrupt request : Rising edge
Timer X/Timer Y : Start of a pulse output at “L” level, and
output of an one-shot “H” level pulse
Generation of CNTR0 /CNTR1 interrupt request : Falling edge
Timer X/Timer Y : Start of a pulse output at “H” level, and
output of an one-shot “L” level pulse
Generation of CNTR 0/CNTR 1 interrupt request : Rising edge
3807 GROUP USER’S MANUAL
3-45
APPENDIX
3.5 List of registers
Timer 123 mode register
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
A
AA
AA
A
Timer 123 mode register (T123M) [Address : 2916]
B
Name
Function
TOUT output active edge switch 0 : Start at outputting “H” signal
0 bit
1 : Start at outputting “L” signal
TOUT output control bit
0 : Disabled TOUT output
1
1 : Enabled TOUT output
Timer 2 write control bit
0 : To a latch and a timer at the same time
2
1 : To only latch
Timer 2 count source selection 0 : Output signal from Timer 1
3 bit
1 : f(XIN)/16
(Note 1)
At reset
0
0
0
0
Timer 3 count source selection 0 : Output signal from Timer 1
1 : f(XIN)/16
(Note 1)
b6 b5
Timer 1 count source selection 0
0
:
f(X
IN
)/16
(Note
1)
5 bit
0 1 : f(XIN)/2
(Note 2)
0
1 0 : f(XCIN)
1 1 : Not available
Nothing is allocated for this bit. It is a write disabled bit.
7 When this bit is read out, the value is “0.”
Note 1 : In low-speed mode f(XCIN)/16 is selected.
2 : In low-speed mode f(XCIN)/2 is selected.
0
4 bit
6
R W
0
0
✕
Fig. 3.5.22 Structure of Timer 123 mode register
Real time port register
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAA
A
AA
AA
A
AAAAAAAAAAAAA
A
AA
AA
A
AAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AA
AA
A
AA
AA
A
AAAAAAAAAAAAAA
AA
AA
A
Real time port register (RTP) [Address : 2A16]
B
0
1
2
3
4
5
6
7
●
●
●
Function
At reset
Sets the data to be output to the Real time port.
Makes it possible to write data into any of Real time port
registers 0 to 7 by specifying the Real time port data pointer
(R/W pointer) and writing data into this register.
Makes it possible to read any data of Real time port registers 0
to 7 by specifying the Real time port data pointer (R/W pointer)
and reading data from this register.
0
0
0
0
0
0
0
0
Fig. 3.5.23 Structure of Real time port register
3-46
3807 GROUP USER’S MANUAL
R W
APPENDIX
3.5 List of registers
Real time port control register 0
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAA
AA
AA
A
AAAAAAA
AAAAAAA
AAAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAA
AAAAAAAAA
AA
AA
A
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
Real time port control register 0 (RTPCON0) [Address : 2B16]
B
Name
Function
(Note 1)
Timer A, Timer B count source 0 : f(XIN)/2
0 selection bit
1 : f(XIN)/16
(Note 2)
Real time port • port allocation 0 : 4-4 division
(Corresponding ports to the Timer A :
selection bit
P82-P85
Corresponding ports to the Timer B :
P86, P87, P30, P31)
1
1 : 2-6 division
(Corresponding ports to the Timer A :
P82-P87
Corresponding ports to the Timer B :
P30, P31)
Timer A start trigger selection
bit
2
Timer A start trigger bit
3
Timer A count source stop bit
4
Timer B start trigger selection
bit
5
Timer B start trigger bit
6
Timer B count source stop bit
7
At reset
0
0
0 : Internal trigger
(occurs by writing “1” to bit 3.)
1 : External trigger
(occurs by inputting trigger to the INT4
pin.)
(Note 3)
0
0 : No operating by writing “0”
1 : Timer A starts counting by
writing “1”
(when bit 2 is set to “0”)
0
0 : Operating
(is set to “0” automatically at generating a start trigger.)
1 : Stop
0 : Internal trigger
(occurs by writing “1” to bit 6.)
1 : External trigger
(occurs by inputting trigger to the INT4
pin.)
(Note 3)
R W
(Note 4)
(Note 4)
1
0
(Note 4)
0 : No operating by writing “0”
1 : Timer B starts counting by
writing “1”
(when bit 5 is set to “0”)
0
0 : Operating
(is set to “0” automatically at generating a start trigger.)
1 : Stop
1
(Note 4)
Note 1: In low-speed mode f(XCIN)/2 is selected.
2: In low-speed mode f(XCIN)/16 is selected.
3: The rising edge or falling edge of the external trigger is switched by the INT4
interrupt edge selection bit (bit 4) of the interrupt edge selection register
(Address : 3A16.) (However, when the One-shot pulse generation mode is
selected, a rising/falling double edge trigger is generated in spite of the
contents of the INT4 interrupt edge selection bit.)
4: At a read operation, “0” is always read out.
Fig. 3.5.24 Structure of Real time port control register 0
3807 GROUP USER’S MANUAL
3-47
APPENDIX
3.5 List of registers
Real time port control register 1
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
AAAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAA
AA
AA
A
AAAAAAA
AAAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAA
AAAAAAAA
AA
AA
A
A
AAAAAAA
AAAAAAA
AA
AA
A
Real time port control register 1 (RTPCON1) [Address : 2C16]
B
Name
Timer A operating mode
0 selection bits
1
2
3
4
5
6
7
Function
0 0 : 8-repeated load mode
0 1 : 6-repeated load mode
1 0 : 5-repeated load mode
1 1 : One-shot pulse generation mode
Real time port data pointer A
0 : R/W pointer
switch bit
(Note 1) 1 : Output pointer
0 : Interrupts occur when a Real
Timer A interrupt mode
time port output pointer value
selection bit
becomes “0002.”
1 : Interrupt request occurs in
spite of a Real time port
output pointer value.
Real time port data pointer A b6 b5 b4
0 0 0 : Real time port register 0
0 0 1 : Real time port register 1
0 1 0 : Real time port register 2
0 1 1 : Real time port register 3
1 0 0 : Real time port register 4
1 0 1 : Real time port register 5
1 1 0 : Real time port register 6
(Note 2) 1 1 1 : Real time port register 7
Timer A write pointer
At reset
R W
b1 b0
0 : Specify the Timer A0 latch
1 : Specify the Timer A1 latch
0
0
0
0
1
1
1
1
Note 1: Use LDM or STA instruction for specifying the Real time port data pointer A
when this bit is switched. When this bit is read, “1” is always read out.
2: When these bits are read, an output pointer is read out.
Fig. 3.5.25 Structure of Real time port control register 1
3-48
3807 GROUP USER’S MANUAL
APPENDIX
3.5 List of registers
Real time port control register 2
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
AAAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAA
AA
AA
A
AAAAAAA
AAAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAA
AAAAAAAA
AA
AA
A
A
AAAAAAA
AAAAAAA
AA
AA
A
Real time port control register 2 (RTPCON2) [Address : 2D16]
B
Name
Timer B operating mode
0 selection bits
1
2
3
4
5
6
7
Function
0 0 : 8-repeated load mode
0 1 : 6-repeated load mode
1 0 : 5-repeated load mode
1 1 : One-shot pulse generation mode
Real time port data pointer B
0 : R/W pointer
switch bit
(Note 1) 1 : Output pointer
0 : Interrupts occur when a Real
Timer B interrupt mode
time port output pointer value
selection bit
becomes “0002.”
1 : Interrupt request occurs in
spite of a Real time port
output pointer value.
Real time port data pointer B b6 b5 b4
0 0 0 : Real time port register 0
0 0 1 : Real time port register 1
0 1 0 : Real time port register 2
0 1 1 : Real time port register 3
1 0 0 : Real time port register 4
1 0 1 : Real time port register 5
1 1 0 : Real time port register 6
(Note 2) 1 1 1 : Real time port register 7
Timer B write pointer
At reset
R W
b1 b0
0 : Specify the Timer B0 latch
1 : Specify the Timer B1 latch
0
0
0
0
1
1
1
1
Note 1: Use LDM or STA instruction for specifying the Real time port data pointer B
when this bit is switched. When this bit is read, “1” is always read out.
2: When these bits are read, an output pointer is read out.
Fig. 3.5.26 Structure of Real time port control register 2
3807 GROUP USER’S MANUAL
3-49
APPENDIX
3.5 List of registers
Real time port control register 3
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
AAAAAAAA
AAAAAAA
AA
AA
A
A
AAAAAAA
AA
AA
A
Real time port control register 3 (RTPCON3) [Address : 2E16]
B
Name
Function
Real time port output selection 0 : I/O port
1 : Real time output port
0 bit (P82)
Real time port output selection
1 bit (P83)
Real time port output selection
2 bit (P84)
At reset
0
0
0
Real time port output selection
0
Real time port output selection
0
3 bit (P85)
4 bit (P86)
Real time port output selection
5 bit (P87)
Real time port output selection
6 bit (P30)
Real time port output selection
7 bit (P31)
R W
0
0
0
Fig. 3.5.27 Structure of Real time port control register 3
Timer A Low-order, Timer A High-order, Timer B Low-order, Timer B High-order
b7 b6 b5 b4 b3 b2 b1 b0
Timer A Low-order (TAL), Timer A High-order (TAH) [Address : 2F16 , 3016]
Timer B Low-order (TBL), Timer B High-order (TBH) [Address : 3116 , 3216]
AAAAAAAAAAAAA
A
AA
AA
A
AAAAAAAAAAAAA
A
AA
AA
A
AAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AA
AA
A
AA
AA
A
AAAAAAAAAAAAAA
AA
AA
A
B
0
1
2
3
4
5
6
7
Function
●
●
●
Sets the real time output cycle.
Writing is performed in the order of low-order and high-order.
There are 2 reload latches. When the high-order side is written,
the next latch is automatically specified. The latch to be written
first can be specified by the Timer A or B write pointer (bit 7
of address 2C16 or 2D16).
Reading is performed in the order of high-order and low-order.
At a read operation, the value being counted is read out.
At reset
1
1
1
1
1
1
1
1
Fig. 3.5.28 Structure of Timer A Low-order, Timer A High-order, Timer B Low-order, Timer B High-order
3-50
3807 GROUP USER’S MANUAL
R W
APPENDIX
3.5 List of registers
D-A control register
b7 b6 b5 b4 b3 b2 b1 b0
D-A control register (DACON) [Address : 3316]
Name
B
DA1
output
enable bit
0
1
2
3
4
5
6
7
Function
At reset
0 : Output disable (P56)
1 : Output enable (DA1 output pin)
DA2 output enable bit
0 : Output disable (P57)
1 : Output enable (DA2 output pin)
0 : Output disable (P80)
DA3 output enable bit
1 : Output enable (DA3 output pin)
0 : Output disable (P81)
DA4 output enable bit
1 : Output enable (DA4 output pin)
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0.”
R W
0
0
0
0
0
0
0
0
✕
✕
✕
✕
Fig. 3.5.29 Structure of D-A control register
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register (ADCON) [Address : 3416]
B
Name
0 Analog input pin selection bits
1
2
3
4 AD conversion completion bit
5 ADVREF input switch bit
Function
b3 b2 b1 b0
0 0 0 0 : P73/SRDY2/ADT/AN0
0 0 0 1 : P74/AN1
0 0 1 0 : P75/AN2
0 0 1 1 : P76/AN3
0 1 0 0 : P77/AN4
0 1 0 1 : P60/AN5
0 1 1 0 : P61/AN6
0 1 1 1 : P62/AN7
1 0 0 0 : P63/CMPIN/AN8
1 0 0 1 : P64/CMPREF/AN9
1 0 1 0 : P65/DAVREF/AN10
1 0 1 1 : P80/DA3/AN11
1 1 0 0 : P81/DA4/AN12
When A-D trigger is invalid
0:Start conversion by writing to “0”
1:Conversion completed
When A-D trigger is valid
0:Conversion in progress
1:Conversion completed
0:Connect only at A-D conversion
1:Connect all time
At reset
R W
0
0
0
0
1
0
6 AD external trigger valid bit
0 : A-D external tirgger invalid
1 : A-D external tirgger valid
0
7 Interrupt source selection bit
0 : At conversion completed
1 : At ADT falling input
0
Fig. 3.5.30 Structure of A-D control register
3807 GROUP USER’S MANUAL
3-51
APPENDIX
3.5 List of registers
A-D conversion register
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (AD) [Address : 3516]
B
Function
0 The read-only register which A-D conversion results are stored.
1
2
3
4
5
6
7
At reset
?
?
?
?
?
?
?
?
R W
✕
✕
✕
✕
✕
✕
✕
✕
Fig. 3.5.31 Structure of A-D conversion register
D-Ai conversion register
b7 b6 b5 b4 b3 b2 b1 b0
D-Ai conversion register (DAi) (i = 1, 2, 3, 4) [Address : 3616, 3716, 3816, 3916]
B
Function
0 1. A value which is set to this register is converted
1
(D-A conversion).
2 2. The converted value is output from a corresponding DAi pin.
3
4
5
6
7
Fig. 3.5.32 Structure of D-Ai conversion register (i=1, 2, 3, 4)
3-52
3807 GROUP USER’S MANUAL
At reset
0
0
0
0
0
0
0
0
R W
APPENDIX
3.5 List of registers
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A16]
Name
B
0 INT0 interrupt edge
selection bit
1 INT1 interrupt edge
selection bit
INT
2 interrupt edge
2
selection bit
3 INT3 interrupt edge
selection bit
4 INT4 interrupt edge
selection bit
Timer
1/INT2 interrupt
5
source bit
6 Timer 2/INT3 interrupt
source bit
7 Timer 3/INT4 interrupt
source bit
Function
At reset
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
0
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
0 : INT2 interrupt
1 : Timer 1 interrupt
0
0 : INT3 interrupt
1 : Timer 2 interrupt
0
0 : INT4 interrupt
1 : Timer 3 interrupt
0
R W
0
0
0
0
Fig. 3.5.33 Structure of Interrupt edge selection register
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register (CPUM) [Address : 3B16]
B
0
Name
Processor mode bits
1
2
Stack page selection bit
3
XCOUT drivability selection bit
4
Port Xc switch bit
5
Main clock (XIN-XOUT) stop bit
Main clock division ratio
6 selection bits
7
Function
At reset
R W
b1 b0
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor
1 1 : Not available
0 : 0 page
1 : 1 page
0 : Low
1 : High
0 : I/O port function
1 : XCIN-XCOUT operating function
0 : Operating
1 : Stopped
0
0
(Note)
0
1
0
0
b7 b6
0
0
1
1
0 : φ = f(XIN)/2 (high-speed mode)
1 : φ = f(XIN)/8 (middle-speed mode)
0 : φ = f(XCIN)/2 (low-speed mode)
1 : Not available
1
0
Note : An initial value of bit 1 is determined by a level of the CNVss pin.
Fig. 3.5.34 Structure of CPU mode register
3807 GROUP USER’S MANUAL
3-53
APPENDIX
3.5 List of registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 1 (IREQ1) [Address : 3C16]
B
Function
Name
At reset
R W
0 INT0 interrupt request bit
0 : No interrupt request
1 : Interrupt request
0
✻
1 INT1 interrupt request bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0
✻
0
✻
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0
✻
0
✻
0 : No interrupt request
1 : Interrupt request
0
: No interrupt request
6 Timer 2/INT3 interrupt request
1 : Interrupt request
bit
7 Timer 3/INT4 interrupt request 0 : No interrupt request
1 : Interrupt request
bit
0
✻
0
✻
0
✻
2 Serial I/O1 receive interrupt
request bit
3 Serial I/O1 transmit interrupt
request bit
4 Timer X interrupt request bit
5 Timer Y interrupt request bit
✻ “0” is set by software, but not “1.”
Fig. 3.5.35 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 2 (IREQ2) [Address : 3D16]
Name
B
CNTR
0
interrupt
request bit
0
1
2
3
4
5
6
7
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
CNTR1 interrupt request bit
1 : Interrupt request
Serial I/O2 interrupt request bit 0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
Timer 1/INT2 interrupt
1 : Interrupt request
request bit
0 : No interrupt request
Timer A interrupt request bit
1 : Interrupt request
0 : No interrupt request
Timer B interrupt request bit
1 : Interrupt request
0 : No interrupt request
ADT/AD conversion
1 : Interrupt request
interrupt request bit
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0.”
✻ “0” is set by software, but not “1.”
Fig. 3.5.36 Structure of Interrupt request register 2
3-54
Function
3807 GROUP USER’S MANUAL
At reset
R W
0
✻
0
✻
0
✻
0
✻
0
✻
0
✻
0
✻
0
✕
APPENDIX
3.5 List of registers
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E16]
B
Function
Name
0 INT0 interrupt enable bit
1 INT1 interrupt enable bit
2 Serial I/O1 receive interrupt
enable bit
Serial
I/O1 transmit interrupt
3
enable bit
4 Timer X interrupt enable bit
5 Timer Y interrupt enable bit
6 Timer 2/INT3 interrupt enable
bit
Timer
3/INT4 interrupt enable
7
bit
At reset
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
R W
0
0
0
0
0
0
Fig. 3.5.37 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address : 3F16]
Name
B
0 CNTR0 interrupt enable bit
Function
At reset
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 CNTR1 interrupt enable bit
1 : Interrupt enabled
2 Serial I/O2 interrupt enable bit 0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
3 Timer 1/INT2 interrupt enable
bit
4 Timer A interrupt enable bit
5 Timer B interrupt enable bit
6 ADT/AD conversion interrupt
enable bit
Fix
this bit to “0.”
7
R W
0
0
0
0
0
0
Fig. 3.5.38 Structure of Interrupt control register 2
3807 GROUP USER’S MANUAL
3-55
APPENDIX
3.6 Mask ROM ordering method
3.6 Mask ROM ordering method
Mask ROM number
GZZ-SH11-00B<68A0>
740 FAMILY MASK ROM CONFIRMATION FORM
Receipt
SINGLE-CHIP MICROCOMPUTER M38073M4-XXXFP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
❈ Customer
TEL
(
Company
name
Date
issued
Date:
)
Issuance
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
❈ 1. Confirmation
Specify the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
EPROM address
000016
Product name
000F16
001016
407F16
408016
7FFD16
7FFE16
7FFF16
ASCII code :
‘M38073M4–’
data
ROM 16254 bytes
27512
In the address space of the microcomputer, the internal ROM
area is from address C08016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
000F16
001016
C07F16
C08016
FFFD16
FFFE16
FFFF16
ASCII code :
‘M38073M4–’
data
ROM 16254 bytes
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38073M4–”
must be entered in addresses 000016 to 000816. And
set the data “FF 16” in addresses 000916 to 000F 16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
(1/2)
3-56
3807 GROUP USER’S MANUAL
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘7’ = 3716
‘3’ = 3316
‘M’ = 4D16
‘4’ = 3416
Address
000816
000916
000A16
000B16
000C 16
000D 16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH11-00B<68A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38073M4-XXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program.
EPROM type
27256
27512
The pseudo-command
*= $8000
.BYTE ‘M38073M4–’
*= $0000
.BYTE
‘M38073M4–’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (80P6N for M38073M4-XXXFP) and attach it to the mask ROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
MHz
f(XIN) =
(2) Which function will you use the pins P41 /XCIN and P40 /XCOUT as P41 and P40, or X CIN and XCOUT?
Ports P41 and P4 0 function
XCIN and XCOUT function (external resonator)
❈ 4. Comments
(2/2)
3807 GROUP USER’S MANUAL
3-57
APPENDIX
3.7 Mark specification form
3-58
3807 GROUP USER’S MANUAL
APPENDIX
3.8 Package outline
3.8 Package outline
3807 GROUP USER’S MANUAL
3-59
APPENDIX
3.9 Machine instructions
3.9 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
ADC
(Note 1)
(Note 5)
When T = 0
A←A+M+C
When T = 1
M(X) ← M(X) + M + C
AND
(Note 1)
When TV= 0
A←A M
When T = 1 V
M(X) ← M(X) M
ASL
C←
7
0
←0
IMM
# OP n
A
# OP n
BIT, A
# OP n
ZP
# OP n
BIT, ZP
# OP n
Adds the carry, accumulator and memory contents. The results are entered into the
accumulator.
Adds the contents of the memory in the address indicated by index register X, the
contents of the memory specified by the addressing mode and the carry. The results are
entered into the memory at the address indicated by index register X.
69 2
2
65 3
2
“AND’s” the accumulator and memory contents.
The results are entered into the accumulator.
“AND’s” the contents of the memory of the address indicated by index register X and the
contents of the memory specified by the addressing mode. The results are entered into
the memory at the address indicated by index
register X.
29 2
2
25 3
2
06 5
2
0A 2
Shifts the contents of accumulator or contents
of memory one bit to the left. The low order bit
of the accumulator or memory is cleared and
the high order bit is shifted into the carry flag.
1
#
BBC
(Note 4)
Ab or Mb = 0?
Branches when the contents of the bit specified in the accumulator or memory is “0”.
13
+
20i
4
2
17
+
20i
5
3
BBS
(Note 4)
Ab or Mb = 1?
Branches when the contents of the bit specified in the accumulator or memory is “1”.
03
+ 4
20i
2
07
+
20i
5
3
BCC
(Note 4)
C = 0?
Branches when the contents of carry flag is
“0”.
BCS
(Note 4)
C = 1?
Branches when the contents of carry flag is
“1”.
BEQ
(Note 4)
Z = 1?
Branches when the contents of zero flag is “1”.
BIT
A
BMI
(Note 4)
N = 1?
Branches when the contents of negative flag is
“1”.
BNE
(Note 4)
Z = 0?
Branches when the contents of zero flag is “0”.
BPL
(Note 4)
N = 0?
Branches when the contents of negative flag is
“0”.
BRA
PC ← PC ± offset
Jumps to address specified by adding offset to
the program counter.
BRK
B←1
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
M(S) ← PS
S←S–1
PCL ← ADL
PCH ← ADH
Executes a software interrupt.
3-60
V
M
24 3
“AND’s” the contents of accumulator and
memory. The results are not entered anywhere.
00 7
3807 GROUP USER’S MANUAL
1
2
APPENDIX
3.9 Machine instructions
Addressing mode
ZP, X
ZP, Y
OP n
# OP n
75 4
ABS
ABS, X
ABS, Y
IND
# OP n
# OP n
# OP n
# OP n
2
6D 4
3 7D 5
3 79 5
35 4
2
2D 4
3 3D 5
3 39 5
16 6
2
0E 6
3 1E 7
3
2C 4
Processor status register
ZP, IND
# OP n
IND, X
IND, Y
REL
SP
# OP n
7
5
4
3
2
1
0
N V
T
B
D
I
Z
C
# OP n
# OP n
# OP n
3
61 6
2 71 6
2
N V
•
•
•
•
Z
C
3
21 6
2 31 6
2
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
90 2
2
•
•
•
•
•
•
•
•
B0 2
2
•
•
•
•
•
•
•
•
F0 2
2
•
•
•
•
•
•
•
•
M7 M6 •
•
•
•
Z
•
3
3807 GROUP USER’S MANUAL
#
6
30 2
2
•
•
•
•
•
•
•
•
D0 2
2
•
•
•
•
•
•
•
•
10 2
2
•
•
•
•
•
•
•
•
80 4
2
•
•
•
•
•
•
•
•
•
•
•
1
•
1
•
•
3-61
APPENDIX
3.9 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
IMM
# OP n
BVC
(Note 4)
V = 0?
Branches when the contents of overflow flag is
“0”.
BVS
(Note 4)
V = 1?
Branches when the contents of overflow flag is
“1”.
CLB
Ab or Mb ← 0
Clears the contents of the bit specified in the
accumulator or memory to “0”.
CLC
C←0
Clears the contents of the carry flag to “0”.
18 2
1
CLD
D←0
Clears the contents of decimal mode flag to
“0”.
D8 2
1
CLI
I←0
Clears the contents of interrupt disable flag to
“0”.
58 2
1
CLT
T←0
Clears the contents of index X mode flag to
“0”.
12 2
1
CLV
V←0
Clears the contents overflow flag to “0”.
B8 2
1
CMP
(Note 3)
When T = 0
A–M
When T = 1
M(X) – M
Compares the contents of accumulator and
memory.
Compares the contents of the memory specified by the addressing mode with the contents
of the address indicated by index register X.
COM
M←M
Forms a one’s complement of the contents of
memory, and stores it into memory.
CPX
X–M
Compares the contents of index register X and
memory.
E0 2
CPY
Y–M
Compares the contents of index register Y and
memory.
C0 2
DEC
A ← A – 1 or
M←M–1
Decrements the contents of the accumulator
or memory by 1.
DEX
X←X–1
Decrements the contents of index register X CA 2
by 1.
1
DEY
Y←Y–1
Decrements the contents of index register Y
by 1.
88 2
1
DIV
A ← (M(zz + X + 1),
M(zz + X)) / A
M(S) ← 1’s complememt
of Remainder
S←S–1
Divides the 16-bit data that is the contents of
M (zz + x + 1) for high byte and the contents of
M (zz + x) for low byte by the accumulator.
Stores the quotient in the accumulator and the
1’s complement of the remainder on the stack.
EOR
(Note 1)
When T = 0
–M
A←AV
“Exclusive-ORs” the contents of accumulator
and memory. The results are stored in the accumulator.
“Exclusive-ORs” the contents of the memory
specified by the addressing mode and the
contents of the memory at the address indicated by index register X. The results are
stored into the memory at the address indicated by index register X.
A
# OP n
BIT, A
# OP n
1B
+ 2
20i
C9 2
ZP
# OP n
BIT, ZP
# OP n
#
1F
+ 5
20i
2
1
C5 3
2
44 5
2
2
E4 3
2
2
C4 3
2
C6 5
2
45 3
2
E6 5
2
2
__
When T = 1
–M
M(X) ← M(X) V
1A 2
49 2
INC
A ← A + 1 or
M←M+1
Increments the contents of accumulator or
memory by 1.
INX
X←X+1
Increments the contents of index register X by
1.
E8 2
1
INY
Y←Y+1
Increments the contents of index register Y by
1.
C8 2
1
3-62
2
3A 2
3807 GROUP USER’S MANUAL
1
1
APPENDIX
3.9 Machine instructions
Addressing mode
ZP, X
OP n
D5 4
D6 6
ZP, Y
# OP n
2
2
ABS
# OP n
CD 4
ABS, X
# OP n
3 DD 5
ABS, Y
# OP n
3 D9 5
IND
# OP n
3
Processor status register
ZP, IND
# OP n
IND, X
# OP n
C1 6
IND, Y
# OP n
2 D1 6
REL
# OP n
2
SP
# OP n
7
#
6
5
4
3
2
1
0
N V
T
B
D
I
Z
C
50 2
2
•
•
•
•
•
•
•
•
70 2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
0
•
•
•
•
•
•
•
•
0
•
•
•
•
0
•
•
•
•
•
•
0
•
•
•
•
•
•
N
•
•
•
•
•
Z
C
N
•
•
•
•
•
Z
•
EC 4
3
N
•
•
•
•
•
Z
C
CC 4
3
N
•
•
•
•
•
Z
C
CE 6
3 DE 7
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
3
E2 16 2
55 4
2
4D 4
3 5D 5
3 59 5
F6 6
2
EE 6
3 FE 7
3
3
41 6
2 51 6
3807 GROUP USER’S MANUAL
2
3-63
APPENDIX
3.9 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
IMM
# OP n
JMP
If addressing mode is ABS
PCL ← ADL
PCH ← ADH
If addressing mode is IND
PCL ← M (AD H, ADL)
PCH ← M (ADH, AD L + 1)
If addressing mode is ZP, IND
PCL ← M(00, AD L)
PCH ← M(00, AD L + 1)
Jumps to the specified address.
JSR
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
After executing the above,
if addressing mode is ABS,
PCL ← ADL
PCH ← ADH
if addressing mode is SP,
PCL ← ADL
PCH ← FF
If addressing mode is ZP, IND,
PCL ← M(00, AD L)
PCH ← M(00, AD L + 1)
After storing contents of program counter in
stack, and jumps to the specified address.
LDA
(Note 2)
When T = 0
A←M
When T = 1
M(X) ← M
Load accumulator with contents of memory.
LDM
M ← nn
Load memory with immediate value.
LDX
X←M
Load index register X with contents of
memory.
A2 2
LDY
Y←M
Load index register Y with contents of
memory.
A0 2
LSR
7
0→
MUL
M(S) · A ← A ✕ M(zz + X)
S←S–1
Multiplies the accumulator with the contents of
memory specified by the zero page X addressing mode and stores the high byte of the result
on the stack and the low byte in the accumulator.
NOP
PC ← PC + 1
No operation.
ORA
(Note 1)
When T = 0
A←AVM
“Logical OR’s” the contents of memory and accumulator. The result is stored in the
accumulator.
“Logical OR’s” the contents of memory indicated by index register X and contents of
memory specified by the addressing mode.
The result is stored in the memory specified by
index register X.
0
→C
When T = 1
M(X) ← M(X) V M
3-64
A9 2
A
# OP n
BIT, A
# OP n
ZP
# OP n
BIT, ZP
# OP n
A5 3
2
3C 4
3
2
A6 3
2
2
A4 3
2
46 5
2
05 3
2
2
Load memory indicated by index register X
with contents of memory specified by the addressing mode.
4A 2
Shift the contents of accumulator or memory
to the right by one bit.
The low order bit of accumulator or memory is
stored in carry, 7th bit is cleared.
EA 2
3807 GROUP USER’S MANUAL
1
1
09 2
2
#
APPENDIX
3.9 Machine instructions
Addressing mode
ZP, X
OP n
B5 4
ZP, Y
# OP n
2
B6 4
ABS
# OP n
ABS, X
# OP n
4C 3
3
20 6
3
AD 4
3 BD 5
2 AE 4
ABS, Y
# OP n
3 B9 5
3
BE 5
IND
Processor status register
ZP, IND
IND, X
# OP n
# OP n
# OP n
6C 5
3 B2 4
2
02 7
2
3
IND, Y
# OP n
REL
# OP n
SP
# OP n
22 5
A1 6
2 B1 6
2
3
7
#
2
6
5
4
3
2
1
0
N V
T
B
D
I
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
B4 4
2
AC 4
3 BC 5
3
N
•
•
•
•
•
Z
•
56 6
2
4E 6
3 5E 7
3
0
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
62 15 2
15 4
2
0D 4
3 1D 5
3 19 5
3
01 6
2 11 6
3807 GROUP USER’S MANUAL
2
3-65
APPENDIX
3.9 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
IMM
OP n
# OP n
A
# OP n
BIT, A
# OP n
ZP
# OP n
BIT, ZP
# OP n
PHA
M(S) ← A
S←S–1
Saves the contents of the accumulator in
memory at the address indicated by the stack
pointer and decrements the contents of stack
pointer by 1.
48 3
1
PHP
M(S) ← PS
S←S–1
Saves the contents of the processor status
register in memory at the address indicated by
the stack pointer and decrements the contents
of the stack pointer by 1.
08 3
1
PLA
S←S+1
A ← M(S)
Increments the contents of the stack pointer
by 1 and restores the accumulator from the
memory at the address indicated by the stack
pointer.
68 4
1
PLP
S←S+1
PS ← M(S)
Increments the contents of stack pointer by 1
and restores the processor status register
from the memory at the address indicated by
the stack pointer.
28 4
1
ROL
7
←
Shifts the contents of the memory or accumulator to the left by one bit. The high order bit is
shifted into the carry flag and the carry flag is
shifted into the low order bit.
2A 2
1
26 5
2
Shifts the contents of the memory or accumulator to the right by one bit. The low order bit is
shifted into the carry flag and the carry flag is
shifted into the high order bit.
6A 2
1
66 5
2
82 8
2
E5 3
2
0
←C ←
ROR
7
C→
RRF
7
→
0
→
0
→
Rotates the contents of memory to the right by
4 bits.
RTI
S←S+1
PS ← M(S)
S←S+1
PCL ← M(S)
S←S+1
PCH ← M(S)
Returns from an interrupt routine to the main
routine.
40 6
1
RTS
S←S+1
PCL ← M(S)
S←S+1
PCH ← M(S)
Returns from a subroutine to the main routine.
60 6
1
SBC
(Note 1)
(Note 5)
When T = 0 _
A←A–M–C
Subtracts the contents of memory and
complement of carry flag from the contents of
accumulator. The results are stored into the
accumulator.
Subtracts contents of complement of carry flag
and contents of the memory indicated by the
addressing mode from the memory at the address indicated by index register X. The
results are stored into the memory of the address indicated by index register X.
When T = 1
_
M(X) ← M(X) – M – C
E9 2
SEB
Ab or Mb ← 1
Sets the specified bit in the accumulator or
memory to “1”.
SEC
C←1
Sets the contents of the carry flag to “1”.
38 2
1
SED
D←1
Sets the contents of the decimal mode flag to
“1”.
F8 2
1
SEI
I←1
Sets the contents of the interrupt disable flag
to “1”.
78 2
1
SET
T←1
Sets the contents of the index X mode flag to
“1”.
32 2
1
3-66
2
2
0B
+
20i
3807 GROUP USER’S MANUAL
1
0F
+ 5
20i
#
2
APPENDIX
3.9 Machine instructions
Addressing mode
ZP, X
OP n
ZP, Y
# OP n
ABS
# OP n
ABS, X
# OP n
ABS, Y
# OP n
IND
# OP n
Processor status register
ZP, IND
# OP n
IND, X
# OP n
IND, Y
# OP n
REL
# OP n
SP
# OP n
7
#
6
5
4
3
2
1
0
N V
T
B
D
I
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
(Value saved in stack)
36 6
2
2E 6
3 3E 7
3
N
•
•
•
•
•
Z
C
76 6
2
6E 6
3 7E 7
3
N
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
(Value saved in stack)
•
•
•
•
•
•
•
N V
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
•
•
•
•
1
•
•
•
•
•
•
•
•
1
•
•
•
•
1
•
•
•
•
•
•
F5 4
2
ED 4
3 FD 5
3 F9 5
3
E1 6
2 F1 6
3807 GROUP USER’S MANUAL
2
3-67
APPENDIX
3.9 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
STA
M←A
# OP n
Stores the contents of accumulator in memory.
Stops the oscillator.
STP
IMM
42 2
A
# OP n
BIT, A
# OP n
ZP
# OP n
BIT, ZP
# OP n
85 4
2
1
STX
M←X
Stores the contents of index register X in
memory.
86 4
2
STY
M←Y
Stores the contents of index register Y in
memory.
84 4
2
TAX
X←A
Transfers the contents of the accumulator to AA 2
index register X.
1
TAY
Y←A
Transfers the contents of the accumulator to A8 2
index register Y.
1
TST
M = 0?
Tests whether the contents of memory are “0”
or not.
64 3
2
TSX
X←S
Transfers the contents of the stack pointer to BA 2
index register X.
1
TXA
A←X
Transfers the contents of index register X to 8A 2
the accumulator.
1
TXS
S←X
Transfers the contents of index register X to 9A 2
the stack pointer.
1
TYA
A←Y
Transfers the contents of index register Y to
the accumulator.
98 2
1
Stops the internal clock.
C2 2
1
WIT
Notes 1
2
3
4
5
3-68
: The number of cycles “n” is increased by 3 when T is 1.
: The number of cycles “n” is increased by 2 when T is 1.
: The number of cycles “n” is increased by 1 when T is 1.
: The number of cycles “n” is increased by 2 when branching has occurred.
: N, V, and Z flags are invalid in decimal operation mode.
3807 GROUP USER’S MANUAL
#
APPENDIX
3.9 Machine instructions
Addressing mode
ZP, X
ZP, Y
OP n
# OP n
95 5
2
96 5
94 5
2
Symbol
ABS
ABS, X
ABS, Y
ZP, IND
IND
# OP n
# OP n
# OP n
# OP n
8D 5
3 9D 6
3 99 6
3
Processor status register
# OP n
IND, X
IND, Y
REL
# OP n
# OP n
# OP n
81 7
2 91 7
2
SP
# OP n
7
#
6
5
4
3
2
1
0
N V
T
B
D
I
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2 8E 5
3
•
•
•
•
•
•
•
•
8C 5
3
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
Contents
Symbol
IMP
IMM
A
Implied addressing mode
Immediate addressing mode
Accumulator or Accumulator addressing mode
BIT, A
Accumulator bit relative addressing mode
ZP
BIT, ZP
Zero page addressing mode
Zero page bit relative addressing mode
ZP, X
ZP, Y
ABS
ABS, X
ABS, Y
IND
Zero page X addressing mode
Zero page Y addressing mode
Absolute addressing mode
Absolute X addressing mode
Absolute Y addressing mode
Indirect absolute addressing mode
ZP, IND
Zero page indirect absolute addressing mode
IND, X
IND, Y
REL
SP
C
Z
I
D
B
T
V
N
Indirect X addressing mode
Indirect Y addressing mode
Relative addressing mode
Special page addressing mode
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
X-modified arithmetic mode flag
Overflow flag
Negative flag
+
–
V
V
–
V
–
←
X
Y
S
PC
PS
PCH
PCL
ADH
ADL
FF
nn
M
M(X)
M(S)
M(AD H, ADL)
M(00, AD L)
Ab
Mb
OP
n
#
3807 GROUP USER’S MANUAL
Contents
Addition
Subtraction
Logical OR
Logical AND
Logical exclusive OR
Negation
Shows direction of data flow
Index register X
Index register Y
Stack pointer
Program counter
Processor status register
8 high-order bits of program counter
8 low-order bits of program counter
8 high-order bits of address
8 low-order bits of address
FF in Hexadecimal notation
Immediate value
Memory specified by address designation of any addressing mode
Memory of address indicated by contents of index
register X
Memory of address indicated by contents of stack
pointer
Contents of memory at address indicated by ADH and
ADL, in ADH is 8 high-order bits and ADL is 8 low-order bits.
Contents of address indicated by zero page ADL
1 bit of accumulator
1 bit of memory
Opcode
Number of cycles
Number of bytes
3-69
APPENDIX
3.10 List of instruction codes
3.10 List of instruction codes
D 7 – D4
D3 – D 0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Hexadecimal
notation
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ORA
ABS
ASL
ABS
SEB
0, ZP
0000
0
BRK
JSR
ORA
IND, X ZP, IND
BBS
0, A
—
ORA
ZP
ASL
ZP
BBS
0, ZP
PHP
ORA
IMM
ASL
A
SEB
0, A
—
0001
1
BPL
ORA
IND, Y
CLT
BBC
0, A
—
ORA
ZP, X
ASL
ZP, X
BBC
0, ZP
CLC
ORA
ABS, Y
DEC
A
CLB
0, A
—
0010
2
JSR
ABS
AND
IND, X
JSR
SP
BBS
1, A
BIT
ZP
AND
ZP
ROL
ZP
BBS
1, ZP
PLP
AND
IMM
ROL
A
SEB
1, A
BIT
ABS
0011
3
BMI
AND
IND, Y
SET
BBC
1, A
—
AND
ZP, X
ROL
ZP, X
BBC
1, ZP
SEC
AND
ABS, Y
INC
A
CLB
1, A
LDM
ZP
0100
4
RTI
EOR
IND, X
STP
BBS
2, A
COM
ZP
EOR
ZP
LSR
ZP
BBS
2, ZP
PHA
EOR
IMM
LSR
A
SEB
2, A
JMP
ABS
0101
5
BVC
EOR
IND, Y
—
BBC
2, A
—
EOR
ZP, X
LSR
ZP, X
BBC
2, ZP
CLI
EOR
ABS, Y
—
CLB
2, A
—
0110
6
RTS
ADC
MUL
IND, X ZP, X
BBS
3, A
TST
ZP
ADC
ZP
ROR
ZP
BBS
3, ZP
PLA
ADC
IMM
ROR
A
SEB
3, A
JMP
IND
0111
7
BVS
ADC
IND, Y
—
BBC
3, A
—
ADC
ZP, X
ROR
ZP, X
BBC
3, ZP
SEI
ADC
ABS, Y
—
CLB
3, A
—
1000
8
BRA
STA
IND, X
RRF
ZP
BBS
4, A
STY
ZP
STA
ZP
STX
ZP
BBS
4, ZP
DEY
—
TXA
SEB
4, A
STY
ABS
STA
ABS
STX
ABS
SEB
4, ZP
1001
9
BCC
STA
IND, Y
—
BBC
4, A
STY
ZP, X
STA
ZP, X
STX
ZP, Y
BBC
4, ZP
TYA
STA
ABS, Y
TXS
CLB
4, A
—
STA
ABS, X
—
CLB
4, ZP
1010
A
LDY
IMM
LDA
IND, X
LDX
IMM
BBS
5, A
LDY
ZP
LDA
ZP
LDX
ZP
BBS
5, ZP
TAY
LDA
IMM
TAX
SEB
5, A
LDY
ABS
LDA
ABS
LDX
ABS
SEB
5, ZP
1011
B
BCS
LDA
JMP
IND, Y ZP, IND
BBC
5, A
LDY
ZP, X
LDA
ZP, X
LDX
ZP, Y
BBC
5, ZP
CLV
LDA
ABS, Y
TSX
CLB
5, A
1100
C
CPY
IMM
CMP
IND, X
WIT
BBS
6, A
CPY
ZP
CMP
ZP
DEC
ZP
BBS
6, ZP
INY
CMP
IMM
DEX
SEB
6, A
CPY
ABS
1101
D
BNE
CMP
IND, Y
—
BBC
6, A
—
CMP
ZP, X
DEC
ZP, X
BBC
6, ZP
CLD
CMP
ABS, Y
—
CLB
6, A
—
1110
E
CPX
IMM
SBC
DIV
IND, X ZP, X
BBS
7, A
CPX
ZP
SBC
ZP
INC
ZP
BBS
7, ZP
INX
SBC
IMM
NOP
SEB
7, A
CPX
ABS
1111
F
BEQ
SBC
IND, Y
BBC
7, A
—
SBC
ZP, X
INC
ZP, X
BBC
7, ZP
SED
SBC
ABS, Y
—
CLB
7, A
—
—
3-byte instruction
2-byte instruction
1-byte instruction
3-70
3807 GROUP USER’S MANUAL
CLB
ASL
ORA
ABS, X ABS, X 0, ZP
AND
ABS
ROL
ABS
SEB
1, ZP
CLB
ROL
AND
ABS, X ABS, X 1, ZP
EOR
ABS
LSR
ABS
SEB
2, ZP
CLB
LSR
EOR
ABS, X ABS, X 2, ZP
ADC
ABS
ROR
ABS
SEB
3, ZP
CLB
ROR
ADC
ABS, X ABS, X 3, ZP
CLB
LDX
LDA
LDY
ABS, X ABS, X ABS, Y 5, ZP
CMP
ABS
DEC
ABS
SEB
6, ZP
CLB
DEC
CMP
ABS, X ABS, X 6, ZP
SBC
ABS
INC
ABS
SEB
7, ZP
CLB
INC
SBC
ABS, X ABS, X 7, ZP
APPENDIX
3.11 SFR memory map
3.11 SFR memory map
000016
Port P0 (P0)
002016
Timer X (low-order) (TXL)
000116
Port P0 direction register (P0D)
002116
Timer X (high-order) (TXH)
000216
Port P1 (P1)
002216
Timer Y (low-order) (TYL)
000316
Port P1 direction register (P1D)
002316
Timer Y (high-order) (TYH)
000416
Port P2 (P2)
002416
Timer 1 (T1)
000516
Port P2 direction register (P2D)
002516
Timer 2 (T2)
000616
Port P3 (P3)
002616
Timer 3 (T3)
000716
Port P3 direction register (P3D)
002716
Timer X mode register (TXM)
000816
Port P4 (P4)
002816
Timer Y mode register (TYM)
000916
Port P4 direction register (P4D)
002916
Timer 123 mode register (T123M)
000A16
Port P5 (P5)
002A16
Real time port register (RTP)
000B16
Port P5 direction register (P5D)
002B16
Real time port control register 0 (RTPCON0)
000C16
Port P6 (P6)
002C16
Real time port control register 1 (RTPCON1)
000D16
Port P6 direction register (P6D)
002D16
Real time port control register 2 (RTPCON2)
000E16
Port P7 (P7)
002E16
Real time port control register 3 (RTPCON3)
000F16
Port P7 direction register (P7D)
002F16
Timer A (low-order) (TAL)
001016
Port P8 (P8)
003016
Timer A (high-order) (TAH)
001116
Port P8 direction register (P8D)
003116
Timer B (low-order) (TBL)
001216
003216
Timer B (high-order) (TBH)
001316
003316
D-A control register (DACON)
001416
Timer XY control register (TXYCON)
003416
A-D control register (ADCON)
001516
Port P2P3 control register (P2P3C)
003516
A-D conversion register (AD)
001616
Pull-up control register (PULL)
003616
D-A1 conversion register (DA1)
001716
Watchdog timer control register (WDTCON)
003716
D-A2 conversion register (DA2)
001816
Transmit/Receive buffer register (TB/RB)
003816
D-A3 conversion register (DA3)
001916
Serial I/O1 status register (SIO1STS)
003916
D-A4 conversion register (DA4)
001A16
Serial I/O1 control register (SIO1CON)
003A16
Interrupt edge selection register (INTEDGE)
001B16
UART control register (UARTCON)
003B16
CPU mode register (CPUM)
001C16
Baud rate generator (BRG)
003C16
Interrupt request register 1(IREQ1)
001D16
Serial I/O2 control register 1 (SIO2CON1)
003D16
Interrupt request register 2(IREQ2)
001E16
Serial I/O2 control register 2 (SIO2CON2)
003E16
Interrupt control register 1(ICON1)
001F16
Serial I/O2 register (SIO2)
003F16
Interrupt control register 2(ICON2)
3807 GROUP USER’S MANUAL
3-71
P62/AN7
P61/AN6
P60/AN5
P77/AN4
P76/AN3
P75/AN2
P74/AN1
P73/SRDY2/ADT/AN0
P72/SCLK2
P71/SOUT2
P70/SIN2
P57/DA2
P56/DA1
P55/CNTR1
P54/CNTR0
P53/INT4
P52/INT3
P51/SCMP2/INT2
P50/TOUT
P47/SRDY1
P46/SCLK1
P45/TXD
P44/RXD
P43/INT1
3-72
3807 GROUP USER’S MANUAL
21
22
23
24
13
14
15
16
17
18
19
20
74
11
12
73
10
P87/RTP5
P86/RTP4
P85/RTP3
P84/RTP2
P83/RTP1
P82/RTP0
P81/DA4/AN12
P80/DA3/AN11
VCC
ADVREF
AVSS
P65/DAVREF/AN10
P64/CMPREF /AN9
P63/CMPIN /AN8
CMPOUT
CMPVCC
5
6
7
8
9
1
2
3
4
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
60
59
61
62
63
64
P30/RTP6
P31/RTP7
P32/ONW
P33/RESETOUT
P34/CKOUT/φ
P35/SYNC
P36/WR
P37/RD
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/AD8
P11/AD9
P12/AD10
P13/AD11
P14/AD12
P15/AD13
P16/AD14
P17/AD15
APPENDIX
3.12 Pin configuration
3.12 Pin configuration
65
40
66
39
67
38
68
37
69
36
70
35
71
34
72
33
M38073M4-XXXFP
32
75
31
30
76
29
77
28
78
27
79
80
26
25
P20/DB0
P21/DB1
P22/DB2
P23/DB3
P24/DB4
P25/DB5
P26/DB6
P27/DB7
VSS
XOUT
XIN
P40/XCOUT
P41/XCIN
RESET
CNVSS
P42/INT0
MITSUBISHI SEMICONDUCTORS
USER’S MANUAL
3807 Group
Nov. First Edition 1996
Editioned by
Committee of editing of Mitsubishi Semiconductor USER’S MANUAL
Published by
Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission
of Mitsubishi Electric Corporation.
©1996 MITSUBISHI ELECTRIC CORPORATION
User’s Manual
3807 Group
H-EF458-A KI-9611 Printed in Japan (ROD)
© 1996 MITSUBISHI ELECTRIC CORPORATION.
New publication, effective Nov. 1996.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev.
No.
1.0
3807 Group User’s Manual
Revision Description
First Edition
Rev.
date
971101
(1/1)