RENESAS 3886

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 38000 SERIES
3886
Group
User’s Manual
Keep safety first in your circuit designs!
●
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with
appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
●
●
●
●
●
●
●
●
These materials are intended as a reference to assist our customers in the selection of the
Mitsubishi semiconductor product best suited to the customer's application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement
of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
All information contained in these materials, including product data, diagrams, charts,
programs and algorithms represents information on products at the time of publication of
these materials, and are subject to change by Mitsubishi Electric Corporation without notice
due to product improvements or other reasons. It is therefore recommended that customers
contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other
loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by
various means, including the Mitsubishi Semiconductor home page (http://
www.mitsubishichips.com).
When using any or all of the information contained in these materials, including product
data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information
as a total system before making a final decision on the applicability of the information and
products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability
or other loss resulting from the information contained herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use
in a device or system that is used under circumstances in which human life is potentially at
stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor when considering the use of a product contained herein
for any specific purposes, such as apparatus or systems for transportation, vehicular, medical,
aerospace, nuclear, or undersea repeater use.
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or
reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions,
they must be exported under a license from the Japanese government and cannot be
imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/
or the country of destination is prohibited.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for further details on these materials or the products contained therein.
REVISION DESCRIPTION LIST
Rev.
No.
3886 GROUP USER’S MANUAL
Revision Description
1.0
First Edition
990215
2.0
•Explanations of “1. Organization” of “BEFORE USING THIS MANUAL” are partly revised.
000922
•Page 1-2; Explanations of “●Power dissipation” of “FEATURES” are partly eliminated.
•Page 1-2; Explanations of “●Memory expansion possible” of “FEATURES” are partly revised.
•Page 1-2; Value of “●Program/Erase voltage” of “<Flash memory mode>” is revised.
•Page 1-2; “Operating temperature range” of “<Flash memory mode>” is added.
•Page 1-2; Explanations of “■Notes” are partly revised.
•Page 1-2; Explanations of “APPLICATION” are partly added.
•Page 1-3; Product name and note into Figure 1 are partly added.
•Page 1-3; Note into Figure 2 is added.
•Page 1-4; Figure 3 is added.
•Page 1-5; Figure 4 is partly revised.
•Page 1-8; Figure 5 is partly revised.
•Page 1-9; Explanations of “Packages” are partly added.
•Page 1-9; Figure 6 is partly revised.
•Page 1-9; Table 3 is partly added.
•Page 1-13; Figure 9 is partly revised.
•Page 1-14; Notes into Figure 10 are partly revised.
•Page 1-16; “Related SFRs” of “P42/INT0/OBF00, P43/INT1/OBF01” into Table 6 are partly
added.
•
Rev.
date
•Page 1-42; “[Port Control Register 2 (PCTL2)]” are added.
•Page 1-46; Explanations of “Bit 5” of “[I2c Clock Control Register (S2)]” are partly revised.
•Page 1-48; Bit name of bit 4 of “[I2c Status Register (S1)]” is revised.
•Page 1-49; Bit name of bit 4 into Figure 41 is revised.
•Page 1-54; Explanations of “(3) RESTART condition generating procedure” are partly revised.
•Page 1-54; “(6) STOP condition input at 7th clock pulse” is added.
•Page 1-54; “(7) ES0 bit switch” is added.
•Page 1-55; Figure 50 is partly revised.
(1/6)
REVISION DESCRIPTION LIST
Rev.
Revision Description
No.
2.0
3886 GROUP USER’S MANUAL
•Page 1-55; Figure 50 is partly revised.
Rev.
date
000922
•Page 1-60; Explanations of “RESET CIRCUIT” are partly revised.
•Page 1-60; Explanations of note into Figure 57 are added.
•Page 1-63; Note 2 into Figure 62 is added.
•Page 1-64; Figure 63 is partly revised.
•Page 1-65; Explanations of “PROCESSOR MODE” are partly revised.
•Page 1-65; Explanations of “(2) Memory expansion mode” are partly added.
•Page 1-65; Explanations of “(3) Microprocessor mode” are partly revised.
•Page 1-65; Explanations into Figure 64 are partly eliminated.
•Page 1-65; Note into Figure 65 is partly revised.
•Page 1-66; Explanations of “BUS CONTROL AT MEMORY EXPANSION” are partly revised.
•Page 1-69; Explanations of CNVss into Table 22 are partly revised.
•Page 1-70; Figure 68 is partly revised.
•Page 1-78; Figure 74 is partly revised.
•Page 1-79; Explanations of CNVss into Table 27 are partly revised.
•Page 1-83; Note is added.
•Page 1-85; Explanations of “Functional Outline” of “(3) Flash memory mode 3 (CPU reprogram
-ming mode)” are partly added.
•Page 1-85; Note into Figure 81 is partly eliminated.
•Page 1-86; Explanations of “<Beginning procedure>” of “●CPU reprogramming mode operation
procedure” are partly eliminated.
•Page 1-86; Figure 83 is partly revised.
•Page 1-89; Explanations of “A-D Converter” of “NOTES ON PROGRAMMING” are partly
eliminated.
•Page 1-90; Explanations of “Handling of Power Source Pins” of “NOTES ON USAGE” are
partly revised.
•Page 1-90; “Erasing of Flash memory version” is added.
(2/6)
REVISION DESCRIPTION LIST
Rev.
No.
2.0
3886 GROUP USER’S MANUAL
Revision Description
•Page 1-90; Explanations of “DATA REQUIRED FOR One Time PROM PROGRAMMING
ORDERS” are partly added.
•Page 1-91; “Interrupt” of “FUNCTIONAL DESCRIPTION SUPPLEMENT” is eliminated.
•Page 1-91; “Timing After Interrupt” of “FUNCTIONAL DESCRIPTION SUPPLEMENT” is
eliminated.
•“2.2 Interrupt” is added.
•“2.8 D-A converter” is added.
•“2.12 Clock generating circuit” is added.
•“2.13 Standby function” is added.
•“2.15 Flash memory” is added.
•Page 2-4; Bit attributes into Figure 2.1.4 are partly revised.
•Page 2-4; Bit attributes into Figure 2.1.5 are partly revised.
•Page 2-5; Explanations of “2.1.3 Port P4/P7 input register” are partly added.
•Page 2-6; Explanations of “●Reason” of “(1) Notes in stand-by state” are partly revised.
•Page 2-7; Explanations of “➁Input ports” and “③I/O ports” of “(1) Terminate unused pins” are
partly revised.
•Page 2-24; Figure 2.3.1 is partly revised.
•Page 2-27; Figure 2.3.6 is added.
•Page 2-31; Figure 2.3.12 is partly revised.
•Page 2-32; Figure 2.3.13 is partly revised.
•Page 2-41; Explanations of “2.3.4 Notes on timer” are partly revised.
•Page 2-75; Explanations of “(7) Transmit interrupt request when transmit enable bit is set” are
partly revised.
•Page 2-75; “(8) Transmit data writing” is added.
•Page 2-87; Clause name and explanations of “2.5.6 I2C-BUS communication usage example”
are partly revised.
•Page 2-88; Figure 2.5.17 is partly revised.
•Page 2-104; Explanations of “(2) Procedure for generating START condition” are partly added.
(3/6)
Rev.
date
000922
REVISION DESCRIPTION LIST
Rev.
No.
2.0
3886 GROUP USER’S MANUAL
Revision Description
•Page 2-104; Sub clause name and explanations of “(3) Procedure for generating RESTART
condition” are partly revised.
•Page 2-105; Explanations of “(6) STOP condition input at 7th clock pulse” are partly revised.
•Page 2-105; Clause of “Notes on programming for SMBUS interface” in Rev.1.0 is eliminated.
•Page 2-118; Explanations of note into Figure 2.7.9 are partly revised.
•Page 2-120; Explanations of “(2) A-D converter power source pin” of “2.7.4 Notes on A-D
converter” are partly eliminated.
•Page 2-120; Explanations of “(3) Clock frequency during A-D conversion” are partly eliminated.
•Page 2-128; Figure 2.9.1 is partly revised.
•Page 2-129; Figure 2.9.3 is partly revised.
•Page 2-132; Figure 2.9.8 is added.
•Page 2-138; Figure 2.10.3 is partly revised.
•Page 2-139; Figure 2.10.4 is partly revised.
•Page 2-141; Figure 2.11.2 is partly revised.
•Page 2-150; Explanations of “(3) Notes on using stop mode” are partly revised.
•Page 2-154; Figure 2.14.2 is partly revised.
•Page 2-156; Figure 2.14.4 is partly revised.
•Page 2-156; Figure 2.14.5 is partly revised.
•Page 2-157; Figure 2.14.6 is partly revised.
•Page 2-160; Figure 2.14.9 is partly revised.
•Page 2-160; Figure 2.14.10 is partly revised.
•Page 2-161; Figure 2.14.11 is partly revised.
•Page 2-165; Table 2.15.2 is partly revised.
•Paragraph of “Mask ROM confirmation” in Rev.1.0 is eliminated.
•Paragraph of “ROM programming confirmation form” in Rev.1.0 is eliminated.
•Paragraph of “Mark specification form” in Rev.1.0 is eliminated.
(4/6)
Rev.
date
000922
REVISION DESCRIPTION LIST
Rev.
No.
2.0
3886 GROUP USER’S MANUAL
Revision Description
For the mask ROM confirmation form, the ROM programming confirmation form, and the
mark specifications, refer to the “Mitsubishi MCU Technical Information” Homepage.
*Data required for ROM orders
(mask ROM confirmation forms, ROM programming confirmation forms)
http://www.infomicom.mesc.co.jp/38000/38ordere.htm
*Mark specification forms
http://www.infomicom.mesc.co.jp/mela/markform.htm
•Page 3-8; Limit of tw(RESET) into Table 3.1.11 is revised.
•Page 3-9; Limit of tw(RESET) into Table 3.1.12 is revised.
•Page 3-18; Figure 3.2.1 is partly revised.
•Page 3-18; Figure 3.2.2 is revised.
•Page 3-19; Figure 3.2.3 is revised.
•Page 3-19; Figure 3.2.4 is revised.
•Page 3-20; Figure 3.2.5 is revised.
•Page 3-20; Figure 3.2.6 is revised.
•Page 3-21; Figure 3.2.7 is revised.
•Page 3-24; Figure 3.2.12 is partly revised.
•Page 3-28; Explanations of “■Reason” of “(1) Notes in stand-by state” of “3.3.1 Notes on input
and output pins” are partly added.
•Page 3-29; Explanations of “➁Input ports” of “(1) Terminate unused pins” of “3.3.2 Termination
of unused pins” is partly revised.
•Page 3-29; Explanations of “③I/O ports” of “(1) Terminate unused pins” of “3.3.2 Termination
of unused pins” is partly revised.
•Page 3-30; Sub clause of “Setting of interrupt request bit and interrupt enable bit” in Rev. 1.0 is
eliminated.
•Page 3-31; “(3) Change of relevant register setting” of “3.3.3 Notes on interrupts” is added.
•Page 3-34; Explanations of “(5) Data transmission control with referring to transmit shift
register completion flag” are partly added.
(5/6)
Rev.
date
000922
REVISION DESCRIPTION LIST
Rev.
Revision Description
No.
2.0
3886 GROUP USER’S MANUAL
Rev.
date
•Page 3-34; Explanations of “(7) Transmit interrupt request when transmit enable bit is set” are 000922
partly revised.
•Page 3-35; Explanations of “(2) Procedure for generating START condition using multi-master”
are partly added.
•Page 3-36; Explanations of “(3) Procedure for generating RESTART condition” are partly
added.
•Page 3-36; Sub clause of “STOP condition generating procedure in master” is eliminated.
•Page 3-36; Explanations of “(6) STOP condition input at 7th clock pulse” are partly added.
•Page 3-37; Explanations of “(2) A-D converter power source pin” are partly revised.
•Page 3-37; Explanations of “(3) Clock frequency during A-D conversion” are partly revised.
•Page 3-37; “3.3.9 Notes on D-A converter” is added.
•Page 3-38; “3.3.12 Notes on CPU reprogramming mode” is added.
•Page 3-38; “3.3.13 Notes on using stop mode” is added.
•Page 3-39; “3.3.14 Notes on wait mode” is added.
•Page 3-39; Explanations of “3.3.16 Notes on restarting oscillation” are partly revised.
•Page 3-41; Figure 3.3.10 is partly revised.
•Page 3-50; Figure 3.5.1 is partly revised.
•Page 3-50; Figure 3.5.2 is partly revised.
•Page 3-62; Bit attributes into Figure 3.5.22 are partly revised.
•Page 3-64; Bit attributes into Figure 3.5.25 are partly revised.
•Page 3-64; Bit attributes into Figure 3.5.26 are partly revised.
•Page 3-70; Figure 3.5.37 is partly revised.
•Page 3-73; Figure 3.5.42 is added.
•Page 3-74; Figure 3.5.43 is added.
•Page 3-87; Product name and note into Figure 3.10.1 are partly added.
•Page 3-87; Note into Figure 3.10.2 is added.
•Page 3-88; Figure 3.10.3 is added.
(6/6)
Preface
This user’s manual describes Mitsubishi’s CMOS 8bit microcomputers 3886 Group.
After reading this manual, the user should have a
through knowledge of the functions and features of
the 3886 Group, and should be able to fully utilize
the product. The manual starts with specifications
and ends with application examples.
For details of software, refer to the “740 Family
Software Manual.”
For details of development support tools, refer to the
“Mitsubishi Microcomputer Development Support Tools”
Homepage (http://www.tool-spt.mesc.co.jp/index_e.htm).
BEFORE USING THIS MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development. Chapter 3 also includes necessary information for
systems development. You must refer to that chapter.
1. Organization
● CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
● CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on
setting examples of relevant registers.
● CHAPTER 3 APPENDIX
This chapter includes necessary information for systems development using the microcomputer, such
as the electrical characteristics, the notes, and the list of registers.
✽For the mask ROM confirmation form, the ROM programming confirmation form, and the mark
specifications, refer to the “Mitsubishi MCU Technical Information” Homepage (http://
www.infomicom.mesc.co.jp/).
2. Structure of register
The figure of each register structure describes its functions, contents at reset, and attributes as follows :
(Note 2)
Bit attributes
Bits
(Note 1)
Contents immediately after reset release
b7 b6 b5 b4 b3 b2 b1 b0
0
CPU mode register (CPUM) [Address : 3B16]
B
Name
0
Processor mode bits
1
Function
b1 b0
0 0 : Single-chip mode
01:
1 0 : Not available
11:
0 : 0 page
1 : 1 page
At reset
R W
0
0
0
2
Stack page selection bit
3
0
✕
4
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
0
✕
5
Fix this bit to “0.”
1
6
Main clock (XIN-XOUT) stop bit
7
Internal system clock selection bit
: Bit in which nothing is arranged
0 : Operating
1 : Stopped
0 : XIN-XOUT selected
1 : XCIN-XCOUT selected
✽
✽
: Bit that is not used for control of the corresponding function
Note 1:. Contents immediately after reset release
0....... “0” at reset release
1....... “1” at reset release
?....... Undefined at reset release
✽.......Contents determined by option at reset release
Note 2: Bit attributes......... The attributes of control register bits are classified into 3 bytes : read-only, writeonly and read and write. In the figure, these attributes are represented as follows :
R....... Read
...... Read enabled
✕.......Read disabled
W......Write
..... Write enabled
✕...... Write disabled
Table of contents
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................ 1-2
FEATURES .................................................................................................................................... 1-2
APPLICATION ................................................................................................................................ 1-2
PIN CONFIGURATION .................................................................................................................. 1-3
FUNCTIONAL BLOCK .................................................................................................................. 1-5
PIN DESCRIPTION ........................................................................................................................ 1-6
PART NUMBERING ....................................................................................................................... 1-8
GROUP EXPANSION .................................................................................................................... 1-9
Memory Type ............................................................................................................................ 1-9
Memory Size ............................................................................................................................. 1-9
Packages ................................................................................................................................... 1-9
FUNCTIONAL DESCRIPTION .................................................................................................... 1-10
Central Processing Unit (CPU) ............................................................................................ 1-10
Memory .................................................................................................................................... 1-14
I/O Ports .................................................................................................................................. 1-16
Interrupts ................................................................................................................................. 1-23
Key Input Interrupt (key-on Wake Up) ................................................................................ 1-27
Timers ...................................................................................................................................... 1-28
Serial I/O ................................................................................................................................. 1-30
Pulse Width Modulation (PWM) Output Circuit .................................................................. 1-36
Bus Interface ........................................................................................................................... 1-39
Multi-master I 2C-BUS Interface ............................................................................................. 1-44
A-D Converter ......................................................................................................................... 1-55
D-A Converter ......................................................................................................................... 1-57
Comparator Circuit ................................................................................................................. 1-58
Watchdog Timer ..................................................................................................................... 1-59
Reset Circuit ........................................................................................................................... 1-60
Clock Generating Circuit ....................................................................................................... 1-62
Processor Mode ...................................................................................................................... 1-65
Bus Control at Memory Expansion ...................................................................................... 1-66
EPROM Mode ......................................................................................................................... 1-67
Flash Memory Mode .............................................................................................................. 1-68
NOTES ON PROGRAMMING ..................................................................................................... 1-89
NOTES ON USAGE ..................................................................................................................... 1-90
DATA REQUIRED FOR MASK ORDERS ................................................................................ 1-90
DATA REQUIRED FOR ONE TIME PROM PROGRAMMING ORDERS ............................. 1-90
FUNCTIONAL DESCRIPTION SUPPLEMENT ......................................................................... 1-91
CHAPTER 2 APPLICATION
2.1 I/O port ..................................................................................................................................... 2-2
2.1.1 Memory map ................................................................................................................... 2-2
2.1.2 Relevant registers .......................................................................................................... 2-3
2.1.3 Port P4/P7 input register .............................................................................................. 2-5
2.1.4 Handling of unused pins ............................................................................................... 2-5
2.1.5 Notes on input and output pins ................................................................................... 2-6
2.1.6 Termination of unused pins .......................................................................................... 2-7
3886 Group User’s Manual
i
Table of contents
2.2 Interrupt ................................................................................................................................... 2-8
2.2.1 Memory map ................................................................................................................... 2-8
2.2.2 Relevant registers .......................................................................................................... 2-8
2.2.3 Interrupt source ............................................................................................................ 2-12
2.2.4 Interrupt operation ........................................................................................................ 2-13
2.2.5 Interrupt control ............................................................................................................ 2-16
2.2.6 INT interrupt .................................................................................................................. 2-19
2.2.7 Key input interrupt ....................................................................................................... 2-20
2.2.8 Notes on interrupts ...................................................................................................... 2-22
2.3 Timer ....................................................................................................................................... 2-24
2.3.1 Memory map ................................................................................................................. 2-24
2.3.2 Relevant registers ........................................................................................................ 2-24
2.3.3 Timer application examples ........................................................................................ 2-30
2.3.4 Notes on timer .............................................................................................................. 2-41
2.4 Serial I/O ................................................................................................................................ 2-42
2.4.1 Memory map ................................................................................................................. 2-42
2.4.2 Relevant registers ........................................................................................................ 2-43
2.4.3 Serial I/O connection examples ................................................................................. 2-50
2.4.4 Setting of serial I/O transfer data format ................................................................. 2-52
2.4.5 Serial I/O application examples ................................................................................. 2-53
2.4.6 Notes on serial I/O ...................................................................................................... 2-73
2.5 Multi-master I 2C-BUS interface ......................................................................................... 2-76
2.5.1 Memory map ................................................................................................................. 2-76
2.5.2 Relevant registers ........................................................................................................ 2-76
2.5.3 I 2C-BUS overview ......................................................................................................... 2-83
2.5.4 Communication format ................................................................................................. 2-84
2.5.5 Synchronization and Arbitration lost .......................................................................... 2-85
2.5.6 I 2C-BUS communication usage example ................................................................... 2-87
2.5.7 Notes on multi-master I 2C-BUS interface ............................................................... 2-103
2.6 PWM ...................................................................................................................................... 2-106
2.6.1 Memory map ............................................................................................................... 2-106
2.6.2 Relevant registers ...................................................................................................... 2-107
2.6.3 PWM application example ......................................................................................... 2-111
2.6.4 Notes on PWM ........................................................................................................... 2-113
2.7 A-D converter ..................................................................................................................... 2-114
2.7.1 Memory map ............................................................................................................... 2-114
2.7.2 Relevant registers ...................................................................................................... 2-114
2.7.3 A-D converter application examples ........................................................................ 2-118
2.7.4 Notes on A-D converter ............................................................................................ 2-120
2.8 D-A Converter ..................................................................................................................... 2-121
2.8.1 Memory map ............................................................................................................... 2-121
2.8.2 Relevant registers ...................................................................................................... 2-122
2.8.3 D-A converter application example .......................................................................... 2-124
2.8.4 Notes on D-A converter ............................................................................................ 2-127
2.9 Bus interface ...................................................................................................................... 2-128
2.9.1 Memory map ............................................................................................................... 2-128
2.9.2 Relevant registers ...................................................................................................... 2-129
2.9.3 Bus interface overview .............................................................................................. 2-133
2.9.4 Input/Output operation ............................................................................................... 2-134
2.9.5 Relevant registers setting ......................................................................................... 2-135
2.10 Watchdog timer ................................................................................................................ 2-137
2.10.1 Memory map ............................................................................................................. 2-137
ii
3886 Group User’s Manual
Table of contents
2.10.2 Relevant registers .................................................................................................... 2-137
2.10.3 Watchdog timer application examples ................................................................. 2-139
2.10.4 Notes on watchdog timer ........................................................................................ 2-140
2.11 Reset .................................................................................................................................. 2-141
2.11.1 Connection example of reset IC ............................................................................ 2-141
2.11.2 Notes on RESET pin ............................................................................................... 2-142
2.12 Clock generating circuit ................................................................................................ 2-143
2.12.1 Relevant registers .................................................................................................... 2-143
2.12.2 Clock generating circuit application example ....................................................... 2-144
2.13 Standby function ............................................................................................................. 2-147
2.13.1 Stop mode ................................................................................................................. 2-147
2.13.2 Wait mode ................................................................................................................. 2-151
2.14 Processor mode ............................................................................................................... 2-154
2.14.1 Memory map ............................................................................................................. 2-154
2.14.2 Relevant registers .................................................................................................... 2-154
2.14.3 Processor mode usage examples ........................................................................ 2-155
2.15 Flash memory ................................................................................................................... 2-162
2.15.1 Overview .................................................................................................................... 2-162
2.15.2 Memory map ............................................................................................................. 2-162
2.15.3 Relevant registers .................................................................................................... 2-163
2.15.4 Parallel I/O mode ..................................................................................................... 2-164
2.15.5 Serial I/O mode ........................................................................................................ 2-165
2.15.6 CPU reprogramming mode ..................................................................................... 2-166
2.15.7 Flash memory mode application examples .......................................................... 2-167
2.15.8 Notes on CPU reprogramming mode .................................................................... 2-176
CHAPTER 3 APPENDIX
3.1 Electrical characteristics ..................................................................................................... 3-2
3.1.1 Absolute maximum ratings ............................................................................................ 3-2
3.1.2 Recommended operating conditions ............................................................................ 3-3
3.1.3 Electrical characteristics ................................................................................................ 3-5
3.1.4 A-D converter characteristics ....................................................................................... 3-7
3.1.5 D-A converter characteristics ....................................................................................... 3-7
3.1.6 Comparator characteristics ........................................................................................... 3-7
3.1.7 Timing requirements ...................................................................................................... 3-8
3.1.8 Timing requirements for system bus interface ......................................................... 3-10
3.1.9 Switching characteristics ............................................................................................. 3-11
3.1.10 Switching characteristics for system bus interface ............................................... 3-11
3.1.11 Timing requirements in memory expansion mode and microprocessor mode .. 3-12
3.1.12 Switching characteristics in memory expansion mode and microprocessor mode .. 3-12
3.1.13 Multi-master I 2C-BUS bus line characteristics ....................................................... 3-17
3.2 Standard characteristics .................................................................................................... 3-18
3.2.1 Power source current characteristic examples ........................................................ 3-18
3.2.2 Port standard characteristic examples ...................................................................... 3-22
3.2.3 Input port standard characteristic examples ............................................................ 3-25
3.2.4 A-D conversion standard characteristics ................................................................... 3-26
3.2.5 D-A conversion standard characteristics ................................................................... 3-27
3.3 Notes on use ........................................................................................................................ 3-28
3.3.1 Notes on input and output pins ................................................................................. 3-28
3.3.2 Termination of unused pins ........................................................................................ 3-29
3.3.3 Notes on interrupts ...................................................................................................... 3-30
3.3.4 Notes on timer .............................................................................................................. 3-31
3886 Group User’s Manual
iii
Table of contents
3.3.5 Notes on serial I/O ...................................................................................................... 3-32
3.3.6 Notes on multi-master I 2C-BUS interface ................................................................. 3-35
3.3.7 Notes on PWM ............................................................................................................. 3-37
3.3.8 Notes on A-D converter .............................................................................................. 3-37
3.3.9 Notes on D-A converter .............................................................................................. 3-37
3.3.10 Notes on watchdog timer .......................................................................................... 3-38
3.3.11 Notes on RESET pin ................................................................................................. 3-38
3.3.12 Notes on CPU reprogramming mode ...................................................................... 3-38
3.3.13 Notes on using stop mode ....................................................................................... 3-38
3.3.14 Notes on wait mode .................................................................................................. 3-39
3.3.15 Notes on low-speed operation mode ...................................................................... 3-39
3.3.16 Notes on restarting oscillation .................................................................................. 3-39
3.3.17 Notes on programming .............................................................................................. 3-40
3.3.18 Programming and test of built-in PROM version ................................................... 3-42
3.3.19 Notes on built-in PROM version .............................................................................. 3-43
3.4 Countermeasures against noise ...................................................................................... 3-44
3.4.1 Shortest wiring length .................................................................................................. 3-44
3.4.2 Connection of bypass capacitor across Vss line and Vcc line ............................. 3-46
3.4.3 Wiring to analog input pins ........................................................................................ 3-46
3.4.4 Oscillator concerns ....................................................................................................... 3-47
3.4.5 Setup for I/O ports ....................................................................................................... 3-48
3.4.6 Providing of watchdog timer function by software .................................................. 3-49
3.5 List of registers ................................................................................................................... 3-50
3.6 Package outline ................................................................................................................... 3-75
3.7 Machine instructions .......................................................................................................... 3-76
3.8 List of instruction code ..................................................................................................... 3-87
3.9 SFR memory map ................................................................................................................ 3-88
3.10 Pin configurations ............................................................................................................. 3-89
iv
3886 Group User’s Manual
List of figures
List of figures
CHAPTER 1 HARDWARE
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1 M38867M8A-XXXHP, M38867E8AHP pin configuration ................................................ 1-3
2 M38867E8AFS pin configuration ...................................................................................... 1-3
3 M38869MFA-XXXGP/HP, M38869FFAGP/HP pin configuration ................................... 1-4
4 Functional block diagram ................................................................................................... 1-5
5 Part numbering .................................................................................................................... 1-8
6 Memory expansion plan ..................................................................................................... 1-9
7 740 Family CPU register structure ................................................................................. 1-10
8 Register push and pop at interrupt generation and subroutine call ......................... 1-11
9 Structure of CPU mode register ..................................................................................... 1-13
10 Memory map diagram .................................................................................................... 1-14
11 Memory map of special function register (SFR) ........................................................ 1-15
12 Port block diagram (1) ................................................................................................... 1-18
13 Port block diagram (2) ................................................................................................... 1-19
14 Port block diagram (3) ................................................................................................... 1-20
15 Port block diagram (4) ................................................................................................... 1-21
16 Structure of port I/O related registers ......................................................................... 1-22
17 Interrupt control ............................................................................................................... 1-25
18 Structure of interrupt-related registers (1) .................................................................. 1-25
19 Structure of interrupt-related registers (2) .................................................................. 1-26
20 Connection example when using key input interrupt and port P3 block diagram ... 1-27
21 Structure of timer XY mode register ............................................................................ 1-28
22 Block diagram of timer X, timer Y, timer 1, and timer 2 ......................................... 1-29
23 Block diagram of clock synchronous serial I/O1 ........................................................ 1-30
24 Operation of clock synchronous serial I/O1 function ................................................ 1-30
25 Block diagram of UART serial I/O1 ............................................................................. 1-31
26 Operation of UART serial I/O1 function ...................................................................... 1-32
27 Structure of serial I/O1 control registers ..................................................................... 1-33
28 Structure of serial I/O2 control register ....................................................................... 1-34
29 Block diagram of serial I/O2 function .......................................................................... 1-34
30 Timing of serial I/O2 function ....................................................................................... 1-35
31 PWM block diagram (PWM0) ........................................................................................ 1-36
32 PWM timing ..................................................................................................................... 1-37
33 14-bit PWM timing (PWM0) .......................................................................................... 1-38
34 Interrupt request circuit of data bus buffer ................................................................. 1-39
35 Structure of bus interface related register .................................................................. 1-40
36 Bus interface device block diagram ............................................................................. 1-41
37 Block diagram of multi-master I 2C-BUS interface ...................................................... 1-44
38 Structure of I 2C address register .................................................................................. 1-45
39 Structure of I 2C clock control register ......................................................................... 1-46
40 Structure of I 2C control register .................................................................................... 1-47
41 Structure of I 2C status register ..................................................................................... 1-49
42 Interrupt request signal generating timing .................................................................. 1-49
43 START condition generating timing diagram .............................................................. 1-50
44 STOP condition generating timing diagram ................................................................ 1-50
45 START condition detecting timing diagram ................................................................. 1-50
3886 Group User’s Manual
v
List of figures
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STOP condition detecting timing diagram ................................................................... 1-50
Structure of I2C START/STOP condition control register ......................................... 1-52
Address data communication format ............................................................................ 1-52
Structure of AD/DA control register ............................................................................. 1-55
Structure of 10-bit A-D mode reading ......................................................................... 1-55
Block diagram of A-D converter ................................................................................... 1-56
Block diagram of D-A converter ................................................................................... 1-57
Equivalent connection circuit of D-A converter (DA1) ............................................... 1-57
Comparator circuit .......................................................................................................... 1-58
Block diagram of Watchdog timer ................................................................................ 1-59
Structure of Watchdog timer control register ............................................................. 1-59
Reset circuit example .................................................................................................... 1-60
Reset sequence .............................................................................................................. 1-60
Internal status at reset .................................................................................................. 1-61
Ceramic resonator circuit .............................................................................................. 1-62
External clock input circuit ............................................................................................ 1-62
System clock generating circuit block diagram (Single-chip mode) ........................ 1-63
State transitions of system clock ................................................................................. 1-64
Memory maps in various processor modes ................................................................ 1-65
Structure of CPU mode register ................................................................................... 1-65
ONW function timing ...................................................................................................... 1-66
Programming and testing of One Time PROM version ............................................ 1-67
Pin connection of M38869FFAHP/GP when operating in parallel input/output mode ... 1-70
Read timing ..................................................................................................................... 1-71
Timings during reading .................................................................................................. 1-72
Input/output timings during programming (Verify data is output at the same timing as
for read.) ......................................................................................................................... 1-73
Input/output timings during erasing (verify data is output at the same timing as for
read.) ............................................................................................................................... 1-74
Programming/Erasing algorithm flow chart ................................................................. 1-76
Pin connection of M38869FFAHP/GP when operating in serial I/O mode ............ 1-78
Timings during reading .................................................................................................. 1-80
Timings during programming ......................................................................................... 1-81
Timings during program verify ...................................................................................... 1-81
Timings at erasing .......................................................................................................... 1-82
Timings during erase verify ........................................................................................... 1-82
Timings at error checking .............................................................................................. 1-83
Flash memory control register bit configuration ......................................................... 1-85
Flash command register bit configuration ................................................................... 1-86
CPU mode register bit configuration in CPU rewriting mode .................................. 1-86
Flowchart of program/erase operation at CPU reprogramming mode .................... 1-88
A-D conversion equivalent circuit ................................................................................. 1-92
A-D conversion timing chart .......................................................................................... 1-92
CHAPTER 2 APPLICATION
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2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.2.1
Memory map of registers relevant to I/O port ......................................................... 2-2
Structure of Port Pi (i = 0 to 8) ................................................................................. 2-3
Structure of Port Pi direction register (i = 0 to 8) .................................................. 2-3
Structure of Port control register 1 ............................................................................ 2-4
Structure of Port control register 2 ............................................................................ 2-4
Memory map of registers relevant to interrupt ........................................................ 2-8
3886 Group User’s Manual
List of figures
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2.2.2 Structure of Port control register 2 ............................................................................ 2-8
2.2.3 Structure of Interrupt source selection register ....................................................... 2-9
2.2.4 Structure of Interrupt edge selection register .......................................................... 2-9
2.2.5 Structure of Interrupt request register 1 ................................................................. 2-10
2.2.6 Structure of Interrupt request register 2 ................................................................. 2-10
2.2.7 Structure of Interrupt control register 1 .................................................................. 2-11
2.2.8 Structure of Interrupt control register 2 .................................................................. 2-11
2.2.9 Interrupt operation diagram ....................................................................................... 2-13
2.2.10 Changes of stack pointer and program counter upon acceptance of interrupt request .. 2-14
2.2.11 Time up to execution of interrupt processing routine ......................................... 2-15
2.2.12 Timing chart after acceptance of interrupt request ............................................. 2-15
2.2.13 Interrupt control diagram ......................................................................................... 2-16
2.2.14 Example of multiple interrupts ................................................................................ 2-18
2.2.15 Connection example and port P3 block diagram when using key input interrupt .. 2-20
2.2.16 Registers setting relevant to key input interrupt (corresponding to Figure 2.2.15) ... 2-21
2.2.17 Sequence of switching detection edge ................................................................. 2-22
2.2.18 Sequence of check of interrupt request bit .......................................................... 2-22
2.2.19 Sequence of changing relevant register ............................................................... 2-23
2.3.1 Memory map of registers relevant to timers .......................................................... 2-24
2.3.2 Structure of Prescaler 12, Prescaler X, Prescaler Y ............................................ 2-24
2.3.3 Structure of Timer 1 .................................................................................................. 2-25
2.3.4 Structure of Timer 2, Timer X, Timer Y ................................................................. 2-25
2.3.5 Structure of Timer XY mode register ...................................................................... 2-26
2.3.6 Structure of Port control register 2 .......................................................................... 2-27
2.3.7 Structure of Interrupt request register 1 ................................................................. 2-28
2.3.8 Structure of Interrupt request register 2 ................................................................. 2-28
2.3.9 Structure of Interrupt control register 1 .................................................................. 2-29
2.3.10 Structure of Interrupt control register 2 ................................................................ 2-29
2.3.11 Timers connection and setting of division ratios ................................................. 2-31
2.3.12 Relevant registers setting ....................................................................................... 2-31
2.3.13 Control procedure ..................................................................................................... 2-32
2.3.14 Peripheral circuit example ....................................................................................... 2-33
2.3.15 Timers connection and setting of division ratios ................................................. 2-33
2.3.16 Relevant registers setting ....................................................................................... 2-34
2.3.17 Control procedure ..................................................................................................... 2-34
2.3.18 Judgment method of valid/invalid of input pulses ............................................... 2-35
2.3.19 Relevant registers setting ....................................................................................... 2-36
2.3.20 Control procedure ..................................................................................................... 2-37
2.3.21 Timers connection and setting of division ratios ................................................. 2-38
2.3.22 Relevant registers setting ....................................................................................... 2-39
2.3.23 Control procedure ..................................................................................................... 2-40
2.4.1 Memory map of registers relevant to Serial I/O .................................................... 2-42
2.4.2 Structure of Transmit/Receive buffer register ........................................................ 2-43
2.4.3 Structure of Serial I/O status register ..................................................................... 2-43
2.4.4 Structure of Serial I/O1 control register .................................................................. 2-44
2.4.5 Structure of UART control register .......................................................................... 2-44
2.4.6 Structure of Baud rate generator ............................................................................. 2-45
2.4.7 Structure of Serial I/O2 control register .................................................................. 2-45
2.4.8 Structure of Serial I/O2 register ............................................................................... 2-46
2.4.9 Structure of Interrupt source selection register ..................................................... 2-46
2.4.10 Structure of Interrupt edge selection register ...................................................... 2-47
2.4.11 Structure of Interrupt request register 1 ............................................................... 2-48
3886 Group User’s Manual
vii
List of figures
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2.4.12 Structure of Interrupt request register 2 ............................................................... 2-48
2.4.13 Structure of Interrupt control register 1 ................................................................ 2-49
2.4.14 Structure of Interrupt control register 2 ................................................................ 2-49
2.4.15 Serial I/O connection examples (1) ....................................................................... 2-50
2.4.16 Serial I/O connection examples (2) ....................................................................... 2-51
2.4.17 Serial I/O transfer data format ............................................................................... 2-52
2.4.18 Connection diagram ................................................................................................. 2-53
2.4.19 Timing chart .............................................................................................................. 2-53
2.4.20 Registers setting relevant to transmitting side ..................................................... 2-54
2.4.21 Registers setting relevant to receiving side ......................................................... 2-55
2.4.22 Control procedure of transmitting side .................................................................. 2-56
2.4.23 Control procedure of receiving side ...................................................................... 2-57
2.4.24 Connection diagram ................................................................................................. 2-58
2.4.25 Timing chart .............................................................................................................. 2-58
2.4.26 Registers setting relevant to Serial I/O1 .............................................................. 2-59
2.4.27 Setting of serial I/O1 transmission data ............................................................... 2-59
2.4.28 Control procedure of Serial I/O1 ............................................................................ 2-60
2.4.29 Registers setting relevant to Serial I/O2 .............................................................. 2-61
2.4.30 Setting of serial I/O2 transmission data ............................................................... 2-61
2.4.31 Control procedure of Serial I/O2 ............................................................................ 2-62
2.4.32 Connection diagram ................................................................................................. 2-63
2.4.33 Timing chart .............................................................................................................. 2-64
2.4.34 Relevant registers setting ....................................................................................... 2-64
2.4.35 Control procedure of master unit ........................................................................... 2-65
2.4.36 Control procedure of slave unit ............................................................................. 2-66
2.4.37 Connection diagram (Communication using UART) ............................................ 2-67
2.4.38 Timing chart (using UART) ..................................................................................... 2-67
2.4.39 Registers setting relevant to transmitting side ..................................................... 2-69
2.4.40 Registers setting relevant to receiving side ......................................................... 2-70
2.4.41 Control procedure of transmitting side .................................................................. 2-71
2.4.42 Control procedure of receiving side ...................................................................... 2-72
2.4.43 Sequence of setting serial I/O1 control register again ....................................... 2-74
2.5.1 Memory map of registers relevant to I2C-BUS interface ...................................... 2-76
2.5.2 Structure of I2C data shift register ........................................................................... 2-76
2.5.3 Structure of I 2C address register ............................................................................. 2-77
2.5.4 Structure of I 2C status register ................................................................................. 2-77
2.5.5 Structure of I 2C control register ............................................................................... 2-78
2.5.6 Structure of I 2C clock control register ..................................................................... 2-79
2.5.7 Structure of I 2C START/STOP condition control register ..................................... 2-80
2.5.8 Structure of Interrupt source selection register ..................................................... 2-80
2.5.9 Structure of Interrupt request register 1 ................................................................. 2-81
2.5.10 Structure of Interrupt request register 2 ............................................................... 2-81
2.5.11 Structure of Interrupt control register 1 ................................................................ 2-82
2.5.12 Structure of Interrupt control register 2 ................................................................ 2-82
2.5.13 I 2C-BUS connection structure ................................................................................. 2-83
2.5.14 I 2C-BUS communication format example .............................................................. 2-84
2.5.15 RESTART condition of master reception .............................................................. 2-85
2.5.16 SCL waveforms when synchronizing clocks ......................................................... 2-86
2.5.17 Initial setting example .............................................................................................. 2-88
2.5.18 Read Word protocol communication as I 2C-BUS master device ....................... 2-89
2.5.19 Generating of START condition and transmission process of slave address + write bit.. 2-90
2.5.20 Transmission process of command ....................................................................... 2-91
3886 Group User’s Manual
List of figures
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2.5.21 Transmission process of RESTART condition and slave address + read bit . 2-92
2.5.22 Reception process of lower data ........................................................................... 2-93
2.5.23 Reception process of upper data .......................................................................... 2-94
2.5.24 Generating of STOP condition ............................................................................... 2-95
2.5.25 Communication example as slave device ............................................................. 2-96
2.5.26 Reception process of START condition and slave address .............................. 2-97
2.5.27 Reception process of command ............................................................................. 2-98
2.5.28 Reception process of RESTART condition and slave address ......................... 2-99
2.5.29 Transmission process of lower data .................................................................... 2-100
2.5.30 Transmission process of upper data ................................................................... 2-101
2.5.31 Reception of STOP condition ............................................................................... 2-102
2.6.1 Memory map of registers relevant to PWM ......................................................... 2-106
2.6.2 Structure of Port control register 1 ........................................................................ 2-107
2.6.3 Structure of PWM0H register ................................................................................. 2-108
2.6.4 Structure of PWM0L register .................................................................................. 2-108
2.6.5 Structure of PWM1H register ................................................................................. 2-109
2.6.6 Structure of PWM1L register .................................................................................. 2-109
2.6.7 Structure of AD/DA control register ....................................................................... 2-110
2.6.8 Connection diagram ................................................................................................. 2-111
2.6.9 Relevant registers setting ....................................................................................... 2-112
2.6.10 Control procedure ................................................................................................... 2-113
2.6.11 PWM 0 output ........................................................................................................... 2-113
2.7.1 Memory map of registers relevant to A-D converter .......................................... 2-114
2.7.2 Structure of AD/DA control register ....................................................................... 2-114
2.7.3 Structure of A-D conversion register 1 ................................................................. 2-115
2.7.4 Structure of A-D conversion register 2 ................................................................. 2-115
2.7.5 Structure of Interrupt source selection register ................................................... 2-116
2.7.6 Structure of Interrupt request register 2 ............................................................... 2-117
2.7.7 Structure of Interrupt control register 2 ................................................................ 2-117
2.7.8 Connection diagram ................................................................................................. 2-118
2.7.9 Relevant registers setting ....................................................................................... 2-118
2.7.10 Control procedure for 8-bit read .......................................................................... 2-119
2.7.11 Control procedure for 10-bit read ........................................................................ 2-119
2.8.1 Memory map of registers relevant to D-A converter .......................................... 2-121
2.8.2 Structure of Port P5 direction register .................................................................. 2-122
2.8.3 Structure of AD/DA control register ....................................................................... 2-122
2.8.4 Structure of D-Ai converter register ...................................................................... 2-123
2.8.5 Peripheral circuit example ....................................................................................... 2-124
2.8.6 Speaker output example ......................................................................................... 2-124
2.8.7 Relevant registers setting ....................................................................................... 2-125
2.8.8 Control procedure ..................................................................................................... 2-126
2.9.1 Memory map of registers relevant to bus interface ............................................ 2-128
2.9.2 Structure of Data bus buffer register i .................................................................. 2-129
2.9.3 Structure of Data bus buffer status register i ...................................................... 2-129
2.9.4 Structure of Data bus buffer control register ....................................................... 2-130
2.9.5 Structure of Interrupt source selection register ................................................... 2-130
2.9.6 Structure of Interrupt request register 1 ............................................................... 2-131
2.9.7 Structure of Interrupt control register 1 ................................................................ 2-131
2.9.8 Structure of Port control register 2 ........................................................................ 2-132
2.9.9 Bus interface block diagram ................................................................................... 2-133
2.9.10 Relevant registers setting ..................................................................................... 2-135
2.9.11 Control procedure using interrupt ........................................................................ 2-136
3886 Group User’s Manual
ix
List of figures
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2.10.1 Memory map of registers relevant to watchdog timer ...................................... 2-137
2.10.2 Structure of Watchdog timer control register ..................................................... 2-137
2.10.3 Structure of CPU mode register .......................................................................... 2-138
2.10.4 Watchdog timer connection and division ratio setting ...................................... 2-139
2.10.5 Relevant registers setting ..................................................................................... 2-140
2.10.6 Control procedure ................................................................................................... 2-140
2.11.1 Example of poweron reset circuit ........................................................................ 2-141
2.11.2 RAM backup system .............................................................................................. 2-141
2.12.1 Structure of CPU mode register .......................................................................... 2-143
2.12.2 Connection diagram ............................................................................................... 2-144
2.12.3 Status transition diagram during power failure .................................................. 2-144
2.12.4 Setting of relevant registers ................................................................................. 2-145
2.12.5 Control procedure ................................................................................................... 2-146
2.13.1 Oscillation stabilizing time at restoration by reset input .................................. 2-148
2.13.2 Execution sequence example at restoration by occurrence of INT0 interrupt request .. 2-150
2.13.3 Reset input time ..................................................................................................... 2-152
2.14.1 Memory map of registers relevant to processor mode ..................................... 2-154
2.14.2 Structure of CPU mode register .......................................................................... 2-154
2.14.3 Expansion example of 32-Kbytes ROM and RAM ............................................ 2-155
2.14.4 Read cycle (OE access, SRAM) .......................................................................... 2-156
2.14.5 Read cycle (OE access, EPROM) ....................................................................... 2-156
2.14.6 Write cycle (W control, SRAM) ............................................................................ 2-157
2.14.7 Usage example of ONW function ........................................................................ 2-158
2.14.8 Expansion example of 32-Kbytes ROM and RAM at f(XIN) = 8 MHz or more ... 2-159
2.14.9 Read cycle (OE access, SRAM) .......................................................................... 2-160
2.14.10 Read cycle (OE access, EPROM) ..................................................................... 2-160
2.14.11 Write cycle (W control, SRAM) .......................................................................... 2-161
2.15.1 Memory map of flash memory version for 3886 Group ................................... 2-162
2.15.2 Memory map of registers relevant to flash memory ......................................... 2-163
2.15.3 Structure of Flash memory control register ........................................................ 2-163
2.15.4 Structure of Flash command register .................................................................. 2-164
2.15.5 Reprogramming example of built-in flash memory in serial I/O mode ........... 2-167
2.15.6 Connection example in serial I/O mode (1) ....................................................... 2-168
2.15.7 Connection example in serial I/O mode (2) ....................................................... 2-168
2.15.8 Connection example in serial I/O mode (3) ....................................................... 2-169
2.15.9 Example of reprogramming system for built-in flash memory in CPU reprogramming mode ... 2-170
2.15.10 CPU reprogramming control program example (1) ......................................... 2-171
2.15.11 CPU reprogramming control program example (2) ......................................... 2-172
2.15.12 CPU reprogramming control program example (3) ......................................... 2-173
2.15.13 CPU reprogramming control program example (4) ......................................... 2-174
2.15.14 V PP control circuit example (1) ........................................................................... 2-175
2.15.15 V PP control circuit example (2) ........................................................................... 2-175
CHAPTER 3 APPENDIX
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3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
Circuit
Circuit
Timing
Timing
Timing
Timing
for measuring output switching characteristics (1) ................................... 3-12
for measuring output switching characteristics (2) ................................... 3-12
diagram (1) (in single-chip mode) ............................................................... 3-13
diagram (2) (in memory expansion mode and microprocessor mode) .. 3-14
diagram (3) (in memory expansion mode and microprocessor mode) .. 3-15
diagram (4) (system bus interface) ............................................................ 3-16
3886 Group User’s Manual
List of figures
Fig. 3.1.7 Timing diagram of multi-master I 2C-BUS ................................................................ 3-17
Fig. 3.2.1 Power source current characteristic examples (in high-speed mode, A-D conversion
and comparator operating) ........................................................................................ 3-18
Fig. 3.2.2 Power source current characteristic examples (in high-speed mode) ................ 3-18
Fig. 3.2.3 Power source current characteristic examples (in high-speed mode, WAIT execution) . 3-19
Fig. 3.2.4 Power source current characteristic examples (in middle-speed mode) ............ 3-19
Fig. 3.2.5 Power source current characteristic examples (in middle-speed mode, WAIT execution) . 3-20
Fig. 3.2.6 Power source current characteristic examples (in low-speed mode) ................. 3-20
Fig. 3.2.7 Power source current characteristic examples (at reset) ..................................... 3-21
Fig. 3.2.8 Standard characteristic examples of CMOS output port at P-channel drive (Ta=25 °C) .. 3-22
Fig. 3.2.9 Standard characteristic examples of CMOS output port at P-channel drive (Ta=90 °C) ... 3-22
Fig. 3.2.10 Standard characteristic examples of CMOS output port at N-channel drive (Ta=25 °C) ... 3-23
Fig. 3.2.11 Standard characteristic examples of CMOS output port at N-channel drive (Ta=90 °C) .. 3-23
Fig. 3.2.12 Standard characteristic examples of CMOS large current output port at N-channel
drive (Ta=25 °C) ...................................................................................................... 3-24
Fig. 3.2.13 Standard characteristic examples of CMOS large current output port at N-channel
drive (Ta=90 °C) ...................................................................................................... 3-24
Fig. 3.2.14 Standard characteristic examples of CMOS input port at pull-up (Ta=25 °C) .. 3-25
Fig. 3.2.15 Standard characteristic examples of CMOS input port at pull-up (Ta=90 °C) .. 3-25
Fig. 3.2.16 A-D conversion standard characteristics ............................................................... 3-26
Fig. 3.2.17 D-A conversion standard characteristics ............................................................... 3-27
Fig. 3.3.1 Sequence of switch the detection edge .................................................................. 3-30
Fig. 3.3.2 Sequence of check of interrupt request bit ............................................................ 3-30
Fig. 3.3.3 Sequence of changing relevant register ................................................................. 3-31
Fig. 3.3.4 Sequence of setting serial I/O1 control register again ......................................... 3-33
Fig. 3.3.5 PWM 0 output ............................................................................................................... 3-37
Fig. 3.3.6 Ceramic resonator circuit .......................................................................................... 3-39
Fig. 3.3.7 Initialization of processor status register ................................................................ 3-40
Fig. 3.3.8 Sequence of PLP instruction execution .................................................................. 3-40
Fig. 3.3.9 Stack memory contents after PHP instruction execution ..................................... 3-40
Fig. 3.3.10 Interrupt routine ........................................................................................................ 3-41
Fig. 3.3.11 Status flag at decimal calculations ........................................................................ 3-41
Fig. 3.3.12 Programming and testing of One Time PROM version ...................................... 3-42
Fig. 3.4.1 Wiring for the RESET pin ......................................................................................... 3-44
Fig. 3.4.2 Wiring for clock I/O pins ........................................................................................... 3-44
Fig. 3.4.3 Wiring for CNVss pin ................................................................................................. 3-45
Fig. 3.4.4 Wiring for the V PP pin of the One Time PROM version and the EPROM version ... 3-45
Fig. 3.4.5 Bypass capacitor across the Vss line and the Vcc line ....................................... 3-46
Fig. 3.4.6 Analog signal line and a resistor and a capacitor ................................................ 3-46
Fig. 3.4.7 Wiring for a large current signal line ...................................................................... 3-47
Fig. 3.4.8 Wiring of RESET pin ................................................................................................. 3-47
Fig. 3.4.9 Vss pattern on the underside of an oscillator ....................................................... 3-48
Fig. 3.4.10 Setup for I/O ports ................................................................................................... 3-48
Fig. 3.4.11 Watchdog timer by software ................................................................................... 3-49
Fig. 3.5.1 Structure of Port Pi .................................................................................................... 3-50
Fig. 3.5.2 Structure of Port Pi direction register ..................................................................... 3-50
Fig. 3.5.3 Structure of I2C data shift register ........................................................................... 3-51
Fig. 3.5.4 Structure of I 2C address register ............................................................................. 3-51
Fig. 3.5.5 Structure of I 2C status register ................................................................................. 3-52
Fig. 3.5.6 Structure of I 2C control register ............................................................................... 3-53
Fig. 3.5.7 Structure of I 2C clock control register ..................................................................... 3-54
Fig. 3.5.8 Structure of I 2C START/STOP condition control register ..................................... 3-55
3886 Group User’s Manual
xi
List of figures
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
xii
3.5.9 Structure of Transmit/Receive buffer register ........................................................ 3-55
3.5.10 Structure of Serial I/O1 status register ................................................................. 3-56
3.5.11 Structure of Serial I/O1 control register ................................................................ 3-56
3.5.12 Structure of UART control register ........................................................................ 3-57
3.5.13 Structure of Baud rate generator ........................................................................... 3-57
3.5.14 Structure of Serial I/O2 control register ................................................................ 3-58
3.5.15 Structure of Watchdog timer control register ....................................................... 3-58
3.5.16 Structure of Serial I/O2 register ............................................................................. 3-59
3.5.17 Structure of Prescaler 12, Prescaler X, Prescaler Y .......................................... 3-59
3.5.18 Structure of Timer 1 ................................................................................................ 3-60
3.5.19 Structure of Timer 2, Timer X, Timer Y ............................................................... 3-60
3.5.20 Structure of Timer XY mode register .................................................................... 3-61
3.5.21 Structure of Data bus buffer register .................................................................... 3-62
3.5.22 Structure of Data bus buffer status register ........................................................ 3-62
3.5.23 Structure of Data bus buffer control register ....................................................... 3-63
3.5.24 Structure of Comparator data register .................................................................. 3-63
3.5.25 Structure of Port control register 1 ....................................................................... 3-64
3.5.26 Structure of Port control register 2 ....................................................................... 3-64
3.5.27 Structure of PWM0H register ................................................................................. 3-65
3.5.28 Structure of PWM0L register .................................................................................. 3-65
3.5.29 Structure of PWM1H register ................................................................................. 3-66
3.5.30 Structure of PWM1L register .................................................................................. 3-66
3.5.31 Structure of AD/DA control register ....................................................................... 3-67
3.5.32 Structure of AD conversion register 1 .................................................................. 3-67
3.5.33 Structure of D-Ai conversion register .................................................................... 3-68
3.5.34 Structure of A-D conversion register 2 ................................................................. 3-68
3.5.35 Structure of Interrupt source selection register ................................................... 3-69
3.5.36 Structure of Interrupt edge selection register ...................................................... 3-69
3.5.37 Structure of CPU mode register ............................................................................ 3-70
3.5.38 Structure of Interrupt request register 1 ............................................................... 3-71
3.5.39 Structure of Interrupt request register 2 ............................................................... 3-71
3.5.40 Structure of Interrupt control register 1 ................................................................ 3-72
3.5.41 Structure of Interrupt control register 2 ................................................................ 3-72
3.5.42 Structure of Flash memory control register .......................................................... 3-73
3.5.43 Structure of Flash command register .................................................................... 3-74
3.10.1 M38867M8A-XXXHP, M38867E8AHP pin configuration ..................................... 3-89
3.10.2 M38867E8AFS pin configuration ............................................................................ 3-89
3.10.3 M38869MFA-XXXGP/HP, M38869FFAGP/HP pin configuration ........................ 3-90
3886 Group User’s Manual
List of tables
List of tables
CHAPTER 1 HARDWARE
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
1 Pin description (1) ........................................................................................................... 1-6
2 Pin description (2) ........................................................................................................... 1-7
3 Support products ............................................................................................................. 1-9
4 Push and pop instructions of accumulator or processor status register ............... 1-11
5 Set and clear instructions of each bit of processor status register ....................... 1-12
6 I/O port function (1) ...................................................................................................... 1-16
7 I/O port function (2) ...................................................................................................... 1-17
8 Interrupt vector addresses and priority ...................................................................... 1-24
9 Relationship between low-order 6 bits of data and period set by the ADD bit ... 1-37
10 Function description of control I/O pins at bus interface function selected ....... 1-43
11 Multi-master I 2C-BUS interface functions ................................................................. 1-44
12 Set values of I 2C clock control register and S CL frequency .................................. 1-46
13 START condition generating timing table ................................................................ 1-50
14 STOP condition generating timing table .................................................................. 1-50
15 START condition/STOP condition detecting conditions .......................................... 1-50
16 Recommended set value to START/STOP condition set bits (SSC4-SSC0) for each
oscillation frequency ................................................................................................... 1-52
17 Port functions in memory expansion mode and microprocessor mode ............... 1-65
18 Programming adapter .................................................................................................. 1-67
19 PROM programmer setup ........................................................................................... 1-67
20 Pin assignments of M38869FFAHP/GP when operating in the parallel input/output
mode ............................................................................................................................. 1-68
21 Assignment states of control input and each state ................................................ 1-68
22 Pin description (flash memory parallel I/O mode) .................................................. 1-69
23 Software command (Parallel input/output mode) .................................................... 1-71
24 DC electrical characteristics ....................................................................................... 1-77
25 Read-only mode ........................................................................................................... 1-77
26 Read/Write mode ......................................................................................................... 1-77
27 Pin description (flash memory serial I/O mode) ..................................................... 1-79
28 Software command (serial I/O mode) ....................................................................... 1-80
29 AC electrical characteristics ....................................................................................... 1-84
30 Relative formula for a reference voltage V REF of A-D converter and V ref ..................... 1-91
31 Change of A-D conversion register during A-D conversion .................................. 1-91
CHAPTER 2 APPLICATION
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
2.1.1 Handling of unused pins (in single-chip mode) .................................................... 2-5
2.1.2 Handling of unused pins (in memory expansion mode, microprocessor mode) ... 2-5
2.2.1 Interrupt sources, vector addresses and priority of 3886 group ...................... 2-12
2.2.2 List of interrupt bits according to interrupt source ............................................. 2-17
2.3.1 CNTR 0/CNTR 1 active edge selection bit function ............................................... 2-26
2.4.1 Setting examples of Baud rate generator values and transfer bit rate values ... 2-68
2.5.1 Set value of I 2C clock control register and SCL frequency .............................. 2-79
2.9.1 Bus control signals and data bus status ........................................................... 2-134
2.13.1 State in stop mode ............................................................................................. 2-147
2.13.2 State in wait mode .............................................................................................. 2-151
2.15.1 Setting of EPROM programmers when parallel programming ...................... 2-164
3886 Group User’s Manual
xiii
List of tables
Table 2.15.2 Connection example to programmer when serial programming ................... 2-165
CHAPTER 3 APPENDIX
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
xiv
3.1.1 Absolute maximum ratings ....................................................................................... 3-2
3.1.2 Recommended operating conditions (1) ................................................................ 3-3
3.1.3 Recommended operating conditions (2) ................................................................ 3-4
3.1.4 Recommended operating conditions (3) ................................................................ 3-4
3.1.5 Electrical characteristics (1) ..................................................................................... 3-5
3.1.6 Electrical characteristics (2) ..................................................................................... 3-6
3.1.7 A-D converter characteristics (1) ............................................................................ 3-7
3.1.8 A-D converter characteristics (2) ............................................................................ 3-7
3.1.9 D-A converter characteristics .................................................................................. 3-7
3.1.10 Comparator characteristics .................................................................................... 3-7
3.1.11 Timing requirements (1) ......................................................................................... 3-8
3.1.12 Timing requirements (2) ......................................................................................... 3-9
3.1.13 Timing requirements for system bus interface (1) ........................................... 3-10
3.1.14 Timing requirements for system bus interface (2) ........................................... 3-10
3.1.15 Switching characteristics (1) ................................................................................ 3-11
3.1.16 Switching characteristics (2) ................................................................................ 3-11
3.1.17 Switching characteristics for system bus interface (1) .................................... 3-11
3.1.18 Switching characteristics for system bus interface (2) .................................... 3-11
3.1.19 Timing requirements in memory expansion mode and microprocessor mode . 3-12
3.1.20 Switching characteristics in memory expansion mode and microprocessor mode .. 3-12
3.1.21 Multi-master I 2C-BUS bus line characteristics .................................................. 3-17
3.3.1 Programming adapters ........................................................................................... 3-43
3.3.2 PROM programmer address setting ..................................................................... 3-43
3.5.1 Set value of I 2C clock control register and SCL frequency .............................. 3-54
3.5.2 CNTR 0/CNTR 1 active edge selection bit function ............................................... 3-61
3886 Group User’s Manual
CHAPTER 1
HARDWARE
DESCRIPTION
FEATURES
APPLICATION
PIN CONFIGURATION
FUNCTIONAL BLOCK
PIN DESCRIPTION
PART NUMBERING
GROUP EXPANSION
FUNCTIONAL DESCRIPTION
NOTES ON PROGRAMMING
NOTES ON USE
DATA REQUIRED FOR MASK ORDERS
DATA REQUIRED FOR ONE TIME
PROM PROGRAMMING ORDERS
FUNCTIONAL DESCRIPTION
SUPPLEMENT
HARDWARE
DESCRIPTION/FEATURES
DESCRIPTION
The 3886 group is the 8-bit microcomputer based on the 740 family core technology.
The 3886 group is designed for controlling systems that require
analog signal processing and include two serial I/O functions, A-D
converters, D-A converters, system data bus interface function,
watchdog timer, and comparator circuit.
The multi-master I2C-BUS interface can be added by option.
FEATURES
<Microcomputer mode>
●Basic machine-language instructions ...................................... 71
●Minimum instruction execution time .................................. 0.4 µs
(at 10 MHz oscillation frequency)
●Memory size
ROM ................................................................. 32K to 60K bytes
RAM ............................................................... 1024 to 2048 bytes
●Programmable input/output ports ............................................ 72
●Software pull-up resistors ................................................. Built-in
●Interrupts ................................................. 21 sources, 16 vectors
(Included key input interrupt)
●Timers ............................................................................. 8-bit ✕ 4
●Serial I/O1 .................... 8-bit ✕ 1(UART or Clock-synchronized)
●Serial I/O2 ................................... 8-bit ✕ 1(Clock-synchronized)
●PWM output circuit ....................................................... 14-bit ✕ 2
●Bus interface .................................................................... 2 bytes
●I2C-BUS interface (option) ........................................... 1 channel
●A-D converter ............................................... 10-bit ✕ 8 channels
●D-A converter ................................................. 8-bit ✕ 2 channels
●Comparator circuit ...................................................... 8 channels
●Watchdog timer ............................................................ 16-bit ✕ 1
●Clock generating circuit ..................................... Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
●Power source voltage
In high-speed mode .................................................. 4.0 to 5.5 V
(at 10 MHz oscillation frequency)
In middle-speed mode ........................................... 2.7 to 5.5 V(*)
(at 10 MHz oscillation frequency)
In low-speed mode ............................................... 2.7 to 5.5 V (*)
(at 32 kHz oscillation frequency)
(*: 4.0 to 5.5 V for Flash memory version)
1-2
●Power dissipation
In high-speed mode .......................................................... 40 mW
(at 10 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode ............................................................ 60 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
●Memory expansion possible (only for M38867M8A/E8A)
●Operating temperature range .................................... –20 to 85°C
<Flash memory mode>
●Supply voltage (at programming/erasing) ...... VCC = 5 V ± 10 %
●Program/Erase voltage ............................... VPP = 11.7 to 12.6 V
●Programming method ...................... Programming in unit of byte
●Erasing method
Batch erasing ........................................ Parallel/Serial I/O mode
Block erasing .................................... CPU reprogramming mode
●Program/Erase control by software command
●Number of times for programming/erasing ............................ 100
●Operating temperature range (at programming/erasing)
..................................................................... Normal temperature
■Notes
1. The flash memory version cannot be used for application embedded in the MCU card.
2. Power source voltage Vcc of the flash memory version is 4.0
to 5.5 V.
APPLICATION
Household product, consumer electronics, communications, note
book PC, etc.
3886 Group User’s Manual
HARDWARE
PIN CONFIGURATION
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
45
44
43
48
47
46
50
49
52
51
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
17
18
14
15
16
11
12
13
7
8
9
10
6
4
5
P16/AD14
P17/AD15
P20/DB0
P21/DB1
P22/DB2
P23/DB3
P24/DB4
P25/DB5
P26/DB6
P27/DB7
VSS
XOUT
XIN
P40/XCOUT
P41/XCIN
RESET
VPP
CNVSS
P42/INT0/OBF00
P43/INT1/OBF01
P44/RXD
P60/AN0
P77/SCL
P76/SDA
P75/INT41
P74/INT31
P73/SRDY2/INT21
P72/SCLK2
P71/SOUT2
P70/SIN2
P57/DA2/PWM11
P56/DA1/PWM01
P55/CNTR1
P54/CNTR0
P53/INT40/W
P52/INT30/R
P51/INT20/S0
P50/A0
P47/SRDY1/S1
P46/SCLK1/OBF10
P45/TXD
1
M38867M8A-XXXHP
M38867E8AHP
2
3
P31/PWM10
P30/PWM00
P87/DQ7
P86/DQ6
P85/DQ5
P84/DQ4
P83/DQ3
P82/DQ2
P81/DQ1
P80/DQ0
VCC
VREF
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
55
54
53
60
59
58
57
56
P32/ONW
P33/RESETOUT
P34/φ
P35/SYNC
P36/WR
P37/RD
P00/P3REF/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/AD8
P11/AD9
P12/AD10
P13/AD11
P14/AD12
P15/AD13
PIN CONFIGURATION (TOP VIEW)
: PROM version
Note: The pin number and the position of the
function pin may change by the kind of
package.
Package type : 80P6Q-A
Fig. 1 M38867M8A-XXXHP, M38867E8AHP pin configuration
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P20/DB0
P21/DB1
P22/DB2
P23/DB3
P24/DB4
P25/DB5
P26/DB6
P27/DB7
VSS
XOUT
XIN
P40/XCOUT
P41/XCIN
RESET
VPP
CNVSS
P42/INT0/OBF00
P62/AN2
P61/AN1
P60/AN0
P77/SCL
P76/SDA
P75/INT41
P74/INT31
P73/SRDY2/INT21
P72/SCLK2
P71/SOUT2
P70/SIN2
P57/DA2/PWM11
P56/DA1/PWM01
P55/CNTR1
P54/CNTR0
P53/INT40/W
P52/INT30/R
P51/INT20/S0
P50/A0
P47/SRDY1/S1
P46/SCLK1/OBF10
P45/TXD
P44/RXD
P43/INT1/OBF01
18
19
20
21
22
23
24
M38867E8AFS
65
66
67
68
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
P87/DQ7
P86/DQ6
P85/DQ5
P84/DQ4
P83/DQ3
P82/DQ2
P81/DQ1
P80/DQ0
VCC
VREF
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
47
46
45
44
43
42
41
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
P30/PWM00
P31/PWM10
P32/ONW
P33/RESETOUT
P34/φ
P35/SYNC
P36/WR
P37/RD
P00/P3REF/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/AD8
P11/AD9
P12/AD10
P13/AD11
P14/AD12
P15/AD13
P16/AD14
P17/AD15
PIN CONFIGURATION (TOP VIEW)
Package type : 80D0
: PROM version
Note: The pin number and the position of
the function pin may change by the
kind of package.
Fig. 2 M38867E8AFS pin configuration
3886 Group User’s Manual
1-3
HARDWARE
PIN CONFIGURATION
41
44
43
42
46
45
50
49
48
47
40
39
38
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
37
36
M38869MFA-XXXGP/HP
M38869FFAGP/HP
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Package type : 80P6S-A/80P6Q-A
Fig. 3 M38869MFA-XXXGP/HP, M38869FFAGP/HP pin configuration
1-4
3886 Group User’s Manual
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
VSS
XOUT
XIN
P40/XCOUT
P41/XCIN
RESET
CNVSS
VPP
P42/INT0/OBF00
P43/INT1/OBF01
P44/RXD
20
18
19
17
15
16
13
14
11
12
9
10
7
8
6
4
5
P60/AN0
P77/SCL
P76/SDA
P75/INT41
P74/INT31
P73/SRDY2/INT21
P72/SCLK2
P71/SOUT2
P70/SIN2
P57/DA2/PWM11
P56/DA1/PWM01
P55/CNTR1
P54/CNTR0
P53/INT40/W
P52/INT30/R
P51/INT20/S0
P50/A0
P47/SRDY1/S1
P46/SCLK1/OBF10
P45/TXD
2
3
76
77
78
79
80
1
P31/PWM10
P30/PWM00
P87/DQ7
P86/DQ6
P85/DQ5
P84/DQ4
P83/DQ3
P82/DQ2
P81/DQ1
P80/DQ0
VCC
VREF
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
57
56
55
54
53
52
51
60
59
58
P32
P33
P34
P35
P36
P37
P00/P3REF
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
PIN CONFIGURATION (TOP VIEW)
: Flash memory version
Note: The pin number and the position of the
function pin may change by the kind of
package.
XCIN
XCOUT
Sub-clock Sub-clock
input
output
2
3886 Group User’s Manual
P7(8)
2 3 4 5 6 7 8 9
I/O port P7
63 64 65 66 67 68 69 70
I/O port P8
AVSS
VREF
I/O port P5
I/O port P6
P5(8)
D-A
converter
1(8)
PC H
10 11 12 13 14 15 16 17
P6(8)
D-A
converter 2
(8)
ROM
30
VSS
74 75 76 77 78 79 80 1
A-D
converter
(10)
RAM
72 73
INT21,
INT31,
INT41
SI/O2(8)
P8(8)
DQ7
to
DQ0
Bus interface
S CL S DA
I C
Reset
Clock generating circuit
29
Main-clock
output
XOUT
Watchdog
timer
28
Main-clock
input
XIN
PS
INT20,
INT30,
INT40
INT0,
INT1
I/O port P4
18 19 20 21 22 23 26 27
P4(8)
PC L
S
Y
X
A
SI/O1(8)
C P U
71
VCC
FUNCTIONAL BLOCK DIAGRAM (Package : 80P6Q-A, 80P6S-A)
XCIN
XCOUT
P3(8)
CNTR1
I/O port P3
I/O port P2
I/O port P1
39 40 41 42 43 44 45 46
P1(8)
P0(8)
I/O port P0
47 48 49 50 51 52 53 54
PWM10,
PWM11
PWM00,
PWM01
31 32 33 34 35 36 37 38
P2(8)
PWM1(14)
Timer Y( 8 )
Timer X( 8 )
Timer 2( 8 )
Timer 1( 8 )
PWM0(14)
Prescaler Y(8)
Prescaler X(8)
Prescaler 12(8)
Key-on
wake-up
CNTR0
24
CNVSS
55 56 57 58 59 60 61 62
Comparator
25
RESET
Reset input
P3REF
HARDWARE
FUNCTIONAL BLOCK
FUNCTIONAL BLOCK
Fig. 4 Functional block diagram
1-5
HARDWARE
PIN DESCRIPTION
PIN DESCRIPTION
Table 1 Pin description (1)
Pin
VCC, VSS
Functions
Name
Power source
Function except a port function
•Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.
•In the flash memory version, apply voltage of 4.0 V – 5.5 V to Vcc, and 0 V to Vss.
•This pin controls the operation mode of the chip.
•Normally connected to VSS.
CNVSS
CNVSS input
•If this pin is connected to Vcc, the internal ROM is inhibited and an external memory is accessed.
•In the flash memory version, connected to VSS.
•In the EPROM version or the flash memory version, this pin functions as the VPP power source input pin.
VREF
Reference voltage
AVSS
Analog power source
RESET
Reset input
•Reset input pin for active “L”.
XIN
Clock input
•Input and output pins for the clock generating circuit.
•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
XOUT
Clock output
•Reference voltage input pin for A-D and D-A converters.
•Analog power source input pin for A-D and D-A converters.
•Connect to VSS.
•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT
pin open.
•8-bit CMOS I/O port.
P00/P3REF
I/O port P0
P01–P07
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Comparator reference power source
input pin
•When the external memory is used, these pins are used as the address bus.
•CMOS compatible input level.
•CMOS 3-state output structure or N-channel open-drain output structure.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually programmed as either input or output.
P10–P17
I/O port P1
•When the external memory is used, these pins are used as the address bus.
•CMOS compatible input level.
•CMOS 3-state output structure or N-channel open-drain output structure.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually programmed as either input or output.
P20–P27
I/O port P2
•When the external memory is used, these pins are used as the data bus.
•CMOS compatible input level.
•CMOS 3-state output structure.
•P24 to P27 (4 bits) are enabled to output large current for LED drive (only in single-chip mode).
•8-bit CMOS I/O port.
•Key-on wake-up input pin
•I/O direction register allows each pin to be individually
programmed as either input or output.
P30/PWM00
P31/PWM10
•When the external memory is used, these pins are
used as the control bus.
I/O port P3
•CMOS compatible input level.
•CMOS 3-state output structure.
P32–P37
1-6
•These pins function as key-on wake-up and comparator input.
•These pins are enabled to control pull-up.
3886 Group User’s Manual
•Comparator input pin
•PWM output pin
•Key-on wake-up input pin
•Comparator input pin
HARDWARE
PIN DESCRIPTION
Table 2 Pin description (2)
Pin
Functions
Name
•8-bit I/O port with the same function as port P0.
Function except a port function
•Sub-clock generating circuit I/O
pins
P40/XCOUT
P41/XCIN
<Input level>
(Connect a resonator.)
P42/INT0
/OBF00
P43/INT1
/OBF01
P40, P41 : CMOS input level
P42–P46 : CMOS compatible input level or TTL input level
P47 : CMOS compatible input level or TTL input
level in the bus interface function
•Interrupt input pins
I/O port P4
•Bus interface function pins
<Output structure>
P40, P41, P47 : CMOS 3-state output structure
P42–P46 : CMOS 3-state output structure or Nchannel open-drain output structure
P44/RxD
P45/TxD
•Serial I/O1 function pins
P46/SCLK1
/OBF10
P47/SRDY1
/S1
•Regardless of input or output port, P42 to P46 can
be input every pin level.
•When P4 2 and P43 are used as output port, the
function which makes P4 2 and P4 3 clear to “0”
when the host CPU reads the output data bus
buffer 0 can be added.
•Serial I/O1 function pins
P50/A0
•8-bit I/O port with the same function as port P0.
•Bus interface function pins
P51/INT20
/S0
P52/INT30
/R
P53/INT40
/W
•CMOS compatible input level.
•CMOS 3-state output structure.
•P50 to P53 can be switched between CMOS compatible input level or TTL input level in the bus
interface function.
•Bus interface function pins
•Timer X, timer Y function pins
P56/DA1
/PWM01
P57/DA2
/PWM11
•D-A converter output pin
•PWM output pin
I/O port P6
•8-bit I/O port with the same function as port P0.
•CMOS compatible input level.
•A-D converter output pin
•CMOS 3-state output structure.
•8-bit I/O port with the same function as port P0.
P70/SIN2
P71/SOUT2
P72/SCLK2
P73/SRDY2
/INT21
P74/INT31
P75/INT41
•Interrupt input pins
I/O port P5
P54/CNTR0
P55/CNTR1
P60/AN0–
P67/AN7
•Bus interface function pins
I/O port P7
P70–P75 : CMOS compatible input level or TTL input level
•Serial I/O2 function pin
P76, P77 : CMOS compatible input level or
SMBUS input level in the I2C-BUS interface function, N-channel open-drain
output structure
•Serial I/O2 function pin
•Interrupt input pin
•Regardless of input or output port, P70 to P75 can
be input every pin level.
P76/SDA
P77/SCL
•Interrupt input pin
•I2C-BUS interface function pin
•8-bit I/O port with the same function as port P0.
P80/DQ0–
P87/DQ7
•CMOS compatible input level.
I/O port P8
•CMOS 3-state output structure.
•Bus interface function pin
•CMOS compatible input level or TTL input level in
the bus interface function.
3886 Group User’s Manual
1-7
HARDWARE
PART NUMBERING
PART NUMBERING
Product name
M3886
7
M
8 A-
XXX
HP
Package type
HP : 80P6Q-A
GP : 80P6S-A
FS : 80D0
ROM number
Omitted in the one time PROM version shipped in blank,
the EPROM version and the flash memory version.
A– : High-speed version
– is omitted in the One Time PROM version shipped in blank,
the EPROM version and the flash memory version.
ROM/PROM size
1 : 4096 bytes
9: 36864 bytes
2 : 8192 bytes
A : 40960 bytes
B : 45056 bytes
3 : 12288 bytes
C: 49152 bytes
4 : 16384 bytes
D: 53248 bytes
5 : 20480 bytes
E : 57344 bytes
6 : 24576 bytes
F : 61440 bytes
7 : 28672 bytes
8 : 32768 bytes
The first 128 bytes and the last 2 bytes of ROM are reserved
areas ; they cannot be used.
However, they can be programmed or erased in the EPROM
version and the flash memory version, so that the users can
use them.
Memory type
M : Mask ROM version
E : EPROM or One Time PROM version
F : Flash memory version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
Fig. 5 Part numbering
1-8
3886 Group User’s Manual
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes
HARDWARE
GROUP EXPANSION
GROUP EXPANSION
Packages
Mitsubishi plans to expand the 3886 group as follows.
80P6Q-A ................................. 0.5 mm-pitch plastic molded LQFP
80P6S-A .................................. 0.65mm-pitch plastic molded QFP
80D0 ....................... 0.8 mm-pitch ceramic LCC (EPROM version)
Memory Type
Support for mask ROM, One Time PROM, EPROM and flash
memory version.
The pin number and the position of the function pin may change
by the kind of package.
Memory Size
ROM size ........................................................... 32 K to 60 K bytes
RAM size ......................................................... 1024 to 2048 bytes
Memory Expansion
ROM size (bytes)
ROM
external
: Mass production
60K
M38869FFA/MFA
48K
M38869MCA
32K
M38869M8A/MCA
M38867E8A/M8A
28K
24K
20K
16K
12K
8K
384
512
640
768
896
1024
1152
RAM size (bytes)
1280
1408
1536
2048
3072
4032
Fig. 6 Memory expansion plan
Currently products are listed below.
As of Sep. 2000
Table 3 Support products
Product name
M38867M8A-XXXHP
M38867E8A-XXXHP
M38867E8AHP
M38867E8AFS
M38869M8A-XXXHP
M38869M8A-XXXGP
M38869MCA-XXXHP
M38869MCA-XXXGP
M38869MFA-XXXHP
M38869MFA-XXXGP
M38869FFAHP
M38869FFAGP
(P) ROM size (bytes)
ROM size for User in ( )
RAM size (bytes)
Package
1024
80P6Q-A
2048
80D0
80P6Q-A
80P6S-A
80P6Q-A
80P6S-A
80P6Q-A
80P6S-A
80P6Q-A
80P6S-A
32768 (32638)
49152 (49022)
61440 (61310)
3886 Group User’s Manual
Remarks
Mask ROM version
One Time PROM version
One Time PROM version (blank)
EPROM version
Mask ROM version
Flash memory version
1-9
HARDWARE
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
[Stack Pointer (S)]
The 3886 group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Index Register Y (Y)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 6.
Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine
calls.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PC H and PCL. It is used to indicate the address of the
next instruction to be executed.
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b7
X
Index register X
b0
b7
Y
b7
Index register Y
b0
S
b15
b7
PCH
Stack pointer
b0
Program counter
PCL
b7
b0
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 7 740 Family CPU register structure
1-10
3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
On-going Routine
Interrupt request
(Note)
M (S)
Execute JSR
Push return address
on stack
M (S)
(PCH)
(S)
(S) – 1
M (S)
(PCL)
(S)
(S)– 1
(S)
M (S)
(S)
M (S)
(S)
Subroutine
POP return
address from stack
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
(S) – 1
(PCL)
Push return address
on stack
(S) – 1
(PS)
Push contents of processor
status register on stack
(S) – 1
Interrupt
Service Routine
Execute RTS
(S)
(PCH)
I Flag is set from “0” to “1”
Fetch the jump vector
Execute RTI
Note: Condition for acceptance of an interrupt
(S)
(S) + 1
(PS)
M (S)
(S)
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
POP contents of
processor status
register from stack
POP return
address
from stack
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 8 Register push and pop at interrupt generation and subroutine call
Table 4 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PLA
Processor status register
PHP
PLP
3886 Group User’s Manual
1-11
HARDWARE
FUNCTIONAL DESCRIPTION
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
•Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 5 Set and clear instructions of each bit of processor status register
D flag
V flag
SEI
SED
B flag
_
T flag
SEC
Z flag
_
I flag
Set instruction
C flag
SET
_
N flag
_
Clear instruction
CLC
_
CLI
CLD
_
CLT
CLV
_
1-12
3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, the
processor mode bits specifying the chip operation mode, etc.
The CPU mode register is allocated at address 003B16.
b7
b0
1
CPU mode register
(CPUM : address 003B16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 : Memory expansion mode (Note)
1 0 : Microprocessor mode (Note)
1 1 : Not available
Stack page selection bit
0 : 0 page
1 : 1 page
Fix this bit to “1”.
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0 0 : φ = f(XIN)/2 (high-speed mode)
0 1 : φ = f(XIN)/8 (middle-speed mode)
1 0 : φ = f(XCIN)/2 (low-speed mode)
1 1 : Not available
Note: This mode is not available for M38869M8A/MCA/MFA and the flash memory version.
Fig. 9 Structure of CPU mode register
3886 Group User’s Manual
1-13
HARDWARE
FUNCTIONAL DESCRIPTION
MEMORY
Special Function Register (SFR) Area
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
Zero Page
RAM
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
Special Page
ROM
Access to this area with only 2 bytes is possible in the special
page addressing mode.
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs. Program/Erase of the reserved ROM area is possible in the EPROM
version and the flash memory version.
RAM area
RAM size
(bytes)
Address
XXXX16
192
256
384
512
640
768
896
1024
1536
2048
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
000016
SFR area
Zero page
004016
RAM
010016
XXXX16
Not used
0FFE16
SFR area (Note 1)
0FFF16
YYYY16
ROM area
ROM size
(bytes)
Address
YYYY16
Address
ZZZZ16
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
Reserved ROM area
(Note 2) (128 bytes)
ZZZZ16
ROM
FF0016
FFDC16
Interrupt vector area
FFFE16
FFFF16
Reserved ROM area
(Note 2)
Notes 1: This area is SFR in M38869FFA.
This area is Reserved in M38869MFA/MCA/M8A.
This area is not used in M38867M8A/E8A.
2: This area is usable in EPROM version and flash memory version.
Fig. 10 Memory map diagram
1-14
Special page
3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
000016
Port P0 (P0)
002016
Prescaler 12 (PRE12)
000116
Port P0 direction register (P0D)
002116
Timer 1 (T1)
000216
Port P1 (P1)
002216
Timer 2 (T2)
000316
Port P1 direction register (P1D)
002316
Timer XY mode register (TM)
000416
Port P2 (P2)
002416
Prescaler X (PREX)
000516
Port P2 direction register (P2D)
002516
Timer X (TX)
000616
Port P3 (P3)
002616
Prescaler Y (PREY)
000716
Port P3 direction register (P3D)
002716
Timer Y (TY)
000816
Port P4 (P4)
002816
Data bus buffer register 0 (DBB0)
000916
Port P4 direction register (P4D)
002916
Data bus buffer status register 0 (DBBSTS0)
000A16
Port P5 (P5)
002A16
Data bus buffer control register (DBBCON)
000B16
Port P5 direction register (P5D)
002B16
Data bus buffer register 1 (DBB1)
000C16
Port P6 (P6)
002C16
Data bus buffer status register 1 (DBBSTS1)
000D16
Port P6 direction register (P6D)
002D16
Comparator data register (CMPD)
000E16
Port P7 (P7)
002E16
Port control register 1 (PCTL1)
000F16
Port P7 direction register (P7D)
002F16
Port control register 2 (PCTL2)
001016
Port P8 (P8)/Port P4 input register (P4I)
003016
PWM0H register (PWM0H)
001116
Port P8 direction register (P8D)/Port P7 input register (P7I)
003116
PWM0L register (PWM0L)
001216
I2C data shift register (S0)
003216
PWM1H register (PWM1H)
001316
I2C address register (S0D)
003316
PWM1L register (PWM1L)
001416
I2C status register (S1)
003416
AD/DA control register (ADCON)
001516
I2C control register (S1D)
003516
A-D conversion register 1 (AD1)
001616
I2C clock control register (S2)
003616
D-A1 conversion register (DA1)
001716
I2C start/stop condition control register (S2D)
003716
D-A2 conversion register (DA2)
001816
Transmit/Receive buffer register (TB/RB)
003816
A-D conversion register 2 (AD2)
001916
Serial I/O1 status register (SIO1STS)
003916
Interrupt source selection register (INTSEL)
001A16
Serial I/O1 control register (SIO1CON)
003A16
Interrupt edge selection register (INTEDGE)
001B16
UART control register (UARTCON)
003B16
CPU mode register (CPUM)
001C16
Baud rate generator (BRG)
003C16
Interrupt request register 1 (IREQ1)
001D16
Serial I/O2 control register (SIO2CON)
003D16
Interrupt request register 2 (IREQ2)
001E16
Watchdog timer control register (WDTCON)
003E16
Interrupt control register 1 (ICON1)
001F16
Serial I/O2 register (SIO2)
003F16
Interrupt control register 2 (ICON2)
0FFE16
Flash memory control register (FCON)
(Note)
0FFF16
Flash command register (FCMD)
(Note)
Note: Only for flash memory version
Fig. 11 Memory map of special function register (SFR)
3886 Group User’s Manual
1-15
HARDWARE
FUNCTIONAL DESCRIPTION
I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input
port or output port.
When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
When the P8 function select bit of the port control register 2 (address 002F 16) is set to “1”, read from address 001016 becomes
the port P4 input register, and read from address 001116 becomes
the port P7 input register.
As the particular function, value of P42 to P46 pins and P70 to P75
pins can be read regardless of setting direction registers, by reading the port P4 input register (address 001016) or the port P7 input
register (address 001116) respectively.
Table 6 I/O port function (1)
Pin
Name
Input/Output
P00/P3REF
CMOS compatible
input level
CMOS 3-state output
or N-channel opendrain output
Port P0
P01–P07
P10–P17
Port P1
P20–P27
Port P2
I/O Structure
P30/PWM00
P31/PWM10
CMOS compatible
input level
CMOS 3-state output
Port P3
Non-Port Function
Address low-order byte
output
Analog comparator
power source input pin
Address low-order byte
output
Address high-order
byte output
Data bus I/O
Control signal I/O
PWM output
Key-on wake up input
Comparator input
Related SFRs
Ref.No.
CPU mode register
Port control register 1
Serial I/O2 control
register
(1)
CPU mode register
Port control register 1
(2)
CPU mode register
(3)
CPU mode register
Port control register 1
AD/DA control register
(4)
(5)
P32–P37
Control signal I/O
Key-on wake up input
Comparator input
CPU mode register
Port control register 1
(6)
P40/XCOUT
P41/XCIN
Sub-clock generating
circuit
CPU mode register
(7)
(8)
External interrupt input
Bus interface function
I/O
Interrupt edge selection
register
Port control register 2
Data bus buffer control
register
(9)
(10)
Serial I/O1 function input
Serial I/O1 control
register
Port control register 2
(11)
P42/INT0/
OBF00
P43/INT1/
OBF01
Input/output,
individual bits
P44/RXD
P45/TXD
Port P4
CMOS compatible
input level or TTL
input level
CMOS 3-state output
or N-channel opendrain output
Serial I/O1 function I/O
Bus interface function
output
P46/SCLK1
/OBF10
P47/SRDY1
/S1
1-16
Serial I/O1 function output
CMOS compatible
input level
CMOS 3-state output
(when selecting bus
interface function)
CMOS compatible
input level or TTL
input level
Serial I/O1 function output
Bus interface function
input
3886 Group User’s Manual
Serial I/O1 control
register
UART control register
Port control register 2
Serial I/O1 control
register
Data bus buffer control
register
Port control register 2
Serial I/O1 control
register
Data bus buffer control
register
(12)
(13)
(14)
HARDWARE
FUNCTIONAL DESCRIPTION
Table 7 I/O port function (2)
Pin
Name
Input/Output
I/O Format
Non-Port Function
Related SFRs
Ref.No.
Bus interface function
input
Data bus buffer control
register
(15)
External interrupt input
Bus interface function
input
Interrupt edge selection
register
Data bus buffer control
register
(16)
Timer X, timer Y function I/O
Timer XY mode register
(17)
D-A converter output
PWM output
AD/DA control register
UART control register
(18)
(19)
A-D converter input
AD/DA control register
(20)
Serial I/O2 function I/O
Serial I/O2 control
register
Port control register 2
(21)
(22)
(23)
Serial I/O2 function output
Bus interface function
input
Serial I/O2 control
register
Port control register 2
(24)
External interrupt input
Interrupt edge selection
register
Port control register 2
(25)
P76/SDA
P77/SCL
CMOS compatible
input level
N-channel open-drain
output
(when selecting I2CBUS interface
function)
CMOS compatible
input level or SMBUS
input level
I2C-BUS interface function I/O
I2C control register
(26)
(27)
P80/DQ0–
P87/DQ7
CMOS compatible
input level
CMOS 3-state output
(when selecting bus
interface function)
CMOS compatible
input level or TTL
input level
Bus interface function
I/O
Data bus buffer control
register
(28)
CMOS compatible
input level
CMOS 3-state output
(when selecting bus
interface function)
CMOS compatible
input level or TTL
input level
P50/A0
P51/INT20
/S0
P52/INT30
/R
P53/INT40
/W
Port P5
P54/CNTR0
P55/CNTR1
P56/DA1/
PWM01
P57/DA2/
PWM11
P60/AN0–
P67/AN7
CMOS compatible
input level
CMOS 3-state output
Port P6
P70/SIN2
P71/SOUT2
P72/SCLK2
Input/output,
individual bits
P73/SRDY2/
INT21
P74/INT31
P75/INT41
CMOS compatible
input level or TTL
input level
N-channel open-drain
output
Port P7
Port P8
Notes1: For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as function I/O ports, refer
to the applicable sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
3886 Group User’s Manual
1-17
HARDWARE
FUNCTIONAL DESCRIPTION
(1) Port P00
(2) Ports P01–P07,P1
P00–P03 output
structure selection bit
P00–P03,
P04–P07,
P10–P13,
P14–P17 output structure
selection bits
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Comparator reference power source input
Comparator reference input
pin select bit
(3) Port P2
(4) Port P30
Direction
register
Data bus
P30–P33 pull-up control bit
PWM0 output pin selection bit
PWM0 enable bit
Direction
register
Port latch
Data bus
Port latch
PWM00 output
(5) Port P31
P30–P33 pull-up control bit
Comparator
input
Key-on wake-up
(6) Ports P32–P37
PWM1 output pin selection bit
PWM1 enable bit
P30–P33,
P34–P37 pull-up control bit
Direction
register
Data bus
Direction
register
Port latch
Data bus
PWM10 output
Port latch
Comparator
input
Key-on wake-up
Comparator
input
Key-on wake-up
(7) Port P40
(8) Port P41
Port XC switch bit
Port XC switch bit
Direction
register
Direction
register
Data bus
Data bus
Port latch
Port latch
Oscillator
Port P41
Port XC switch bit
Fig. 12 Port block diagram (1)
1-18
3886 Group User’s Manual
Sub-clock generating circuit input
HARDWARE
FUNCTIONAL DESCRIPTION
(9) Port P42
(10) Port P43
P4 output structure selection bit
P4 output structure selection bit
OBF00 output enable bit
OBF01 output enable bit
Direction
register
Data bus
Direction
register
Port latch
Data bus
Port latch
✻1
✻1
✻2
✻2
OBF01 output
OBF00 output
INT1 interrupt input
INT0 interrupt input
(11) Port P44
(12) Port P45
P4 output structure selection bit
Serial I/O1 enable bit
Receive enable bit
P45/TXD P-channel output disable bit
Serial I/O1 enable bit
Transmit enable bit
Direction
register
Direction
register
Data bus
Port latch
Port latch
Data bus
✻1
✻1
✻2
✻2
Serial I/O1 output
Serial I/O1 input
(13) Port P46
(14) Port P47
Serial I/O1
P4 output structure selection bit
synchronous clock selection bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Serial I/O1 enable bit
SRDY1 output enable bit
Data bus buffer function
selection bit
Direction
register
Serial I/O1 mode selection bit
Serial I/O1 enable bit
OBF10 output enable bit
Direction
register
Port latch
Data bus
Port latch
Data bus
✻1
✻3
Serial I/O1 ready output
✻2
S1 input
Data bus buffer function
selection bit
Serial I/O1 clock output
OBF10 output
Serial I/O1 external clock input
(15) Port P50
(16) Ports P51,P52,P53
Data bus buffer enable bit
Data bus buffer enable bit
Direction
register
Data bus
Direction
register
Port latch
Port latch
Data bus
✻3
A0 input
Data bus buffer
enable bit
INT20, INT30, INT40 interrupt input
✻3
S0,R,W input
Data bus buffer
enable bit
✻1. The input level can be switched between CMOS compatible input level and TTL level by the P4 input level selection bit of the port control
register 2 (address 002F16).
✻2. The input level can be switched between CMOS compatible input level and TTL level by the P4 input level selection bit of the port control
register 2 (address 002F16).
The port P8 and port P4 input register can be switched by the P8 function selection bit of the port control register 2 (address 002F16).
✻3. The input level can be switched between CMOS compatible input level and TTL level by the input level selection bit of the data bus buffer
control register (address 002A16).
Fig. 13 Port block diagram (2)
3886 Group User’s Manual
1-19
HARDWARE
FUNCTIONAL DESCRIPTION
(17) Ports P54,P55
(18) Port P56
Direction
register
Data bus
PWM0 output pin selection bit
PWM0 enable bit
Direction
register
Port latch
Data bus
Port latch
Pulse output mode
Timer output
CNTR0,CNTR1 interrupt input
PWM01 output
(19) Port P57
D-A converter output
D-A1 output enable bit
(20) Port P6
PWM1 output pin selection bit
PWM1 enable bit
Direction
register
Direction
register
Data bus
Data bus
Port latch
Port latch
A-D converter input
Analog input pin selection bit
PWM11 output
D-A converter output
D-A2 output enable bit
(21) Port P70
(22) Port P71
Serial IO/2 transmit completion signal
Serial I/O2 port selection bit
Direction
register
Direction
register
Port latch
Data bus
Port latch
Data bus
✻4
✻5
✻4
Serial I/O2 input
✻5
Serial I/O2 output
(23) Port P72
(24) Port P73
Serial I/O2 synchronization
clock selection bit
Serial I/O2 port selection bit
Direction
register
SRDY2 output enable bit
Direction
register
Data bus
Data bus
Port latch
Port latch
✻4
✻4
✻5
✻5
Serial I/O2 ready output
Serial I/O2 clock output
INT21 interrupt input
Serial I/O2
external clock input
✻4. The input level can be switched between CMOS compatible input level and TTL level by the P7 input level selection bit of the port
control register 2 (address 002F16).
✻5. The input level can be switched between CMOS compatible input level and TTL level by the P7 input level selection bit of the port
control register 2 (address 002F16).
The port P8 direction register and port P7 input register can be switched by the P8 function selection bit of the port control register 2
(address 002F16).
Fig. 14 Port block diagram (3)
1-20
3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
(25) Ports P74,P75
(26) Port P76
I2C-BUS interface
enable bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
✻4
✻5
INT31,INT41 interrupt input
SDA output
SDA input
(27) Port P77
(28) Port P8
S0
S1
R
Data bus buffer enable bit
Direction
register
I2C-BUS interface
enable bit
Direction
register
Data bus
✻6
Data bus
Port latch
Port latch
Output buffer 0
SCL output
SCL input
✻6
Status register 0
Output buffer 1
Status register 1
✻3
Input buffer 0
✻3
Input buffer 1
✻6. The input level can be switched between CMOS compatible input level and SMBUS level by the I2C-BUS interface pin input
selection bit of the I2C control register (address 001516).
Fig. 15 Port block diagram (4)
3886 Group User’s Manual
1-21
HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
Port control register 1
(PCTL1: address 002E16)
P00–P03 output structure selection bit
0: CMOS
1: N-channel open-drain
P04–P07 output structure selection bit
0: CMOS
1: N-channel open-drain
P10–P13 output structure selection bit
0: CMOS
1: N-channel open-drain
P14–P17 output structure selection bit
0: CMOS
1: N-channel open-drain
P30–P33 pull-up control bit
0: No pull-up
1: Pull-up
P34–P37 pull-up control bit
0: No pull-up
1: Pull-up
PWM0 enable bit
0: PWM0 output disabled
1: PWM0 output enabled
PWM1 enable bit
0: PWM1 output disabled
1: PWM1 output enabled
b7
b0
Port control register 2
(PCTL2: address 002F16)
P4 input level selection bit (P42–P46)
0: CMOS level input
1: TTL level input
P7 input level selection bit (P70–P75)
0: CMOS level input
1: TTL level input
P4 output structure selection bit (P42, P43, P44, P46)
0: CMOS
1: N-channel open-drain
P8 function selection bit
0: Port P8/Port P8 direction register
1: Port P4 input register/Port P7 input register
INT2, INT3, INT4 interrupt switch bit
0: INT20, INT30, INT40 interrupt
1: INT21, INT31, INT41 interrupt
Timer Y count source selection bit
0: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
1: f(XCIN)
Oscillation stabilizing time set after STP instruction released bit
0: Automatic set “0116” to timer 1 and “FF16” to prescaler 12
1: No automatic set
Port output P42/P43 clear function selection bit
0: Only software clear
1: Software clear and output data bus buffer 0 reading
(system bus side)
Fig. 16 Structure of port I/O related register
1-22
3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
INTERRUPTS
Interrupt Source Selection
Interrupts occur by 16 sources among 21 sources: nine external,
eleven internal, and one software.
Any of the following interrupt sources can be selected by the interrupt source selection register (address 003916).
1. INT0 or Input buffer full
2. INT1 or Output buffer empty
3. Serial I/O1 transmission or SCLSDA
4. CNTR0 or SCLSDA
5. Serial I/O2 or I2C
6. INT2 or I2C
7. CNTR1 or Key-on wake-up
8. A-D conversion or Key-on wake-up
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
External Interrupt Pin Selection
The occurrence sources of the external interrupt INT2, INT3, and
INT4 can be selected from either input from INT20, INT30, INT 40
pin, or input from INT21, INT31, INT41 pin by the INT2, INT3, INT4
interrupt switch bit (bit 4 of address 002F16).
■ Notes
Interrupt Operation
By acceptance of an interrupt, the following operations are automatically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
When setting of the following register or bit is changed, the interrupt request bit may be set to “1.”
• Interrupt edge selection register (address 003A16)
• Interrupt source selection register (address 003916)
• INT2, INT3, INT4 interrupt switch bit of Port control register 2 (bit
4 of address 002F16)
Accept the interrupt after clearing the interrupt request bit to “0” after interrupt is disabled and the above register or bit is set.
3886 Group User’s Manual
1-23
HARDWARE
FUNCTIONAL DESCRIPTION
Table 8 Interrupt vector addresses and priority
Interrupt Source
Reset (Note 2)
Priority
1
Vector Addresses (Note 1)
High
Low
FFFD16
FFFC16
INT0
2
FFFB16
FFFA16
Interrupt Request
Generating Conditions
At reset
Non-maskable
At detection of either rising or
falling edge of INT0 input
External interrupt
(active edge selectable)
Input buffer full
(IBF)
At input data bus buffer writing
INT1
At detection of either rising or
falling edge of INT1 input
Output buffer
empty (OBE)
Serial I/O1
reception
Serial I/O1
transmission
3
FFF916
FFF816
4
FFF716
FFF616
5
FFF516
FFF416
SCL, SDA
Timer X
Timer Y
Timer 1
Timer 2
6
7
8
9
FFF316
FFF216
FFF116
FFEF16
FFED16
FFF016
FFEE16
FFEC16
CNTR0
At timer 1 underflow
At timer 2 underflow
At detection of either rising or
falling edge of CNTR0 input
FFE916
FFE816
12
FFE716
FFE616
At completion of serial I/O2 data
transfer
FFE416
At completion of data transfer
At detection of either rising or
falling edge of INT2 input
13
FFE516
I 2C
At detection of either rising or
falling edge of SCL or SDA
At detection of either rising or
falling edge of CNTR1 input
At falling of port P3 (at input) input logical level AND
14
FFE316
FFE216
At detection of either rising or
falling edge of INT3 input
INT4
15
FFE116
FFE016
At detection of either rising or
falling edge of INT4 input
16
FFDF16
FFDE16
External interrupt
(active edge selectable)
STP release timer underflow
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (falling edge
valid)
Valid when serial I/O2 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
At completion of A-D conversion
A-D converter
Key-on wake-up
17
FFDD16
FFDC16
At falling of port P3 (at input) input logical level AND
At BRK instruction execution
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
1-24
Valid when serial I/O1 is selected
At completion of data transfer
INT3
BRK instruction
Valid when serial I/O1 is selected
At timer Y underflow
11
I 2C
INT2
At completion of serial I/O1
transfer shift or when transmission buffer is empty
At detection of either rising or
falling edge of SCL or SDA
At timer X underflow
FFEA16
Key-on wake-up
Serial I/O2
At completion of serial I/O1 data
reception
FFEB16
CNTR1
External interrupt
(active edge selectable)
At output data bus buffer reading
10
SCL, SDA
Remarks
3886 Group User’s Manual
External interrupt (falling edge
valid)
Non-maskable software interrupt
HARDWARE
FUNCTIONAL DESCRIPTION
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
Fig. 17 Interrupt control
b7
b0 Interrupt edge selection register
(INTEDGE : address 003A16)
INT0 active edge selection bit
INT1 active edge selection bit
Not used (returns “0” when read)
INT2 active edge selection bit
INT3 active edge selection bit
INT4 active edge selection bit
Not used (returns “0” when read)
b7
0 : Falling edge active
1 : Rising edge active
b0 Interrupt request register 1
(IREQ1 : address 003C16)
b7
INT0/input buffer full interrupt request
bit
INT1/output buffer empty interrupt
request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit/SCL, SDA interrupt
request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
b7
b0
CNTR0/SCL, SDA interrupt request bit
CNTR1/key-on wake-up interrupt
request bit
Serial I/O2/I2C interrupt request bit
INT2/I2C interrupt request bit
INT3 interrupt request bit
INT4 interrupt request bit
AD converter/key-on wake-up interrupt
request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
Interrupt control register 1
(ICON1 : address 003E16)
b0 Interrupt request register 2
(IREQ2 : address 003D16)
INT0/input buffer full interrupt enable bit
INT1/output buffer empty interrupt
enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit/SCL, SDA interrupt
enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
b0
Interrupt control register 2
(ICON2 : address 003F16)
CNTR0/SCL, SDA interrupt enable bit
CNTR1/key-on wake-up interrupt
enable bit
Serial I/O2/I2C interrupt enable bit
INT2/I2C interrupt enable bit
INT3 interrupt enable bit
INT4 interrupt enable bit
AD converter/key-on wake-up interrupt
enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 18 Structure of interrupt-related registers (1)
3886 Group User’s Manual
1-25
HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
Interrupt source selection register
(INTSEL: address 003916)
INT0/input buffer full interrupt source selection bit
0 : INT0 interrupt
1 : Input buffer full interrupt
INT1/output buffer empty interrupt source selection bit
0 : INT1 interrupt
1 : Output buffer empty interrupt
Serial I/O1 transmit/SCL,SDA interrupt source selection bit
0 : Serial I/O1 transmit interrupt
1 : SCL,SDA interrupt
CNTR0/SCL,SDA interrupt source selection bit
0 : CNTR0 interrupt
1 : SCL,SDA interrupt
(Do not write “1” to these bits simultaneously.)
Serial I/O2/I2C interrupt source selection bit
0 : Serial I/O2 interrupt
1 : I2C interrupt
INT2/I2C interrupt source selection bit
0 : INT2 interrupt
1 : I2C interrupt
(Do not write “1” to these bits simultaneously.)
CNTR1/key-on wake-up interrupt source selection bit
0 : CNTR1 interrupt
1 : Key-on wake-up interrupt
(Do not write “1” to these bits simultaneously.)
AD converter/key-on wake-up interrupt source selection bit
0 : A-D converter interrupt
1 : Key-on wake-up interrupt
Fig. 19 Structure of interrupt-related registers (2)
1-26
3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Key Input Interrupt (Key-on Wake Up)
A Key input interrupt request is generated by applying “L” level to
any pin of port P3 that have been set to input mode. In other
words, it is generated when AND of input level goes from “1” to
“0”. An example of using a key input interrupt is shown in Figure
20, where an interrupt request is generated by pressing one of the
keys consisted as an active-low key matrix which inputs to ports
P30–P33.
Port PXx
“L” level output
Port control register 1
Bit 5 = “1”
Port P37
direction register = “1”
✻
✻✻
✻
✻✻
Key input interrupt request
Port P37
latch
P37 output
Port P36
direction register = “1”
Port P36
latch
P36 output
✻
Port P35
direction register = “1”
✻✻
Port P35
latch
P35 output
✻
Port P34
direction register = “1”
✻✻
Port P34
latch
P34 output
✻
P33 input
✻
Port control register 1
Bit 4 = “1”
✻✻
Port P33
latch
✻✻
✻
Port P32
latch
Port P31
direction register = “0”
✻✻
P31 input
P30 input
Port P3
Input reading circuit
Comparator circuit
Port P32
direction register = “0”
P32 input
✻
Port P33
direction register = “0”
Port P31
latch
Port P30
direction register = “0”
✻✻
Port P30
latch
✻ P-channel transistor for pull-up
✻✻ CMOS output buffer
Fig. 20 Connection example when using key input interrupt and port P3 block diagram
3886 Group User’s Manual
1-27
HARDWARE
FUNCTIONAL DESCRIPTION
TIMERS
Timer 1 and Timer 2
The 3886 group has four timers: timer X, timer Y, timer 1, and
timer 2.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are count down. When the timer reaches “0016”, an underflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
The count source of prescaler 12 is the oscillation frequency divided by 16. The output of prescaler 12 is counted by timer 1 and
timer 2, and a timer underflow sets the interrupt request bit.
Timer X and Timer Y
Timer X and Timer Y can each select in one of four operating
modes by setting the timer XY mode register.
(1) Timer Mode
The timer counts f(XIN)/16.
(2) Pulse Output Mode
b7
b0
Timer XY mode register
(TM : address 002316)
Timer X operating mode bit
b1b0
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR0 active edge selection bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Timer X count stop bit
0: Count start
1: Count stop
Timer Y operating mode bit
b5b4
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR1 active edge selection bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Timer Y count stop bit
0: Count start
1: Count stop
Fig. 21 Structure of timer XY mode register
1-28
Timer X (or timer Y) counts f(XIN)/16. Whenever the contents of
the timer reach “00 16 ”, the signal output from the CNTR 0 (or
CNTR1) pin is inverted. If the CNTR0 (or CNTR1) active edge selection bit is “0”, output begins at “ H”.
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P54 ( or port P55) direction register to output mode.
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode,
except that the timer counts signals input through the CNTR0 or
CNTR1 pin.
When the CNTR0 (or CNTR1) active edge selection bit is “0”, the
rising edge of the CNTR0 (or CNTR1) pin is counted.
When the CNTR0 (or CNTR1) active edge selection bit is “1”, the
falling edge of the CNTR0 (or CNTR1) pin is counted.
(4) Pulse Width Measurement Mode
If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer
counts f(X IN)/16 while the CNTR0 (or CNTR1) pin is at “H”. If the
CNTR 0 (or CNTR 1 ) active edge selection bit is “1”, the timer
counts while the CNTR0 (or CNTR1) pin is at “L”.
The count can be stopped by setting “1” to the timer X (or timer Y)
count stop bit in any mode. The corresponding interrupt request
bit is set each time a timer overflows.
The count source for timer Y in the timer mode or the pulse output
mode can be selected from either f(XIN)/16 or f(XCIN) by the timer
Y count source selection bit of the port control register 2 (bit 5 of
address 002F16).
3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Data bus
Divider
Oscillator
f(XIN)
Prescaler X latch (8)
1/16
Pulse width
measurement
mode
(f(XCIN) in low-speed mode)
Timer mode
Pulse output mode
Prescaler X (8)
CNTR0 active
edge selection
bit “0”
P54/CNTR0
“1 ”
Event
counter
mode
Timer X (8)
To timer X interrupt
request bit
Timer X count stop bit
To CNTR0 interrupt
request bit
CNTR0 active
edge selection “1”
bit
“0”
Q
Toggle flip-flop T
Q
R
Timer X latch write pulse
Pulse output mode
Port P54
latch
Port P54
direction register
Timer X latch (8)
Pulse output mode
Data bus
Oscillator
Divider
f(XIN)
Timer Y count source
selection bit
“0 ”
1/16
(f(XCIN) in low-speed mode)
Prescaler Y latch (8)
Oscillator
“1”
f(XCIN)
Prescaler Y (8)
CNTR1 active
edge selection
bit “0”
P55/CNTR1
“1 ”
Event
counter
mode
Port P55
direction register
Timer Y (8)
To timer Y interrupt
request bit
Timer Y count stop bit
To CNTR1 interrupt
request bit
CNTR1 active
edge selection “1”
bit
Q
Toggle flip-flop T
Q
Port P55
latch
Timer Y latch (8)
Pulse width
Timer mode
measurement mode Pulse output mode
“0 ”
R
Timer Y latch write pulse
Pulse output mode
Pulse output mode
Data bus
Prescaler 12 latch (8)
Oscillator
f(XIN)
Timer 1 latch (8)
Timer 2 latch (8)
Timer 1 (8)
Timer 2 (8)
Divider
1/16
Prescaler 12 (8)
To timer 2 interrupt
request bit
(f(XCIN) in low-speed mode)
To timer 1 interrupt
request bit
Fig. 22 Block diagram of timer X, timer Y, timer 1, and timer 2
3886 Group User’s Manual
1-29
HARDWARE
FUNCTIONAL DESCRIPTION
SERIAL I/O
Serial I/O1
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O1 mode can be selected by setting
the serial I/O1 mode selection bit of the serial I/O1 control register
(bit 6 of address 001A16) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
Data bus
Serial I/O1 control register
Address 001816
Receive buffer register
Receive interrupt request (RI)
Receive shift register
P44/RXD
Address 001A16
Receive buffer full flag (RBF)
Shift clock
Clock control circuit
P46/SCLK1/OBF10
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
1/4
BRG count source selection bit
f(XIN)
(f(XCIN) in low-speed mode)
1/4
P47/SRDY1/S1
F/F
Address 001C16
Clock control circuit
Falling-edge detector
Shift clock
P45/TXD
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit shift register
Transmit buffer register
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Address 001916
Address 001816
Data bus
Fig. 23 Block diagram of clock synchronous serial I/O1
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
D0
D1
D2
D3
D4
D5
D6
D7
Serial input RxD
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY1
Write pulse to receive/transmit
buffer register (address 001816)
TBE = 0
RBF = 1
TSC = 1
Overrun error (OE)
detection
TBE = 1
TSC = 0
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1
control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 24 Operation of clock synchronous serial I/O1 function
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3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit of the serial I/O1 control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Data bus
Address 001816
Serial I/O1 control register Address 001A16
Receive buffer register
P44/RXD
Receive buffer full flag (RBF)
Receive interrupt request (RI)
OE
Character length selection bit
ST detector
7 bits
Receive shift register
1/16
8 bits
PE FE
SP detector
Clock control circuit
UART control register
Address 001B16
Serial I/O1 synchronous clock selection bit
P46/SCLK1/OBF10
BRG count source selection bit Frequency division ratio 1/(n+1)
f(XIN)
Baud rate generator
(f(XCIN) in low-speed mode)
Address 001C16
1/4
ST/SP/PA generator
1/16
Transmit shift register
P45/TXD
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer register
Address 001816
Transmit buffer empty flag (TBE)
Serial I/O1 status register Address 001916
Data bus
Fig. 25 Block diagram of UART serial I/O1
3886 Group User’s Manual
1-31
HARDWARE
FUNCTIONAL DESCRIPTION
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TSC=0
TBE=1
Serial output TXD
TBE=0
TSC=1✽
TBE=1
ST
D0
D1
SP
ST
D0
SP
D1
✽
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Generated at 2nd bit in 2-stop-bit mode
Receive buffer read
signal
RBF=0
RBF=1
Serial input RXD
ST
D0
D1
SP
RBF=1
ST
D0
D1
SP
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 26 Operation of UART serial I/O1 function
[Serial I/O1 Control Register (SIO1CON)]
001A16
[Transmit Buffer Register/Receive Buffer
Register (TB/RB)] 001816
The serial I/O1 control register consists of eight control bits for the
serial I/O function.
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P45/TXD pin.
[Serial I/O1 Status Register (SIO1STS)]
001916
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE
(bit 7 of the serial I/O control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at
reset, but if the transmit enable bit (bit 4) of the serial I/O1 control
register has been set to “1”, the transmit shift completion flag (bit
2) and the transmit buffer empty flag (bit 0) become “1”.
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3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
b7
Serial I/O1 status register
(SIO1STS : address 001916)
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
SRDY1 output enable bit (SRDY)
0: P47 pin operates as ordinary I/O pin
1: P47 pin operates as SRDY1 output pin
Overrun error flag (OE)
0: No error
1: Overrun error
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Not used (returns “1” when read)
b0
Serial I/O1 control register
(SIO1CON : address 001A16)
BRG count source selection bit (CSS)
0: f(XIN) (f(XCIN) in low-speed mode)
1: f(XIN)/4 (f(XCIN)/4 in low-speed mode)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
b7
b0
Serial I/O1 enable bit (SIOE)
0: Serial I/O disabled
(pins P44 to P47 operate as ordinary I/O pins)
1: Serial I/O enabled
(pins P44 to P47 operate as serial I/O pins)
UART control register
(UARTCON : address 001B16)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P45/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
Fig. 27 Structure of serial I/O1 control registers
3886 Group User’s Manual
1-33
HARDWARE
FUNCTIONAL DESCRIPTION
Serial I/O2
b7
The serial I/O2 function can be used only for clock synchronous
serial I/O.
For clock synchronous serial I/O the transmitter and the receiver
must use the same clock. If the internal clock is used, transfer is
started by a write signal to the serial I/O2 register.
b0
Serial I/O2 control register
(SIO2CON : address 001D16)
Internal synchronous clock selection bits
b2 b1 b0
0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode)
0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode)
0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode)
1 1 0: f(XIN)/128 (f(XCIN)/128 in low-speed mode)
1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode)
[Serial I/O2 Control Register (SIO2CON)]
001D16
Serial I/O2 port selection bit
0: I/O port
1: SOUT2,SCLK2 signal output
The serial I/O2 control register contains seven bits which control
various serial I/O functions.
SRDY2 output enable bit
0: I/O port
1: SRDY2 signal output
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O2 synchronous clock selection bit
0: External clock
1: Internal clock
Comparator reference input selection bit
0: P00/P3REF input
1: Reference input fixed
Fig. 28 Structure of serial I/O2 control register
1/8
XCIN
Internal synchronous
clock selection bits
1/16
“10”
Divider
Main clock divide ratio
selection bits (Note)
“00”
“01”
XIN
1/32
Data bus
1/64
1/128
1/256
P73 latch
P73/SRDY2
/INT21
Serial I/O2 synchronous
clock selection bit “1”
SRDY2
“1”
SRDY2 output enable bit
Synchronization
circuit
SCLK2
“0”
“0 ”
External clock
P72 latch
“0 ”
P72/SCLK2
“1 ”
Serial I/O2 port selection bit
Serial I/O counter 2 (3)
P71 latch
“0 ”
P71/SOUT2
“1 ”
Serial I/O2 port selection bit
P70/SIN2
Serial I/O2 register (8)
Note: These are assigned to bits 7 and 6 of the CPU mode register (address 003B16).
These bits select any of the high-speed mode, the middle-speed mode, and the low-speed mode.
Fig. 29 Block diagram of serial I/O2 function
1-34
3886 Group User’s Manual
Serial I/O2
interrupt request
HARDWARE
FUNCTIONAL DESCRIPTION
Transfer clock (Note 1)
Serial I/O2 register
write signal
(Note 2)
Serial I/O2 output SOUT2
D0
D1
D2
D3
D4
D5
D6
D7
Serial I/O2 input SIN2
Receive enable signal SRDY2
Serial I/O2 interrupt request bit set
Notes 1: When the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial
I/O2 control register.
2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion.
Fig. 30 Timing of serial I/O2 function
3886 Group User’s Manual
1-35
HARDWARE
FUNCTIONAL DESCRIPTION
PULSE WIDTH MODULATION (PWM)
OUTPUT CIRCUIT
The 3886 group has two PWM output circuits, PWM0 and PWM1,
with 14-bit resolution respectively. These can operate independently. When the oscillation frequency X IN is 10 MHz, the
minimum resolution bit width is 200 ns and the cycle period is
3276.8 µs. The PWM timing generator supplies a PWM control
signal based on a signal that is the frequency of the XIN clock.
The following explanation assumes f(XIN) = 8 MHz.
Data Bus
Set to “1”
at write
PWM0L register (address 003116)
bit 7
bit 5
bit 0
bit 0
bit 7
PWM0H register
(address 003016)
PWM0 latch (14 bits)
MSB
LSB
14
P30 latch
P30/PWM00
PWM0
14-bit PWM0 circuit
PWM0 enable bit
f(XIN)
(8MHz)
1/2
(4MHz)
PWM0
timing
generator
PWM0 output selection bit
PWM0 enable bit
(64 µs period)
(4096 µs period)
P30 direction register
P56 latch
P56/DA1/PWM01
PWM0 enable bit
PWM0 output selection bit
PWM0 enable bit
P56 direction register
Fig. 31 PWM block diagram (PWM0)
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3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Data Setup (PWM0)
mum resolution (250 ns).
“H” or “L” of the bit in the ADD part shown in Figure 33 is added
to this “H” duration by the contents of the low-order 6-bit data according to the rule in Table 9.
That is, only in the sub-period tm shown by Table 9 in the PWM
cycle period T = 64t, its “H” duration is lengthened to the minimum resolution τ added to the length of other periods.
The PWM0 output pin also functions as port P3 0 or P5 6 . The
PWM0 output pin is selected from either P3 0 /PWM 00 or
P5 6 /PWM 01 by bit 4 of the AD/DA control register (address
003416).
The PWM0 output becomes enabled state by setting bit 6 of the
port control register 1 (address 002E16). The high-order eight bits
of output data are set in the PWM0H register (address 003016 )
and the low-order six bits are set in the PWM0L register (address
003116).
PWM1 is set as the same way.
For example, if the high-order eight bits of the 14-bit data are
0316 and the low-order six bits are 0516 , the length of the “H”level output in sub-periods t8, t24, t32, t40, and t56 is 4 τ, and its
length is 3 τ in all other sub-periods.
Time at the “H” level of each sub-period almost becomes equal,
because the time becomes length set in the high-order 8 bits or
becomes the value plus τ, and this sub-period t (= 64 µs, approximate 15.6 kHz) becomes cycle period approximately.
PWM Operation
The 14-bit PWM data is divided into the low-order six bits and the
high-order eight bits in the PWM latch.
The high-order eight bits of data determine how long an “H”-level
signal is output during each sub-period. There are 64 sub-periods
in each period, and each sub-period is 256 ✕ τ (64 µs) long. The
signal is “H” for a length equal to N times τ, where τ is the mini-
Transfer From Register to Latch
Data written to the PWML register is transferred to the PWM
latch at each PWM period (every 4096 µs), and data written to
the PWMH register is transferred to the PWM latch at each subperiod (every 64 µs). The signal which is output to the PWM
output pin is corresponding to the contents of this latch. When
the PWML register is read, the latch contents are read. However,
bit 7 of the PWML register indicates whether the transfer to the
PWM latch is completed; the transfer is completed when bit 7 is
“0” and it is not done when bit 7 is “1.”
Table 9 Relationship between low-order 6 bits of data and
period set by the ADD bit
Low-order 6 bits of data (PWML)
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
Sub-periods tm Lengthened (m=0 to 63)
LSB
0
1
0
0
0
0
0
None
m=32
m=16, 48
m=8, 24, 40, 56
m=4, 12, 20, 28, 36, 44, 52, 60
m=2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
m=1, 3, 5, 7, ................................................ ,57, 59, 61, 63
4096 µs
64 µs
64 µs
64 µs
64 µs
m=0
m=7
m=8
m=9
15.75 µs
15.75 µs
15.75 µs
16.0 µs
Pulse width modulation register H :
00111111
Pulse width modulation register L :
000101
Sub-periods where “H” pulse width is 16.0 µs :
Sub-periods where “H” pulse width is 15.75 µs :
15.75 µs
64 µs
m=63
15.75 µs
15.75 µs
m = 8, 24, 32, 40, 56
m = all other values
Fig. 32 PWM timing
3886 Group User’s Manual
1-37
HARDWARE
FUNCTIONAL DESCRIPTION
Data 6A16 stored at address 003016
PWM0H
register
5916
Data 7B16 stored at address 003016
6A16
7B16
Data 2416 stored at address 003116
PWM0L
register
1316
Bit 7 cleared after transfer
A416
Data 3516 stored at address 003116
2416
3516
Transfer from register to latch
PWM0 latch
(14bits)
165316
1A9316
Transfer from register to latch
B516
1AA416
1AA416
1EE416
1EF516
When bit 7 of PWM0L is 0, transfer
from register to latch is disabled.
T = 4096 µs
(64 ✕ 64 µs)
t = 64 µs
Example 1
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6B
5
2
5
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
PWM0 output
1
low-order
6-bit output:
H
L
6A16, 2416
Example 2
5
5
5
5
6B16 ·············· 36 times
(107)
6A
6A 6A
6A
6B
6A
5
5
5
6A16 ············· 28 times
(106)
6B
6A
6B
6A
6A
6A
5
5
5
5
5
106 ✕ 64 + 36
6B
6A
6B
6A
6B
6A
6A
6A
6B
6A
6B
6A
6B
6A
PWM0 output
low-order
6-bit output:
H
L
6A16, 1816
4
6B16
3
··············
4
4
3
4
6A16 ······· 40 times
24 times
4
3
4
106 ✕ 64 + 24
t = 64 µs
(256 ✕ 0.25 µs)
Minimum resolution bit width τ = 0.25 µs
PWM output
2
6B
6A
69
68
67
·······
02
01
ADD
8-bit
counter
02
01
00
FF
The ADD
portions with
additional t are
determined by
PWML.
FE
FD
FC
·······
97
96
95
·······
02
01
H duration length specified by PWM0H
256 τ (64 µs), fixed
Fig. 33 14-bit PWM timing (PWM0)
1-38
6A
69
68
67
·······
02
01
FF
FE
FD
FC
·······
97
96
ADD
3886 Group User’s Manual
00
95
·······
6A
HARDWARE
FUNCTIONAL DESCRIPTION
BUS INTERFACE
The 3886 group has a 2-byte bus interface function which is almost functionally equal to MELPS8-41 series and the control
signal from the host CPU side can operate it (slave mode).
It is possible to connect the 3886 group with the RD and WR
separated CPU bus directly. Figure 36 shows the block diagram of
the bus interface function.
The data bus buffer function I/O pins (P42, P43, P4 6, P47, P5 0–
P53, P8) also function as the normal digital port I/O pins. When bit
0 (data bus buffer enable bit) of the data bus buffer control register (address 002A16) is “0,” these pins become the normal digital
port I/O pins. When it is “1,” these bits become the data bus buffer
function I/O pins.
Input buffer
full flag 0 IBF0
The selection of either the single data bus buffer mode, which
uses 1 byte: data bus buffer 0 only, or the double data bus buffer
mode, which uses 2 bytes: data bus buffer 0 and data bus buffer
1, is performed by bit 1 (data bus buffer function selection bit) of
the data bus buffer control register (address 002A16). Port P47 becomes S1 input in the double data bus buffer mode. When data is
written from the host CPU side, an input buffer full interrupt occurs. When data is read from the host CPU, an output buffer
empty interrupt occurs. This microcomputer shares two input
buffer full interrupt requests and two output buffer empty interrupt
requests as shown in Figure 34, respectively.
One-shot pulse
generating circuit
Rising edge
detection circuit
Input buffer full interrupt
request signal IBF
Input buffer
full flag 1 IBF1
Output buffer
full flag 0
OBF0
One-shot pulse
generating circuit
Rising edge
detection circuit
OBE0
Output buffer
full flag 1
OBF1
OBE1
Rising edge
detection circuit
One-shot pulse
generating circuit
Rising edge
detection circuit
One-shot pulse
generating circuit
Output buffer empty interrupt
request signal OBE
IBF0
IBF1
IBF
Interrupt request is set at this rising edge
OBF0
(OBE0)
OBF1
(OBE1)
OBE
Interrupt request is set at this rising edge
Fig. 34 Interrupt request circuit of data bus buffer
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HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
Data bus buffer control register
(DBBCON : address 002A16)
Data bus buffer enable bit
0 : P50–P53, P8 I/O port
1 : Data bus buffer enabled
Data bus buffer function selection bit
0 : Single data bus buffer mode (P47 functions as I/O port.)
1 : Double data bus buffer mode (P47 functions S1 input.)
OBF0 output selection bit
0 : OBF00 valid
1 : OBF01 valid
OBF00 output enable bit
0 : P42 functions as port I/O pin.
1 : P42 functions as OBF00 output pin.
OBF01 output enable bit
0 : P43 functions as port I/O pin.
1 : P43 functions as OBF01 output pin.
OBF10 output enable bit
0 : P46 functions as port I/O pin.
1 : P46 functions as OBF10 output pin.
Input level selection bit
0 : CMOS level input
1 : TTL level input
Reserved
Do not write “1” to this bit.
b7
b0
Data bus buffer status register 0
(DBBSTS0 : address 002916)
Output buffer full flag 0 (OBF0)
0 : Buffer empty
1 : Buffer full
Input buffer full flag 0 (IBF0)
0 : Buffer empty
1 : Buffer full
User definable flag (U02)
This flag can be defined by user freely.
A00 flag (A00)
This flag indicates the condition of A00 status
when the IBF0 flag is set.
User definable flag (U04–U07)
This flag can be defined by user freely.
b7
b0
Data bus buffer status register 1
(DBBSTS1 : address 002C16)
Output buffer full flag 1 (OBF1)
0 : Buffer empty
1 : Buffer full
Input buffer full flag 1 (IBF1)
0 : Buffer empty
1 : Buffer full
User definable flag (U12)
This flag can be defined by user freely.
A01 flag (A01)
This flag indicates the condition of A01 status
when the IBF1 flag is set.
User definable flag (U14–U17)
This flag can be defined by user freely.
Fig. 35 Structure of bus interface related register
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3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
(Address 002A16)
b7
b6
b5
b4
b3
b2
b1
b0
P42/INT0/OBF00
P43/INT1/OBF01
P50/A0
P51/INT20/S0
P52/INT30/R
P53/INT40/W
(Address 002916)
U07
P80/DQ0
U06
U05
U04
A00
U02 IBF0 OBF0
Output data bus buffer 0
(Address 002816)
P82/DQ2
WR
DBBSTS0
P84/DQ4
System bus
Input data bus buffer 0
P83/DQ3
Internal data bus
P81/DQ1
(Address 002816)
RD
DBB0
RD
DBB1
Input data bus buffer 1
P85/DQ5
DBBSTS1
WR
(Address 002B16)
P86/DQ6
P87/DQ7
Output data bus buffer 1
(Address 002B16)
U17
U16
U15
U14
A01
U12
IBF1 OBF1
(Address 002C16)
P47/SRDY1/S1
P46/SCLK1/OBF10
Fig. 36 Bus interface device block diagram
3886 Group User’s Manual
1-41
HARDWARE
FUNCTIONAL DESCRIPTION
[Data Bus Buffer Status Register 0, 1
(DBBSTS0, DBBSTS1)] 002916, 002C16
The data bus buffer status registers 0 and 1 consist of eight bits.
Bits 0, 1, and 3 are read-only bits and indicate the condition of the
data bus buffer. Bits 2, 4, 5, 6, and 7 are user definable flags
which can be set by program, and can be read/written. This register can be read from the host CPU when the A 0 pin is set to “H”
only.
•Bit 0: Output buffer full flag OBF0, OBF1
When writing data to the output data bus buffer, these flags are
set to “1”. When reading the output data bus buffer from the host
CPU, these flags are cleared to “0”.
•Bit 1: Input buffer full flag IBF0, IBF1
When writing data from the host CPU to the input data bus
buffer, these flags are set to “1”. When reading the input data
bus buffer from the slave CPU side, these flags are cleared to
“0”.
•Bit 3: A0 flag A00, A01
When writing data from the host CPU to the input data bus
buffer, the level of the A0 pin is latched.
[Input Data Bus Buffer Register 0, 1 (DBBIN0,
DBBIN1)] 002816, 002B16
Data on the data bus is latched to DBBIN by writing request from
the host CPU. Data of DBBIN can be read from the data bus
buffer registers (address 002816 or 002B16) on SFR.
[Output Data Bus Buffer Register 0, 1
(DBBOUT0, DBBOUT1)] 002816, 002B16
When writing data to the data bus buffer registers (address 002816
or 002B16) on SFR, data is set to DBBOUT. Data of DBBOUT is
output from the host CPU to the data bus by performing the reading request when the A0 pin is set to “L”.
[Port control Register 2 (PCTL2)] 002F16
Even if the data bus buffer function is enabled, both P42 and P43
function as ports when the OBF00 output enable bit (bit 3 of address 2A16) or the OBF01 output enable bit (bit 4 of address 2A16)
is “0”. Ports P42 and P43 are cleared to “0” by changing the input
buffer full flag 0 (bit 1 of address 2916) from “1” to “0” under the following conditions: the port output P42/P43 clear function selection
bit (bit 7) is set to “1”, both ports are in the output mode of the port
function, and both port latches are “1”.
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HARDWARE
FUNCTIONAL DESCRIPTION
Table 10 Function description of control I/O pins at bus interface function selected
Pin
Name
OBF00
output
enable bit
OBF01
output
enable bit
OBF10
output
enable bit
Input
/Output
P47/SRDY1
/S1
S1
–
–
–
Input
P50/A0
A0
–
–
–
Input
P51/INT20
/S0
S0
–
–
–
Input
R
–
–
–
Input
W
–
–
–
Input
OBF00
1
0
0
Output
OBF01
0
1
0
Output
OBF10
0
0
1
Output
P52/INT30
/R
P53/INT40
/W
P42/INT0
/OBF00
P43/INT1
/OBF01
P46/SCLK1
/OBF10
3886 Group User’s Manual
Functions
Chip select input
This is used for selecting the data bus buffer 1 and
is selected at “L” level.
Address input
This is used for selecting DBBSTS and DBBOUT
when the host CPU is read.
This is used for distinguishing command from data
when writing to the host CPU.
Chip select input
This is used for selecting the data bus buffer 0 and
is selected at “L” level.
This is a timing signal for reading data from the
data bus buffer to the host CPU.
This is a timing signal for writing data to the data
bus buffer by the host CPU.
Status output signal
OBF00 signal is output.
Status output signal
OBF01 signal is output.
Status output signal
OBF10 signal is output.
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HARDWARE
FUNCTIONAL DESCRIPTION
MULTI-MASTER I2C-BUS INTERFACE
Table 11 Multi-master I2C-BUS interface functions
I2C-BUS
The multi-master
interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This
interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial
communications.
Figure 37 shows a block diagram of the multi-master I2C-BUS interface and Table 11 lists the multi-master I 2 C-BUS interface
functions.
This multi-master I2C-BUS interface consists of the I2C address
register, the I2C data shift register, the I2C clock control register,
the I2C control register, the I2C status register, the I2C start/stop
condition control register and other control circuits.
When using the multi-master I 2C-BUS interface, set 1 MHz or
more to φ.
b7
Interrupt
generating
circuit
Interrupt request signal
(SCL SDAIRQ)
Item
Format
Communication mode
SCL clock frequency
Function
In conformity with Philips I2C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I2C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at φ= 4 MHz)
20.2 kHz to 312.5 kHz (at φ = 5 MHz)
System clock φ = f(XIN)/2 (high-speed mode)
φ = f(XIN)/8 (middle-speed mode)
I2C address register
SA D6 SA D5 SAD4 SA D3 SA D2 SA D1 SAD0
b0
Interrupt
generating
circuit
RWB
S0D
Interrupt request signal
(I2CIRQ)
Address comparator
Serial data
(SDA)
Noise
elimination
circuit
Data
control
circuit
b0
b7
I2C data shift register
b7
b0
S0
AL AAS AD0 LRB
MST TRX BB PIN
S2D
STSP
SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0
SEL
AL
circuit
S1
I2C status register
I2C start/stop condition
control register
Internal data bus
BB
circuit
Serial
clock
(SCL)
Noise
elimination
circuit
Clock
control
circuit
b7
ACK
b0
ACK F AST CCR4 CCR3 CCR2 CCR1 CCR0
BIT MODE
I2C clock control register
S1D
b0
b7
TISS
CLK
STP
10 BIT
S AD
ALS ES0 BC2 BC1 BC0
S2
I2C clock control register
Clock division
Stop selection
System clock (φ)
Bit counter
Fig. 37 Block diagram of multi-master I2C-BUS interface
✽ : Purchase of MITSUBISHI ELECTRIC CORPORATIONS I2C components conveys a license under the Philips I2C Patent Rights to use these components
an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
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FUNCTIONAL DESCRIPTION
[I2C Data Shift Register (S0)] 001216
The I2C data shift register (S0 : address 001216) is an 8-bit shift
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to
the outside from bit 7 in synchronization with the S CL clock, and
each time one-bit data is output, the data of this register are
shifted by one bit to the left. When data is received, it is input to
this register from bit 0 in synchronization with the SCL clock, and
each time one-bit data is input, the data of this register are shifted
by one bit to the left. The minimum 2 cycles of φ are required from
the rising of the SCL clock until input to this register.
The I2C data shift register is in a write enable status only when the
I2C-BUS interface enable bit (ES0 bit : bit 3 of address 1516) of the
I 2C control register is “1.” The bit counter is reset by a write instruction to the I2C data shift register. When both the ES0 bit and
the MST bit of the I2C status register (address 001416) are “1,” the
SCL is output by a write instruction to the I2 C data shift register.
Reading data from the I2C data shift register is always enabled regardless of the ES0 bit value.
b7
b0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB
I2C address register
(S0D: address 001316)
Read/write bit
Slave address
Fig. 38 Structure of I2C address register
[I2C Address Register (S0D)] 001316
The I2C address register (address 001316) consists of a 7-bit slave
address and a read/write bit. In the addressing mode, the slave address written in this register is compared with the address data to be
received immediately after the START condition is detected.
•Bit 0: Read/write bit (RWB)
This is not used in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared
with the contents (SAD6 to SAD0 + RWB) of the I2C address register.
The RWB bit is cleared to “0” automatically when the stop condition is detected.
•Bits 1 to 7: Slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing mode, the address data
transmitted from the master is compared with the contents of
these bits.
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HARDWARE
FUNCTIONAL DESCRIPTION
[I2C Clock Control Register (S2)] 001616
Note: Do not write data into the I2C clock control register during transfer. If
data is written during transfer, the I2C clock generator is reset, so
that data cannot be transferred normally.
1-46
A CK F AST
3 CCR2 CCR1 CCR0
B IT MODE CCR4 CCR
I2C clock control register
(S2 : address 001616)
SCL frequency control
bits
Refer to Table 12.
SCL mode specification bit
0 : Standard clock mode
1 : High-speed clock
mode
ACK bit
0 : ACK is returned.
1 : ACK is not
returned.
ACK clock bit
0 : No ACK clock
1 : ACK clock
Fig. 39 Structure of I2C clock control register
Table 12 Set values of I 2 C clock control register and S CL
frequency
SCL frequency
Setting value of
(at φ = 4 MHz, unit : kHz) (Note 1)
CCR4–CCR0
Standard clock High-speed clock
CCR4 CCR3 CCR2 CCR1 CCR0
mode
mode
0
0
0
Setting disabled
Setting disabled
0
0
0
1
Setting disabled
Setting disabled
0
0
0
1
0
Setting disabled
Setting disabled
0
0
0
1
1
– (Note 2)
333
0
0
1
0
0
– (Note 2)
250
0
0
1
0
1
100
400 (Note 3)
0
0
1
1
0
83.3
166
1000/CCR value
(Note 3)
…
0
0
…
0
…
•Bit 7: ACK clock bit (ACK)
This bit specifies the mode of acknowledgment which is an acknowledgment response of data transfer. When this bit is set to
“0,” the no ACK clock mode is selected. In this case, no ACK clock
occurs after data transmission. When the bit is set to “1,” the ACK
clock mode is selected and the master generates an ACK clock
each completion of each 1-byte data transfer. The device for
transmitting address data and control data releases the SDA at the
occurrence of an ACK clock (makes SDA “H”) and receives the
ACK bit generated by the data receiving device.
b0
A CK
…
✽ACK clock: Clock for acknowledgment
b7
…
The I2C clock control register (address 001616) is used to set ACK
control, SCL mode and SCL frequency.
•Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
These bits control the SCL frequency. Refer to Table 12.
•Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the S CL mode. When this bit is set to “0,” the
standard clock mode is selected. When the bit is set to “1,” the
high-speed clock mode is selected.
When connecting the bus according to the high-speed mode I2C
bus standard (maximum 400 kbits/s), use 8 MHz or more oscillation frequency f(XIN) and high-speed mode (2 division main clock).
•Bit 6: ACK bit (ACK BIT)
This bit sets the S DA status when an ACK clock ✽ is generated.
When this bit is set to “0,” the ACK return mode is selected and
SDA goes to “L” at the occurrence of an ACK clock. When the bit is
set to “1,” the ACK non-return mode is selected. The SDA is held in
the “H” status at the occurrence of an ACK clock.
However, when the slave address agree with the address data in
the reception of address data at ACK BIT = “0,” the SDA is automatically made “L” (ACK is returned). If there is a disagreement
between the slave address and the address data, the SDA is automatically made “H” (ACK is not returned).
500/CCR value
(Note 3)
1
1
1
0
1
17.2
34.5
1
1
1
1
0
16.6
33.3
1
1
1
1
1
16.1
32.3
Notes 1: Duty of SCL clock output is 50 %. The duty becomes 35 to 45 %
only when the high-speed clock mode is selected and CCR value
= 5 (400 kHz, at φ = 4 MHz). “H” duration of the clock fluctuates
from –4 to +2 cycles of φ in the standard clock mode, and fluctuates from –2 to +2 cycles of φ in the high-speed clock mode. In
the case of negative fluctuation, the frequency does not increase
because “L” duration is extended instead of “H” duration reduction.
These are value when SCL clock synchronization by the synchronous function is not performed. CCR value is the decimal
notation value of the SCL frequency control bits CCR4 to CCR0.
2: Each value of SCL frequency exceeds the limit at φ = 4 MHz or
more. When using these setting value, use φ of 4 MHz or less.
3: The data formula of SCL frequency is described below:
φ/(8 ✕ CCR value) Standard clock mode
φ/(4 ✕ CCR value) High-speed clock mode (CCR value ≠ 5)
φ/(2 ✕ CCR value) High-speed clock mode (CCR value = 5)
Do not set 0 to 2 as CCR value regardless of φ frequency.
Set 100 kHz (max.) in the standard clock mode and 400 kHz
(max.) in the high-speed clock mode to the SCL frequency by setting the SCL frequency control bits CCR4 to CCR0.
3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
[I2C Control Register (S1D)] 001516
The I2C control register (address 001516) controls data communication format.
•Bits 0 to 2: Bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be
transmitted. The I2C interrupt request signal occurs immediately
after the number of count specified with these bits (ACK clock is
added to the number of count when ACK clock is selected by ACK
bit (bit 7 of address 001616)) have been transferred, and BC0 to
BC2 are returned to “0002”.
Also when a START condition is received, these bits become
“0002” and the address data is always transmitted and received in
8 bits.
•Bit 3: I2C interface enable bit (ES0)
This bit enables to use the multi-master I2C-BUS interface. When
this bit is set to “0,” the use disable status is provided, so that the
SDA and the SCL become high-impedance. When the bit is set to
“1,” use of the interface is enabled.
When ES0 = “0,” the following is performed.
• PIN = “1,” BB = “0” and AL = “0” are set (which are bits of the I2C
status register at address 001416 ).
• Writing data to the I2C data shift register (address 001216) is dis
abled.
•Bit 4: Data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses.
When this bit is set to “0,” the addressing format is selected, so
that address data is recognized. When a match is found between
a slave address and address data as a result of comparison or
when a general call (refer to “(5) I2C Status Register,” bit 1) is received, transfer processing can be performed. When this bit is set
to “1,” the free data format is selected, so that slave addresses are
not recognized.
•Bit 5: Addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit
is set to “0,” the 7-bit addressing format is selected. In this case,
only the high-order 7 bits (slave address) of the I2C address register (address 001316) are compared with address data. When this
bit is set to “1,” the 10-bit addressing format is selected, and all
the bits of the I 2C address register are compared with address
data.
•Bit 6: System clock stop selection bit (CLKSTP)
When executing the WIT or STP instruction, this bit selects the
condition of system clock provided to the multi-master I2C-BUS interface. When this bit is set to “0,” system clock and operation of
the multi-master I2C-BUS interface stop by executing the WIT or
STP instruction.
When this bit is set to “1,” system clock and operation of the multimaster I 2 C-BUS interface do not stop even when the WIT
instruction is executed.
When the system clock stop selection bit is “1,” do not execute the
STP instruction.
•Bit 7: I2C-BUS interface pin input level selection bit
This bit selects the input level of the SCL and SDA pins of the multimaster I2C-BUS interface.
b7
b0
10 B IT
TISS CLK SAD ALS ES0 BC2 BC1 BC0
STP
I2C control register
(S1D : address 001516)
Bit counter (Number of
transmit/receive bits)
b2 b1 b0
0 0 0 : 8
0 0 1 : 7
0 1 0 : 6
0 1 1 : 5
1 0 0 : 4
1 0 1 : 3
1 1 0 : 2
1 1 1 : 1
I2C-BUS interface
enable bit
0 : Disabled
1 : Enabled
Data format selection bit
0 : Addressing format
1 : Free data format
Addressing format selection
bit
0 : 7-bit addressing
format
1 : 10-bit
addressing format
System clock stop
selection bit
0 : System clock stop
when executing WIT
or STP instruction
1 : Not system clock
stop when executing
WIT instruction
(Do not use the STP
instruction.)
I2C-BUS interface pin input
level selection bit
0 : CMOS input
1 : SMBUS input
Fig. 40 Structure of I2C control register
3886 Group User’s Manual
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HARDWARE
FUNCTIONAL DESCRIPTION
[I2C Status Register (S1)] 001416
The I2C status register (address 001416) controls the I2C-BUS interface status. The low-order 4 bits are read-only bits and the
high-order 4 bits can be read out and written to.
Set “00002” to the low-order 4 bits, because these bits become the
reserved bits at writing.
•Bit 0: Last receive bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an
ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned,
this bit is set to “1.” Except in the ACK mode, the last bit value of
received data is input. The state of this bit is changed from “1” to
“0” by executing a write instruction to the I2C data shift register
(address 001216).
•Bit 1: General call detecting flag (AD0)
When the ALS bit is “0,” this bit is set to “1” when a general call✽
whose address data is all “0” is received in the slave mode. By a
general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to “0” by
detecting the STOP condition or START condition, or reset.
✽General call: The master transmits the general call address “0016 ” to all
slaves.
•Bit 2: Slave address comparison flag (AAS)
This flag indicates a comparison result of address data when the
ALS bit is “0”.
➀ In the slave receive mode, when the 7-bit addressing format is
selected, this bit is set to “1” in one of the following conditions:
• The address data immediately after occurrence of a START
condition agrees with the slave address stored in the high-order 7 bits of the I2C address register (address 001316).
• A general call is received.
➁ In the slave reception mode, when the 10-bit addressing format
is selected, this bit is set to “1” with the following condition:
• When the address data is compared with the I2C address register (8 bits consisting of slave address and RWB bit), the first
bytes agree.
➂ This bit is set to “0” by executing a write instruction to the I2C
data shift register (address 001216) when ES0 is set to “1” or
reset.
•Bit 3: Arbitration lost✽ detecting flag (AL)
In the master transmission mode, when the SDA is made “L” by
any other device, arbitration is judged to have been lost, so that
this bit is set to “1.” At the same time, the TRX bit is set to “0,” so
that immediately after transmission of the byte whose arbitration
was lost is completed, the MST bit is set to “0.” The arbitration lost
can be detected only in the master transmission mode. When arbitration is lost during slave address transmission, the TRX bit is
set to “0” and the reception mode is set. Consequently, it becomes
possible to detect the agreement of its own slave address and address data transmitted by another master device.
•Bit 4: SCL pin Low hold bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte
data is transmitted, the PIN bit changes from “1” to “0.” At the
same time, an interrupt request signal occurs to the CPU. The PIN
bit is set to “0” in synchronization with a falling of the last clock (including the ACK clock) of an internal clock and an interrupt
request signal occurs in synchronization with a falling of the PIN
bit. When the PIN bit is “0,” the SCL is kept in the “0” state and
clock generation is disabled. Figure 42 shows an interrupt request
signal generating timing chart.
The PIN bit is set to “1” in one of the following conditions:
• Executing a write instruction to the I 2C data shift register (address 001216). (This is the only condition which the prohibition of
the internal clock is released and data can be communicated except for the start condition detection.)
• When the ES0 bit is “0”
• At reset
• When writing “1” to the PIN bit by software
The conditions in which the PIN bit is set to “0” are shown below:
• Immediately after completion of 1-byte data transmission (including when arbitration lost is detected)
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately after completion of slave address agreement or general call
address reception
• In the slave reception mode, with ALS = “1” and immediately after completion of address data reception
•Bit 5: Bus busy flag (BB)
This bit indicates the status of use of the bus system. When this
bit is set to “0,” this bus system is not busy and a START condition
can be generated. The BB flag is set/reset by the SCL, SDA pins input signal regardless of master/slave. This flag is set to “1” by
detecting the start condition, and is set to “0” by detecting the stop
condition. The condition of these detecting is set by the start/stop
condition setting bits (SSC4–SSC0) of the I2C start/stop condition
control register (address 001716). When the ES0 bit (bit 3) of the
I2C control register (address 001516) is “0” or reset, the BB flag is
set to “0.”
For the writing function to the BB flag, refer to the sections
“START Condition Generating Method” and “STOP Condition Generating Method” described later.
✽Arbitration lost :The status in which communication as a master is disabled.
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FUNCTIONAL DESCRIPTION
•Bit 6: Communication mode specification bit (transfer direction specification bit: TRX)
This bit decides a direction of transfer for data communication.
When this bit is “0,” the reception mode is selected and the data of
a transmitting device is received. When the bit is “1,” the transmission mode is selected and address data and control data are
output onto the SDA in synchronization with the clock generated on
the SCL.
This bit is set/reset by software and hardware. About set/reset by
hardware is described below. This bit is set to “1” by hardware
when all the following conditions are satisfied:
• When ALS is “0”
• In the slave reception mode or the slave transmission mode
• When the R/W bit reception is “1”
This bit is set to “0” in one of the following conditions:
• When arbitration lost is detected.
• When a STOP condition is detected.
• When writing “1” to this bit by software is invalid by the START
condition duplication preventing function (Note).
• With MST = “0” and when a START condition is detected.
• With MST = “0” and when ACK non-return is detected.
• At reset
•Bit 7: Communication mode specification bit (master/slave
specification bit: MST)
This bit is used for master/slave specification for data communication. When this bit is “0,” the slave is specified, so that a START
condition and a STOP condition generated by the master are received, and data communication is performed in synchronization
with the clock generated by the master. When this bit is “1,” the
master is specified and a START condition and a STOP condition
are generated. Additionally, the clocks required for data communication are generated on the SCL.
This bit is set to “0” in one of the following conditions.
• Immediately after completion of 1-byte data transfer when arbitration lost is detected
• When a STOP condition is detected.
• Writing “1” to this bit by software is invalid by the START condition duplication preventing function (Note).
• At reset
Note: START condition duplication preventing function
The MST, TRX, and BB bits is set to “1” at the same time after confirming that the BB flag is “0” in the procedure of a START condition
occurrence. However, when a START condition by another master
device occurs and the BB flag is set to “1” immediately after the contents of the BB flag is confirmed, the START condition duplication
preventing function makes the writing to the MST and TRX bits invalid. The duplication preventing function becomes valid from the
rising of the BB flag to reception completion of slave address.
b7
b0
MST TRX BB PIN AL AAS AD0 LRB
I2C status register
(S1 : address 001416)
Last receive bit (Note)
0 : Last bit = “0”
1 : Last bit = “1”
General call detecting flag
(Note)
0 : No general call detected
1 : General call detected
Slave address comparison flag
(Note)
0 : Address disagreement
1 : Address agreement
Arbitration lost detecting flag
(Note)
0 : Not detected
1 : Detected
SCL pin Low hold bit
0 : Low hold
1 : Op e n
Bus busy flag
0 : Bus free
1 : Bus busy
Communication mode
specification bits
00 : Slave receive mode
01 : Slave transmit mode
10 : Master receive mode
11 : Master transmit mode
Note: These bit and flags can be read out but cannot
be written.
Write “0” to these bits at writing.
Fig. 41 Structure of I2C status register
SCL
PIN
I2CIRQ
Fig. 42 Interrupt request signal generating timing
3886 Group User’s Manual
1-49
HARDWARE
FUNCTIONAL DESCRIPTION
START Condition Generating Method
START/STOP Condition Detecting Operation
When writing “1” to the MST, TRX, and BB bits of the I2C status
register (address 001416) at the same time after writing the slave
address to the I2C data shift register (address 0012 16) with the
condition in which the ES0 bit of the I2C control register (address
001516) and the BB flag are “0”, a START condition occurs. After
that, the bit counter becomes “0002” and an SCL for 1 byte is output. The START condition generating timing is different in the
standard clock mode and the high-speed clock mode. Refer to
Figure 43, the START condition generating timing diagram, and
Table 13, the START condition generating timing table.
The START/STOP condition detection operations are shown in
Figures 45, 46, and Table 15. The START/STOP condition is set
by the START/STOP condition set bit.
The START/STOP condition can be detected only when the input
signal of the SCL and SDA pins satisfy three conditions: SCL release time, setup time, and hold time (see Table 15).
The BB flag is set to “1” by detecting the START condition and is
reset to “0” by detecting the STOP condition.
The BB flag set/reset timing is different in the standard clock mode
and the high-speed clock mode. Refer to Table 15, the BB flag set/
reset time.
Note: When a STOP condition is detected in the slave mode (MST = 0), an
interrupt request signal “I2CIRQ” occurs to the CPU.
I2C
status register
write signal
SCL release time
SC L
Setup
time
SDA
Hold time
SCL
SDA
Setup
time
BB flag
reset
time
Fig. 43 START condition generating timing diagram
BB flag
Table 13 START condition generating timing table
START/STOP condition
Standard
High-speed
Item
generating selection bit clock mode
clock mode
Setup
time
Hold
time
5.0 µs (20 cycles)
13.0 µs (52 cycles)
5.0 µs (20 cycles)
13.0 µs (52 cycles)
“0”
“1”
“0”
“1”
2.5 µs (10 cycles)
6.5 µs (26 cycles)
2.5 µs (10 cycles)
6.5 µs (26 cycles)
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the
number of φ cycles.
Hold time
Fig. 45 START condition detecting timing diagram
SCL release time
SCL
SDA
BB flag
Setup
time
Hold time
BB flag
reset
time
Fig. 46 STOP condition detecting timing diagram
STOP Condition Generating Method
I 2C
When the ES0 bit of the
control register (address 001516) is
“1,” write “1” to the MST and TRX bits, and write “0” to the BB bit
of the I2C status register (address 001416) simultaneously. Then a
STOP condition occurs. The STOP condition generating timing is
different in the standard clock mode and the high-speed clock
mode. Refer to Figure 44, the STOP condition generating timing
diagram, and Table 14, the STOP condition generating timing
table.
SDA
Standard clock mode
SCL release time
SSC value + 1 cycle (6.25 µs)
Setup time
SSC value + 1 cycle < 4.0 µs (3.25 µs)
2
SSC value
cycle < 4.0 µs (3.0 µs)
2
Hold time
BB flag set/
reset time
I2C status register
write signal
SCL
Table 15 START condition/STOP condition detecting conditions
Setup
time
2 cycles (1.0 µs)
2 cycles (0.5 µs)
3.5 cycles (0.875 µs)
Note: Unit : Cycle number of system clock φ
SSC value is the decimal notation value of the START/STOP condition set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC
value. The value in parentheses is an example when the I2C START/
STOP condition control register is set to “1816” at φ = 4 MHz.
Hold time
Fig. 44 STOP condition generating timing diagram
Table 14 STOP condition generating timing table
High-speed
START/STOP condition
Standard
Item
clock mode
generating selection bit clock mode
5.5 µs (22 cycles) 3.0 µs (12 cycles)
“0”
Setup
time
13.5 µs (54 cycles) 7.0 µs (28 cycles)
“1”
5.5 µs (22 cycles) 3.0 µs (12 cycles)
“0”
Hold
time
“1”
13.5 µs (54 cycles) 7.0 µs (28 cycles)
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the
number of φ cycles.
1-50
SSC value –1 + 2 cycles (3.375 µs)
2
High-speed clock mode
4 cycles (1.0 µs)
3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
[I2C START/STOP Condition Control Register
(S2D)] 001716
The I2C START/STOP condition control register (address 001716)
controls START/STOP condition detection.
•Bits 0 to 4: START/STOP condition set bit (SSC4–SSC0)
SCL release time, setup time, and hold time change the detection
condition by value of the main clock divide ratio selection bit and
the oscillation frequency f(XIN) because these time are measured
by the internal system clock. Accordingly, set the proper value to
the START/STOP condition set bits (SSC4 to SSC0) in considered
of the system clock frequency. Refer to Table 16.
Do not set “000002” or an odd number to the START/STOP condition set bit (SSC4 to SSC0).
•Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP)
An interrupt can occur when detecting the falling or rising edge of
the SCL or SDA pin. This bit selects the polarity of the SCL or SDA
pin interrupt pin.
•Bit 6: SCL/SDA interrupt pin selection bit (SIS)
This bit selects the pin of which interrupt becomes valid between
the SCL pin and the SDA pin.
Note: When changing the setting of the SCL/SDA interrupt pin polarity selection bit, the S CL/S DA interrupt pin selection bit, or the I 2C-BUS
interface enable bit ES0, the S CL/SDA interrupt request bit may be
set. When selecting the SCL/SDA interrupt source, disable the interrupt before the SCL/SDA interrupt pin polarity selection bit, the S CL/
S DA interrupt pin selection bit, or the I 2C-BUS interface enable bit
ES0 is set. Reset the request bit to “0” after setting these bits, and
enable the interrupt.
➁ 10-bit addressing format
To adapt the 10-bit addressing format, set the 10BIT SAD bit of
the I 2C control register (address 0015 16 ) to “1.” An address
comparison is performed between the first-byte address data
transmitted from the master and the 8-bit slave address stored
in the I2C address register (address 001316). At the time of this
comparison, an address comparison between the RWB bit of
the I 2 C address register (address 0013 16) and the R/W bit
which is the last bit of the address data transmitted from the
master is made. In the 10-bit addressing mode, the RWB bit
which is the last bit of the address data not only specifies the
direction of communication for control data, but also is processed as an address data bit.
When the first-byte address data agree with the slave address,
the AAS bit of the I2C status register (address 001416) is set to
“1.” After the second-byte address data is stored into the I2C
data shift register (address 001216), perform an address comparison between the second-byte data and the slave address
by software. When the address data of the 2 bytes agree with
the slave address, set the RWB bit of the I2C address register
(address 001316) to “1” by software. This processing can make
the 7-bit slave address and R/W data agree, which are received after a RESTART condition is detected, with the value of
the I2C address register (address 001316). For the data transmission format when the 10-bit addressing format is selected,
refer to Figure 48, (3) and (4).
•Bit 7: START/STOP condition generating selection bit
(STSPSEL)
Setup/Hold time when the START/STOP condition is generated
can be selected.
Cycle number of system clock becomes standard for setup/hold
time. Additionally, setup/hold time is different between the START
condition and the STP condition. (Refer to Tables 13 and 14.) Set
“1” to this bit when the system clock frequency is 4 MHz or more.
Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective
address communication formats are described below.
➀ 7-bit addressing format
To adapt the 7-bit addressing format, set the 10BIT SAD bit of
the I2C control register (address 001516) to “0.” The first 7-bit
address data transmitted from the master is compared with the
high-order 7-bit slave address stored in the I2C address register
(address 001316). At the time of this comparison, address comparison of the RWB bit of the I 2 C address register (address
0013 16 ) is not performed. For the data transmission format
when the 7-bit addressing format is selected, refer to Figure 48,
(1) and (2).
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HARDWARE
FUNCTIONAL DESCRIPTION
b7
STS P
SE L
b0
SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0
I2C START/STOP condition
control register
(S2D : address 001716)
START/STOP condition set bit
SCL/SDA interrupt pin polarity
selection bit
0 : Falling edge active
1 : Rising edge active
SCL/SDA interrupt pin selection bit
0 : SDA valid
1 : SCL valid
START/STOP condition generating
selection bit
0 : Setup/Hold time short mode
1 : Setup/Hold time long mode
Fig. 47 Structure of I2C START/STOP condition control register
Table 16 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency
Oscillation
frequency
f(XIN) (MHz)
Main clock
divide ratio
System
clock φ
(MHz)
START/STOP
condition
control register
SCL release time
(µs)
Setup time
(µs)
Hold time
(µs)
10
2
5
8
2
4
8
8
1
4
2
2
2
2
1
XXX11110
XXX11010
XXX11000
XXX00100
XXX01100
XXX01010
XXX00100
6.2 µs (31 cycles)
6.75 µs (27 cycles)
6.25 µs (25 cycles)
5.0 µs (5 cycles)
6.5 µs (13 cycles)
5.5 µs (11 cycles)
5.0 µs (5 cycles)
3.2 µs (16 cycles)
3.5 µs (14 cycles)
3.25 µs (13 cycles)
3.0 µs (3 cycles)
3.5 µs (7 cycles)
3.0 µs (6 cycles)
3.0 µs (3 cycles)
3.0 µs (15 cycles)
3.25 µs (13 cycles)
3.0 µs (12 cycles)
2.0 µs (2 cycles)
3.0 µs (6 cycles)
2.5 µs (5 cycles)
2.0 µs (2 cycles)
Note: Do not set “000002” or an odd number to the START/STOP condition set bit (SSC4 to SSC0).
S
Slave address R/W
A
Data
A
Data
A/A
P
A
P
7 bits
“0”
1 to 8 bits
1 to 8 bits
(1) A master-transmitter transmits data to a slave-receiver
S
Slave address R/W
A
Data
A
Data
7 bits
“1”
1 to 8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
S
Slave address
R/W
1st 7 bits
A
Slave address
2nd bytes
A
Data
A
Data
A/A
P
7 bits
“0”
8 bits
1 to 8 bits
1 to 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
S
Slave address
R/W
1st 7 bits
A
Slave address
2nd bytes
A
Sr
Slave address
R/W
1st 7 bits
“1”
7 bits
“0”
8 bits
7 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W : Read/Write bit
Fig. 48 Address data communication format
1-52
3886 Group User’s Manual
A
Data
1 to 8 bits
A
Data
1 to 8 bits
A
P
HARDWARE
FUNCTIONAL DESCRIPTION
Example of Master Transmission
An example of master transmission in the standard clock mode, at
the S CL frequency of 100 kHz and in the ACK return mode is
shown below.
➀ Set a slave address in the high-order 7 bits of the I2C address
register (address 001316) and “0” into the RWB bit.
➁ Set the ACK return mode and SCL = 100 kHz by setting “8516” in
the I2C clock control register (address 001616).
➂ Set “0016” in the I 2C status register (address 001416) so that
transmission/reception mode can become initializing condition.
➃ Set a communication enable status by setting “0816” in the I2C
control register (address 001516).
➄ Confirm the bus free condition by the BB flag of the I2C status
register (address 001416).
➅ Set the address data of the destination of transmission in the
high-order 7 bits of the I2C data shift register (address 001216)
and set “0” in the least significant bit.
➆ Set “F016” in the I2C status register (address 001416) to generate a START condition. At this time, an SCL for 1 byte and an
ACK clock automatically occur.
➇ Set transmit data in the I2C data shift register (address 001216).
At this time, an SCL and an ACK clock automatically occur.
➈ When transmitting control data of more than 1 byte, repeat step
➇.
➉ Set “D016” in the I2C status register (address 001416) to generate a STOP condition if ACK is not returned from slave
reception side or transmission ends.
Example of Slave Reception
■Precautions when using multi-master I2CBUS interface
(1) Read-modify-write instruction
The precautions when the read-modify-write instruction such as
SEB, CLB etc. is executed for each register of the multi-master
I2C-BUS interface are described below.
• I2C data shift register (S0: address 001216)
When executing the read-modify-write instruction for this register during transfer, data may become a value not intended.
• I2C address register (S0D: address 001316)
When the read-modify-write instruction is executed for this register at detecting the STOP condition, data may become a value
not intended. It is because H/W changes the read/write bit
(RWB) at the above timing.
• I2C status register (S1: address 001416)
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by H/W.
• I2C control register (S1D: address 001516)
When the read-modify-write instruction is executed for this register at detecting the START condition or at completing the byte
transfer, data may become a value not intended. Because H/W
changes the bit counter (BC0-BC2) at the above timing.
• I2C clock control register (S2: address 001616)
The read-modify-write instruction can be executed for this register.
• I 2 C START/STOP condition control register (S2D: address
001716)
The read-modify-write instruction can be executed for this register.
An example of slave reception in the high-speed clock mode, at
the SCL frequency of 400 kHz, in the ACK non-return mode and
using the addressing format is shown below.
➀ Set a slave address in the high-order 7 bits of the I2C address
register (address 001316) and “0” in the RWB bit.
➁ Set the no ACK clock mode and SCL = 400 kHz by setting “2516”
in the I2C clock control register (address 001616).
➂ Set “0016” in the I 2C status register (address 001416) so that
transmission/reception mode can become initializing condition.
➃ Set a communication enable status by setting “0816” in the I2C
control register (address 001516).
➄ When a START condition is received, an address comparison is
performed.
➅ •When all transmitted addresses are “0” (general call):
AD0 of the I 2C status register (address 001416 ) is set to “1”
and an interrupt request signal occurs.
• When the transmitted addresses agree with the address set in
➀:
AAS of the I2C status register (address 001416) is set to “1”
and an interrupt request signal occurs.
• In the cases other than the above AD0 and AAS of the I2C status register (address 0014 16) are set to “0” and no interrupt
request signal occurs.
➆ Set dummy data in the I2C data shift register (address 001216).
➇ When receiving control data of more than 1 byte, repeat step ➆.
➈ When a STOP condition is detected, the communication ends.
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HARDWARE
FUNCTIONAL DESCRIPTION
(2) START condition generating procedure using multi-master
1. Procedure example (The necessary conditions of the generating procedure are described in Items 2 to 5 below.
.....
LDA —
SEI
BBS 5, S1, BUSBUSY
BUSFREE:
STA S0
LDM #$F0, S1
CLI
(Taking out of slave address value)
(Interrupt disabled)
(BB flag confirming and branch process)
(Writing of slave address value)
(Trigger of START condition generating)
(Interrupt enabled)
.....
.....
BUSBUSY:
CLI
(Interrupt enabled)
2. Use “Branch on Bit Set” of “BBS 5, $0014, –” for the BB flag
confirming and branch process.
3. Use “STA $12, STX $12” or “STY $12” of the zero page addressing instruction for writing the slave address value to the
I2C data shift register.
4. Execute the branch instruction of Item 2 and the store instruction of Item 3 continuously, as shown in the procedure example
above.
5. Disable interrupts during the following three process steps:
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts
immediately.
(3) RESTART condition generating procedure
This procedure cannot be applied to M38867M8A and
M38867E8A when the external memory is used and the bus cycle
is extended by ONW function.
1. Procedure example (The necessary conditions for the procedure are described in items 2 to 4 below.)
Execute the following procedure when the PIN bit is “0.”
(4) Writing to I2C status register
Do not execute an instruction to set the PIN bit to “1” from “0” and
an instruction to set the MST and TRX bits to “0” from “1” simultaneously. Because it may enter the state that the S CL pin is
released and the S DA pin is released after about one machine
cycle. Do not execute an instruction to set the MST and TRX bits
to “0” from “1” simultaneously when the PIN bit is “1.” Because it
may become the same as above.
(5) Process of after STOP condition generating
Do not write data in the I2C data shift register S0 and the I2C status register S1 until the bus busy flag BB becomes “0” after
generating the STOP condition in the master mode. Because the
STOP condition waveform might not be normally generated.
Reading to the above registers do not have the problem.
(6) STOP condition input at 7th clock pulse
The SDA line may be held at LOW even if flag BB is set to “0”
when all the following conditions are satisfied:
•In the slave mode
•The STOP condition is input at the 7th clock pulse while receiving
a slave address or data.
•The clock pulse is continuously input.
Countermeasure:
Write dummy data to the I2C shift register or reset the ES0 bit in
the S1D register (ES0 = “L” → ES0 = “H”) during a stop condition
interrupt routine with flag PIN = “1”.
Note: Do not use the read-modify-write instruction at this time.
Furthermore, when the ES0 bit is set to “0”, the SDA pin becomes a general-purpose port; the port must be set to input
mode or output “H”.
(7) ES0 bit switch
In standard clock mode when SSC = “000102” or in high-speed
clock mode, flag BB may switch to “1” if ES0 bit is set to “1” when
SDA is “L”.
Countermeasure:
Set ES0 to “1” when SDA is “H”.
.....
.....
LDM #$00, S1
LDA —
SEI
STA S0
LDM #$F0, S1
CLI
(Select slave receive mode)
(Take out of slave address value)
(Disable interrupt)
(Write slave address value)
(Trigger RESTART condition generation)
(Enable interrupt)
2. Select the slave receive mode when the PIN bit is “0.” Do not
write “1” to the PIN bit. Neither “0” nor “1” is specified as input to
the BB bit.
The TRX bit becomes “0” and the SDA pin is released.
3. The SCL pin is released by writing the slave address value to
the I2C data shift register.
4. Disable interrupts during the following two process steps:
• Write slave address value
• Trigger RESTART condition generation
1-54
3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
A-D CONVERTER
[A-D Conversion Register 1,2 (AD1, AD2)]
003516, 003816
The A-D conversion register is a read-only register that stores the
result of an A-D conversion. When reading this register during an
A-D conversion, the previous conversion result is read.
Bit 7 of the A-D conversion register 2 is the conversion mode selection bit. When this bit is set to “0,” the A-D converter becomes
the 10-bit A-D mode. When this bit is set to “1,” that becomes the
8-bit A-D mode. The conversion result of the 8-bit A-D mode is
stored in the A-D conversion register 1. As for 10-bit A-D mode,
10-bit reading or 8-bit reading can be performed by selecting the
reading procedure of the A-D conversion register 1, 2 after A-D
conversion is completed (in Figure 50).
The A-D conversion register 1 performs the 8-bit reading inclined
to MSB after reset, the A-D conversion is started, or reading of the
A-D converter register 1 is generated; and the register becomes
the 8-bit reading inclined to LSB after the A-D converter register 2
is generated.
Channel Selector
The channel selector selects one of ports P60/AN 0 to P6 7/AN 7,
and inputs the voltage to the comparator.
Comparator and Control Circuit
The comparator and control circuit compares an analog input voltage with the comparison voltage, and then stores the result in the
A-D conversion registers 1, 2. When an A-D conversion is completed, the control circuit sets the A-D conversion completion bit
and the A-D interrupt request bit to “1”.
Note that because the comparator consists of a capacitor coupling, set f(XIN) to 500 kHz or more during an A-D conversion.
b7
b0
AD/DA control register
(ADCON : address 003416)
Analog input pin selection bits
b2 b1 b0
0
0
0
0
1
1
1
1
[AD/DA Control Register (ADCON)] 003416
The AD/DA control register controls the A-D conversion process.
Bits 0 to 2 select a specific analog input pin. Bit 3 signals the
completion of an A-D conversion. The value of this bit remains at
“0” during an A-D conversion, and changes to “1” when an A-D
conversion ends. Writing “0” to this bit starts the A-D conversion.
0
0
1
1
0
0
1
1
0: P60/AN0
1: P61/AN1
0: P62/AN2
1: P63/AN3
0: P64/AN4
1: P65/AN5
0: P66/AN6
1: P67/AN7
A-D conversion completion bit
0: Conversion in progress
1: Conversion completed
PWM0 output pin selection bit
0: P56/PWM01
1: P30/PWM00
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AVSS and VREF into 1024, and outputs the divided voltages in the
10-bit A-D mode (256 division in 8-bit A-D mode).
The A-D converter successively compares the comparison voltage
Vref in each mode, dividing the VREF (see below), with the input
voltage.
• 10-bit A-D mode (10-bit reading)
VREF
Vref = 1024 ✕ n (n = 0–1023)
• 10-bit A-D mode (8-bit reading)
VREF
Vref = 256 ✕ n (n = 0–255)
• 8-bit A-D mode
VREF
Vref = 256 ✕ (n–0.5) (n = 1–255)
=0
(n = 0)
PWM1 output pin selection bit
0: P57/PWM11
1: P31/PWM10
DA1 output enable bit
0: DA1 output disabled
1: DA1 output enabled
DA2 output enable bit
0: DA2 output disabled
1: DA2 output enabled
Fig. 49 Structure of AD/DA control register
10-bit reading
(Read address 003816 before 003516)
b7
(Address 003816)
0
b0
b9 b8
b7
(Address 003516)
b0
b7 b6 b5 b4 b3 b2 b1 b0
Note: Bits 2 to 6 of address 003816 becomes “0”at reading.
8-bit reading (Read only address 003516)
b7
(Address 003516)
b0
b9 b8 b7 b6 b5 b4 b3 b2
Fig. 50 Structure of 10-bit A-D mode reading
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HARDWARE
FUNCTIONAL DESCRIPTION
Data bus
AD/DA control register
(Address 003416)
b7
b0
3
A-D control circuit
Channel selector
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
Comparator
A-D conversion register 2 (Address 003816)
A-D conversion register 1 (Address 003516)
10
Resistor ladder
VREF AVSS
Fig. 51 Block diagram of A-D converter
1-56
A-D interrupt request
3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
D-A CONVERTER
The 3886 group has two internal D-A converters (DA1 and DA2)
with 8-bit resolution.
The D-A converter is performed by setting the value in each D-A
conversion register. The result of D-A conversion is output from
the DA1 or DA2 pin by setting the DA output enable bit to “1”.
When using the D-A converter, the corresponding port direction
register bit (P56/DA1/PWM01 or P5 7/DA2/PWM11) must be set to
“0” (input status).
The output analog voltage V is determined by the value n (decimal
notation) in the D-A conversion register as follows:
D-A1 conversion register (8)
Data bus
R-2R resistor ladder
V = VREF ✕ n/256 (n = 0 to 255)
Where VREF is the reference voltage.
DA1 output enable bit
P56/DA1/PWM01
D-A2 conversion register (8)
At reset, the D-A conversion registers are cleared to “0016”, the
DA output enable bits are cleared to “0”, and the P56/DA1/PWM01
and P57/DA2/PWM11 pins become high impedance.
The DA output does not have buffers. Accordingly, connect an external buffer when driving a low-impedance load.
Set VCC to 4.0 V or more when using the D-A converter.
R-2R resistor ladder
DA2 output enable bit
P57/DA2/PWM11
Fig. 52 Block diagram of D-A converter
“0” DA1 output enable bit
R
R
R
R
R
R
R
2R
P56/DA1/PWM01
“1”
2R
2R
2R
2R
MSB
D-A1 conversion register
“0”
2R
2R
2R
2R
LSB
“1”
AVSS
VREF
Fig. 53 Equivalent connection circuit of D-A converter (DA1)
3886 Group User’s Manual
1-57
HARDWARE
FUNCTIONAL DESCRIPTION
COMPARATOR CIRCUIT
Comparator Configuration
performed by the writing operation to the comparator data register
(address 002D 16). After 14 cycles of the internal system clock φ
(the time required for the comparison), the comparison result is
stored in the comparator data register (address 002D16).
If the analog input voltage is greater than the internal reference
voltage, each bit of this register is “1”; if it is less than the internal
reference voltage, each bit of this register is “0”. To perform another comparison, the voltage comparison must be performed
again by writing to the comparator data register (address 002D16).
Read the result when 14 cycles of φ or more have passed after the
comparator operation starts. The ladder resistor is turned on during 14 cycles of φ , which is required for the comparison, and the
reference voltage is generated. An unnecessary current is not
consumed because the ladder resistor is turned off while the comparator operation is not performed. Since the comparator consists
of capacitor coupling, the electric charge is lost if the clock frequency is low.
Keep that the clock frequency is 1 MHz or more during the comparator operation. Do not execute the STP, WIT, or port P3 I/O
instruction.
The comparator circuit consists of resistors, comparators, a comparator control circuit, the comparator reference input selection bit
(bit 7 of address 001D 16), a comparator data register (address
002D16), the comparator reference power source input pin (P00/
P3REF) and analog signal input pins (P30–P37). The analog input
pin (P30–P37) also functions as an ordinary digital port.
Comparator Operation
To activate the comparator, first set port P3 to input mode by setting the corresponding direction register (address 000716) to “0” to
use port P3 as an analog voltage input pin. The internal fixed analog voltage (VCC ✕ 29/32) can be generated by setting “1” to the
comparator reference input selection bit (bit 7) of the serial I/O2
control register (address 001D16). (The internal fixed analog voltage becomes about 4.5 V at VCC = 5.0 V.) When setting “0” to the
comparator reference input selection bit, the P0 0/P3REF pin becomes the comparator reference power source input pin and it is
possible to input the comparator reference power source optionally from the external. The voltage comparison is immediately
Data bus
8
8
P3 (8)
Comparator data register
(address 002D16)
b0
P37
Comparator
P36
Comparator
Comparator reference input selection
bit (bit 7) of serial I/O2 control
register(address 001D16)
“0”
P30
Comparator
P00/P3REF
“1”
Comparator
Comparator connecting control circuit Ladder resistor
signal
connecting signal VSS
Fig. 54 Comparator circuit
1-58
3886 Group User’s Manual
VCC
VCC✕29/32
HARDWARE
FUNCTIONAL DESCRIPTION
WATCHDOG TIMER
●Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 001E16) permits selecting a watchdog timer H count source. When this bit is
set to “0”, the count source becomes the underflow signal of
watchdog timer L. The detection time is set to f(XIN)=131.072 ms
at 8 MHz frequency and f(XCIN)=32.768 s at 32 kHz frequency.
When this bit is set to “1”, the count source becomes the signal
divided by 16 for f(XIN) (or f(XCIN)). The detection time in this case
is set to f(XIN)= 512 µs at 8 MHz frequency and f(XCIN)=128 ms at
32 kHz frequency. This bit is cleared to “0” after resetting.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control register (address 001E16) after resetting, the watchdog timer is in the
stop state. The watchdog timer starts to count down by writing an
optional value into the watchdog timer control register (address
001E16) and an internal reset occurs at an underflow of the watchdog timer H.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 001E 16) may be
started before an underflow. When the watchdog timer control register (address 001E16) is read, the values of the high-order 6 bits
of the watchdog timer H, STP instruction disable bit, and watchdog timer H count source selection bit are read.
●Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 001E16) permits disabling the STP instruction when the watchdog timer is in
operation.
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled.
Once the STP instruction is executed, an internal reset occurs.
When this bit is set to “1”, it cannot be rewritten to “0” by program.
This bit is cleared to “0” after resetting.
Initial Value of Watchdog Timer
At reset or writing to the watchdog timer control register (address
001E16), each watchdog timer H and L is set to “FF16.”
XCIN
“10”
Main clock division
ratio selection bits
(Note)
XIN
“FF16” is set when
watchdog timer
control register is
written to.
Data bus
“0”
Watchdog timer L (8)
1/16
“1”
“00”
“01”
Watchdog timer H (8)
“FF16” is set when
watchdog timer
control register is
written to.
Watchdog timer H count
source selection bit
STP instruction disable bit
STP instruction
Reset
circuit
RESET
Internal reset
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
Fig. 55 Block diagram of Watchdog timer
b7
b0
Watchdog timer control register
(WDTCON : address 001E16)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/16 or f(XCIN)/16
Fig. 56 Structure of Watchdog timer control register
3886 Group User’s Manual
1-59
HARDWARE
FUNCTIONAL DESCRIPTION
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an "L"
level for 16 cycles or more of XIN. Then the RESET pin is returned
to an "H" level (the power source voltage should be between 2.7 V
and 5.5 V (4.0 V to 5.5 V for flash memory version), and the oscillation should be stable), reset is released. After the reset is
completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order
byte). Make sure that the reset input voltage is less than 0.54 V for
VCC of 2.7 V. For flash memory version, make sure that the reset
input voltage is less than 0.8 V for Vcc of 4.0 V.
Poweron
RESET
VCC
Power source
voltage
0V
Reset input
voltage
0V
(Note)
0.2VCC
Note : Reset release voltage ; Vcc=2.7 V
(Vcc = 4.0 V for flash memory version)
RESET
VCC
Power source
voltage detection
circuit
Fig. 57 Reset circuit example
XIN
φ
RESET
Internal
reset
?
?
Address
?
?
FFFC
FFFD
ADH,L
Reset address from the vector table.
?
Data
?
?
?
ADL
ADH
SYNC
XIN: 10.5 to 18.5 clock cycles
Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN)=8 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 58 Reset sequence
1-60
3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Address Register contents
Address Register contents
(1)
Port P0 (P0)
000016
0016
(33) Prescaler 12 (PRE12)
002016
FF16
(2)
Port P0 direction register (P0D)
000116
0016
(34) Timer 1 (T1)
002116
0116
(3)
Port P1 (P1)
000216
0016
(35) Timer 2 (T2)
002216
FF16
(4)
Port P1 direction register (P1D)
000316
0016
(36) Timer XY mode register (TM)
002316
0016
(5)
Port P2 (P2)
000416
0016
(37) Prescaler X (PREX)
002416
FF16
(6)
Port P2 direction register (P2D)
000516
0016
(38) Timer X (TX)
002516
FF16
(7)
Port P3 (P3)
000616
0016
(39) Prescaler Y (PREY)
002616
FF16
(8)
Port P3 direction register (P3D)
000716
0016
(40) Timer Y (TY)
002716
FF16
(9)
Port P4 (P4)
000816
0016
(41) Data bus buffer register 0 (DBB0) 002816 X X X X X X X X
(10) Port P4 direction register (P4D)
000916
0016
(42) Data bus buffer status register 0 (DBBSTS0)
002916
0016
(11) Port P5 (P5)
000A16
0016
(43) Data bus buffer control register (DBBCON)
002A16
0016
(12) Port P5 direction register (P5D)
000B16
0016
(44) Data bus buffer register 1 (DBB1) 002B16 X X X X X X X X
(13) Port P6 (P6)
000C16
0016
(45) Data bus buffer status register 1 (DBBSTS1)
002C16
(14) Port P6 direction register (P6D)
000D16
0016
(46) Comparator data register (CMPD)
002D16 X X X X X X X X
(15) Port P7 (P7)
000E16
0016
(47) Port control register 1 (PCTL1)
002E16
0016
(16) Port P7 direction register (P7D)
000F16
0016
(48) Port control register 2 (PCTL2)
002F16
0016
(17) Port P8 (P8)
001016
0016
(49) PWM0H register (PWM0H)
003016 X X X X X X X X
(18) Port P8 direction register (P8D)
001116
0016
(50) PWM0L register (PWM0L)
003116 X 0 X X X X X X
(19) I2C data shift register (S0)
001216 X X X X X X X X
(51) PWM1H register (PWM1H)
003216 X X X X X X X X
(20) I2C address register (S0D)
001316
(52) PWM1L register (PWM1L)
003316 X 0 X X X X X X
(21) I2C status register (S1)
001416 0 0 0 1 0 0 0 X
(53) AD/DA control register (ADCON)
003416 0 0 0 0 1 0 0 0
(22) I2C control register (S1D)
001516
0016
(54) A-D conversion register 1 (AD1)
003516 X X X X X X X X
(23) I2C clock control register (S2)
001616
0016
(55) D-A1 conversion register (DA1)
003616
0016
(24) I2C start/stop condition control register (S2D)
001716 0 0 0 1 1 0 1 0
(56) D-A2 conversion register (DA2)
003716
0016
(25) Transmit/Receive buffer register (TB/RB)
001816 X X X X X X X X
(57) A-D conversion register 2 (AD2)
003816 0 0 0 0 0 0 X X
(26) Serial I/O1 status register (SIO1STS)
001916 1 0 0 0 0 0 0 0
(58) Interrupt source selection register (INTSEL)
003916
0016
(27) Serial I/O1 control register (SIO1CON)
001A16
(59) Interrupt edge selection register (INTEDGE)
003A16
0016
(28) UART control register (UARTCON)
001B16 1 1 1 0 0 0 0 0
(60) CPU mode register (CPUM)
003B16 0 1 0 0 1 0
(29) Baud rate generator (BRG)
001C16 X X X X X X X X
(61) Interrupt request register 1 (IREQ1)
003C16
0016
(30) Serial I/O2 control register (SIO2CON)
001D16
(62) Interrupt request register 2 (IREQ2)
003D16
0016
(31) Watchdog timer control register (WDTCON)
001E16 0 0 1 1 1 1 1 1
(63) Interrupt control register 1 (ICON1)
003E16
0016
(32) Serial I/O2 register (SIO2)
001F16 X X X X X X X X
(64) Interrupt control register 2 (ICON2)
003F16
0016
(65) Flash memory control register (FCON) 0FFE16
0016
(66) Flash command register (FCMD)
0FFF16
0016
(67) Processor status register
(PS)
(68) Program counter
(PCH)
FFFD16 contents
(PCL)
FFFC16 contents
0016
0016
0016
Note: ✻ The initial values depend on level of the CNVSS pin.
X : Not fixed
Since the initial values for other than above mentioned registers and
RAM contents are indefinite at reset, they must be set.
0016
✻
0
X X X X X1 X X
Fig. 59 Internal status at reset
3886 Group User’s Manual
1-61
HARDWARE
FUNCTIONAL DESCRIPTION
CLOCK GENERATING CIRCUIT
(2) Wait mode
The 3886 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer’s recommended values. No external resistor is needed between XIN and XOUT since a feed-back
resistor exists on-chip. However, an external feed-back resistor is
needed between XCIN and XCOUT.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ restarts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after
the clock is restarted.
Frequency Control
(1) Middle-speed mode
XCIN
The internal clock φ is the frequency of XIN divided by 8. After reset, this mode is selected.
XCOUT
Rf
CCIN
(2) High-speed mode
XIN
XOUT
Rd
CCOUT
CIN
COUT
The internal clock φ is half the frequency of XIN.
Fig. 60 Ceramic resonator circuit
(3) Low-speed mode
The internal clock φ is half the frequency of XCIN.
■Note
If you switch the mode between middle/high-speed and lowspeed, stabilize both XIN and XCIN oscillations. The sufficient time
is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. When switching the
mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3f(XCIN).
XCIN
(4) Low power dissipation mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set
bit 5 of the CPU mode register to “1.” When the main clock XIN is
restarted (by setting the main clock stop bit to “0”), set sufficient
time for oscillation to stabilize.
XIN
Open
External oscillation
circuit
External oscillation
circuit
VCC
VSS
Fig. 61 External clock input circuit
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillators stop. When the oscillation
stabilizing time set after STP instruction released bit is “0,” the
prescaler 12 is set to “FF16” and timer 1 is set to “0116.” When the
oscillation stabilizing time set after STP instruction released bit is
“1,” set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1.
Either X IN or X CIN divided by 16 is input to the prescaler 12 as
count source, and the output of the prescaler 12 is connected to
timer 1. Set the timer 1 interrupt enable bit to disabled (“0”) before
executing the STP instruction. Oscillator restarts when an external
interrupt is received, but the internal clock φ is not supplied to the
CPU (remains at “H”) until timer 1 underflows. The internal clock φ
is supplied for the first time, when timer 1 underflows. Therefore
make sure not to set the timer 1 interrupt request bit to “1” before
the STP instruction stops the oscillator. When the oscillator is restarted by reset, apply “L” level to the RESET pin until the
oscillation is stable since a wait time will not be generated.
3886 Group User’s Manual
XOUT
Open
VCC
VSS
Oscillation Control
(1) Stop mode
1-62
XCOUT
HARDWARE
FUNCTIONAL DESCRIPTION
XCOUT
XCIN
“0”
“1”
Port XC
switch bit
XOUT
XIN
Main clock division ratio
selection bits (Note 1)
Low-speed mode
1/2
1/4
Prescaler 12
1/2
High-speed or
middle-speed
mode
Timer 1
Reset or
0116 STP instruction
FF16
(Note 2)
Main clock division ratio
selection bits (Note 1)
Middle-speed mode
Timing f (internal clock)
High-speed or
low-speed mode
Main clock stop bit
Q
S
R
S Q
STP instruction
WIT instruction
Q S
R
R
STP instruction
Reset
Interrupt disable flag l
Interrupt request
Notes 1: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mode is selected, set port Xc switch bit (b4) to “1”.
2: When bit 6 of the port control register 2 is “0”, the initial value is not set to the prescaler 12 and timer 1 at STP
instruction execution.
Fig. 62 System clock generating circuit block diagram (Single-chip mode)
3886 Group User’s Manual
1-63
HARDWARE
FUNCTIONAL DESCRIPTION
Reset
C
“0 M4
C M ”←
“1 6 →“
1”
”←
→
“0
”
”
“0
→
C M ”←
0”
“1 M6 →“
C ”←
“1
4
CM6
“1”←→“0”
C
“0 M7
CM ”←→
“1 6
“1
”←
”
→
“0
”
High-speed mode
(f(φ)=5 MHz)
CM7=0
CM6=0
CM5=0(10 MHz oscillating)
CM4=1(32 kHz oscillating)
CM7
“1”←→“0”
CM4
“1”←→“0”
CM7=0
CM6=1
CM5=0(10 MHz oscillating)
CM4=0(32 kHz stopped)
Middle-speed mode
(f(φ)=1.25 MHz)
CM7=0
CM6=1
CM5=0(10 MHz oscillating)
CM4=1(32 kHz oscillating)
High-speed mode
(f(φ)=5 MHz)
CM7=0
CM6=0
CM5=0(10 MHz oscillating)
CM4=0(32 kHz stopped)
C M6
“1”←→“0”
CM4
“1”←→“0”
Middle-speed mode
(f(φ)=1.25 MHz)
Low-speed mode
(f(φ)=16 kHz)
b7
CM5
“1”←→“0”
CM7=1
CM6=0
CM5=0(10 MHz oscillating)
CM4=1(32 kHz oscillating)
Low-speed mode
(f(φ)=16 kHz)
CM7=1
CM6=0
CM5=1(10 MHz stopped)
CM4=1(32 kHz oscillating)
b4
CPU mode register
(CPUM : address 003B16)
CM4 : Port Xc switch bit
0 : I/O port function (stop oscillating)
1 : XCIN-XCOUT oscillating function
CM5 : Main clock (XIN- XOUT) stop bit
0 : Operating
1 : Stopped
CM7, CM6: Main clock division ratio selection bit
b7 b6
0 0 : φ = f(XIN)/2 ( High-speed mode)
0 1 : φ = f(XIN)/8 (Middle-speed mode)
1 0 : φ = f(XCIN)/2 (Low-speed mode)
1 1 : Not available
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is
ended.
3 : Timer operates in the wait mode.
4 : When the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 and Timer 1 in middle/high-speed mode.
5 : When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 and Timer 2 in low-speed mode.
6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed
mode.
7 : The example assumes that 10 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Fig. 63 State transitions of system clock
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3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
PROCESSOR MODE
Single-chip mode, memory expansion mode, and microprocessor
mode in the M38867M8A/E8A can be selected by changing the
contents of the processor mode bits (CM0 and CM1 : b1 and b0 of
address 003B16). In memory expansion mode and microprocessor
mode, memory can be expanded externally through ports P0 to
P3. In these modes, ports P0 to P3 lose their I/O port functions
and become bus pins.
000816
Port P3
Function
Outputs low-order 8 bits of address.
Outputs high-order 8 bits of address.
Operates as I/O pins for data D7 to D0
(including instruction code).
P30 and P31 function only as output pins
(except that the port latch cannot be read).
P32 is the ONW input pin.
P33 is the RESETOUT output pin. (Note)
P34 is the φ output pin.
P35 is the SYNC output pin.
P36 is the WR output pin, and P37 is the RD output pin.
000816
SFR area
SFR area
004016
004016
Internal RAM
reserved area
Table 17 Port functions in memory expansion mode and
microprocessor mode
Port Name
Port P0
Port P1
Port P2
000016
000016
XXXX16*
Internal RAM
reserved area
XXXX16*
YYYY16*
Internal ROM
FFFF16
FFFF16
Memory expansion mode
Microprocessor mode
The shaded area are external memory area.
*: XXXX16 indicates the last address of internal RAM.
YYYY16 indicates the first address of internal ROM.
Note : If CNVSS is connected to VSS, the microcomputer goes to singlechip mode after a reset, so that this pin cannot be used as the
RESETOUT output pin.
Fig. 64 Memory maps in various processor modes
(1) Single-chip mode
Select this mode by resetting the microcomputer with CNVSS connected to VSS.
(2) Memory expansion mode
Select this mode by setting the processor mode bits (b1, b0) to
“01” in software with CNVSS connected to VSS. This mode enables
external memory expansion while maintaining the validity of the internal ROM.
However, do not set this mode in the M38869M8A/MCA/MFA and
the flash memory version.
b7
b0
CPU mode register
(CPUM : address 003B16)
Processor mode bits (CM1, CM0)
b1 b0
0
0
1
1
(3) Microprocessor mode
Select this mode by resetting the microcomputer with CNVSS connected to VCC, or by setting the processor mode bits to “10” in
software with CNVSS connected to VSS. In microprocessor mode,
the internal ROM is no longer valid and external memory must be
used.
Do not set this mode in the M38869M8A/MCA/MFA and the flash
memory version.
0: Single-chip mode
1: Memory expansion mode (Note)
0: Microprocessor mode (Note)
1: Not available
Stack page selection bit
0: 0 page
1: 1 page
Note: This is not available for the products except
M38867M8A/E8A.
Fig. 65 Structure of CPU mode register
3886 Group User’s Manual
1-65
HARDWARE
FUNCTIONAL DESCRIPTION
BUS CONTROL AT MEMORY EXPANSION
The M38867M8A/E8A have a built-in ONW function to facilitate
access to an external (expanded) memory and I/O devices in
memory expansion mode or microprocessor mode.
If an “L” level signal is input to the P32/ONW pin when the CPU is
in a read or write state, the corresponding read or write cycle is
extended by one cycle of φ. During this extended term, the RD
and WR signals remain at “L.” This extension function is valid only
for writing to and reading from addresses 000016 to 0007 16 and
044016 to FFFF16, and only read and write cycles are extended.
Read cycle
Dummy cycle Write cycle
Read cycle Dummy cycle
Write cycle
φ
AD15—AD0
RD
WR
ONW
*
*
*
* Term where ONW input signal is received.
During this term, the ONW signal must be fixed at either “H” or “L”. At all other times, the input level of the ONW
signal has no affect on operations. The bus cycles is not extended for an address in the area 000816 to 043F16,
because the ONW signal is not received.
Fig. 66 ONW function timing
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3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
EPROM MODE
The built-in PROM of the blank One Time PROM version and builtin EPROM version can be read or programmed with a
general-purpose PROM programmer using a special programming
adapter. The One Time PROM version and the built-in EPROM
version have the function of the M5M27C101 corresponding for
writing to the built-in PROM. Set the address of PROM programmer in the user ROM area.
Table 18 Programming adapter
Package
Name of Programming Adapter
80P6Q-A
PCA4738H-80A
80D0
PCA4738L-80A
Table 19 PROM programmer setup
PROM programmer setup
Product name
Corresponding
device
M38867E8AHP M5M27C101K
byte
program
M38867E8AFS
Writing
area
0808016
|
0FFFD16
ROM area of
microcomputer
808016
|
FFFD16
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in
Figure 67 is recommended to verify programming.
Programming with PROM
programmer
Screening (Caution)
(150 °C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
Caution : The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Fig. 67 Programming and testing of One Time PROM version
3886 Group User’s Manual
1-67
HARDWARE
FUNCTIONAL DESCRIPTION
FLASH MEMORY MODE
Functional Outline (parallel input/output mode)
The M38869FFAHP/GP has the flash memory mode in addition to
the normal operation mode (microcomputer mode). The user can
use this mode to perform read, program, and erase operations for
the internal flash memory.
The M38869FFAHP/GP has three modes the user can choose:
the parallel input/output and serial input/output mode, where the
flash memory is handled by using the external programmer, and
the CPU reprogramming mode, where the flash memory is
handled by the central processing unit (CPU). The following explains these modes.
In the parallel input/output mode, the M38869FFAHP/GP allow the
user to choose an operation mode between the read-only mode
and the read/write mode (software command control mode) depending on the voltage applied to the VPP pin. When VPP = VPPL,
the read-only mode is selected, and the user can choose one of
three states (e.g., read, output disable, or standby) depending on
___ ___
___
inputs to the CE, OE, and WE pins. When VPP = VPPH, the read/
write mode is selected, and the user can choose one of four states
(e.g., read, output disable, standby, or write) depending on inputs
__ __
___
to the CE, OE, and WE pins. Table 21 shows assignment states of
control input and each state.
(1) Flash memory mode 1 (parallel I/O mode)
● Read
__
The microcomputer enters the read state by driving the CE, and
__
___
OE pins low and the WE pin high; and the contents of memory
corresponding to the address to be input to address input pins
(A0–A16) are output to the data input/output pins (D0–D7).
The parallel I/O mode can be selected by connecting wires as
shown in Figures 68 and supplying power to the V CC and V PP
pins. In this mode, the M38869FFAHP/GP operates as an equivalent of MITSUBISHI’s CMOS flash memory M5M28F101.
However, because the M38869FFAHP/GP’s internal memory has
a capacity of 60 Kbytes, programming is available for addresses
0100016 to 0FFFF16, and make sure that the data in addresses
0000016 to 00FFF16 and addresses 1000016 to 1FFFF16 are FF16.
Note also that the M38869FFAHP/GP does not contain a facility to
read out a device identification code by applying a high voltage to
address input (A9). Be careful not to erratically set program conditions when using a general-purpose PROM programmer.
Table 20 shows the pin assignments when operating in the parallel input/output mode.
Table 20
● Output disable
The microcomputer enters the output disable state by driving the
__
___
__
CE pin low and the WE and OE pins high; and the data input/output pins enter the floating state.
● Standby
__
The microcomputer enters the standby state by driving the CE pin
high. The M38869FFAHP/GP is placed in a power-down state
consuming only a minimal supply current. At this time, the data input/output pins enter the floating state.
Pin assignments of M38869FFAHP/GP when
operating in the parallel input/output mode
VCC
VPP
VSS
Address input
Data I/O
__
CE
___
OE
___
WE
M38869FFAHP/GP
VCC
CNVSS
VSS
Ports P0, P1, P31
Port P2
P36
P37
P33
● Write
The microcomputer enters the write state by driving the VPP pin
___
__
high (V PP = V PPH) and then the WE pin low when the CE pin is
__
low and the OE pin is high. In this state, software commands can
be input from the data input/output pins, and the user can choose
program or erase operation depending on the contents of this software command.
M5M28F101
VCC
VPP
VSS
A0–A16
D0–D7
__
CE
__
OE
___
WE
Table 21 Assignment sates of control input and each state
Pin
Mode
Read-only
Read/Write
State
Read
Output disable
Standby
Read
Output disable
Standby
Write
CE
__
OE
__
___
WE
VPP
Data I/O
VIL
VIL
VIH
VIL
VIL
VIH
VIL
VIL
VIH
×
VIL
VIH
×
VIH
VIH
VIH
×
VIH
VIH
×
VIL
VPPL
VPPL
VPPL
VPPH
VPPH
VPPH
VPPH
Output
Floating
Floating
Output
Floating
Floating
Input
Note: × can be VIL or VIH.
1-68
3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Table 22 Pin description (flash memory parallel I/O mode)
Pin
Name
VCC, VSS
CNVSS
_____
RESET
XIN
XOUT
AVSS
VREF
P00–P07
P10–P17
P20–P27
P30–P37
Power supply
VPP input
Reset input
Clock input
Clock output
Analog supply input
Reference voltage input
Address input (A0–A7)
Address input (A8–A15)
Data I/O (D0–D7)
Control signal input
P40–P47
P50–P57
P60–P67
P70–P77
P80–P87
Input port P4
Input port P5
Input port P6
Input port P7
Input port P8
Input
/Output
—
Input
Input
Input
Output
—
Input
Input
Input
I/O
Input
Input
Input
Input
Input
Input
Functions
Supply 5 V ± 10 % to VCC and 0 V to VSS.
Connect to 5 V ± 10 % in read-only mode, connect to 11.7 to 12.6 V in read/write mode.
Connect to VSS.
Connect a ceramic resonator between XIN and XOUT.
Connect to VSS.
Connect to VSS.
Port P0 functions as 8-bit address input (A0–A7).
Port P1 functions as 8-bit address input (A8–A15).
Function as 8-bit data’s I/O pins__
(D0__
–D7). ___
P37, P36 and P33 function as the OE, CE and WE input pins respectively. P31 functions as
the A16 input pin. Connect P30 and P32 to VSS. Input “H” or “L” to P34, P35, or keep
them open.
Connect P44, P46 to VSS. Input “H” or “L” to P40 - P43, P45, P47, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
3886 Group User’s Manual
1-69
HARDWARE
A13
A12
A11
A9
A8
A10
A7
A6
A5
A4
A3
A2
A1
CE
A0
OE
P32
P33
P34
P35
P36
P37
P00/P3REF
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
WE
FUNCTIONAL DESCRIPTION
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
A16
Vcc
P31/PWM10
P30/PWM00
P87/DQ7
P86/DQ6
P85/DQ5
P84/DQ4
P83/DQ3
P82/DQ2
P81/DQ1
P80/DQ0
VCC
VREF
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
62
40
39
63
64
65
66
38
37
36
35
67
68
34
33
61
69
70
71
72
M38869FFAHP
M38869FFAGP
32
31
30
29
73
74
28
27
75
76
77
78
79
80
26
25
24
23
22
21
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
VSS
XOUT
XIN
P40/XCOUT
P41/XCIN
RESET
CNVSS
P42/INT0/OBF00
P43/INT1/OBF01
P44/RXD
A14
A15
D0
D1
D2
D3
D4
D5
D6
D7
Vss
*
Vpp
P60/AN0
P77/SCL
P76/SDA
P75/INT41
P74/INT31
P73/SRDY2/INT21
P72/SCLK2
P71/SOUT2
P70/SIN2
P57/DA2/PWM11
P56/DA1/PWM01
P55/CNTR1
P54/CNTR0
P53/INT40/W
P52/INT30/R
P51/INT20/S0
P50/A0
P47/SRDY1/S1
P46/SCLK1/OBF10
P45/TXD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
* :Coninndeicctattoesththeeceflarasmh imc eomscoilrlay tpioinn.circuit.
Fig. 68 Pin connection of M38869FFAHP/GP when operating in parallel input/output mode
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3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Read-only Mode
The microcomputer enters the read-only mode by applying VPPL
to the VPP pin. In this mode, the user can input the address of a
memory location to be read and the control signals at the timing
shown in Figure 69, and the M38869FFAHP/GP will output the
contents of the user’s specified address from data I/O pin to the
external. In this mode, the user cannot perform any operation
other than read.
VIH
Address
Valid address
VIL
tRC
VIH
CE
VIL
ta(CE)
VIH
OE
VIL
tWRR
tDF
VIH
WE
VIL
VOH
Data
ta(OE)
tDH
tOLZ
Floating
tCLZ
VOL
Dout
Floating
ta(AD)
Fig. 69 Read timing
Read/Write Mode
The microcomputer enters the read/write mode by applying VPPH
to the VPP pin. In this mode, the user must first input a software
command to choose the operation (e. g., read, program, or erase)
to be performed on the flash memory (this is called the first cycle),
and then input the information necessary for execution of the command (e.g, address and data) and control signals (this is called
the second cycle). When this is done, the M38869FFAHP/GP executes the specified operation.
Table 23 shows the software commands and the input/output information in the first and the second cycles. The input address is
___
latched internally at the falling edge of the WE input; software
commands and other input data are latched internally at the rising
___
edge of the WE input.
The following explains each software command. Refer to Figures 70
to 72 for details about the signal input/output timings.
Table 23 Software command (Parallel input/output mode)
Symbol
Read
Program
Program verify
Erase
Erase verify
Reset
Device identification
First cycle
Address input
×
×
×
×
Verify address
×
×
Data input
0016
4016
C016
2016
A016
FF16
9016
Second cycle
Address input
Data I/O
Read address
Read data (Output)
Program address
Program data (Input)
×
Verify data (Output)
×
2016 (Input)
×
Verify data (Output)
×
FF16 (Input)
ADI
DDI (Output)
Note: ADI = Device identification address : manufacturer’s code 0000016, device code 0000116
DDI = Device identification data : manufacturer’s code 1C16, device code D016
X can be VIL or VIH.
3886 Group User’s Manual
1-71
HARDWARE
FUNCTIONAL DESCRIPTION
● Read command
The microcomputer enters the read mode by inputting command
code “0016” in the first cycle. The command code is latched into
___
the internal command latch at the rising edge of the WE input.
When the address of a memory location to be read is input in the
second cycle, with control signals input at the timing shown in
Figure 70, the M38869FFAHP/GP outputs the contents of the
specified address from the data I/O pins to the external.
The read mode is retained until any other command is latched into
the command latch. Consequently, once the M38869FFAHP/GP enters the read mode, the user can read out the successive memory
contents simply by changing the input address and executing the
second cycle only. Any command other than the read command
must be input beginning from its command code over again each
time the user execute it. The contents of the command latch immediately after power-on is 0016.
VIH
Address
Valid address
VIL
tRC
tWC
VIH
CE
VIL
tCH
ta(CE)
tCS
VIH
OE
VIL
tRRW
tWP
tWRR
tDF
VIH
WE
VIL
ta(OE)
tDS
VIH
tOLZ
0016
Data
VIL
tDH
tVSC
tCLZ
ta(AD)
VPPH
VPP
VPPL
Fig. 70 Timings during reading
1-72
3886 Group User’s Manual
Dout
tDH
HARDWARE
FUNCTIONAL DESCRIPTION
● Program command
The microcomputer enters the program mode by inputting command code “4016” in the first cycle. The command code is latched
___
into the internal command latch at the rising edge of the WE input.
When the address which indicates a program location and data is
input in the second cycle, the M38869FFAHP/GP internally
___
latches the address at the falling edge of the WE input and the
___
data at the rising edge of the WE input. The M38869FFAHP/GP
___
starts programming at the rising edge of the WE input in the second cycle and finishes programming within 10 µs as measured by
its internal timer. Programming is performed in units of bytes.
Note: A programming operation is not completed by executing the
program command once. Always be sure to execute a program verify command after executing the program command.
When the failure is found in this verification, the user must repeatedly execute the program command until the pass. Refer
to Figure 73 for the programming flowchart.
● Program verify command
The microcomputer enters the program verify mode by inputting
command code “C016” in the first cycle. This command is used to
verify the programmed data after executing the program command. The command code is latched into the internal command
___
latch at the rising edge of the WE input. When control signals are
input in the second cycle at the timing shown in Figure 71, the
M38869FFAHP/GP outputs the programmed address’s contents to
the external. Since the address is internally latched when the program command is executed, there is no need to input it in the
second cycle.
Program verify
VIH
Program
address
Address
VIL
tAS
tWC
Program
tAH
VIH
CE
VIL
tCS
tCS
tCS
tCH
tCH
tCH
VIH
OE
VIL
tRRW
tWP
tWPH
tWP
tDP
tWP
tWRR
VIH
WE
VIL
tDS
tDS
tDS
VIH
4016
Data
VIL
DIN
tDH
C016
tDH
Dout
tDH
Verify data output
tVSC
VPPH
VPP
VPPL
Fig. 71 Input/output timings during programming (Verify data is output at the same timing as for read.)
3886 Group User’s Manual
1-73
HARDWARE
FUNCTIONAL DESCRIPTION
● Erase command
The erase command is executed by inputting command code 2016
in the first cycle and command code 20 16 again in the second
cycle. The command code is latched into the internal command
___
latch at the rising edges of the WE input in the first cycle and in
the second cycle, respectively. The erase operation is initiated at
___
the rising edge of the WE input in the second cycle, and the
memory contents are collectively erased within 9.5 ms as measured by the internal timer. Note that data 0016 must be written to
all memory locations before executing the erase command.
Note: An erase operation is not completed by executing the erase
command once. Always be sure to execute an erase verify
command after executing the erase command. When the failure is found in this verification, the user must repeatedly execute the erase command until the pass. Refer to Figure 73
for the erase flowchart.
● Erase verify command
The user must verify the contents of all addresses after completing the erase command. The microcomputer enters the erase
verify mode by inputting the verify address and command code
A016 in the first cycle. The address is internally latched at the fall___
ing edge of the WE input, and the command code is internally
___
latched at the rising edge of the WE input. When control signals
are input in the second cycle at the timing shown in Figure 72, the
M38869FFAHP/GP outputs the contents of the specified address
to the external.
Note: If any memory location where the contents have not been
erased is found in the erase verify operation, execute the operation of “erase → erase verify” over again. In this case,
however, the user does not need to write data 0016 to memory
locations before erasing.
Erase verify
VIH
Address
Erase
VIL
Verify
address
tAS
tWC
tAH
VIH
CE
VIL
tCS
tCS
tCS
tCH
tCH
tCH
VIH
OE
VIL
tRRW
tWP
tWPH
tWP
tDE
tWP
tWRR
VIH
WE
VIL
tDS
tDS
tDS
VIH
2016
Data
2016
A016
VIL
Verify data output
tVSC
tDH
tDH
tDH
VPPH
VPP
VPPL
Fig. 72 Input/output timings during erasing (verify data is output at the same timing as for read.)
1-74
Dout
3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
● Reset command
The reset command provides a means of stopping execution of
the erase or program command safely. If the user inputs command
code FF16 in the second cycle after inputting the erase or program
command in the first cycle and again input command code FF16 in
the third cycle, the erase or program command is disabled (i.e.,
reset), and the M38869FFAHP/GP is placed in the read mode. If
the reset command is executed, the contents of the memory does
not change.
● Device identification code command
By inputting command code 9016 in the first cycle, the user can
read out the device identification code. The command code is
latched into the internal command latch at the rising edge of the
___
WE input. At this time, the user can read out manufacture’s code
1C16 (i.e., MITSUBISHI) by inputting 000016 to the address input
pins in the second cycle; the user can read out device code D016
(i. e., 1M-bit flash memory) by inputting 000116.
These command and data codes are input/output at the same timing as for read.
3886 Group User’s Manual
1-75
HARDWARE
FUNCTIONAL DESCRIPTION
Program
Erase
START
START
VCC = 5 V, VPP = VPPH
VCC = 5 V, VPP = VPPH
ADRS = first location
ALL
BYTES = 0016 ?
YES
X=0
NO
WRITE PROGRAM
COMMAND
4016
WRITE PROGRAM
DATA
DIN
PROGRAM
ALL BYTES = 0016
ADRS = first location
X=0
DURATION = 10 µs
X=X+1
WRITE PROGRAM-VERIFY
COMMAND
C016
WRITE ERASE
COMMAND
2016
WRITE ERASE
COMMAND
2016
DURATION = 9.5 ms
DURATION = 6 µs
YES
X=X+1
X = 25 ?
WRITE ERASE-VERIFY
COMMAND
NO
PASS
FAIL
VERIFY BYTE ?
DURATION = 6 µs
VERIFY BYTE ?
PASS
FAIL
YES
X = 1000 ?
NO
INC ADRS
A016
LAST ADRS ?
NO
YES
WRITE READ COMMAND
PASS
FAIL
VERIFY BYTE ?
0016
VERIFY BYTE ?
FAIL
PASS
VPP = VPPL
NO
INC ADRS
DEVICE
PASSED
DEVICE
FAILED
LAST ADRS ?
YES
WRITE READ COMMAND
0016
VPP = VPPL
DEVICE
PASSED
Fig. 73 Programming/Erasing algorithm flow chart
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3886 Group User’s Manual
DEVICE
FAILED
HARDWARE
FUNCTIONAL DESCRIPTION
Table 24 DC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, VCC = 5 V ± 10 %, unless otherwise noted)
Symbol
Parameter
Test conditions
Min.
Limits
Typ.
Max.
1
__
ISB1
ISB2
VCC = 5.5 V, CE = VIH
V
CC = 5.5 V,
__
CE = VCC ± 0.2 V
__
VCC = 5.5 V, CE = VIL,
tRC = 150 ns, IOUT = 0 mA
VPP = VPPH
VPP = VPPH
0≤VPP≤VCC
VCC<VPP≤VCC + 1.0 V
VPP = VPPH
VPP = VPPH
VPP = VPPH
VCC supply current (at standby)
ICC1
VCC supply current (at read)
ICC2
ICC3
VCC supply current (at program)
VCC supply current (at erase)
IPP1
VPP supply current (at read)
IPP2
IPP3
VIL
VIH
VOL
VOH1
VOH2
VPP supply current (at program)
VPP supply current (at erase)
“L” input voltage
“H” input voltage
“L” output voltage
“H” output voltage
VPPL
VPPH
VPP supply voltage (read only)
2.4
VCC –0.4
VCC
VPP supply voltage (read/write)
11.7
12.0
mA
100
µA
15
mA
15
15
10
100
100
30
30
0.8
VCC
0.45
mA
mA
µA
µA
µA
mA
mA
V
V
V
V
V
VCC + 1.0
12.6
V
V
0
2.0
IOL = 2.1 mA
IOH = –400 µA
IOH = –100 µA
Unit
AC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, VCC = 5 V ± 10 %, unless otherwise noted)
Table 25 Read-only mode
Symbol
tRC
ta(AD)
ta(CE)
ta(OE)
tCLZ
tOLZ
tDF
tDH
tWRR
Parameter
Read cycle time
Address access time
__
CE access time
__
OE access time
__
Output enable time (after CE)
__
Output enable time (after OE)
__
Output floating time (after OE)
__ __
Output valid time (after CE, OE, address)
Write recovery time (before read)
Limits
Min.
250
Max.
250
250
100
0
0
35
0
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
Table 26 Read/Write mode
Symbol
tWC
tAS
tAH
tDS
tDH
tWRR
tRRW
tCS
tCH
tWP
tWPH
tDP
tDE
tVSC
Parameter
Write cycle time
Address set up time
Address hold time
Data setup time
Data hold time
Write recovery time (before read)
Read recovery time (before write)
__
CE setup time
__
CE hold time
Write pulse width
Write pulse waiting time
Program time
Erase time
VPP setup time
Limits
Min.
150
0
60
50
10
6
0
20
0
60
20
10
9.5
1
Max.
Unit
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
µs
ms
µs
Note: Read timing of Read/Write mode is same as Read-only mode.
3886 Group User’s Manual
1-77
HARDWARE
FUNCTIONAL DESCRIPTION
(2) Flash memory mode 2 (serial I/O mode)
connecting wires as shown in Figures 74 and powering on the VCC
pin and then applying VPPH to the VPP pin.
In the serial I/O mode, the user can use six types of software commands: read, program, program verify, erase, erase verify and
error check.
Serial input/output is accomplished synchronously with the clock,
beginning from the LSB (LSB first).
P32
P33
P34
P35
P36
P37
P00/P3REF
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
OE
The M38869FFAHP/GP has a function to serially input/output the
software commands, addresses, and data required for operation
on the internal flash memory (e. g., read, program, and erase) using only a few pins. This is called the serial I/O (input/output)
mode. This mode can be selected by driving the SDA (serial data
__
input/output), SCLK (serial clock input ), and OE pins high after
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
Vcc
P31/PWM10
P30/PWM00
P87/DQ7
P86/DQ6
P85/DQ5
P84/DQ4
P83/DQ3
P82/DQ2
P81/DQ1
P80/DQ0
VCC
VREF
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
M38869FFAHP
M38869FFAGP
31
30
29
28
27
26
25
24
23
22
21
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
VSS
XOUT
XIN
P40/XCOUT
P41/XCIN
RESET
CNVSS
P42/INT0/OBF00
P43/INT1/OBF01
P44/RXD
Vss
*
Vpp
SDA
SCLK
BUSY
P60/AN0
P77/SCL
P76/SDA
P75/INT41
P74/INT31
P73/SRDY2/INT21
P72/SCLK2
P71/SOUT2
P70/SIN2
P57/DA2/PWM11
P56/DA1/PWM01
P55/CNTR1
P54/CNTR0
P53/INT40/W
P52/INT30/R
P51/INT20/S0
P50/A0
P47/SRDY1/S1
P46/SCLK1/OBF10
P45/TXD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
to the ceramic oscillation circuit.
* :Connect
indicates the flash memory pin.
Fig. 74 Pin connection of M38869FFAHP/GP when operating in serial I/O mode
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FUNCTIONAL DESCRIPTION
Table 27 Pin description (flash memory serial I/O mode)
Pin
VCC, VSS
CNVSS
_____
RESET
XIN
XOUT
AVSS
VREF
P00–P07
P10–P17
P20–P27
P30–P36
P37
P40–P43,
P45
P44
P46
P47
P50–P57
P60–P67
P70–P77
P80–P87
Name
Power supply
VPP input
Reset input
Clock input
Clock output
Analog supply input
Reference voltage input
Input port P0
Input port P1
Input port P2
Input port P3
Control signal input
Input port P4
SDA I/O
SCLK input
BUSY output
Input port P5
Input port P6
Input port P7
Input port P8
Input
/Output
—
Input
Input
Input
Output
—
Input
Input
Input
Input
Input
Input
Input
I/O
Input
Output
Input
Input
Input
Input
Functions
Supply 5 V ± 10 % to VCC and 0 V to VSS.
Connect to 11.7 to 12.6 V.
Connect to VSS.
Connect a ceramic resonator between XIN and XOUT.
Connect to VSS.
Input an arbitrary level between the range of VSS and VCC.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
__
OE input pin
Input “H” or “L” to P40 - P43, P45, or keep them open.
This pin is for serial data I/O.
This pin is for serial clock input.
This pin is for BUSY signal output.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
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HARDWARE
FUNCTIONAL DESCRIPTION
Functional Outline (serial I/O mode)
Data is transferred in units of eight bits.
In the first transfer, the user inputs the command code. This is followed by address input and data input/output according to the
contents of the command. Table 28 shows the software commands used in the serial I/O mode. The following explains each
software command.
In the serial I/O mode, data is transferred synchronously with the
clock using serial input/output. The input data is read from the
SDA pin into the internal circuit synchronously with the rising edge
of the serial clock pulse; the output data is output from the SDA
pin synchronously with the falling edge of the serial clock pulse.
Table 28 Software command (serial I/O mode)
Number of transfers First command
code input
0016
4016
C016
2016
A016
8016
Command
Read
Program
Program verify
Erase
Erase verify
Error check
Second
Third
Read address L (Input)
Program address L (Input)
Verify data (Output)
2016 (Input)
Verify address L (Input)
Error code (Output)
Fourth
Read address H (Input)
Program address H (Input)
—————
—————
Verify address H (Input)
—————
Read data (Output)
Program data (Input)
—————
—————
Verify data (Output)
—————
__
● Read command
Input command code 0016 in the first transfer. Proceed and input
the low-order 8 bits and the high-order 8 bits of the address and
__
pull the OE pin low. When this is done, the M38869FFAHP/GP
reads out the contents of the specified address, and then latches
it into the internal data latch. When the OE pin is released back
high and serial clock is input to the SCLK pin, the read data that
has been latched into the data latch is serially output from the
SDA pin.
tCH
tCH
SCLK
A0
SDA
A7
0 0 0 0 0 0 0 0
Command code input (0016) Read address input (L)
A8
A15
Read address input (H)
tCR
D0
tWR
tRC
Read data output
OE
Read
BUSY “L”
Note : When outputting the read data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit).
Fig. 75 Timings during reading
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HARDWARE
FUNCTIONAL DESCRIPTION
● Program command
Input command code 4016 in the first transfer. Proceed and input
the low-order 8 bits and the high-order 8 bits of the address and
then program data. Programming is initiated at the last rising edge
of the serial clock during program data transfer. The BUSY pin is
driven high during program operation. Programming is completed
within 10 µs as measured by the internal timer, and the BUSY pin
is pulled low.
tCH
Note : A programming operation is not completed by executing the
program command once. Always be sure to execute a program verify command after executing the program command.
When the failure is found in the verification, the user must repeatedly execute the program command until the pass in the
verification. Refer to Figure 73 for the programming flowchart.
tCH
tCH
SCLK
tPC
A0
SDA
0 0 0 0 0 0 1 0
Command code input (4016)
A7
A8
A15
Program address input (L) Program address input (H)
D0
D7
Program data input
OE
tWP
Program
BUSY
Fig. 76 Timings during programming
● Program verify command
Input command code C016 in the first transfer. Proceed and drive
__
the OE pin low. When this is done, the M38869FFAHP/GP verifyreads the programmed address’s contents, and then latches it into
__
the internal data latch. When the OE pin is released back high and
serial clock is input to the SCLK pin, the verify data that has been
latched into the data latch is serially output from the SDA pin.
SCLK
D0
SDA
0 0 0 0 0 0 1 1
Command code input (C016)
D7
Verify data output
tCRPV
tWR
tRC
OE
Verify read
BUSY “L”
Note: When outputting the verify data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit).
Fig. 77 Timings during program verify
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HARDWARE
FUNCTIONAL DESCRIPTION
● Erase command
Input command code 2016 in the first transfer and command code
20 16 again in the second transfer. When this is done, the
M38869FFAHP/GP executes an erase command. Erase is initiated at the last rising edge of the serial clock. The BUSY pin is
driven high during the erase operation. Erase is completed within
9.5 ms as measured by the internal timer, and the BUSY pin is
pulled low. Note that data 0016 must be written to all memory loca-
tions before executing the erase command.
Note: A erase operation is not completed by executing the erase
command once. Always be sure to execute a erase verify
command after executing the erase command. When the failure is found in the verification, the user must repeatedly execute the erase command until the pass in the verification.
Refer to Figure 73 for the erase flowchart.
tCH
SCLK
tEC
SDA
0 0 0 0 0 1 0 0
0 0 0 0 0 1 0 0
Command code input (2016) Command code input (2016)
“H”
OE
twE
BUSY
Erase
Fig. 78 Timings at erasing
● Erase verify command
The user must verify the contents of all addresses after completing the erase command. Input command code A0 16 in the first
transfer. Proceed and input the low-order 8 bits and the high-order
__
8 bits of the address and pull the OE pin low. When this is done,
the M38869FFAHP/GP reads out the contents of the specified ad__
dress, and then latches it into the internal data latch. When the OE
pin is released back high and serial clock is input to the SCLK pin,
tCH
the verify data that has been latched into the data latch is serially
output from the SDA pin.
Note: If any memory location where the contents have not been
erased is found in the erase verify operation, execute the operation of “erase → erase verify” over again. In this case,
however, the user does not need to write data 00 16 to
memory locations before erasing.
tCH
SCLK
A0
SDA
A7
0 0 0 0 0 1 0 1
Command code input (A016) Verify address input (L)
A8
A15
Verify address input (H)
tCREV
D0
tWR
tRC
D7
Verify data output
OE
Verify read
BUSY “L”
Note : When outputting the verify data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit).
Fig. 79 Timings during erase verify
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FUNCTIONAL DESCRIPTION
● Error check command
Input command code 80 16 in the first transfer, and the
M38869FFAHP/GP outputs error information from the SDA pin,
beginning at the next falling edge of the serial clock. If the LSB bit
of the 8-bit error information is 1, it indicates that a command error
has occurred. A command error means that some invalid commands other than commands shown in Table 28 has been input.
When a command error occurs, the serial communication circuit
sets the corresponding flag and stops functioning to avoid an erroneous programming or erase. When being placed in this state, the
serial communication circuit does not accept the subsequent serial
clock and data (even including an error check command). Therefore, if the user wants to execute an error check command,
temporarily drop the VPP pin input to the V PPL level to terminate
the serial input/output mode. Then, place the M38869FFAHP/GP
into the serial I/O mode back again. The serial communication circuit is reset by this operation and is ready to accept commands.
The error flag alone is not cleared by this operation, so the user
can examine the serial communication circuit’s error conditions
before reset. This examination is done by the first execution of an
error check command after the reset. The error flag is cleared
when the user has executed the error check command. Because
the error flag is undefined immediately after power-on, always be
sure to execute the error check command.
tCH
SCLK
E0
SDA
OE
0 0 0 0 0 0 0 1
Command code input (8016)
? ? ? ? ? ? ?
Error flag output
“H”
BUSY “L”
Note: When outputting the error flag, the SDA pin is switched for output at the first falling edge of the serial clock. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of the serial clock (at the 8th bit).
Fig. 80 Timings at error checking
Note: The programming/erasing algorithm flow chart of the serial
I/O mode is the same as that of the parallel I/O mode. Refer to Figure 73.
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FUNCTIONAL DESCRIPTION
DC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, VCC = 5 V ± 10 %, VPP = 11.7 to 12.6 V, unless otherwise noted)
ICC, IPP-relevant standards during read, program, and erase are the same as in the parallel input/output mode. VIH, VIL, VOH, VOL, IIH, and
__
IIL for the SCLK, SDA, BUSY, OE pins conform to the microcomputer modes.
Table 29 AC Electrical characteristics
(Ta = 25 °C, VCC = 5 V ± 10 %, VPP = 11.7 to 12.6 V, f(XIN) = 10 MHz, unless otherwise noted)
Symbol
tCH
tCR
tWR
tRC
tCRPV
tWP
tPC
tCREV
tWE
tEC
tc(CK)
tw(CKH)
tw(CKL)
tr(CK)
tf(CK)
td(C-Q)
th(C-Q)
th(C-E)
tsu(D-C)
th(C-D)
Limits
Min.
Max.
500(Note 1)
500(Note 1)
400(Note 2)
500(Note 1)
6
10
500(Note 1)
6
9.5
500(Note 1)
250
100
100
20
20
0
90
0
150(Note 3) 250(Note 4)
30
90
Parameter
Serial transmission interval
Read waiting time after transmission
Read pulse width
Transfer waiting time after read
Waiting time before program verify
Programming time
Transfer waiting time after programming
Waiting time before erase verify
Erase time
Transfer waiting time after erase
SCLK input cycle time
SCLK high-level pulse width
SCLK low-level pulse width
SCLK rise time
SCLK fall time
SDA output delay time
SDA output hold time
SDA output hold time (only the 8th bit)
SDA input set up time
SDA input hold time
Unit
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: When f(XIN) = 10 MHz or less, calculate the minimum value according to formula 1.
5000
× 106
f(XIN)
2: When f(XIN) = 10 MHz or less, calculate the minimum value according to formula 2.
Formula 1 :
4000
× 106
f(XIN)
3: When f(XIN) = 10 MHz or less, calculate the minimum value according to formula 3.
Formula 2 :
1500
× 106
f(XIN)
4: When f(XIN) = 10 MHz or less, calculate the minimum value according to formula 4
Formula 3 :
Formula 4 :
2500
f(XIN)
× 106
AC waveforms
tf(CK)
tw(CKL)
tc(CK)
tr(CK)
tw(CKH)
SCLK
th(C-Q)
td(C-Q)
th(C-E)
Test conditions for AC characteristics
SDA output
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
tsu(D-C)
th(C-D)
SDA input
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• Input timing voltage : VIL = 0.2 VCC, VIH = 0.8 VCC
HARDWARE
FUNCTIONAL DESCRIPTION
(3) Flash memory mode 3 (CPU reprogramming
mode)
The M38869FFAHP/GP has the CPU reprogramming mode where
a built-in flash memory is handled by the central processing unit
(CPU).
In CPU reprogramming mode, the flash memory is handled by
writing and reading to/from the flash memory control register (see
Figure 81) and the flash command register (see Figure 82).
The CNVSS pin is used as the VPP power supply pin in CPU reprogramming mode. It is necessary to apply the power-supply voltage
of VPPH from the external to this pin.
Functional Outline (CPU reprogramming mode)
Figure 81 shows the flash memory control register bit configuration. Figure 82 shows the flash command register bit
configuration.
Bit 0 of the flash memory control register is the CPU reprogramming mode select bit. When this bit is set to “1” and V PPH is
applied to the CNVss/V PP pin, the CPU reprogramming mode is
selected. Whether the CPU reprogramming mode is realized or
not is judged by reading the CPU reprogramming mode monitor
flag (bit 2 of the flash memory control register).
Bit 1 is a busy flag which becomes “1” during erase and program
execution.
7
6
0
5
4
3
0
2
1
Whether each operation has been completed or not is judged by
checking this flag after execution of each erase or program command.
Bits 4, 5 of the flash memory control register are the erase/program area select bits. These bits specify an area where erase and
program is operated. When the erase command is executed after
an area is specified by these bits, only the specified area is
erased. Programming is enabled only for the specified area: programming is disabled for all other areas.
When CPU reprogramming mode is valid, the area not specified
by the erase/program area select bits cannot be read out.
Transfer the CPU reprogramming mode control program to internal RAM before entering the CPU reprogramming mode, and then
execute this program on internal RAM.
If an interrupt occurs while this program is being executed, the
flash memory area is accessed, but normal operations cannot be
performed because the flash memory area cannot be read out.
Execute processes such as interrupt disable during the CPU reprogramming mode control program.
Figure 83 shows the CPU mode register bit configuration in the
CPU reprogramming mode. Set bits 1 and 0 to “00” (single-chip
mode) in the CPU reprogramming mode.
0
Flash memory control register
(FCON : address 0FFE16)
CPU reprogramming mode select bit (Note)
0 : CPU reprogramming mode is invalid. (Normal operation mode)
1 : When applying 0 V or VPPL to CNVSS/VPP pin, CPU reprogramming mode is
invalid. When applying VPPH to CNVSS/VPP pin, CPU reprogramming mode is valid.
Erase/Program busy flag
0 : Erase and program are completed or not have been executed.
1 : Erase/program is being executed.
CPU reprogramming mode monitor flag
0 : CPU reprogramming mode is invalid.
1 : CPU reprogramming mode is valid.
Fix this bit to “0.”
Erase/Program area select bits
0 0 : Addresses 100016 to FFFF16 (total 60 Kbytes)
0 1 : Addresses 100016 to 7FFF16 (total 28 Kbytes)
1 0 : Addresses 800016 to FFFF16 (total 32 Kbytes)
1 1 : Not available
Fix this bit to “0.”
Not used (returns "0" when read)
Note: Bit 0 can be reprogrammed only when 0 V is applied to the CNVSS/VPP pin.
Fig. 81 Flash memory control register bit configuration
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FUNCTIONAL DESCRIPTION
● CPU reprogramming mode operation procedure
The operation procedure in CPU reprogramming mode is described below.
< Beginning procedure >
➀ Apply 0 V to the CNVss/VPP pin for reset release.
➁ After CPU reprogramming mode control program is transferred to
internal RAM, jump to this control program on RAM. (The following operations are controlled by this control program).
➂ Set “1" to the CPU reprogramming mode select bit.
➃ Apply VPPH to the CNVSS/VPP pin.
➄ Wait till CNVSS/VPP pin becomes 12 V.
➅ Read the CPU reprogramming mode monitor flag to confirm
whether the CPU reprogramming mode is valid.
➆ The operation of the flash memory is executed by software-command-writing to the flash command register .
Note: The following are necessary other than this:
•Control for data which is input from the external (serial I/O
etc.) and to be programmed to the flash memory
•Initial setting for ports etc.
•Writing to the watchdog timer
< Release procedure >
➀ Apply 0V to the CNVSS/VPP pin.
➁ Wait till CNVSS/VPP pin becomes 0V.
➂ Set the CPU reprogramming mode select bit to “0.”
Each software command is explained as follows.
● Read command
When “00 16 " is written to the flash command register, the
M38869FFAHP/GP enters the read mode. The contents of the
corresponding address can be read by reading the flash memory
(For instance, with the LDA instruction etc.) under this condition.
The read mode is maintained until another command code is written
to the flash command register. Accordingly, after setting the read
mode once, the contents of the flash memory can continuously be
read.
After reset and after the reset command is executed, the read
mode is set.
b7
7
6
5
4
3
2
1
0
Flash command register
(FCMD : address 0FFF16)
<Command code>
• Read command
“0016”
• Program command
“4016”
• Program verify command
“C016”
• Erase command
“2016” + “2016”
• Erase verify command
“A016”
• Reset command
“FF16” + “FF16”
1-86
0
CPU mode register
(CPUM : address 003B16)
Stack page selection bit
0 : 0 page
1 : 1 page
Fix this bit to “1”.
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0 0 : φ = f(XIN)/2 (high-speed mode)
0 1 : φ = f(XIN)/8 (middle-speed mode)
1 0 : φ = f(XCIN)/2 (low-speed mode)
1 1 : Not available
Note: The flash command register is write-only register.
Fig. 82 Flash command register bit configuration
0
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 : Not available
1 X : Not available
Writing of software command
<Software command name>
b0
1
Fig. 83 CPU mode register bit configuration in CPU rewriting
mode
3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
● Program command
When “40 16 ” is written to the flash command register, the
M38869FFAHP/GP enters the program mode.
Subsequently to this, if the instruction (for instance, STA
instruction) for writing byte data in the address to be programmed
is executed, the control circuit of the flash memory executes the
program. The erase/program busy flag of the flash memory control
register is set to “1” when the program starts, and becomes “0”
when the program is completed. Accordingly, after the write instruction is executed, CPU can recognize the completion of the
program by polling this bit.
The programmed area must be specified beforehand by the erase/
program area select bits.
During programming, watchdog timer stops with “FFFF16” set.
Note: A programming operation is not completed by executing the
program command once. Always be sure to execute a program verify command after executing the program command.
When the failure is found in this verification, the user must repeatedly execute the program command until the pass. Refer
to Figure 84 for the flow chart of the programming.
● Program verify command
When “C0 16 ” is written to the flash command register, the
M38869FFAHP/GP enters the program verify mode. Subsequently
to this, if the instruction (for instance, LDA instruction) for reading
byte data from the address to be verified (i.e., previously programmed address), the contents which has been written to the
address actually is read.
CPU compares this read data with data which has been written by
the previous program command. In consequence of the comparison, if not agreeing, the operation of “program → program verify”
must be executed again.
● Erase verify command
When “A0 16 ” is written to the flash command register, the
M38869FFAHP/GP enters the erase verify mode. Subsequently to
this, if the instruction (for instance, LDA instruction) for reading
byte data from the address to be verified, the contents of the address is read.
CPU must erase and verify to all erased areas in a unit of address.
If the address of which data is not “FF16” (i.e., data is not erased)
is found, it is necessary to discontinue erasure verification there,
and execute the operation of “erase → erase verify” again.
Note: By executing the operation of “erase → erase verify” again
when the memory not erased is found. It is unnecessary to
write data “0016” before erasing in this case.
● Reset command
The reset command is a command to discontinue the program or
erase command on the way. When “FF16” is written to the command
register two times continuously after “4016” or “2016” is written to the
flash command register, the program, or erase command becomes
invalid (reset), and the M38869FFAHP/GP enters the reset mode.
The contents of the memory does not change even if the reset command is executed.
DC Electric Characteristics
Note: The characteristic concerning the flash memory part are the
same as the characteristic of the parallel I/O mode.
AC Electric Characteristics
Note: The characteristics are the same as the characteristic of the
microcomputer mode.
● Erase command
When writing “2016” twice continuously to the flash command register, the flash memory control circuit performs erase to the area
specified beforehand by the erase/program area select bits.
Erase/program busy flag of the flash memory control register becomes “1” when erase begins, and it becomes “0” when erase
completes. Accordingly, CPU can recognize the completion of
erase by polling this bit.
Data “0016” must be written to all areas to be erased by the program and the program verify commands before the erase
command is executed.
During erasing, watchdog timer stops with “FFFF16” set.
Note: The erasing operation is not completed by executing the erase
command once. Always be sure to execute an erase verify
command after executing the erase command. When the failure is found in this verification, the user must repeatedly execute the erase command until the pass. Refer to Figure 84 for
the erasing flowchart.
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HARDWARE
FUNCTIONAL DESCRIPTION
Program
Erase
START
START
ADRS = first location
ALL
BYTES = 0016 ?
YES
X=0
NO
WRITE PROGRAM
COMMAND
4016
WRITE PROGRAM
DATA
DIN
PROGRAM
ALL BYTES = 0016
ADRS = first location
X=0
WAIT 1µs
NO
ERASE PROGRAM
BUSY FLAG = 0
YES
X=X+1
WRITE ERASE
COMMAND
2016
WRITE ERASE
COMMAND
2016
WAIT 1µs
WRITE PROGRAM-VERIFY
COMMAND
C016
NO
ERASE PROGRAM
BUSY FLAG = 0
DURATION = 6 µs
YES
X=X+1
X = 25 ?
YES
WRITE ERASE-VERIFY
COMMAND
NO
PASS
FAIL
VERIFY BYTE ?
DURATION = 6 µs
VERIFY BYTE ?
PASS
A016
FAIL
YES
X = 1000 ?
INC ADRS
NO
LAST ADRS ?
NO
YES
WRITE READ COMMAND
PASS
FAIL
VERIFY BYTE ?
VERIFY BYTE ?
0016
FAIL
PASS
DEVICE
PASSED
DEVICE
FAILED
NO
INC ADRS
LAST ADRS ?
YES
WRITE READ COMMAND
DEVICE
PASSED
Fig. 84 Flowchart of program/erase operation at CPU reprogramming mode
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0016
DEVICE
FAILED
HARDWARE
NOTES ON PROGRAMMING
NOTES ON PROGRAMMING
Serial I/O
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” After a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt
request register, execute at least one instruction before performing a BBC or BBS instruction.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY1 signal, set the transmit
enable bit, the receive enable bit, and the SRDY1 output enable bit
to “1.”
Serial I/O1 continues to output the final bit from the TXD pin after
transmission is completed. SOUT2 pin for serial I/O2 goes to high
impedance after transfer is completed.
When in serial I/O1 (clock-synchronous mode) or in serial I/O2, an
external clock is used as synchronous clock, write transmission
data to the transmit buffer register or serial I/O2 register, during
transfer clock is “H.”
A-D Converter
The comparator uses capacitive coupling amplifier whose charge
will be lost if the clock frequency is too low.
Therefore, make sure that f(XIN) is at least on 500 kHz during an
A-D conversion.
Do not execute the STP instruction during an A-D conversion.
D-A Converter
The accuracy of the D-A converter becomes rapidly poor under
the VCC = 4.0 V or less condition; a supply voltage of VCC ≥ 4.0 V
is recommended. When a D-A converter is not used, set all values
of D-Ai conversion registers (i=1, 2) to “0016.”
Instruction Execution Time
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.
• The execution of these instructions does not change the contents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The instruction with the addressing mode which uses the value
of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to
a direction register.
Use instructions such as LDM and STA, etc., to set the port direction registers.
The instruction execution time is obtained by multiplying the period of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The period of the internal clock φ is half of the XIN period in highspeed mode.
When the ONW function is used in modes other than single-chip
mode, the period of the internal clock φ may be four times that of
the XIN.
3886 Group User’s Manual
1-89
HARDWARE
NOTES ON USAGE/DATA REQUIRED FOR MASK ORDERS AND ONE TIME PROM PROGRAMMING ORDERS
NOTES ON USAGE
Handling of Power Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power
source pin (V CC pin) and GND pin (VSS pin), between power
source pin (VCC pin) and analog power source input pin (AVSS
pin). Connect the same kind of capacitor between program power
source pin (CNVss/VPP) and GND pin when executing on-board
reprogramming of flash memory version. Make sure the connection between each pin is as short as possible. We recommend
using a ceramic capacitor of 0.01 µF to 0.1 µF.
EPROM version/One Time PROM version/
Flash memory version
The CNVSS pin is connected to the internal memory circuit block
by a low-ohmic resistance, since it has the multiplexed function to
be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVSS
pin and VSS pin or VCC pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNVSS pin has no operational interference even if it is connected to Vss pin or Vcc pin via a
resistor.
Erasing of Flash memory version
For the parallel I/O mode and the serial I/O mode, set addresses
0100016 to 0FFFF16 as the memory area to be erased. If an incorrect address is set as the memory area to be erased, the product
may be permanently damaged.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production:
1.Mask ROM Confirmation Form✽1
2.Mark Specification Form✽2
3.Data to be written to ROM, in EPROM form (three identical copies)
DATA REQUIRED FOR One Time PROM
PROGRAMMING ORDERS
The following are necessary when ordering a PROM programming
service:
1.ROM Programming Confirmation Form✽1
2.Mark Specification Form✽2
3.Data to be programmed to PROM, in EPROM form (three identical copies)
For the mask ROM confirmation, the ROM programming confirmation, and the mark specifications, refer to the “Mitsubishi MCU
Technical Information” Homepage.
✽1 Mask ROM Confirmation Forms
http://www.infomicom.mesc.co.jp/38000/38ordere.htm
✽2 Mark Specification Forms
http://www.infomicom.mesc.co.jp/mela/markform.htm
1-90
3886 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
FUNCTIONAL DESCRIPTION SUPPLEMENT
A-D Converter
By repeating the above operations up to the lowest-order bit of the
A-D conversion register, an analog value converts into a digital
value.
A-D conversion completes at 61 clock cycles (15.25 µs at f(XIN) = 8
MHz) after it is started, and the result of the conversion is stored
into the A-D conversion register.
Concurrently with the completion of A-D conversion, A-D conversion
interrupt request occurs, so that the AD conversion interrupt request
bit is set to “1.”
A-D conversion is started by setting AD conversion completion bit to
“0.” During A-D conversion, internal operations are performed as
follows.
1. After the start of A-D conversion, A-D conversion register goes to
“0016.”
2. The highest-order bit of A-D conversion register is set to “1,” and
the comparison voltage Vref is input to the comparator. Then, Vref
is compared with analog input voltage VIN.
3. As a result of comparison, when Vref < VIN, the highest-order bit
of A-D conversion register becomes “1.” When Vref > V IN , the
highest-order bit becomes “0.”
Table 30 Relative formula for a reference voltage V REF of A-D
converter and Vref
When n = 0
Vref = 0
When n = 1 to 1023
Vref =
VREF
✕n
1024
n: Value of A-D converter (decimal numeral)
Table 31 Change of A-D conversion register during A-D conversion
Change of A-D conversion register
Value of comparison voltage (Vref)
At start of conversion
0
0
0
0
0
0
0
0
0
0
First comparison
1
0
0
0
0
0
0
0
0
0
Second comparison
✽1
1
0
0
0
0
0
0
0
0
Third comparison
✽1 ✽2
1
0
0
0
0
0
0
0
After completion of tenth
comparison
A result of A-D conversion
✽1 ✽ 2
✽3 ✽4 ✽5 ✽6
✽ 7 ✽8 ✽ 9 ✽10
0
VREF
2
VREF
±
2
VREF
4
VREF
±
2
VREF
4
±
VREF
8
VREF
±
2
VREF
4
±
••••
±
VREF
1024
✽1–✽10: A result of the first comparison to the tenth comparison
3886 Group User’s Manual
1-91
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Figures 85 shows the A-D conversion equivalent circuit, and Figure
86 shows the A-D conversion timing chart.
VCC
VSS
VCC AVSS
About 2 kW
VIN
AN0
Sampling
clock
AN1
C
AN2
Chopper
amplifier
AN3
AN4
A-D conversion register (high-order)
b4
b2 b1 b0
A-D control register
A-D conversion register
(low-order)
Vref
VREF
Built-in
D-A converter
Reference
clock
AV SS
Fig. 85 A-D conversion equivalent circuit
φ
Write signal for A-D
control register
61 cycles
AD conversion
completion bit
Sampling clock
Fig. 86 A-D conversion timing chart
1-92
3886 Group User’s Manual
AD conversion interrupt request
CHAPTER 2
APPLICATION
2.1 I/O port
2.2 Interrupt
2.3 Timer
2.4 Serial I/O
2.5 Multi-master I 2C-BUS interface
2.6 PWM
2.7 A-D converter
2.8 D-A converter
2.9 Bus interface
2.10 Watchdog timer
2.11 Reset
2.12 Clock generating circuit
2.13 Standby function
2.14 Processor mode
2.15 Flash memory
APPLICATION
2.1 I/O port
2.1 I/O port
This paragraph explains the registers setting method and the notes relevant to the I/O ports.
2.1.1 Memory map
000016
Port P0 (P0)
000116
Port P0 direction register (P0D)
000216
Port P1 (P1)
000316
Port P1 direction register (P1D)
000416
Port P2 (P2)
000516
Port P2 direction register (P2D)
000616
Port P3 (P3)
000716
000816
Port P3 direction register (P3D)
000916
Port P4 direction register (P4D)
000A16
Port P5 (P5)
000B16
Port P5 direction register (P5D)
000C16
Port P6 (P6)
000D16
Port P6 direction register (P6D)
000E16
Port P7 (P7)
000F16
001016
Port P7 direction register (P7D)
001116
Port P8 direction register (P8D)/Port P7 input register (P7I)
002E16
Port control register 1 (PCTL1)
002F16
Port control register 2 (PCTL2)
Port P4 (P4)
Port P8 (P8)/Port P4 input register (P4I)
Fig. 2.1.1 Memory map of registers relevant to I/O port
2-2
3886 Group User’s Manual
APPLICATION
2.1 I/O port
2.1.2 Relevant registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)
[Address : 00 16, 0216, 04 16, 0616, 0816, 0A 16, 0C 16, 0E16, 10 16]
B
Name
0 Port Pi 0
Function
●
1 Port Pi1
●
2 Port Pi2
In output mode
Write
Port latch
Read
In input mode
Write : Port latch
Read : Value of pins
At reset
R W
?
?
?
3 Port Pi3
?
4 Port Pi4
?
5 Port Pi5
?
6 Port Pi6
?
7 Port Pi7
?
Fig. 2.1.2 Structure of Port Pi (i = 0 to 8)
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)
[Address : 01 16, 03 16, 05 16, 0716, 0916, 0B16, 0D 16, 0F16, 1116]
B
0 Port Pi direction register
1
2
3
4
5
6
7
Function
Name
0 : Port Pi 0 input mode
1 : Port Pi 0 output mode
0 : Port Pi 1 input mode
1 : Port Pi 1 output mode
0 : Port Pi 2 input mode
1 : Port Pi 2 output mode
0 : Port Pi 3 input mode
1 : Port Pi 3 output mode
0 : Port Pi 4 input mode
1 : Port Pi 4 output mode
0 : Port Pi 5 input mode
1 : Port Pi 5 output mode
0 : Port Pi 6 input mode
1 : Port Pi 6 output mode
0 : Port Pi 7 input mode
1 : Port Pi 7 output mode
At reset
R W
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
Fig. 2.1.3 Structure of Port Pi direction register (i = 0 to 8)
3886 Group User’s Manual
2-3
APPLICATION
2.1 I/O port
Port control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Port control register 1 (PCTL1) [Address 2E 16]
B
Function
Name
0 P00–P03 output structure
selection bit
P0
4–P0 7 output structure
1
selection bit
2 P10–P13 output structure
selection bit
P1
4–P1 7 output structure
3
selection bit
4 P30–P33 pull-up control bit
5 P34–P37 pull-up control bit
6 PWM0 enable bit
7 PWM1 enable bit
At reset
0: CMOS
1: N-channel open-drain
0: CMOS
1: N-channel open-drain
0: CMOS
1: N-channel open-drain
0
0: CMOS
1: N-channel open-drain
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: PWM 0 output disabled
1: PWM 0 output enabled
0
0: PWM 1 output disabled
1: PWM 1 output enabled
0
R W
0
0
0
0
0
Fig. 2.1.4 Structure of Port control register 1
Port control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Port control register 2 (PCTL2) [Address 2F 16]
B
Name
0
P4 input level selection bit
(P4 2–P4 6)
P7 input level selection bit
(P7 0–P7 5)
P4 output structure selection bit
(P4 2, P43, P4 4, P4 6)
P8 function selection bit
1
2
3
4 INT2, INT3, INT4 interrupt
switch bit
5 Timer Y count source
selection bit
6 Oscillation stabilizing time set
7
after STP instruction released
bit
Port output P4 2/P43 clear
function selection bit
Function
0
0: Port P8/Port P8 direction
register
1: Port P4 input register/Port P7
input register
0
0: INT 20, INT 30, INT40 interrupt
1: INT 21, INT 31, INT41 interrupt
0: f(XIN)/16 (f(X CIN)/16 in lowspeed mode)
1: f(XCIN)
0: Automatic set “01 16” to timer 1
and “FF 16” to prescaler 12
1: No automatic set
0: Only software clear
1: Software clear and output data
bus buffer 0 reading
(system bus side)
0
Fig. 2.1.5 Structure of Port control register 2
2-4
At reset
0: CMOS level input
1: TTL level input
0: CMOS level input
1: TTL level input
0: CMOS
1: N-channel open-drain
3886 Group User’s Manual
0
0
0
0
0
R W
APPLICATION
2.1 I/O port
2.1.3 Port P4/P7 input register
Port P4 input register/port P7 input register is selected by setting the port P8 function selection bit of port
control register 2 to “1”. By reading port P4/P7 input register, the contents of pins can be read out even
if the pins are set as output pins. That is, the port state can be read out when the output “H” voltage is
falling or the output “L” voltage is rising.
N-channel open-drain output structure is selected by setting the P4 output structure selection bit of port
control register 2 to “1”. TTL level input is selected by setting the P4 input level selection bit and the P7
input level selection bit of port control register 2 to “1”. Pull-up is selected by setting the P3 0–P3 3 pull-up
control bit and the P3 4–P3 7 pull-up control bit of port control register 1 to “1”.
2.1.4 Handling of unused pins
Table 2.1.1 Handling of unused pins (in single-chip mode)
Handling
Pins/Ports name
P0, P1, P2, P3, P4, •Set to the input mode and connect each to Vcc or Vss through a resistor of 1 kΩ
to 10 kΩ.
P5, P6, P7, P8
•Set to the output mode and open at “L” or “H” level.
VREF
AVSS
XOUT
•Connect to Vss (GND).
•Connect to Vss (GND).
•Open, only when using an external clock.
Table 2.1.2 Handling of unused pins (in memory expansion mode, microprocessor mode)
Pins/Ports name
P30, P31
Handling
•Open.
P4, P5, P6, P7, P8 •Set to the input mode and connect each to Vcc or Vss through a resistor of 1 kΩ to
10 kΩ.
•Set to the output mode and open at “L” or “H” level.
VREF
ONW
RESET OUT
φ
SYNC
AVSS
XOUT
•Connect to Vss (GND).
•Connect to Vcc through a resistor of 1 kΩ to 10 kΩ.
•Open.
•Open.
•Open.
•Connect to Vss (GND).
•Open, only when using an external clock.
3886 Group User’s Manual
2-5
APPLICATION
2.1 I/O port
2.1.5 Notes on input and output pins
(1) Notes in stand-by state
In stand-by state* 1 for low-power dissipation, do not make input levels of an input port and an I/O
port “undefined”, especially for I/O ports of the N-channel open-drain.
Pull-up (connect the port to V CC ) or pull-down (connect the port to V SS ) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using built-in pull-up or pull-down resistor, note on varied current values.
• When setting as an input port: Fix its input level
• When setting as an output port: Prevent current from flowing out to external
● Reason
In I/O ports of the N-channel open-drain, in spite of setting as an output port with its direction
register, when the content of the port latch is “1”, the transistor becomes the OFF state, which
causes the ports to be the high-impedance state. Note that the level becomes “undefined” depending
on external circuits.
Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the
state that input levels of an input port and an I/O port are “undefined”. This may cause power
source current.
* 1 stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
(2) Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction*2, the value of the
unspecified bit may be changed.
● Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
• As for a bit which is set for an input port :
The pin state is read in the CPU, and is written to this bit after bit managing.
• As for a bit which is set for an output port :
The bit value of the port latch is read in the CPU, and is written to this bit after bit managing.
Note the following :
• Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
• As for a bit of the port latch which is set for an input port, its value may be changed even when
not specified with a bit managing instruction in case where the pin state differs from its port latch
contents.
* 2 bit managing instructions : SEB, and CLB instructions
2-6
3886 Group User’s Manual
APPLICATION
2.1 I/O port
2.1.6 Termination of unused pins
(1) Terminate unused pins
➀ Output ports : Open
➁ Input ports :
Connect each pin to VCC or VSS through each resistor of 1 kΩ to 10 kΩ. With regard to ports which
can select the built-in pull-up resistor, the built-in pull-up resistor can be used. As for pins whose
potential affects to operation modes such as CNVSS pin or others, select the V CC pin or the VSS
pin according to their operation mode.
➂ I/O ports :
• Set the I/O ports for the input mode and connect them to V CC or V SS through each resistor of
1 kΩ to 10 kΩ. With regard to ports which can select the built-in pull-up resistor, the built-in pullup resistor can be used.
Set the I/O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the mode
of the ports is switched over to the output mode by the program after reset. Thus, the potential
at these pins is undefined and the power source current may increase in the input mode. With
regard to an effects on the system, thoroughly perform system evaluation on the user side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
➃ The AVss pin when not using the A-D/D-A converter :
• When not using the A-D/D-A converter, handle a power source pin for the A-D/D-A converter,
AVss pin as follows:
• AVss: Connect to the Vss pin
(2) Termination remarks
➀ Input ports and I/O ports :
Do not open in the input mode.
● Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➁ and
➂ shown on the above.
➁ I/O ports :
When setting for the input mode, do not connect to V CC or V SS directly.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and V CC (or V SS).
➂ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to V CC or VSS through
a resistor.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
3886 Group User’s Manual
2-7
APPLICATION
2.2 Interrupt
2.2 Interrupt
This paragraph explains the registers setting method and the notes relevant to the interrupt.
2.2.1 Memory map
002F16
Port control register 2 (PCTL2)
003916
Interrupt source selection register (INTSEL)
003A16
Interrupt edge selection register (INTEDGE)
003B16
003C16
Interrupt request register 1 (IREQ1)
003D16
Interrupt request register 2 (IREQ2)
003E16
Interrupt control register 1 (ICON1)
003F16
Interrupt control register 2 (ICON2)
Fig. 2.2.1 Memory map of registers relevant to interrupt
2.2.2 Relevant registers
Port control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Port control register 2 (PCTL2) [Address 2F 16]
Name
B
0 P4 input level selection bit
At reset
0
4 INT2, INT3, INT4 interrupt
0: INT20, INT30, INT40 interrupt
1: INT21, INT31, INT41 interrupt
0: f(XIN)/16 (f(XCIN)/16 in lowspeed mode)
1: f(XCIN)
6 Oscillation stabilizing time set 0: Automatic set “0116” to timer 1
and “FF16” to prescaler 12
after STP instruction released
1: No automatic set
bit
0: Only software clear
7 Port output P42/P43 clear
1: Software clear and output data
function selection bit
bus buffer 0 reading
(system bus side)
0
switch bit
5 Timer Y count source
selection bit
0
Fig. 2.2.2 Structure of Port control register 2
2-8
Function
0: CMOS level input
(P42–P46)
1: TTL level input
1 P7 input level selection bit
0: CMOS level input
(P70–P75)
1: TTL level input
2 P4 output structure selection bit 0: CMOS
(P42, P43, P44, P46)
1: N-channel open-drain
0: Port P8/Port P8 direction
3 P8 function selection bit
register
1: Port P4 input register/Port P7
input register
3886 Group User’s Manual
0
0
0
0
0
R W
APPLICATION
2.2 Interrupt
Interrupt source selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt source selection register [INTSEL: address 003916]
B
Name
Function
0 INT0/input buffer full interrupt 0 : INT0 interrupt
source selection bit
1 : Input buffer full interrupt
0 : INT1 interrupt
1 INT1/output buffer empty
interrupt source selection bit 1 : Output buffer empty interrupt
0 : Serial I/O1 transmit interrupt ✽1
2 Serial I/O1 transmit/SCL,SDA
interrupt source selection bit 1 : SCL,SDA interrupt
✽1
0 : CNTR0 interrupt
3 CNTR0/SCL,SDA interrupt
source selection bit
1 : SCL,SDA interrupt
✽2
0 : Serial I/O2 interrupt
4 Serial I/O2/I2C interrupt
source selection bit
1 : I2C interrupt
✽2
0 : INT2 interrupt
5 INT2/I2C interrupt source
selection bit
1 : I2C interrupt
✽3
0 : CNTR1 interrupt
6 CNTR1/key-on wake-up
interrupt source selection bit 1 : Key-on wake-up interrupt
✽3
7 AD converter/key-on wake-up 0 : A-D converter interrupt
interrupt source selection bit 1 : Key-on wake-up interrupt
✽1: Do not write “1” to these bits simultaneously.
✽2: Do not write “1” to these bits simultaneously.
✽3: Do not write “1” to these bits simultaneously.
At reset
R W
0
0
0
0
0
0
0
0
Fig. 2.2.3 Structure of Interrupt source selection register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A16]
B
Name
0 INT0 interrupt edge
1
2
3
4
5
Function
0 : Falling edge active
1 : Rising edge active
selection bit
INT1 interrupt edge
0 : Falling edge active
selection bit
1 : Rising edge active
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
0 : Falling edge active
INT2 interrupt edge
1 : Rising edge active
selection bit
0 : Falling edge active
INT3 interrupt edge
1 : Rising edge active
selection bit
0 : Falling edge active
INT4 interrupt edge
1 : Rising edge active
selection bit
6 Nothing is allocated for these bits. These are write disabled bits.
At reset
R W
0
0
0
✕
0
0
0
0
✕
0
✕
When these bits are read out, the values are “0”.
7
Fig. 2.2.4 Structure of Interrupt edge selection register
3886 Group User’s Manual
2-9
APPLICATION
2.2 Interrupt
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address : 3C16]
Name
B
0 INT0/input buffer full interrupt
request bit
1 INT1/output buffer empty
interrupt request bit
2 Serial I/O1 receive interrupt
request bit
3 Serial I/O1 transmit/SCL, SDA
interrupt request bit
4 Timer X interrupt request bit
5 Timer Y interrupt request bit
6 Timer 1 interrupt request bit
7 Timer 2 interrupt request bit
Function
At reset
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
R W
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.2.5 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2) [Address : 3D16]
Name
B
0 CNTR0/SCL, SDA interrupt
Function
At reset
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
INT3 interrupt request bit
1 : Interrupt request issued
0 : No interrupt request issued
INT4 interrupt request bit
1 : Interrupt request issued
AD converter/key-on wake-up 0 : No interrupt request issued
interrupt request bit
1 : Interrupt request issued
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
request bit
1 CNTR1/key-on wake-up
interrupt request bit
2 Serial I/O2/I2C interrupt
request bit
3 INT2/I2C interrupt request bit
4
5
6
7
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.2.6 Structure of Interrupt request register 2
2-10
3886 Group User’s Manual
R W
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✕
APPLICATION
2.2 Interrupt
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E16]
B
Name
0
INT0/input buffer full interrupt
enable bit
INT1/output buffer empty
interrupt enable bit
Serial I/O1 receive interrupt
enable bit
Serial I/O1 transmit/SCL, SDA
interrupt enable bit
1
2
3
4 Timer X interrupt enable bit
5 Timer Y interrupt enable bit
6 Timer 1 interrupt enable bit
7 Timer 2 interrupt enable bit
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset
R W
0
0
0
0
0
0
0
0
Fig. 2.2.7 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2 (ICON2) [Address : 3F16]
Name
B
0 CNTR0/SCL, SDA interrupt
1
2
3
4
5
6
7
Function
0 : Interrupt disabled
1 : Interrupt enabled
enable bit
0 : Interrupt disabled
CNTR1/key-on wake-up
1 : Interrupt enabled
interrupt enable bit
Serial I/O2/I2C interrupt enable 0 : Interrupt disabled
bit
1 : Interrupt enabled
INT2/I2C interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
INT3 interrupt enable bit
1 : Interrupt enabled
INT4 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
AD converter/key-on wake-up 0 : Interrupt disabled
interrupt enable bit
1 : Interrupt enabled
Fix this bit to “0”.
At reset
R W
0
0
0
0
0
0
0
0
Fig. 2.2.8 Structure of Interrupt control register 2
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APPLICATION
2.2 Interrupt
2.2.3 Interrupt source
The 3886 group permits interrupts of 16 sources among 21 sources. These are vector interrupts with a
fixed priority system. Accordingly, when two or more interrupt requests occur during the same sampling,
the higher-priority interrupt is accepted first. This priority is determined by hardware, but a variety of priority
processing can be performed by software, using an interrupt enable bit and an interrupt disable flag.
For interrupt sources, vector addresses and interrupt priority, refer to Table 2.2.1.
Table 2.2.1 Interrupt sources, vector addresses and priority of 3886 group
Interrupt Source
Reset (Note 2)
Priority
1
Vector Addresses (Note 1)
High
Low
FFFD16
FFFC16
INT0
2
FFFB16
FFFA16
Interrupt Request
Generating Conditions
At reset
Non-maskable
At detection of either rising or
falling edge of INT0 input
External interrupt
(active edge selectable)
Input buffer full
(IBF)
At input data bus buffer writing
INT1
At detection of either rising or
falling edge of INT1 input
Output buffer
empty (OBE)
Serial I/O1
reception
Serial I/O1
transmission
3
FFF916
FFF816
4
FFF716
FFF616
5
FFF516
FFF416
SCL, SDA
Timer X
Timer Y
Timer 1
Timer 2
6
7
8
9
FFF316
FFF116
FFEF16
FFED16
FFF216
FFF016
FFEE16
FFEC16
10
FFEB16
FFEA16
11
FFE916
FFE816
CNTR0
SCL, SDA
CNTR1
Serial I/O2
12
FFE716
INT2
13
FFE516
At completion of serial I/O1 data
reception
At completion of serial I/O1
transfer shift or when transmission buffer is empty
At detection of either rising or
falling edge of SCL or SDA
At timer X underflow
At timer 1 underflow
At timer 2 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of SCL or SDA
At detection of either rising or
falling edge of CNTR1 input
FFE416
At completion of data transfer
At detection of either rising or
falling edge of INT2 input
I 2C
14
FFE316
FFE216
At detection of either rising or
falling edge of INT3 input
INT4
15
FFE116
FFE016
At detection of either rising or
falling edge of INT4 input
16
FFDF16
FFDE16
External interrupt
(active edge selectable)
STP release timer underflow
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (falling edge valid)
Valid when serial I/O2 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
At completion of A-D conversion
A-D converter
Key-on wake-up
17
FFDD16
FFDC16
At falling of port P3 (at input) input logical level AND
External interrupt (falling edge valid)
At BRK instruction execution
Non-maskable software interrupt
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
2-12
Valid when serial I/O1 is selected
At completion of data transfer
INT3
BRK instruction
Valid when serial I/O1 is selected
At timer Y underflow
FFE616
I 2C
External interrupt
(active edge selectable)
At output data bus buffer reading
At falling of port P3 (at input) input logical level AND
At completion of serial I/O2 data
transfer
Key-on wake-up
Remarks
3886 Group User’s Manual
APPLICATION
2.2 Interrupt
2.2.4 Interrupt operation
When an interrupt request is accepted, the contents of the following registers just before acceptance of the
interrupt requests is automatically pushed onto the stack area in the order of ➀, ➁ and ➂.
➀High-order contents of program counter (PC H)
➁Low-order contents of program counter (PC L)
➂Contents of processor status register (PS)
After the contents of the above registers are pushed onto the stack area, the accepted interrupt vector
address enters the program counter and consequently the interrupt processing routine is executed.
When the RTI instruction is executed at the end of the interrupt processing routine, the contents of the
above registers pushed onto the stack area are restored to the respective registers in the order of ➂, ➁
and ➀; and the microcomputer resumes the processing executed just before acceptance of the interrupts.
Figure 2.2.9 shows an interrupt operation diagram.
Executing routine
·······
Interrupt occurs
(Accepting interrupt request)
Suspended
operation
Resume processing
Contents of program counter (high-order) are pushed onto stack
Contents of program counter (low-order) are pushed onto stack
Contents of processor status register are pushed onto stack
·······
Interrupt
processing
routine
RTI instruction
Contents of processor status register are popped from stack
Contents of program counter (low-order) are popped from stack
Contents of program counter (high-order) are popped from stack
: Operation commanded by software
: Internal operation performed automatically
Fig. 2.2.9 Interrupt operation diagram
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APPLICATION
2.2 Interrupt
(1) Processing upon acceptance of interrupt request
Upon acceptance of an interrupt request, the following operations are automatically performed.
➀The processing being executed is stopped.
➁The contents of the program counter and the processor status register are pushed onto the stack
area. Figure 2.2.10 shows the changes of the stack pointer and the program counter upon acceptance
of an interrupt request.
➂Concurrently with the push operation, the jump destination address (the beginning address of the
interrupt processing routine) of the occurring interrupt stored in the vector address is set in the
program counter, then the interrupt processing routine is executed.
➃After the interrupt processing routine is started, the corresponding interrupt request bit is automatically
cleared to “0”. The interrupt disable flag is set to “1” so that multiple interrupts are disabled.
Accordingly, for executing the interrupt processing routine, it is necessary to set the jump destination
address in the vector area corresponding to each interrupt.
Stack area
Program counter
PCL Program counter (low-order)
PCH Program counter (high-order)
Interrupt disable flag = “0”
Stack pointer
S
(S)
(S)
Interrupt
request is
accepted
Program counter
PCL
Vector address
PCH
(from Interrupt vector area)
Stack area
Interrupt disable flag = “1”
(s) – 3
Processor status register
Stack pointer
S
Program counter (low-order)
(S) – 3
(S) Program counter (high-order)
Fig. 2.2.10 Changes of stack pointer and program counter upon acceptance of interrupt request
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APPLICATION
2.2 Interrupt
(2) Timing after acceptance of interrupt request
The interrupt processing routine begins with the machine cycle following the completion of the
instruction that is currently being executed.
Figure 2.2.11 shows the time up to execution of interrupt processing routine and Figure 2.2.12 shows
the timing chart after acceptance of interrupt request.
Interrupt request generated
Start of interrupt processing
Waiting time for Stack push and
post-processing Vector fetch
of pipeline
Main routine
Interrupt processing routine
✽
0 to 16 cycles
2 cycles
5 cycles
7 to 23 cycles
(When f(XIN) = 8 MHz, 1.75 µs to 5.75 µs)
✽ When executing DIV instruction
Fig. 2.2.11 Time up to execution of interrupt processing routine
Waiting time for pipeline
post-processing
Push onto stack
Vector fetch
Interrupt operation starts
φ
SYNC
RD
WR
Address bus
Data bus
PC
Not used
S, SPS
S-1, SPS S-2, SPS
PCH
PCL
BL
PS
BH
AL
AL, AH
AH
SYNC : CPU operation code fetch cycle
(This is an internal signal that cannot be observed from the external unit.)
BL, BH : Vector address of each interrupt
AL, AH : Jump destination address of each interrupt
SPS : “0016” or “0116”
Fig. 2.2.12 Timing chart after acceptance of interrupt request
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APPLICATION
2.2 Interrupt
2.2.5 Interrupt control
The acceptance of all interrupts, excluding the BRK instruction interrupt, can be controlled by the interrupt
request bit, interrupt enable bit, and an interrupt disable flag, as described in detail below. Figure 2.2.13
shows an interrupt control diagram.
Interrupt request bit
Interrupt enable bit
Interrupt request
Interrupt disable flag
BRK instruction
Reset
Fig. 2.2.13 Interrupt control diagram
The interrupt request bit, interrupt enable bit and interrupt disable flag function independently and do not
affect each other. An interrupt is accepted when all the following conditions are satisfied.
●Interrupt request bit .......... “1”
●Interrupt enable bit ........... “1”
●Interrupt disable flag ........ “0”
Though the interrupt priority is determined by hardware, a variety of priority processing can be performed
by software using the above bits and flag. Table 2.2.2 shows a list of interrupt control bits according to the
interrupt source.
(1) Interrupt request bits
The interrupt request bits are allocated to the interrupt request register 1 (address 3C16) and interrupt
request register 2 (address 3D 16).
The occurrence of an interrupt request causes the corresponding interrupt request bit to be set to
“1”. The interrupt request bit is held in the “1” state until the interrupt is accepted. When the interrupt
is accepted, this bit is automatically cleared to “0”.
Each interrupt request bit can be set to “0”, but cannot be set to “1”, by software.
(2) Interrupt enable bits
The interrupt enable bits are allocated to the interrupt control register 1 (address 003E 16) and the
interrupt control register 2 (address 3F 16).
The interrupt enable bits control the acceptance of the corresponding interrupt request.
When an interrupt enable bit is “0”, the corresponding interrupt request is disabled. If an interrupt
request occurs when this bit is “0”, the corresponding interrupt request bit is set to “1” but the
interrupt is not accepted. In this case, unless the interrupt request bit is set to “0” by software, the
interrupt request bit remains in the “1” state.
When an interrupt enable bit is “1”, the corresponding interrupt is enabled. If an interrupt request
occurs when this bit is “1”, the interrupt is accepted (when interrupt disable flag = “0”).
Each interrupt enable bit can be set to “0” or “1” by software.
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APPLICATION
2.2 Interrupt
(3) Interrupt disable flag
The interrupt disable flag is allocated to bit 2 of the processor status register. The interrupt disable
flag controls the acceptance of interrupt request except BRK instruction.
When this flag is “1”, the acceptance of interrupt requests is disabled. When the flag is “0”, the
acceptance of interrupt requests is enabled. This flag is set to “1” with the SEI instruction and is set
to “0” with the CLI instruction.
When a main routine branches to an interrupt processing routine, this flag is automatically set to “1”,
so that multiple interrupts are disabled. To use multiple interrupts, set this flag to “0” with the CLI
instruction within the interrupt processing routine. Figure 2.2.14 shows an example of multiple interrupts.
Table 2.2.2 List of interrupt bits according to interrupt source
Interrupt source
INT 0/Input buffer full
INT 1/Output buffer empty
Serial I/O1 reception
Serial I/O1 transmission/SCL, S DA
Timer X
Timer Y
Timer 1
Timer 2
CNTR 0/S CL, S DA
CNTR1/Key-on wake-up
Serial I/O2/I 2C
INT2/I2C
INT3
INT4
A-D converter/Key-on wake-up
Interrupt enable bit
Address
003E16
003E16
003E16
003E16
003E16
003E16
003E16
003E16
003F 16
003F 16
003F 16
003F 16
003F 16
003F 16
003F 16
3886 Group User’s Manual
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b0
b1
b2
b3
b4
b5
b6
Interrupt request bit
Address
003C 16
003C 16
003C 16
003C 16
003C 16
003C 16
003C 16
003C 16
003D 16
003D 16
003D 16
003D 16
003D 16
003D 16
003D 16
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b0
b1
b2
b3
b4
b5
b6
2-17
APPLICATION
2.2 Interrupt
Interrupt request
Nesting
Reset
Time
Main routine
I=1
C1 = 0, C2 = 0
Interrupt
request 1
C1 = 1
I=0
Interrupt 1
I=1
Interrupt
request 2
Multiple interrupt
C2 = 1
I=0
Interrupt 2
I=1
RTI
I=0
RTI
I=0
I : Interrupt disable flag
C1 : Interrupt enable bit of interrupt 1
C2 : Interrupt enable bit of interrupt 2
: Set automatically.
: Set by software.
Fig. 2.2.14 Example of multiple interrupts
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APPLICATION
2.2 Interrupt
2.2.6 INT interrupt
The INT interrupt requests is generated when the microcomputer detects a level change of each INT pin
(INT 0–INT 4).
(1) Active edge selection
INT 0–INT4 can be selected from either a falling edge or rising edge detection as an active edge by
the interrupt edge selection register. In the “0” state, the falling edge of the corresponding pin is
detected. In the “1” state, the rising edge of the corresponding pin is detected.
(2) INT 0–INT 2 interrupt sources selection
Which of interrupt source of the following interrupt sources can be selected by the interrupt source
selection register (address 39 16). (Set each bit to “0” when using INT.)
•INT 0 or input buffer full (bit 0)
•INT 1 or output buffer empty (bit 1)
•INT 2 or I 2C (bit 5)
(3) INT 2–INT 4 input pins selection
The occurrence sources of the external interrupt INT 2 to INT 4 can be selected from which of the
following by the INT2, INT 3, INT 4 interrupt switch bit of the port control register 2 (address 2F 16).
•INT 20, INT30, INT 40 or
•INT 21, INT 31, INT41
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APPLICATION
2.2 Interrupt
2.2.7 Key input interrupt
A key input interrupt request is generated by applying “L” level to any port P3 pin that has been set to the
input mode. In other words, it is generated when AND of the input level goes from “1” to “0”.
(1) Connection example when Key input interrupt is used
When using the Key input interrupt, compose an active-low key matrix which inputs to port P3. Figure
2.2.15 shows a connection example and the port P3 block diagram when using a key input interrupt.
In the connection example in Figure 2.2.15, a key input interrupt request is generated by pressing
one of the keys corresponding to ports P3 0 to P3 3.
Port PXx
“L” level output
Port control register 1
Bit 5 = “0”
Port P37
direction register = “1”
✻
✻✻
✻
✻✻
✻
✻✻
Port P35
latch
✻
✻✻
Port P34
latch
Key input interrupt request
Port P37
latch
P37 output
Port P36
direction register = “1”
Port P36
latch
P36 output
Port P35
direction register = “1”
P35 output
Port P34
direction register = “1”
P34 output
✻
P33 input
Port control register 1
Bit 4 = “1”
✻✻
Port P33
latch
Port P3
Input reading circuit
Comparator circuit
Port P32
direction register = “0”
✻
✻✻
✻
✻✻
✻
✻✻
P32 input
Port P32
latch
Port P31
direction register = “0”
P31 input
P30 input
Port P33
direction register = “0”
Port P31
latch
Port P30
direction register = “0”
Port P30
latch
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✻
[✻[ ✻
CM
ouotp
CO
MS
OS
uu
tpt ubtubffuefrfer
Fig. 2.2.15 Connection example and port P3 block diagram when using key input interrupt
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3886 Group User’s Manual
APPLICATION
2.2 Interrupt
(2) Relevant registers setting
Figure 2.2.16 shows the relevant registers setting (corresponding to Figure 2.2.15).
Port P3 direction register (address 0716)
b7
P3D
b0
1 1 1 1 0 0 0 0
Bits corresponding to P37 to P30
0: Input port
1: Output port
Port control register 1 (address 2E16)
b7
b0
PCTL1
1
P30 to P33 pull-up
Interrupt source selection register (address 3916)
b7
INTSEL
b0
N o te N o te
1
1
Key-on wake-up interrupt
Interrupt request register 2 (address 3D16)
b7
IREQ2
b0
N o te
2
N o te
2
Key-on wake-up interrupt request (Note 2)
Interrupt control register 2 (address 3F16)
b7
ICON2
0
b0
N o te
3
N o te
3
Key-on wake-up interrupt: Enabled (Note 3)
Notes 1: Set “1” to the bit which is selected as the key-on wake-up interrupt source from either b7 or b6
of the interrupt source selection register. Do not set “1” to these bits simultaneously. (When
setting “1” to b6, set “0” to b7. When setting “0” to b6, set “1” to b7.)
2: When setting “1” to b7 of the interrupt source selection register, set “0” to b6 of the interrupt
request register 2. When setting “1” to b6 of the interrupt source selection register, set “0” to
b1 of the interrupt request register 2.
3: When setting “1” to b7 of the interrupt source selection register, set “1” to b6 of the interrupt
control register 2. When setting “1” to b6 of the interrupt source selection register, set “1” to b1
of the interrupt control register 2.
Fig. 2.2.16 Registers setting relevant to key input interrupt (corresponding to Figure 2.2.15)
(3) Key input interrupt source selection
When using a key input interrupt source, select which of the following by the interrupt source
selection register (address 39 16).
•CNTR 0 or key-on wake-up (bit 6)
•A-D converter or key-on wake-up (bit 7)
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APPLICATION
2.2 Interrupt
2.2.8 Notes on interrupts
(1) Switching external interrupt detection edge
When switching the external interrupt detection edge, switch it in the following sequence.
Clear an interrupt enable bit to “0” (interrupt disabled)
↓
Switch the detection edge
↓
Clear an interrupt request bit to “0”
(no interrupt request issued)
↓
Set the interrupt enable bit to “1” (interrupt enabled)
Fig. 2.2.17 Sequence of switching detection edge
■ Reason
The interrupt circuit recognizes the switching of the detection edge as the change of external input
signals. This may cause an unnecessary interrupt.
(2) Check of interrupt request bit
● When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request
register immediately after this bit is set to “0” by using a data transfer instruction, execute one or
more instructions before executing the BBC or BBS instruction.
Clear the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Data transfer instruction:
LDM, LDA, STA, STX, and STY instructions
Fig. 2.2.18 Sequence of check of interrupt request bit
■ Reason
If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt
request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0”
is read.
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APPLICATION
2.2 Interrupt
(3) Change of relevant register settings
When the setting of the following registers or bits is changed, the interrupt request bit may be set
to “1”.
•Interrupt edge selection register (address 3A 16)
•Interrupt source selection register (address 39 16)
•INT2, INT3, INT4 interrupt switch bit of port control register 2 (bit 4 of address 2F16)
Set the above listed registers or bits as the following sequence.
Clear an interrupt enable bit to “0” (interrupt disabled)
↓
Set the above listed registers or bits
↓
Clear an interrupt request bit to “0”
(no interrupt request issued)
↓
Set the interrupt enable bit to “1” (interrupt enabled)
Fig. 2.2.19 Sequence of changing relevant register
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APPLICATION
2.3 Timer
2.3 Timer
This paragraph explains the registers setting method and the notes relevant to the timers.
2.3.1 Memory map
002016
Prescaler 12 (PRE12)
002116
Timer 1 (T1)
002216
Timer 2 (T2)
002316
Timer XY mode register (TM)
002416
Prescaler X (PREX)
002516
Timer X (TX)
002616
002716
Prescaler Y (PREY)
002F16
Port control register 2 (PCTL2)
003C16
Interrupt request register 1 (IREQ1)
003D16
Interrupt request register 2 (IREQ2)
003E16
Interrupt control register 1 (ICON1)
003F16
Interrupt control register 2 (ICON2)
Timer Y (TY)
Fig. 2.3.1 Memory map of registers relevant to timers
2.3.2 Relevant registers
Prescaler 12, Prescaler X, Prescaler Y
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 12 (PRE12) [Address : 20 16]
Prescaler X (PREX) [Address : 24 16]
Prescaler Y (PREY) [Address : 26 16]
B
Name
Function
0 •Set a count value of each prescaler.
•The value set in this register is written to both each prescaler
and the corresponding prescaler latch at the same time.
•When this register is read out, the count value of the corres2 ponding prescaler is read out.
1
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 2.3.2 Structure of Prescaler 12, Prescaler X, Prescaler Y
2-24
At reset
3886 Group User’s Manual
R W
APPLICATION
2.3 Timer
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1 (T1) [Address : 21 16]
B
Name
Function
0 •Set a count value of timer 1.
At reset
R W
1
•The value set in this register is written to both timer 1 and timer 1
1 latch at the same time.
•When this register is read out, the timer 1’s count value is read
2 out.
0
0
3
0
4
0
5
0
6
0
7
0
Fig. 2.3.3 Structure of Timer 1
Timer 2, Timer X, Timer Y
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2 (T2) [Address : 22 16]
Timer X (TX) [Address : 25 16]
Timer Y (TY) [Address : 27 16]
B
Name
Function
0 •Set a count value of each timer.
•The value set in this register is written to both each timer and
1 each timer latch at the same time.
•When this register is read out, each timer’s count value is read
2 out.
At reset
R W
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 2.3.4 Structure of Timer 2, Timer X, Timer Y
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APPLICATION
2.3 Timer
Timer XY mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer XY mode register (TM) [Address : 23 16 ]
B
Function
Name
0 Timer X operating mode bits
1
b1 b0
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement
mode
At reset
0
0
The function depends on the
operating mode of Timer X.
(Refer to Table 2.2.1)
0
3 Timer X count stop bit
0 : Count start
1 : Count stop
0
4 Timer Y operating mode bits
b5 b4
0
2 CNTR 0 active edge selection
bit
5
6 CNTR 1 active edge selection
bit
7 Timer Y count stop bit
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement
mode
The function depends on the
operating mode of Timer Y.
(Refer to Table 2.2.1)
0 : Count start
1 : Count stop
R W
0
0
0
Fig. 2.3.5 Structure of Timer XY mode register
Table 2.3.1 CNTR 0 /CNTR 1 active edge selection bit function
Timer X /Timer Y operation
modes
Timer mode
CNTR0 / CNTR1 active edge selection bit
(bits 2, 6 of address 23 16) contents
“0” CNTR 0 / CNTR 1 interrupt request occurrence: Falling edge
; No influence to timer count
“1” CNTR 0 / CNTR 1 interrupt request occurrence: Rising edge
Pulse output mode
; No influence to timer count
“0” Pulse output start: Beginning at “H” level
CNTR 0 / CNTR 1 interrupt request occurrence: Falling edge
“1” Pulse output start: Beginning at “L” level
CNTR 0 / CNTR 1 interrupt request occurrence: Rising edge
Event counter mode
“0” Timer X / Timer Y: Rising edge count
CNTR 0 / CNTR 1 interrupt request occurrence: Falling edge
“1” Timer X / Timer Y: Falling edge count
CNTR 0 / CNTR 1 interrupt request occurrence: Rising edge
Pulse width measurement mode
“0” Timer X / Timer Y: “H” level width measurement
CNTR 0 / CNTR 1 interrupt request occurrence: Falling edge
“1” Timer X / Timer Y: “L” level width measurement
CNTR 0 / CNTR 1 interrupt request occurrence: Rising edge
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APPLICATION
2.3 Timer
Port control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Port control register 2 (PCTL2) [Address 2F 16]
B
Name
0
P4 input level selection bit
(P4 2–P4 6)
P7 input level selection bit
(P7 0–P7 5)
P4 output structure selection bit
(P4 2, P43, P4 4, P4 6)
P8 function selection bit
1
2
3
4 INT2, INT3, INT4 interrupt
switch bit
5 Timer Y count source
selection bit
6 Oscillation stabilizing time set
7
after STP instruction released
bit
Port output P4 2/P43 clear
function selection bit
Function
At reset
0: CMOS level input
1: TTL level input
0: CMOS level input
1: TTL level input
0: CMOS
1: N-channel open-drain
0
0: Port P8/Port P8 direction
register
1: Port P4 input register/Port P7
input register
0
0: INT 20, INT 30, INT40 interrupt
1: INT 21, INT 31, INT41 interrupt
0: f(XIN)/16 (f(X CIN)/16 in lowspeed mode)
1: f(XCIN)
0: Automatic set “01 16” to timer 1
and “FF 16” to prescaler 12
1: No automatic set
0: Only software clear
1: Software clear and output data
bus buffer 0 reading
(system bus side)
0
R W
0
0
0
0
0
Fig. 2.3.6 Structure of Port control register 2
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APPLICATION
2.3 Timer
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address : 3C
B
Function
Name
0 INT 0/input buffer full interrupt
request bit
1 INT 1/output buffer empty
interrupt request bit
2 Serial I/O1 receive interrupt
request bit
3 Serial I/O1 transmit/S CL, SDA
interrupt request bit
4 Timer X interrupt request bit
5 Timer Y interrupt request bit
6 Timer 1 interrupt request bit
7 Timer 2 interrupt request bit
16]
At reset
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.3.7 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2) [Address : 3D
B
16]
Function
Name
At reset
0
✽
0
✽
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
4 interrupt request bit
INT
0 : No interrupt request issued
5
1 : Interrupt request issued
AD
converter/key-on
wake-up
0 : No interrupt request issued
6
1 : Interrupt request issued
interrupt request bit
7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
0
✽
0
✽
0
✽
0
✕
3 INT 2/I2C interrupt request bit
4 INT 3 interrupt request bit
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.3.8 Structure of Interrupt request register 2
2-28
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 CNTR 0/SCL, SDA interrupt
request bit
1 CNTR 1/key-on wake-up
interrupt request bit
2
2 Serial I/O2/I C interrupt
request bit
3886 Group User’s Manual
APPLICATION
2.3 Timer
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E
B
0
1
2
3
Function
Name
INT 0/input buffer full interrupt
enable bit
INT 1/output buffer empty
interrupt enable bit
Serial I/O1 receive interrupt
enable bit
Serial I/O1 transmit/S CL, SDA
interrupt enable bit
4 Timer X interrupt enable bit
5 Timer Y interrupt enable bit
6 Timer 1 interrupt enable bit
7 Timer 2 interrupt enable bit
16]
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset
R W
0
0
0
0
0
0
0
0
Fig. 2.3.9 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2 (ICON2) [Address : 3F16]
B
Name
0 CNTR0/SCL, SDA interrupt
enable bit
1 CNTR1/key-on wake-up
interrupt enable bit
2 Serial I/O2/I2C interrupt enable
bit
3 INT2/I2C interrupt enable bit
4 INT3 interrupt enable bit
5 INT4 interrupt enable bit
6 AD converter/key-on wake-up
interrupt enable bit
7 Fix this bit to “0”.
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset
R W
0
0
0
0
0
0
0
0
Fig. 2.3.10 Structure of Interrupt control register 2
3886 Group User’s Manual
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APPLICATION
2.3 Timer
2.3.3 Timer application examples
(1) Basic functions and uses
[Function 1] Control of Event interval (Timer X, Timer Y, Timer 1, Timer 2)
When a certain time, by setting a count value to each timer, has passed, the timer interrupt request
occurs.
<Use>
•Generation of an output signal timing
•Generation of a wait time
[Function 2] Control of Cyclic operation (Timer X, Timer Y, Timer 1, Timer 2)
The value of the timer latch is automatically written to the corresponding timer each time the timer
underflows, and each timer interrupt request occurs in cycles.
<Use>
•Generation of cyclic interrupts
•Clock function (measurement of 250 ms); see Application example 1
•Control of a main routine cycle
[Function 3] Output of Rectangular waveform (Timer X, Timer Y)
The output level of the CNTR0 pin or CNTR1 pin is inverted each time the timer underflows (in the
pulse output mode).
<Use>
•Piezoelectric buzzer output; see Application example 2
•Generation of the remote control carrier waveforms
[Function 4] Count of External pulses (Timer X, Timer Y)
External pulses input to the CNTR 0 pin or CNTR 1 pin are counted as the timer count source (in
the event counter mode).
<Use>
•Frequency measurement; see Application example 3
•Division of external pulses
•Generation of interrupts due to a cycle using external pulses as the count source; count of a
reel pulse
[Function 5] Measurement of External pulse width (Timer X, Timer Y)
The “H” or “L” level width of external pulses input to CNTR0 pin or CNTR1 pin is measured (in the
pulse width measurement mode).
<Use>
•Measurement of external pulse frequency (measurement of pulse width of FG pulse ✽ for a
motor); see Application example 4
•Measurement of external pulse duty (when the frequency is fixed)
FG pulse ✽: Pulse used for detecting the motor speed to control the motor speed.
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APPLICATION
2.3 Timer
(2) Timer application example 1: Clock function (measurement of 250 ms)
Outline: The input clock is divided by the timer so that the clock can count up at 250 ms intervals.
Specifications: •The clock f(X IN) = 4.19 MHz (2 22 Hz) is divided by the timer.
•The clock is counted up in the process routine of the timer X interrupt which occurs
at 250 ms intervals.
Figure 2.3.11 shows the timers connection and setting of division ratios; Figure 2.3.12 shows the
relevant registers setting; Figure 2.3.13 shows the control procedure.
f(XIN) = 4.19 MHz
Fixed
Prescaler X
Timer X
Timer X interrupt
request bit
1/16
1/256
1/256
0 or 1
Dividing by 4 with software
1/4
250 ms
1 second
0 : No interrupt request issued
1 : Interrupt request issued
Fig. 2.3.11 Timers connection and setting of division ratios
Timer XY mode register (address 23 16)
b7
b0
1
TM
0 0
Timer X operating mode: Timer mode
Timer X count: Stop
Clear to “0” when starting count.
Prescaler X (address 24 16)
b7
PREX
b0
255
Timer X (address 25 16)
b7
Set “division ratio – 1”
b0
255
TX
Interrupt request register 1 (address 3C 16)
b7
b0
0
IREQ1
Timer X interrupt request
(becomes “1” at 250 ms intervals)
Interrupt control register 1 (address 3E 16)
b7
ICON1
b0
1
Timer X interrupt: Enabled
Fig. 2.3.12 Relevant registers setting
3886 Group User’s Manual
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APPLICATION
2.3 Timer
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SEI
•All interrupts disabled
.....
TM
IREQ1
ICON1
•Timer X operating mode : Timer mode
•Timer X interrupt request bit cleared
•Timer X interrupt enabled
(address 24 16)
(address 25 16)
256 – 1
256 – 1
•“Division ratio – 1” set to Prescaler X and Timer X
(address 23 16), bit3
0
•Timer X count start
.....
xxxx1x002
(address 23 16)
xxx0xxxx 2
(address 3C 16)
1
(address 3E 16), bit4
PREX
TX
.....
TM
.....
CLI
•Interrupts enabled
Main processing
.....
<Procedure for completion of clock set>
(Note 1)
TM
PREX
TX
IREQ1
TM
(address 23 16), bit3
(address 24 16)
(address 25 16)
(address 3C 16), bit4
(address 23 16), bit3
•Timer X count stop
•Timer reset to restart count from 0 second after completion of
clock set
1
256 – 1
256 – 1
0
0
•Timer X count start
Note 1: Perform procedure for completion of clock set only
when completing clock set.
Timer X interrupt process routine
CLT (Note 2)
CLD (Note 3)
Push registers to stack
Clock stop ?
Note 2: When using Index X mode flag (T)
Note 3: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
Y
•Judgment whether clock stops
N
Clock count up (1/4 second to year)
Pop registers
•Clock counted up
•Pop registers pushed to stack
RTI
Fig. 2.3.13 Control procedure
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APPLICATION
2.3 Timer
(3) Timer application example 2: Piezoelectric buzzer output
Outline: The rectangular waveform output function of the timer is applied for a piezoelectric buzzer
output.
Specifications: •The rectangular waveform, dividing the clock f(XIN) = 4.19 MHz (2 22 Hz) into about
2 kHz (2048 Hz), is output from the P5 4/CNTR 0 pin.
•The level of the P54/CNTR 0 pin is fixed to “H” while a piezoelectric buzzer output
stops.
Figure 2.3.14 shows a peripheral circuit example, and Figure 2.3.15 shows the timers connection and
setting of division ratios. Figures 2.3.16 shows the relevant registers setting, and Figure 2.3.17
shows the control procedure.
The “H” level is output while a piezoelectric buzzer output stops.
CNTR 0 output
P54/CNTR 0
PiPiPi.....
244 µs 244 µs
Set a division ratio so that the
underflow output period of the timer X
can be 244 µs.
3886 Group
Fig. 2.3.14 Peripheral circuit example
f(XIN) = 4.19 MHz
Fixed
Prescaler X
Timer X
Fixed
1/16
1
1/64
1/2
CNTR 0
Fig. 2.3.15 Timers connection and setting of division ratios
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APPLICATION
2.3 Timer
Timer XY mode register (address 23 16)
b7
b0
TM
1 0 0 1
Timer X operating mode: Pulse output mode
CNTR0 active edge selection: Output starting at “H” level
Timer X count: Stop
Clear to “0” when starting count.
Timer X (address 25 16)
b7
b0
63
TX
Set “division ratio – 1”.
Prescaler X (address 24 16)
b7
b0
0
PREX
Fig. 2.3.16 Relevant registers setting
RESET
Initialization
.....
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
(address 0A 16), bit4
(address 0B 16)
P5
P5D
1
XXX1XXXX2
.....
ICON1
TM
TX
PREX
(address 3E 16), bit4
(address 23 16)
(address 25 16)
(address 24 16)
•Timer X interrupt disabled
•CNTR0 output stop; Piezoelectric buzzer output stop
•“Division ratio – 1” set to Timer X and Prescaler X
0
XXXX1001 2
64 – 1
1–1
.....
Main processing
.....
Output unit
Yes
•Processing piezoelectric buzzer request, generated during
main processing, in output unit
Piezoelectric buzzer request ?
No
TM (address 23 16), bit3
TX (address 25 16)
1
64 – 1
TM (address 23 16), bit3
0
Piezoelectric buzzer output start
Stop piezoelectric buzzer output
Fig. 2.3.17 Control procedure
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APPLICATION
2.3 Timer
(4) Timer application example 3: Frequency measurement
Outline: The following two values are compared to judge whether the frequency is within a valid
range.
•A value by counting pulses input to P5 5/CNTR 1 pin with the timer.
•A reference value
Specifications: •The pulse is input to the P5 5/CNTR 1 pin and counted by the timer Y.
•A count value is read out at about 2 ms intervals, the timer 1 interrupt interval.
When the count value is 28 to 40, it is judged that the input pulse is valid.
•Because the timer is a down-counter, the count value is compared with 227 to 215
(Note).
Note: 227 to 215 = {255 (initial value of counter) – 28} to {255 – 40}; 28 to 40 means the number
of valid value.
Figure 2.3.18 shows the judgment method of valid/invalid of input pulses; Figure 2.3.19 shows the
relevant registers setting; Figure 2.3.20 shows the control procedure.
......
Input pulse
71.4 µs or more
(14 kHz or less)
......
71.4 µs
(14 kHz)
......
50 µs
(20 kHz)
Valid
Invalid
2 ms = 28 counts
71.4 µs
50 µs or less
(20 kHz or more)
Invalid
2 ms
50 µs
= 40 counts
Fig. 2.3.18 Judgment method of valid/invalid of input pulses
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APPLICATION
2.3 Timer
Timer XY mode register (address 23 16)
b7
TM
1
b0
1 1 0
Timer Y operating mode: Event counter mode
CNTR1 active edge selection: Falling edge count
Timer Y count: Stop
Clear to “0” when starting count.
Prescaler 12 (address 20 16)
b7
b0
PRE12
63
Timer 1 (address 21 16)
b7
b0
T1
7
Set “division ratio – 1”.
Prescaler Y (address 26 16)
b7
b0
PREY
0
Timer Y (address 27 16)
b7
b0
TY
Set 255 just before counting pulses.
(After a certain time has passed, the number of input
pulses is decreased from this value.)
255
Interrupt control register 1 (address 3E 16)
b7
b0
1 0
ICON1
Timer Y interrupt: Disabled
Timer 1 interrupt: Enabled
Interrupt request register 1 (address 3C 16)
b7
IREQ1
b0
0
Judge Timer Y interrupt request bit.
( “1” of this bit when reading the count value indicates the 256 or more
pulses input in the condition of Timer Y = 255)
Fig. 2.3.19 Relevant registers setting
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APPLICATION
2.3 Timer
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrary.
Initialization
SEI
•All interrupts disabled
.....
TM
PRE12
T1
PREY
TY
ICON1
1110 XXXX2
(address 23 16)
64 – 1
(address 20 16)
8–1
(address 21 16)
1–1
(address 26 16)
(address 27 16)
256 – 1
(address 3E 16), bit6
1
•Timer 1 interrupt enabled
(address 23 16), bit7
•Timer Y count start
•Timer Y operating mode : Event counter mode
(Count a falling edge of pulses input from CNTR 1 pin.)
•Division ratio set so that Timer 1 interrupt will occur at
2 ms intervals.
.....
TM
0
.....
•Interrupts enabled
CLI
Timer 1 interrupt process routine
CLT (Note 1)
CLD (Note 2)
Push registers to stack
Note 1: When using Index X mode flag (T)
Note 2: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
1
IREQ1(address 3C 16), bit5 ?
•Processing as out of range when the count value is 256 or more
0
(A)
TY (address 27 16)
•Count value read
•Count value into Accumulator (A) stored
In range
•Read value with reference value
compared
•Comparison result to flag Fpulse
stored
214 < (A) < 228
Out of range
Fpulse
TY
IREQ1
0
(address 27 16)
(address 3C 16), bit5
Fpulse
256 – 1
0
1
•Counter value initialized
•Timer Y interrupt request bit cleared
Process judgment result
Pop registers
•Pop registers pushed to stack
RTI
Fig. 2.3.20 Control procedure
3886 Group User’s Manual
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APPLICATION
2.3 Timer
(5) Timer application example 4: Measurement of FG pulse width for motor
Outline: The timer X counts the “H” level width of the pulses input to the P5 4 /CNTR 0 pin. An
underflow is detected by the timer X interrupt and an end of the input pulse “H” level is
detected by the CNTR 0 interrupt.
Specifications: •The timer X counts the “H” level width of the FG pulse input to the P54/CNTR 0 pin.
<Example>
When the clock frequency is 4.19 MHz, the count source is 3.8 µs, which is obtained by dividing
the clock frequency by 16. Measurement can be performed to 250 ms in the range of FFFF 16 to
0000 16.
Figure 2.3.21 shows the timers connection and setting of division ratio; Figure 2.3.22 shows the
relevant registers setting; Figure 2.3.23 shows the control procedure.
f(XIN) = 4.19 MHz
Fixed
Prescaler X
Timer X
Timer X interrupt
request bit
1/16
1/256
1/256
0 or 1
250 ms
0 : No interrupt request issued
1 : Interrupt request issued
Fig. 2.3.21 Timers connection and setting of division ratios
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APPLICATION
2.3 Timer
Timer XY mode register (address 23 16)
b7
b0
1 0 1 1
TM
Timer X operating mode: Pulse width measurement mode
CNTR 0 active edge selection: “H” level width measurement
Timer X count: Stop
Clear to “0” when starting count.
Prescaler X (address 24 16)
b7
PREX
b0
255
Timer X (address 25 16)
b7
Set “division ratio – 1”.
b0
255
TX
Interrupt control register 1 (address 3E 16)
b7
ICON1
b0
1
Timer X interrupt: Enabled
Interrupt request register 1 (address 3C 16)
b7
IREQ1
b0
0
Timer X interrupt request
(Set to “1” automatically when Timer X underflows)
Interrupt control register 2 (address 3F 16)
b7
ICON2
b0
1
CNTR0 interrupt: Enabled
Interrupt request register 2 (address 3D 16)
b7
IREQ2
b0
0
CNTR 0 interrupt request
(Set to “1” automatically when “H” level input came to the end)
Fig. 2.3.22 Relevant registers setting
3886 Group User’s Manual
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APPLICATION
2.3 Timer
RESET
l x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SEI
•All interrupts disabled
.....
TM
PREX
TX
IREQ1
ICON1
IREQ2
ICON2
(address 23 16)
(address 24 16)
(address 25 16)
(address 3C 16), bit4
(address 3E 16), bit4
(address 3D 16), bit0
(address 3F16), bit0
256 – 1
256 – 1
0
1
0
1
•Timer X operating mode : Pulse width measurement mode
(Measure “H” level of pulses input from CNTR 0 pin.)
•Set division ratio so that Timer X interrupt will occur at
250 ms intervals.
•Timer X interrupt request bit cleared
•Timer X interrupt enabled
•CNTR0 interrupt request bit cleared
•CNTR0 interrupt enabled
0
•Timer X count start
XXXX10112
.....
TM
(address 23 16), bit3
.....
•Interrupts enabled
CLI
Timer X interrupt process routine
•Error occurs
Process errors
RTI
CNTR0 interrupt process routine
CLT (Note 1)
CLD (Note 2)
Push registers to stack
(A)
Low-order 8-bit result of
pulse width measurement
(A)
High-order 8-bit result of
pulse width measurement
PREX (address 24 16)
TX
(address 25 16)
Pop registers
Note 1: When using Index X mode flag (T)
Note 2: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
PREX
Inverted (A)
•Read the count value and store it to RAM
TX
Inverted (A)
256 – 1
256 – 1
•Division ratio set so that Timer X interrupt will occur at
250 ms intervals.
•Pop registers pushed to stack
RTI
Fig. 2.3.23 Control procedure
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APPLICATION
2.3 Timer
2.3.4 Notes on timer
● If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
● When switching the count source by the timer Y count source selection bit, the value of timer count
is altered in unconsiderable amount owing to generating of a thin pulses in the count input signals.
Therefore, select the timer count source before set the value to the prescaler and the timer.
3886 Group User’s Manual
2-41
APPLICATION
2.4 Serial I/O
2.4 Serial I/O
This paragraph explains the registers setting method and the notes relevant to the Serial I/O.
2.4.1 Memory map
~
~
~
~
001816
Transmit/Receive buffer register (TB/RB)
001916
Serial I/O1 status register (SIO1STS)
001A16
Serial I/O1 control register (SIO1CON)
001B16
UART control register (UARTCON)
001C16
Baud rate generator (BRG)
001D16
Serial I/O2 control register (SIO2CON)
001F16
Serial I/O2 register (SIO2)
~
~
~
~
003916
Interrupt source selection register (INTSEL)
003A16
Interrupt edge selection register (INTEDGE)
003C16
Interrupt request register 1 (IREQ1)
003D16
Interrupt request register 2 (IREQ2)
003E16
Interrupt control register 1 (ICON1)
003F16
Interrupt control register 2 (ICON2)
Fig. 2.4.1 Memory map of registers relevant to Serial I/O
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APPLICATION
2.4 Serial I/O
2.4.2 Relevant registers
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB) [Address : 1816]
B
Name
Function
0 The transmission data is written to or the receive data is read out
from this buffer register.
1 • At writing: A data is written to the transmit buffer register.
• At reading: The contents of the receive buffer register are read
out.
2
At reset
R W
?
?
?
3
?
4
?
5
?
6
?
7
?
Note: The contents of transmit buffer register cannot be read out.
The data cannot be written to the receive buffer register.
Fig. 2.4.2 Structure of Transmit/Receive buffer register
Serial I/O1 status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 status register (SIO1STS) [Address : 1916]
B
Name
0 Transmit buffer empty flag
1
2
3
4
5
6
7
Function
0 : Buffer full
(TBE)
1 : Buffer empty
Receive buffer full flag (RBF) 0 : Buffer empty
1 : Buffer full
0 : Transmit shift in progress
Transmit shift register shift
1 : Transmit shift completed
completion flag (TSC)
0 : No error
Overrun error flag (OE)
1 : Overrun error
Parity error flag (PE)
0 : No error
1 : Parity error
0 : No error
Framing error flag (FE)
1 : Framing error
0 : (OE) U (PE) U (FE) = 0
Summing error flag (SE)
1 : (OE) U (PE) U (FE) = 1
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “1”.
At reset
R W
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
1
✕
Fig. 2.4.3 Structure of Serial I/O status register
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APPLICATION
2.4 Serial I/O
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register (SIO1CON) [Address : 1A16]
B
Name
Function
At reset
0 BRG count source
selection bit (CSS)
1 Serial I/O1 synchronous
clock selection bit (SCS)
0 : f(XIN) (f(XCIN) in Low Speed Mode)
1 : f(XIN)/4 (f(XCIN)/4 in Low Speed Mode)
• In clock synchronous serial I/O
0 : BRG output divided by 4
1 : External clock input
• In UART
0 : BRG output divided by 16
1 : External clock input divided by 16
0
2 SRDY1 output enable bit
0 : P47 pin operates as ordinary I/O pin
1 : P47 pin operates as SRDY1 output pin
0
0 : Interrupt when transmit buffer has emptied
1 : Interrupt when transmit shift operation is
completed
0 : Transmit disabled
1 : Transmit enabled
0 : Receive disabled
1 : Receive enabled
0 : Clock asynchronous(UART) serial I/O
1 : Clock synchronous serial I/O
0
0 : Serial I/O1 disabled
(pins P44 to P47 operate as ordinary I/O pins)
1 : Serial I/O1 enabled
(pins P44 to P47 operate as serial I/O pins)
0
(SRDY)
3 Transmit interrupt
source selection bit (TIC)
4 Transmit enable bit (TE)
5 Receive enable bit (RE)
6 Serial I/O1 mode selection bit
(SIOM)
7 Serial I/O1 enable bit
(SIOE)
R W
0
0
0
0
Fig. 2.4.4 Structure of Serial I/O1 control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register (UARTCON) [Address : 1B16]
Name
B
C
h
a
r
a
c
t
e
r
l
e
ngth selection bit
0
1
2
3
4
5
At reset
R W
0
0
0
0
0
1
✕
6
1
✕
7
1
✕
Fig. 2.4.5 Structure of UART control register
2-44
Function
0 : 8 bits
(CHAS)
1 : 7 bits
Parity enable bit
0 : Parity checking disabled
(PARE)
1 : Parity checking enabled
Parity selection bit
0 : Even parity
(PARS)
1 : Odd parity
0 : 1 stop bit
Stop bit length selection bit
1 : 2 stop bits
(STPS)
P45/TxD P-channel output
In output mode
disable bit (POFF)
0 : CMOS output
1 : N-channel open-drain output
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “1”.
3886 Group User’s Manual
APPLICATION
2.4 Serial I/O
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator (BRG) [Address : 1C16]
B
Function
0 Set a count value of baud rate generator.
At reset
R W
?
1
?
2
?
3
?
4
?
5
?
6
?
7
?
Fig. 2.4.6 Structure of Baud rate generator
Serial I/O2 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register (SIO2CON) [Address : 1D16 ]
B
0
Name
Internal synchronous clock
selection bits
1
2
3
4
5
6
7
Function
b2 b1 b0
0 0 0: f(XIN)/8
0 0 1: f(XIN)/16
0 1 0: f(XIN)/32
0 1 1: f(XIN)/64
1 1 0: f(XIN)/128
1 1 1: f(XIN)/256
0: I/O port (P71, P72)
1: SOUT2,SCLK2 signal output
SRDY2 output enable bit
0: I/O port (P73)
1: SRDY2 signal output
Transfer direction selection bit 0: LSB first
1: MSB first
Serial I/O2 synchronous clock 0: External clock
selection bit
1: Internal clock
Comparator reference input
0: P00/P3REF input
selection bit
1: Reference input fixed
Serial I/O2 port selection bit
At reset
R W
0
0
0
0
0
0
Fig. 2.4.7 Structure of Serial I/O2 control register
3886 Group User’s Manual
2-45
APPLICATION
2.4 Serial I/O
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 register (SIO2) [Address : 1F16]
B
Name
Function
0 •Serial I/O2 register is the shift register for serial transfer.
At reset
R W
?
•At transmit: transmit data is set.
1 •At receive: receive data is set.
?
2
?
3
?
4
?
5
?
6
?
7
?
Fig. 2.4.8 Structure of Serial I/O2 register
Interrupt source selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt source selection register [INTSEL: address 003916]
B
Name
Function
0 INT0/input buffer full interrupt 0 : INT0 interrupt
source selection bit
1 : Input buffer full interrupt
0 : INT1 interrupt
1 INT1/output buffer empty
interrupt source selection bit 1 : Output buffer empty interrupt
0 : Serial I/O1 transmit interrupt ✽1
2 Serial I/O1 transmit/SCL,SDA
interrupt source selection bit 1 : SCL,SDA interrupt
✽1
0 : CNTR0 interrupt
3 CNTR0/SCL,SDA interrupt
source selection bit
1 : SCL,SDA interrupt
✽2
0 : Serial I/O2 interrupt
4 Serial I/O2/I2C interrupt
source selection bit
1 : I2C interrupt
✽2
0 : INT2 interrupt
5 INT2/I2C interrupt source
selection bit
1 : I2C interrupt
✽3
0 : CNTR1 interrupt
6 CNTR1/key-on wake-up
interrupt source selection bit 1 : Key-on wake-up interrupt
✽3
7 AD converter/key-on wake-up 0 : A-D converter interrupt
interrupt source selection bit 1 : Key-on wake-up interrupt
✽1: Do not write “1” to these bits simultaneously.
✽2: Do not write “1” to these bits simultaneously.
✽3: Do not write “1” to these bits simultaneously.
Fig. 2.4.9 Structure of Interrupt source selection register
2-46
3886 Group User’s Manual
At reset
0
0
0
0
0
0
0
0
R W
APPLICATION
2.4 Serial I/O
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A16]
B
0
1
2
3
4
5
6
Name
Function
INT0 interrupt edge
0 : Falling edge active
selection bit
1 : Rising edge active
0 : Falling edge active
INT1 interrupt edge
1 : Rising edge active
selection bit
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
0 : Falling edge active
INT2 interrupt edge
1 : Rising edge active
selection bit
0 : Falling edge active
INT3 interrupt edge
1 : Rising edge active
selection bit
0 : Falling edge active
INT4 interrupt edge
1 : Rising edge active
selection bit
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
7
At reset
R W
0
0
0
✕
0
0
0
0
✕
0
✕
Fig. 2.4.10 Structure of Interrupt edge selection register
3886 Group User’s Manual
2-47
APPLICATION
2.4 Serial I/O
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address : 3C16]
B
Name
0 INT0/input buffer full interrupt
request bit
1 INT1/output buffer empty
interrupt request bit
2 Serial I/O1 receive interrupt
request bit
3 Serial I/O1 transmit/SCL, SDA
interrupt request bit
4 Timer X interrupt request bit
5 Timer Y interrupt request bit
6 Timer 1 interrupt request bit
7 Timer 2 interrupt request bit
Function
At reset
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
R W
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.4.11 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2) [Address : 3D16]
B
Name
Function
At reset
0
✽
0
✽
0
✽
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
6 AD converter/key-on wake-up 0 : No interrupt request issued
interrupt request bit
1 : Interrupt request issued
7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
0
✽
0
✽
0
✕
request bit
1 CNTR1/key-on wake-up
interrupt request bit
2 Serial I/O2/I2C interrupt
request bit
3 INT2/I2C interrupt request bit
4 INT3 interrupt request bit
5 INT4 interrupt request bit
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.4.12 Structure of Interrupt request register 2
2-48
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 CNTR0/SCL, SDA interrupt
3886 Group User’s Manual
APPLICATION
2.4 Serial I/O
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E16]
B
Name
0 INT0/input buffer full interrupt
enable bit
1 INT1/output buffer empty
interrupt enable bit
2 Serial I/O1 receive interrupt
enable bit
3 Serial I/O1 transmit/SCL, SDA
interrupt enable bit
4 Timer X interrupt enable bit
5 Timer Y interrupt enable bit
6 Timer 1 interrupt enable bit
7 Timer 2 interrupt enable bit
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset
R W
0
0
0
0
0
0
0
0
Fig. 2.4.13 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2 (ICON2) [Address : 3F16]
B
Name
0 CNTR0/SCL, SDA interrupt
enable bit
1 CNTR1/key-on wake-up
interrupt enable bit
Serial
I/O2/I2C interrupt enable
2
bit
3 INT2/I2C interrupt enable bit
4 INT3 interrupt enable bit
5 INT4 interrupt enable bit
6 AD converter/key-on wake-up
interrupt enable bit
7 Fix this bit to “0”.
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset
R W
0
0
0
0
0
0
0
0
Fig. 2.4.14 Structure of Interrupt control register 2
3886 Group User’s Manual
2-49
APPLICATION
2.4 Serial I/O
2.4.3 Serial I/O connection examples
(1) Control of peripheral IC equipped with CS pin
Figure 2.4.15 shows connection examples of a peripheral IC equipped with the CS pin.
There are connection examples using a clock synchronous serial I/O mode.
(1) Only transmission
(Using the RXD pin as an I/O port)
Port
CS
SCLK
CLK
TX D
DATA
3886 group
Peripheral IC
(OSD controller etc.)
(3) Transmission and reception
(When connecting RXD with TXD)
(When connecting IN with OUT in
peripheral IC)
3886
✽1:
✽2:
(2) Transmission and reception
CS
CLK
TX D
RX D
IN
3886 group
OUT
Peripheral IC
(E 2 PROM etc.)
(4) Connection of plural IC
Port
CS
Port
CS
SCLK
CLK
SCLK
CLK
TX D
RX D
IN
TX D
IN
RX D
Port
OUT
group ✽1
OUT
IC✽2
Peripheral
(E2 PROM etc.)
Peripheral IC 1
3886 group
Select an N-channel open-drain output for TXD pin output control.
Use the OUT pin of peripheral IC which is an N-channel opendrain output and becomes high impedance during receiving data.
Notes 1: “Port” means an output port controlled by software.
2: When serial I/O2 is used, SOUT and SIN are used,
not TxD and RxD.
Fig. 2.4.15 Serial I/O connection examples (1)
2-50
Port
SCLK
3886 Group User’s Manual
CS
CLK
IN
OUT
Peripheral IC 2
APPLICATION
2.4 Serial I/O
(2) Connection with microcomputer
Figure 2.4.16 shows connection examples with another microcomputer.
(1) Selecting internal clock
SCLK
CLK
TX D
RX D
3886 group
(2) Selecting external clock
SCLK
CLK
IN
TX D
IN
OUT
RX D
OUT
Microcomputer
(3) Using SRDY signal output function
(Selecting an external clock)
3886 group
Microcomputer
(4) In UART ✽
SRDY
RDY
SCLK
CLK
TX D
RX D
TX D
IN
RX D
TX D
RX D
OUT
3886 group
3886 group
Microcomputer
Microcomputer
✽. When serial I/O2 is used, UART cannot be used.
Note: When serial I/O2 is used, SOUT and SIN are used, not TxD and RxD.
Fig. 2.4.16 Serial I/O connection examples (2)
3886 Group User’s Manual
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APPLICATION
2.4 Serial I/O
2.4.4 Setting of serial I/O transfer data format
A clock synchronous or clock asynchronous (UART) can be selected as a data format of Serial I/O1.
A clock synchronous is used as a data format of Serial I/O2.
Figure 2.4.17 shows the serial I/O transfer data format.
1ST-8DATA-1SP
ST
LSB
MSB
SP
1ST-7DATA-1SP
ST
LSB
MSB
SP
1ST-8DATA-1PAR-1SP
ST
LSB
MSB
PAR
PAR
SP
MSB
2SP
SP
1ST-7DATA-1PAR-1SP
ST
UART
LSB
MSB
1ST-8DATA-2SP
ST
LSB
1ST-7DATA-2SP
ST
Serial I/O1
LSB
MSB
2SP
1ST-8DATA-1PAR-2SP
ST
LSB
MSB
PAR
PAR
2SP
1ST-7DATA-1PAR-2SP
ST
Clock synchronous
Serial I/O
LSB
LSB first
LSB first
Serial I/O2
Clock synchronous
Serial I/O
MSB first
Fig. 2.4.17 Serial I/O transfer data format
2-52
MSB
3886 Group User’s Manual
ST : Start bit
SP : Stop bit
PAR : Parity bit
2SP
APPLICATION
2.4 Serial I/O
2.4.5 Serial I/O application examples
(1) Communication using clock synchronous serial I/O (transmit/receive)
Outline : 2-byte data is transmitted and received, using the clock synchronous serial I/O.
The SRDY1 signal is used for communication control.
Figure 2.4.18 shows a connection diagram, and Figure 2.4.19 shows a timing chart.
Figure 2.4.20 shows a registers setting relevant to the transmitting side, and Figure 2.4.21 shows
registers setting relevant to the receiving side.
Transmitting side
Receiving side
P42/INT0
SRDY1
SCLK1
SCLK1
TX D
RX D
3886 group
3886 group
Fig. 2.4.18 Connection diagram
Specifications : •
•
•
•
The Serial I/O1 is used (clock synchronous serial I/O is selected.)
Synchronous clock frequency : 125 kHz (f(X IN) = 4 MHz is divided by 32)
The SRDY1 (receivable signal) is used.
The receiving side outputs the SRDY1 signal at intervals of 2 ms (generated by timer),
and 2-byte data is transferred from the transmitting side to the receiving side.
SRDY1
••••
SCLK1
••••
TX D
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1
••••
2 ms
Fig. 2.4.19 Timing chart
3886 Group User’s Manual
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APPLICATION
2.4 Serial I/O
Transmitting side
Serial I/O1 status register (Address : 1916)
b7
b0
SIO1STS
Transmit buffer empty flag
• Confirm that the data has been transferred from Transmit buffer
register to Transmit shift register.
• When this flag is “1”, it is possible to write the next transmission
data in to Transmit buffer register.
Transmit shift register shift completion flag
Confirm completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Serial I/O1 control register (Address : 1A16)
b7
SIO1CON
b0
1 1 0 1
0 0
BRG counter source selection bit : f(XIN)
Serial I/O1 synchronous clock selection bit : BRG/4
Transmit enable bit : Transmit enabled
Receive enable bit : Receive disabled
Serial I/O1 mode selection bit : Clock synchronous serial I/O
Serial I/O1 enable bit : Serial I/O1 enabled
Baud rate generator (Address : 1C16)
b7
BRG
b0
Set “division ratio – 1”.
7
Interrupt edge selection register (Address : 3A16)
b7
INTEDGE
b0
0
INT0 interrupt edge selection bit : Falling edge active
Fig. 2.4.20 Registers setting relevant to transmitting side
2-54
3886 Group User’s Manual
APPLICATION
2.4 Serial I/O
Receiving side
Serial I/O1 status register (Address : 1916)
b7
b0
SIO1STS
Receive buffer full flag
Confirm completion of receiving 1-byte data with this flag.
“1” : At completing reception
“0” : At reading out contents of Receive buffer register
Overrun error flag
“1” : When data is ready in Receive shift register while Receive buffer
register contains the data.
Parity error flag
“1” : When a parity error occurs in enabled parity.
Framing error flag
“1” : When stop bits cannot be detected at the specified timing.
Summing error flag
“1” : when any one of the following errors occurs.
• Overrun error
• Parity error
• Framing error
Serial I/O1 control register (Address : 1A16)
b7
SIO1CON 1 1 1 1
b0
1 1
Serial I/O1 synchronous clock selection bit : External clock
SRDY1 output enable bit : SRDY1 output enabled
Transmit enable bit : Transmit enabled
Set this bit to “1”, using SRDY1 output.
Receive enable bit : Receive enabled
Serial I/O1 mode selection bit : Clock synchronous serial I/O
Serial I/O1 enable bit : Serial I/O1 enabled
Fig. 2.4.21 Registers setting relevant to receiving side
3886 Group User’s Manual
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APPLICATION
2.4 Serial I/O
Figure 2.4.22 shows a control procedure of the transmitting side, and Figure 2.4.23 shows a control
procedure of the receiving side.
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
.....
SIO1CON (Address : 1A16)
1101xx002
(Address : 1C16)
8–1
BRG
0
INTEDGE (Address : 3A16), bit0
0
IREQ1 (Address:3C16), bit0?
• Detection of INT0 falling edge
1
IREQ1 (Address : 3C16), bit0
TB/RB (Address : 1816)
0
The first byte of a
transmission data
SIO1STS (Address : 1916), bit0?
0
1
TB/RB (Address : 1816)
The second byte of a
transmission data
SIO1STS (Address : 1916), bit0?
0
1
SIO1STS (Address : 1916), bit2?
0
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
• Judgment of transferring from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
• Judgment of transferring from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
• Judgment of shift completion of Transmit shift register
(Transmit shift register shift completion flag)
1
Fig. 2.4.22 Control procedure of transmitting side
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3886 Group User’s Manual
APPLICATION
2.4 Serial I/O
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
.....
SIO1CON (Address : 1A16)
1111x11x2
N
Pass 2 ms?
• An interval of 2 ms generated by Timer
Y
TB/RB (Address : 1816)
Dummy data
• SRDY1 output
SRDY1 signal is output by writing data to the TB/RB.
Using the SRDY1, set Transmit enable bit
(bit4) of the SIO1CON to “1.”
0
SIO1STS (Address : 1916), bit1?
• Judgment of completion of receiving
(Receive buffer full flag)
1
• Reception of the first byte data
Receive buffer full flag is set to “0” by reading data.
Read out reception data from
TB/RB (Address : 1816)
0
SIO1STS (Address : 1916), bit1?
• Judgment of completion of receiving
(Receive buffer full flag)
1
Read out reception data from
TB/RB (Address : 1816)
• Reception of the second byte data.
Receive buffer full flag is set to “0” by reading data.
Fig. 2.4.23 Control procedure of receiving side
3886 Group User’s Manual
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APPLICATION
2.4 Serial I/O
(2) Output of serial data (control of peripheral IC)
Outline : 4-byte data is transmitted and received, using the clock synchronous serial I/O.
The CS signal is output to a peripheral IC through port P53.
The example for using Serial I/O1 and the example using for Serial I/O2 are shown. The specification
of these examples are the same.
Figure 2.4.24 shows a connection diagram, and Figure 2.4.25 shows a timing chart.
P53
SCLK1
TXD
CS
CLK
DATA
3886 group
P53
CS
CLK
SCLK2
DATA
SOUT2
Peripheral IC
CS
CLK
DATA
3886 group
(1) Example for using Serial I/O1
CS
CLK
DATA
Peripheral IC
(2) Example for using Serial I/O2
Fig. 2.4.24 Connection diagram
Specifications : • The Serial I/O is used (clock synchronous serial I/O is selected.)
• Synchronous clock frequency : 125 kHz (f(X IN) = 4 MHz is divided by 32)
• Transfer direction : LSB first
• The Serial I/O interrupt is not used.
• Port P53 is connected to the CS pin (“L” active) of the peripheral IC for transmission
control; the output level of port P5 3 is controlled by software.
CS
CLK
DATA
DO0
DO1
DO2
DO3
Note: When serial I/O2 is used, SOUT2 pin is in the high-impedance state
after the transfer is completed.
Fig. 2.4.25 Timing chart
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3886 Group User’s Manual
APPLICATION
2.4 Serial I/O
Figure 2.4.26 shows registers setting relevant to Serial I/O1, and Figure 2.4.27 shows a setting of
serial I/O1 transmission data.
Serial I/O1 control register (Address : 1A16)
b7
SIO1CON
b0
1 1 0 1 1 0 0 0
BRG count source selection bit : f(XIN)
Serial I/O1 synchronous clock selection bit : BRG/4
SRDY1 output en able bit : SRDY1 output disabled
Transmit interrupt source selection bit : Transmit shift operating
completion
Transmit enable bit : Transmit enabled
Receive enable bit : Receive disabled
Serial I/O1 mode selection bit : Clock synchronous serial I/O
Serial I/O1 enable bit : Serial I/O1 enabled
UART control register (Address : 1B16)
b7
b0
0
UARTCON
P45/TXD P-channel output disable bit : CMOS output
Baud rate generator (Address : 1C16)
b7
b0
7
B RG
Set “division ratio – 1”.
Interrupt control register 1 (Address : 3E16)
b7
ICON1
b0
0
Serial I/O1 transmit interrupt enable bit : Interrupt disabled
Interrupt request register 1 (Address : 3C16)
b7
IREQ1
b0
0
Serial I/O1 transmit interrupt request bit
Confirm completion of transmitting
1-byte data by one unit.
“1” : Transmit shift completion
Fig. 2.4.26 Registers setting relevant to Serial I/O1
Transmit/Receive buffer register (Address : 1816)
b7
TB/RB
b0
Set a transmission data.
Confirm that transmission of the previous data is
completed (bit 3 of the Interrupt request register 1
is “1”) before writing data.
Fig. 2.4.27 Setting of serial I/O1 transmission data
3886 Group User’s Manual
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APPLICATION
2.4 Serial I/O
When the registers are set as shown in Fig. 2.4.26, the Serial I/O1 can transmit 1-byte data by writing
data to the transmit buffer register.
Thus, after setting the CS signal to “L”, write the transmission data to the transmit buffer register by
each 1 byte, and return the CS signal to “H” when the target number of bytes has been transmitted.
Figure 2.4.28 shows a control procedure of Serial I/O1.
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
....
SIO1CON (Address : 1A16) 110110002
0
UARTCON (Address : 1B16), bit4
8–1
(Address : 1C16)
BRG
0
(Address : 3E16), bit3
ICON1
1
(Address : 0A16), bit3
P5
(Address : 0B16) xxxx1xxx2
P5D
•Serial I/O1 set
•Serial I/O1 transmit interrupt : Disabled
....
•CS signal output port set
(“H” level output)
P5 (Address : 0A16), bit3
IREQ1 (Address : 3C16), bit3
TB/RB (Address : 1816)
•CS signal output level to “L” set
0
•Serial I/O1 transmit interrupt
request bit set to “0”
0
•Transmission
data write
(Start of transmit 1-byte data)
a transmission
data
IREQ1 (Address : 3C16), bit3?
0
•Judgment of completion of transmitting
1-byte data
1
N
Complete to transmit data?
Y
P5 (Address : 0A16), bit3
1
•Use any of RAM area as a counter for
counting the number of transmitted bytes
•Judgment of completion of transmitting
the target number of bytes
•Return the CS signal output level to “H”
when transmission of the target number
of bytes is completed
Fig. 2.4.28 Control procedure of Serial I/O1
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3886 Group User’s Manual
APPLICATION
2.4 Serial I/O
Figure 2.4.29 shows registers setting relevant to Serial I/O2, and Figure 2.4.30 shows a setting of
serial I/O2 transmission data.
Serial I/O2 control register (Address : 1D16)
b7
SIO2CON
b0
X 1 0 0 1 0 1 0
Internal synchronous clock selection bits: f(XIN)/32
Serial I/O2 port selection bit: Serial I/O2 used
SRDY2 output enable bit: SRDY2 output not used
Transfer direction selection bit: LSB first
Serial I/O2 synchronous clock selection bit: Internal clock
Interrupt control register 2 (Address : 3F16)
b7
ICON2
b0
0
Serial I/O2 transmit interrupt enable bit : Interrupt disabled
Interrupt request register 2 (Address : 3D16)
b7
IREQ2
b0
0
Serial I/O2 transmit interrupt request bit
Confirm completion of transmitting
1-byte data by one unit.
“1” : Transmit shift completion
Fig. 2.4.29 Registers setting relevant to Serial I/O2
Serial I/O2 register (Address : 1F16)
b7
SIO2
b0
Set a transmission data.
Confirm that transmission of the previous data is
completed (bit 2 of the Interrupt request register 2
is “1”) before writing data.
Fig. 2.4.30 Setting of serial I/O2 transmission data
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APPLICATION
2.4 Serial I/O
When the registers are set as shown in Fig. 2.4.29, the Serial I/O2 can transmit 1-byte data by writing
data to the serial I/O2 register.
Thus, after setting the CS signal to “L”, write the transmission data to Serial I/O2 by each 1 byte, and
return the CS signal to “H” when the target number of bytes has been transmitted.
Figure 2.4.31 shows a control procedure of Serial I/O2.
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
....
SIO2CON
ICON2
P5
P5D
•Serial I/O2 control register set
(Address : 1D16) 010010102
(Address : 3F16), bit2
0
(Address : 0A16), bit3
1
(Address : 0B16) xxxx1xxx2
....
•Serial I/O2 transmit interrupt : Disabled
•CS signal output port set
(“H” level output)
P5 (Address : 0A16), bit3
0
IREQ2 (Address : 3D16), bit2
SIO2 (Address : 1F16)
•CS signal output level to “L” set
0
•Serial I/O2 interrupt request bit set to “0”
•Transmission
data write
(Start of transmit 1-byte data)
a transmission
data
IREQ2 (Address : 3D16), bit2?
0
•Judgment of completion of transmitting 1byte data
1
N
Complete to transmit data?
•Use any of RAM area as a counter for
counting the number of transmitted bytes
•Judgment of completion of transmitting
the target number of bytes
Y
P5 (Address : 0A16), bit3
1
•Return the CS signal output level to “H”
when transmission of the target number
of bytes is completed
Fig. 2.4.31 Control procedure of Serial I/O2
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APPLICATION
2.4 Serial I/O
(3) Cyclic transmission or reception of block data (data of specified number of bytes) between
two microcomputers
Outline : When the clock synchronous serial I/O is used for communication, synchronization of the
clock and the data between the transmitting and receiving sides may be lost because of
noise included in the synchronous clock. It is necessary to correct that constantly, using
“heading adjustment”.
This “heading adjustment” is carried out by using the interval between blocks in this
example.
Figure 2.4.32 shows a connection diagram.
SCLK
SCLK
RXD
TXD
TXD
RXD
Master unit
Slave unit
Note: When serial I/O2 is used, SOUT and SIN are used, not TxD and RxD.
Fig. 2.4.32 Connection diagram
Specifications :
•
•
•
•
•
•
•
•
The serial I/O is used (clock synchronous serial I/O is selected).
Synchronous clock frequency : 131 kHz (f(X IN) = 4.19 MHz is divided by 32)
Byte cycle: 488 µs
Number of bytes for transmission or reception : 8 byte/block
Block transfer cycle : 16 ms
Block transfer term : 3.5 ms
Interval between blocks : 12.5 ms
Heading adjustment time : 8 ms
Limitations of specifications :
• Reading of the reception data and setting of the next transmission data must be
completed within the time obtained from “byte cycle – time for transferring 1-byte
data” (in this example, the time taken from generating of the serial I/O1 receive
interrupt request to input of the next synchronous clock is 431 µs).
• “Heading adjustment time < interval between blocks” must be satisfied.
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APPLICATION
2.4 Serial I/O
The communication is performed according to the timing shown in Figure 2.4.33. In the slave unit,
when a synchronous clock is not input within a certain time (heading adjustment time), the next clock
input is processed as the beginning (heading) of a block.
When a clock is input again after one block (8 byte) is received, the clock is ignored.
Figure 2.4.34 shows relevant registers setting.
D0
D1
D2
D7
D0
Byte cycle
Block transfer term
Interval between blocks
Block transfer cycle
Heading adjustment time
Processing for heading adjustment
Fig. 2.4.33 Timing chart
Master unit
Slave unit
Serial I/O1 control register (Address : 1A16)
b7
b0
Serial I/O1 control register (Address : 1A16)
b7
b0
SIO1CON 1 1 1 1 1 0 0 0
SIO1CON 1 1 1 1
0 1
BRG count source : f(XIN)
Synchronous clock : BRG/4
SRDY1 output disabled
Not affected by external clock
Synchronous clock : External clock
Transmit interrupt source :
Transmit shift operating completion
Transmit enabled
Receive enabled
Not use the serial I/O1 transmit interrupt
SRDY1 output disabled
Transmit enabled
Receive enabled
Clock synchronous serial I/O
Clock synchronous serial I/O
Serial I/O1 enabled
Serial I/O1 enabled
Both of units
UART control register (Address : 1B16)
b7
b0
0
UARTCON
P45/TXD pin : CMOS output
Baud rate generator (Address : 1C16)
b7
b0
BRG
7
Set “division ratio – 1”.
Fig. 2.4.34 Relevant registers setting
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APPLICATION
2.4 Serial I/O
Control procedure :
● Control in the master unit
After setting the relevant registers shown in Figure 2.4.34, the master unit starts transmission or
reception of 1-byte data by writing transmission data to the transmit buffer register.
To perform the communication in the timing shown in Figure 2.4.33, take the timing into account
and write transmission data. Additionally, read out the reception data when the serial I/O1 transmit
interrupt request bit is set to “1,” or before the next transmission data is written to the transmit
buffer register.
Figure 2.4.35 shows a control procedure of the master unit using timer interrupts.
Interrupt processing routine
executed every 488 µs
CLT (Note 1)
CLD (Note 2)
Push register to stack
Within a block
transfer term?
Note 1: When using the Index X mode flag (T).
Note 2: When using the Decimal mode flag (D).
•Push the register used in the interrupt
processing routine into the stack
N
•Generation of a certain block interval
by using a timer or other functions
Y
Complete to transfer
a block?
Y
Start a block transfer?
Pop registers
N
Y
N
Write a transmission data
•Check the block interval counter and
determine to start a block transfer
Count a block interval counter
Read a reception data
Write the first transmission data
(first byte) in a block
•Pop registers which is pushed to stack
R TI
Fig. 2.4.35 Control procedure of master unit
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2.4 Serial I/O
● Control in the slave unit
After setting the relevant registers as shown in Figure 2.4.34, the slave unit becomes the state
where a synchronous clock can be received at any time, and the serial I/O1 receive interrupt
request bit is set to “1” each time an 8-bit synchronous clock is received.
In the serial I/O1 receive interrupt processing routine, the data to be transmitted next is written to
the transmit buffer register after the received data is read out.
However, if no serial I/O1 receive interrupt occurs for a certain time (heading adjustment time or
more), the following processing will be performed.
1. The first 1-byte data of the transmission data in the block is written into the transmit buffer register.
2. The data to be received next is processed as the first 1 byte of the received data in the block.
Figure 2.4.36 shows a control procedure of the slave unit using the serial I/O1 receive interrupt
and any timer interrupt (for heading adjustment).
Timer interrupt processing
routine
Serial I/O1 receive interrupt
processing routine
CLT (Note 1)
CLD (Note 2)
Push register to stack
Within a block
transfer term?
N
CLT (Note 1)
•Push the register used in the
CLD (Note 2)
interrupt processing routine into
Push register to stack
the stack
•Confirmation of the received
byte counter to judge the
block transfer term
Heading adjustment counter – 1
Y
Read a reception data
Heading adjustment
counter = 0?
A received byte counter +1
Write the first transmission
data (first byte) in a block
•Push the register used in
the interrupt processing
routine into the stack
N
Y
A received byte
counter ≥ 8?
A received byte counter
Y
0
N
Pop registers
Write a transmission data
Write dummy data (FF16)
•Pop registers which is
pushed to stack
R TI
Initial
value
(Note 3)
Heading
adjustment
counter
Pop registers
R TI
•Pop registers which is pushed to stack
Notes 1: When using the Index X mode flag (T).
2: When using the Decimal mode flag (D).
3: In this example, set the value which is equal to the
heading adjustment time divided by the timer interrupt
cycle as the initial value of the heading adjustment
counter.
For example: When the heading adjustment time is 8 ms
and the timer interrupt cycle is 1 ms, set 8
as the initial value.
Fig. 2.4.36 Control procedure of slave unit
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APPLICATION
2.4 Serial I/O
(4) Communication (transmit/receive) using asynchronous serial I/O (UART)
Outline : 2-byte data is transmitted and received, using the asynchronous serial I/O.
Port P4 0 is used for communication control.
Figure 2.4.37 shows a connection diagram, and Figure 2.4.38 shows a timing chart.
Transmitting side
Receiving side
P40
P40
T XD
RXD
3886 group
3886 group
Fig. 2.4.37 Connection diagram (Communication using UART)
Specifications : • The Serial I/O1 is used (UART is selected).
• Transfer bit rate : 9600 bps (f(X IN) = 4.9152 MHz is divided by 512)
• Communication control using port P4 0
(The output level of port P4 0 is controlled by software.)
• 2-byte data is transferred from the transmitting side to the receiving side at intervals
of 10 ms generated by the timer.
ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2) ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2)
~
~
TXD
.....
~
~
P40
.
ST D0
.....
.
10 ms
Fig. 2.4.38 Timing chart (using UART)
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APPLICATION
2.4 Serial I/O
Table 2.4.1 shows setting examples of the baud rate generator (BRG) values and transfer bit rate
values; Figure 2.4.39 shows registers setting relevant to the transmitting side; Figure 2.4.40 shows
registers setting relevant to the receiving side.
Table 2.4.1 Setting examples of Baud rate generator values and transfer bit rate values
BRG count source
(Note 1)
BRG setting value
Transfer bit rate (bps) (Note 2)
at f(X IN) = 4.9152 MH Z
at f(X IN ) = 8 MH Z
f(XIN)/4
255(FF 16)
300
488.28125
f(XIN)/4
127(7F 16)
600
976.5625
f(XIN)/4
63(3F16)
1200
1953.125
f(XIN)/4
31(1F16)
2400
3906.25
f(XIN)/4
15(0F16)
4800
7812.5
f(XIN)/4
7(07 16)
9600
15625
f(XIN)/4
3(03 16)
19200
31250
f(XIN)/4
1(01 16)
38400
62500
f(XIN)
3(03 16)
76800
125000
f(XIN)
1(01 16)
153600
250000
f(XIN)
0(00 16)
307200
500000
Notes 1: Select the BRG count source with bit 0 of the serial I/O1 control register (Address : 1A 16 ).
2: Equation of transfer bit rate:
Transfer bit rate (bps) =
f(XIN)
(BRG setting value + 1) ✕ 16 ✕ m✽
✽m: When bit 0 of the serial I/O1 control register (Address : 1A16 ) is set to “0,” a value of m
is 1.
When bit 0 of the serial I/O1 control register (Address : 1A 16 ) is set to “1,” a value of m
is 4.
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APPLICATION
2.4 Serial I/O
Transmitting side
Serial I/O1 status register (Address : 1916)
b7
b0
SIO1STS
Transmit buffer empty flag
• Confirm that the data has been transferred from Transmit buffer
register to Transmit shift register.
• When this flag is “1”, it is possible to write the next transmission
data in to Transmit buffer register.
Transmit shift register shift completion flag
Confirm completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Serial I/O1 control register (Address : 1A16)
b7
b0
SIO1CON 1 0 0 1
0 0 1
BRG count source selection bit : f(XIN)/4
Serial I/O1 synchronous clock selection bit : BRG/16
SRDY1 output enable bit :SRDY1 out disabled
Transmit enable bit : Transmit enabled
Receive enable bit : Receive disabled
Serial I/O1 mode selection bit : Asynchronous serial I/O(UART)
Serial I/O1 enable bit : Serial I/O1 enabled
UART control register (Address : 1B16)
b7
UARTCON
b0
0 1
0 0
Character length selection bit : 8 bits
Parity enable bit : Parity checking disabled
Stop bit length selection bit : 2 stop bits
P45/TXD P-channel output disable bit : CMOS output
Baud rate generator (Address : 1C16)
b7
B RG
b0
7
Set
f(XIN)
Transfer bit rate ✕ 16 ✕ m
✽
–1
✽ When bit 0 of the Serial I/O1 control register (Address : 1A16) is set to “0,”
a value of m is 1.
When bit 0 of the Serial I/O1 control register (Address : 1A16) is set to “1,”
a value of m is 4.
Fig. 2.4.39 Registers setting relevant to transmitting side
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APPLICATION
2.4 Serial I/O
Receiving side
Serial I/O1 status register (Address : 1916)
b7
b0
SIO1STS
Receive buffer full flag
Confirm completion of receiving 1-byte data with this flag.
“1” : At completing reception
“0” : At reading out contents of Receive buffer register
Overrun error flag
“1” : When data is ready in Receive shift register while Receive buffer
register contains the data.
Parity error flag
“1” : When a parity error occurs in enabled parity.
Framing error flag
“1” : When stop bits cannot be detected at the specified timing.
Summing error flag
“1” : When any one of the following errors occurs.
• Overrun error
• Parity error
• Framing error
Serial I/O1 control register (Address : 1A16)
b7
SIO1CON
b0
1 0 1 0
0 0 1
BRG count source selection bit : f(XIN)/4
Serial I/O1 synchronous clock selection bit : BRG/16
SRDY1 output enable bit : SRDY1 out disabled
Transmit enable bit : Transmit disabled
Receive enable bit : Receive enabled
Serial I/O1 mode selection bit : Asynchronous serial I/O(UART)
Serial I/O1 enable bit : Serial I/O1 enabled
UART control register (Address : 1B16)
b7
b0
UARTCON
1
0 0
Character length selection bit : 8 bits
Parity enable bit : Parity checking disabled
Stop bit length selection bit : 2 stop bits
Baud rate generator (Address : 1C16)
b7
B RG
b0
7
f(XIN)
–1
Transfer bit rate ✕ 16 ✕ m ✽
✽ When bit 0 of the Serial I/O1 control register (Address : 1A16) is set to “0,”
a value of m is 1.
When bit 0 of the Serial I/O1 control register (Address : 1A16) is set to “1,”
a value of m is 4.
Set
Fig. 2.4.40 Registers setting relevant to receiving side
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APPLICATION
2.4 Serial I/O
Figure 2.4.41 shows a control procedure of the transmitting side, and Figure 2.4.42 shows a control
procedure of the receiving side.
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
.....
1001x0012
SIO1CON (Address : 1A16)
000010002
UARTCON (Address : 1B16)
8–1
(Address : 1C16)
BRG
(Address : 0816), bit0
0
P4
(Address : 0916)
P4D
xxxxxxx12
• Port P40 set for communication control
N
Pass 10 ms?
• An interval of 10 ms generated by Timer
Y
P4 (Address : 0816), bit0
TB/RB (Address : 1816)
• Communication start
1
The first byte of a
transmission data
0
SIO1STS (Address : 1916), bit0?
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
• Judgment of transferring data from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
1
TB/RB (Address : 1816)
The second byte of
a transmission data
SIO1STS (Address : 1916), bit0?
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
0
• Judgment of transferring data from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
0
• Judgment of shift completion of Transmit shift register
(Transmit shift register shift completion flag)
1
SIO1STS (Address : 1916), bit2?
1
P4 (Address : 0816), bit0
0
• Communication completion
Fig. 2.4.41 Control procedure of transmitting side
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APPLICATION
2.4 Serial I/O
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
.....
SIO1CON (Address : 1A16)
UARTCON (Address : 1B16)
BRG
(Address : 1C16)
P4D
(Address : 0916)
1010x0012
000010002
8–1
xxxxxxx02
SIO1STS (Address : 1916), bit1?
0
• Judgment of completion of receiving
(Receive buffer full flag)
1
• Reception of the first byte data
Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from RB (Address : 1816)
SIO1STS (Address : 1916), bit6?
1
• Judgment of an error flag
0
• Judgment of completion of
receiving
(Receive buffer full flag)
0
SIO1STS (Address : 1916), bit1?
1
• Reception of the second byte data
Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from RB (Address : 1816)
SIO1STS (Address : 1916), bit6?
1
• Judgment of an error flag
Processing for error
0
1
P4 (Address : 0816), bit0?
0
SIO1CON (Address : 1A16)
SIO1CON (Address : 1A16)
0000x0012
1010x0012
• Countermeasure for a bit slippage
Fig. 2.4.42 Control procedure of receiving side
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APPLICATION
2.4 Serial I/O
2.4.6 Notes on serial I/O
(1) Notes when selecting clock synchronous serial I/O (Serial I/O1)
➀ Stop of transmission operation
Clear the serial I/O1 enable bit and the transmit enable bit to “0” (Serial I/O1 and transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O1 enable bit is cleared to “0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O ports, the transmission data
is not output). When data is written to the transmit buffer register in this state, data starts to be
shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O1 enable bit to “0”
(Serial I/O1 disabled).
➂ Stop of transmit/receive operation
Clear the transmit enable bit and receive enable bit to “0” simultaneously (transmit and receive
disabled).
(when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
● Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.
If any one of transmission and reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,
the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clearing the serial I/O1 enable bit to
“0” (Serial I/O1 disabled) (refer to (1) ➀).
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APPLICATION
2.4 Serial I/O
(2) Notes when selecting clock asynchronous serial I/O (Serial I/O1)
➀ Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O1 enable bit is cleared to “0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O ports, the transmission data
is not output). When data is written to the transmit buffer register in this state, data starts to be
shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
➂ Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O1 enable bit is cleared to “0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O ports, the transmission data
is not output). When data is written to the transmit buffer register in this state, data starts to be
shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TxD pin and an operation failure occurs.
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
(3) SRDY1 output of reception side (Serial I/O1)
When signals are output from the SRDY1 pin on the reception side by using an external clock in the
clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY1 output enable bit, and
the transmit enable bit to “1” (transmit enabled).
(4) Setting serial I/O1 control register again (Serial I/O1)
Set the serial I/O1 control register again after the transmission and the reception circuits are reset
by clearing both the transmit enable bit and the receive enable bit to “0.”
Clear both the transmit enable bit (TE)
and the receive enable bit (RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O1 control register
↓
Set both the transmit enable bit (TE) and
the receive enable bit (RE), or one of
them to “1”
Can be set with the LDM instruction at the same time
Fig. 2.4.43 Sequence of setting serial I/O1 control register again
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2.4 Serial I/O
(5) Data transmission control with referring to transmit shift register completion flag (Serial I/O1)
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(6) Transmission control when external clock is selected (Serial I/O1)
When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the S CLK input level. Also, write the transmit data to the transmit buffer
register (serial I/O shift register) at “H” of the S CLK input level.
(7) Transmit interrupt request when transmit enable bit is set (Serial I/O1)
When the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as shown
in the following sequence.
➀ Set the interrupt enable bit to “0” (disabled) with CLB instruction.
➁ Prepare serial I/O for transmission/reception.
➂ Set the interrupt request bit to “0” with CLB instruction after 1 or more instruction has been
executed.
➃ Set the interrupt enable bit to “1” (enabled).
● Reason
When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift
register completion flag are set to “1”. The interrupt request is generated and the transmission
interrupt bit is set regardless of which of the two timings listed below is selected as the timing for
the transmission interrupt to be generated.
• Transmit buffer empty flag is set to “1”
• Transmit shift register completion flag is set to “1”
(8) Transmit data writing (Serial I/O2)
In the clock synchronous serial I/O, when selecting an external clock as synchronous clock, write the
transmit data to the serial I/O2 register (serial I/O shift register) at “H” of the transfer clock input level.
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APPLICATION
2.5 Multi-master I2C-BUS interface
2.5 Multi-master I 2C-BUS interface
The multi-master I2C-BUS interface is a serial communication circuit, conforming to the Philips I2C-BUS data
transfer format. This paragraph explains the overview and the communication example.
2.5.1 Memory map
~
~
~
~
001216 I2C data shift register (S0)
001316 I2C address register (S0D)
001416 I2C status register (S1)
001516 I2C control register (S1D)
001616 I2C clock control register (S2)
001716 I2C START/STOP condition control register (S2D)
~
~
~
~
003916 Interrupt source selection register (INTSEL)
~
~
~
~
003C16 Interrupt request register 1 (IREQ1)
003D16 Interrupt request register 2 (IREQ2)
003E16 Interrupt control register 1 (ICON1)
003F16 Interrupt control register 2 (ICON2)
Fig. 2.5.1 Memory map of registers relevant to I 2C-BUS interface
2.5.2 Relevant registers
I2C data shift register
b7 b6 b5 b4 b3 b2 b1 b0
I2C data shift register (S0) [Address : 1216]
B
Function
0 This register is an 8-bit shift register to store receive data or write
At reset
R W
?
transmit data.
1
?
2
?
3
?
4
?
5
?
6
?
7
?
Note: Secure 8 machine cycles from clearing MST bit to “0” (slave mode) until writing
data to I2C data shift register.
If executing the read-modify-write instruction(SEB, CLB etc.) for this register
during transfer, data may become a value not intended.
Fig. 2.5.2 Structure of I 2C data shift register
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2.5 Multi-master I 2C-BUS interface
I2C address register
b7 b6 b5 b4 b3 b2 b1 b0
I2C address register (S0D) [Address : 1316]
B
Name
0 Read / write bit (RWB)
Function
At reset
0 : Write bit
1 : Read bit
T
hese bits are compared with the
1 Slave address
(SAD0, SAD1, SAD2, SAD3, address data transmitted from the
master.
SAD4, SAD5, SAD6)
2
0
3
0
4
0
5
0
6
0
7
0
R W
0
0
Note: If the read-modify-write instruction(SEB, CLB, etc.) is executed for this register
at detecting the stop condition, data may become a value not to intend.
Fig. 2.5.3 Structure of I 2C address register
I2C status register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address : 1416]
B
Name
0 Last receive bit (LRB)
1
2
3
4
5
6
7
Function
0 : Last bit = “0”
1 : Last bit = “1”
(Note1)
General call detecting
0 : No general call detected
1 : General call detected(Note1, 2)
flag(AD0)
Slave address comparison
0 : Address disagreement
1 : Address agreement (Note1, 2)
flag (AAS)
Arbitration lost detecting flag 0 : Not detected
(AL)
1 : Detected
(Note1)
SCL pin low hold bit (PIN)
0 : SCL pin low hold
1 : SCL pin low release
Bus busy flag (BB)
0 : Bus free
1 : Bus busy
Communication mode
00 : Slave receive mode
specification bits (TRX, MST) 01 : Slave transmit mode
10 : Master receive mode
11 : Master transmit mode
At reset
R W
?
✕
0
✕
0
✕
0
✕
1
✽
0
0
0
Notes 1: These bits and flags can be read out, but cannot be written.
2: These bits can be detected when data format selection bit (ALS) of I2C control
register is “0”.
3: Do not execute the read-modify-write instruction (SEB, CLB) for this register
because all bits of this register are changed by hardware.
✽ : “1” can be written to this bit, but “0” cannot be written by program.
Fig. 2.5.4 Structure of I 2C status register
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2.5 Multi-master I2C-BUS interface
I2C control register
b7 b6 b5 b4 b3 b2 b1 b0
I2C control register (S1D) [Address :1516]
B
Name
0 Bit counter (Number of
transmit/receive bits)
(BC0, BC1, BC2)
1
2
3 I2C-BUS interface enable bit
(ES0)
4 Data format selection bit
(ALS)
5 Addressing format selection
bit (10 BIT SAD)
Function
b2 b1 b0
0 0 0:8
0 0 1:7
0 1 0:6
0 1 1:5
1 0 0:4
1 0 1:3
1 1 0:2
1 1 1:1
0 : Disabled
1 : Enabled
0 : 7-bit addressing format
1 : 10-bit addressing format
0
7 I2C-BUS interface pin input
0 : CMOS input
1 : SMBUS input
level selection bit (TISS)
0
0
0 : System clock stop when
executing WIT or STP
instruction
1 : Not system clock stop when
executing WIT instruction
(Do not use the STP
instruction.)
R W
0
0 : Addressing format
1 : Free data format
6 System clock stop selection
bit (CLKSTP)
At reset
0
0
Notes : When the read-modify-write instruction is executed for this register at detecting
the START condition or at completing the byte transfer, data may become a
value not intended.
Fig. 2.5.5 Structure of I2C control register
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I2C clock control register
b7 b6 b5 b4 b3 b2 b1 b0
I2C clock control register (S2) [Address : 1616]
Name
B
S
C
L
f
r
e
q
u
e
ncy control bits
0
Function
At reset
Refer to Table 2.5.1
0
0 : Standard clock mode
1 : High-speed clock mode
0 : ACK is returned
1 : ACK is not returned
0 : No ACK clock
1 : ACK clock
0
(CCR0, CCR1, CCR2, CCR3,
CCR4)
R W
1
2
3
4
5 SCL mode specification bit
(FAST MODE)
6 ACK bit (ACK BIT)
7 ACK clock bit (ACK)
0
0
Fig. 2.5.6 Structure of I 2C clock control register
Table 2.5.1 Set value of I 2C clock control register and SCL frequency
Setting value of
CCR4–CCR0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
…
…
…
1
1
1
1
1
1
1
1
1
0
1
1
0
1
0
1
0
1
0
…
0
0
0
0
0
0
0
…
CCR4 CCR3 CCR2 CCR1 CCR0
1
0
1
SCL frequency (Note 1)
(at φ = 4 MHz, unit : kHz)
Standard clock
mode
Setting disabled
Setting disabled
Setting disabled
– (Note 2)
– (Note 2)
100
83.3
High-speed
clock mode
Setting disabled
Setting disabled
Setting disabled
333
250
400 (Note 3)
166
500/CCR value
1000/CCR value
17.2
16.6
16.1
34.5
33.3
32.3
Notes 1: Duty of SCL clock output is 50 %. The duty becomes 35 to 45 % only when the high-speed clock mode is selected
and CCR value = 5 (400 kHz, at φ = 4 MHz). “H” duration of the clock fluctuates from –4 to +2 machine cycles in
the standard clock mode, and fluctuates from –2 to +2 machine cycles in the high-speed clock mode. In the case of
negative fluctuation, the frequency does not increase because “L” duration is extended instead of “H” duration
reduction.
These are value when SCL clock synchronization by the synchronous function is not performed. CCR value is the
decimal notation value of the SCL frequency control bits CCR4 to CCR0.
2: Each value of SCL frequency exceeds the limit at φ = 4 MHz or more. When using these setting value, use φ of
4 MHz or less.
3: The data formula of SCL frequency is described below:
φ/(8 ✕ CCR value) Standard clock mode
φ/(4 ✕ CCR value) High-speed clock mode (CCR value ≠ 5)
φ/(2 ✕ CCR value) High-speed clock mode (CCR value = 5)
Do not set 0 to 2 as CCR value regardless of φ frequency.
Set 100 kHz (max.) in the standard clock mode and 400 kHz (max.) in the high-speed clock mode to the S CL
frequency by setting the SCL frequency control bits CCR4 to CCR0.
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I2C START/STOP condition control register
b7 b6 b5 b4 b3 b2 b1 b0
I2C START/STOP condition control register (S2D) [Address : 1716]
Name
Function
B
0 START/STOP condition set bit SCL release time
(SSC0, SSC1, SSC2, SSC3,
SSC4)
(Note)
1
= φ(µs) ✕ (SSC+1)
At reset
R W
?
Set up time
= φ(µs) ✕ (SSC+1)/2
2
Hold time
= φ(µs) ✕ (SSC+1)/2
3
4
5 SCL/SDA interrupt pin polarity
selection bit(SIP)
6 SCL/SDA interrupt pin selection
bit (SIS)
7 START/STOP condition
generating selection bit
(STSPSEL)
0 : Falling edge active
1 : Rising edge active
0 : SDA valid
1 : SCL valid
0 : Setup/Hold time short mode
1 : Setup/Hold time long mode
0
0
0
Note: Do not set “000002” or an odd number to the START/STOP condition set bit
(SSC4 to SSC0).
Fig. 2.5.7 Structure of I 2C START/STOP condition control register
Interrupt source selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt source selection register [INTSEL: address 003916]
B
Name
0 INT0/input buffer full interrupt
Function
0 : INT0 interrupt
source selection bit
1 : Input buffer full interrupt
0 : INT1 interrupt
1 INT1/output buffer empty
interrupt source selection bit 1 : Output buffer empty interrupt
0 : Serial I/O1 transmit interrupt ✽1
2 Serial I/O1 transmit/SCL,SDA
interrupt source selection bit 1 : SCL,SDA interrupt
✽1
0 : CNTR0 interrupt
3 CNTR0/SCL,SDA interrupt
source selection bit
1 : SCL,SDA interrupt
✽2
0 : Serial I/O2 interrupt
4 Serial I/O2/I2C interrupt
source selection bit
1 : I2C interrupt
✽2
0 : INT2 interrupt
5 INT2/I2C interrupt source
selection bit
1 : I2C interrupt
✽3
0 : CNTR1 interrupt
6 CNTR1/key-on wake-up
interrupt source selection bit 1 : Key-on wake-up interrupt
✽3
7 AD converter/key-on wake-up 0 : A-D converter interrupt
interrupt source selection bit 1 : Key-on wake-up interrupt
✽1: Do not write “1” to these bits simultaneously.
✽2: Do not write “1” to these bits simultaneously.
✽3: Do not write “1” to these bits simultaneously.
Fig. 2.5.8 Structure of Interrupt source selection register
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At reset
0
0
0
0
0
0
0
0
R W
APPLICATION
2.5 Multi-master I 2C-BUS interface
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address : 3C16]
B
Name
0 INT0/input buffer full interrupt
request bit
1 INT1/output buffer empty
interrupt request bit
2 Serial I/O1 receive interrupt
request bit
3 Serial I/O1 transmit/SCL, SDA
interrupt request bit
4 Timer X interrupt request bit
5 Timer Y interrupt request bit
6 Timer 1 interrupt request bit
7 Timer 2 interrupt request bit
Function
At reset
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
R W
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
At reset
R W
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.5.9 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2) [Address : 3D16]
B
0
1
2
3
4
5
6
7
Name
Function
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
INT3 interrupt request bit
1 : Interrupt request issued
0 : No interrupt request issued
INT4 interrupt request bit
1 : Interrupt request issued
AD converter/key-on wake-up 0 : No interrupt request issued
1 : Interrupt request issued
interrupt request bit
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
CNTR0/SCL, SDA interrupt
request bit
CNTR1/key-on wake-up
interrupt request bit
Serial I/O2/I2C interrupt
request bit
INT2/I2C interrupt request bit
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✕
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.5.10 Structure of Interrupt request register 2
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Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E16]
B
Name
I
N
T
0
/
i
n
p
u
t
b
uffer full interrupt
0
enable bit
1 INT1/output buffer empty
interrupt enable bit
2 Serial I/O1 receive interrupt
enable bit
3 Serial I/O1 transmit/SCL, SDA
interrupt enable bit
4 Timer X interrupt enable bit
5 Timer Y interrupt enable bit
6 Timer 1 interrupt enable bit
7 Timer 2 interrupt enable bit
Function
At reset
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
R W
0
0
0
0
0
0
Fig. 2.5.11 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2 (ICON2) [Address : 3F16]
B
Name
0 CNTR0/SCL, SDA interrupt
enable bit
1 CNTR1/key-on wake-up
interrupt enable bit
2 Serial I/O2/I2C interrupt enable
bit
3 INT2/I2C interrupt enable bit
4 INT3 interrupt enable bit
5 INT4 interrupt enable bit
6 AD converter/key-on wake-up
interrupt enable bit
7 Fix this bit to “0”.
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 2.5.12 Structure of Interrupt control register 2
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At reset
0
0
0
0
0
0
0
0
R W
APPLICATION
2.5 Multi-master I 2C-BUS interface
2.5.3 I2C-BUS overview
The I2C-BUS is a both directions serial bus connected with two signal lines; the SCL which transmits a
clock and the SDA which transmits data.
Each port has an N-channel open-drain structure for output and a CMOS structure for input. The devices
connected with the I 2C-BUS interface use an open drain, so that external pull-up resistors are required.
Accordingly, while any one of devices always outputs “L”, other devices cannot output “H”.
Figure 2.5.13 shows the I 2C-BUS connection structure.
SCL output
SCL output
SCL input
SCL input
SDA output
SDA output
SDA input
SDA input
SCL output
SCL input
SDA output
SDA input
Fig. 2.5.13 I2C-BUS connection structure
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2.5.4 Communication format
Figure 2.5.14 shows an I2C-BUS communication format example.
The I 2C-BUS consists of the following:
•START condition to indicate communication start
•Slave address and data to specify each device
•ACK to indicate acknowledgment of address and data
•STOP condition to indicate communication completion.
Bus busy term
S
Slave address
7 bits
R/W A
Data
8 bits
A
Data
8 bits
Data 0 to 7
ACK
Data 0 to 7
A P
SCL
SDA
Start Addresses 0 to 6 W ACK
ACK
Stop
Fig. 2.5.14 I2C-BUS communication format example
(1) START condition
When communication starts, the master device outputs the START condition to the slave device. The
I2C-BUS defines that data can be changed when a clock line is “L”. Accordingly, data change when
a clock line is “H” is treated as STOP or START condition.
The data line change from “H” to “L” when a clock line is “H” is START condition.
(2) STOP condition
Just as in START condition, the data line change from “L” to “H” when a clock line is “H” is STOP
condition.
The term from START condition to STOP condition is called “Bus busy”. The master device is
inhibited from starting data transfer during that term.
The Bus busy status can be judged by using the BB flag of I 2C status register (bit 5 of address
0014 16).
(3) Slave address
The slave address is transmitted after START condition. This address consists of 7 bits and the 7th bit functions as the read/write (R/W) bit which indicates a data transmission method. The slave
devices connected with the same I2C-BUS must have their addresses, individually. It is because that
address is defined for the master to specify the transmitted/received slave device.
The read/write (R/W) bit indicates a data transmission direction; “L” means write from the master to
the slave, and “H” means read in.
(4) Data
The data has an 8-bit length. There are two cases depending on the read/write (R/W) bit of a slave
address; one is from the master to the slave and the other is from the slave to the master.
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(5) ACK bit
The ACK bit clock is generated by the master. This is used for indication of acknowledgment on the
SDA line, the slave’s busy and the data end.
For example, the slave device makes the SDA line “L” for acknowledgment when confirming the slave
address following the START condition. The built-in I2C-BUS interface has the slave address automatic
judgment function and the ACK acknowledgment function. “L” is automatically output when the ACK
bit of I2C clock control register (bit 6 of address 001616) is “0” and an address data is received. When
the slave address and the address data do not correspond, “H” (NACK) is automatically output.
In case the slave device cannot receive owing to an interrupt process, performing operation or
others, the master can output STOP condition and complete data transfer by making the ACK data
of the slave address “H” for acknowledgment. Even in case the slave device cannot receive data
during data transferring, the communication can be interrupted by performing NACK acknowledgment
to the following data.
When the master is receiving the data from the slave, the master can notify the slave of completion
of data reception by performing NACK acknowledgment to the last data received from the slave.
(6) RESTART condition
The master can receive or transmit data without transmission of STOP condition while the master is
transmitting or receiving a data.
For example, after the master transmitted a data to the slave, transmitting a slave address + R
(Read) following RESTART condition can make the following data treat as a reception data.
Additionally, transmitting a slave address + W (Write) following RESTART condition can make the
following data treat as a transmission data.
START condition
S
Master reception
1st-byte
RESTART condition
Slave address R/W A
7 bits
“0”
Write
Data
A Sr Slave address R/W A
8 bits
7 bits
Lower data
“1”
Read
8 bits
A
Master reception
2nd-byte
Upper data
A P
8 bits
NACK expression end of
master reception data
S: START condition
P: STOP condition
A: ACK bit
R/W: Read/Write bit
Sr: RESTART condition
Master to slave
Slave to master
Fig. 2.5.15 RESTART condition of master reception
2.5.5 Synchronization and Arbitration lost
(1) Synchronization
When a plural master exists on the I2C-BUS and the masters, which have different speed, are going
to simultaneously communicate; there is a rule to unify clocks so that a clock of each bit can be
output correctly.
Figure 2.5.16 shows a synchronized SCL line example. The SCL (A) and the SCL (B) are the master
devices having a different speed. The SCL is synchronized waveforms.
As shown by Figure 2.5.16, the SCL lines can be synchronized by the following method; the device
which first finishes “H” term makes the SCL line “L” and the device which last remains “L” makes the
SCL line “H”.
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➀
SCL(A)
➁
➅
➂
➄
SCL(B)
➃
➆
SCL
Fig. 2.5.16 SCL waveforms when synchronizing clocks
➀ After START condition, the masters, which have different speed, simultaneously start clock transmission.
➁ The SCL outputs “L” because (A) finished counting “H” output; then (B)’s “H” output counting is
interrupted and (B) starts counting “L” output.
➂ The (A) outputs “H” because (A) finished counting “L” term; the SCL level does not become “H”
because (B) outputs “L”, and counting “H” term does not start but stop.
➃ (B) outputs “L” term.
➄ The SCL outputs “H” because (B) finished counting “L” term; then (B)’s “H” output counting is
started at the same time as (A).
➅ The SCL outputs “L” because (A) first finished counting “H” output; then (B)’s “H” output counting
is interrupted and (B) starts counting “L” output.
➆ The above are repeatedly performed.
(2) Clock synchronization during communication
In the I 2C-BUS, the slave device is permitted to retain the SCL line “L” and become waiting status
for transmission from the master. By byte unit, for the reception preparation of the slave device, the
master can become waiting status by making the SCL line “L”, which is after completion of byte
reception or the ACK.
By bit unit, it is possible to slow down a clock speed by retaining the SCL line “L” for slave devices
having limited hardware.
The 3886 group can transmit data correctly without reduction of data bits toward waiting status
request from the slave device. It is because the synchronization circuit is included for the case when
retaining the SCL line “L” as an internal hardware.
After the last bit, including the ACK bit, of a transmission/reception data byte, the SCL line automatically
remains “L” and waiting status is generated until completion of an interrupt process or reception
preparation.
(3) Arbitration lost
A plural master exists on the same bus in the I2C-BUS and there are possibility to start communication
simultaneously. Even when the master devices having the same transmission frequency start
communication simultaneously, which device must transmit data correctly. Accordingly, there is the
definition to detect a communication confliction on the SDA line in the I 2C-BUS.
The SDA line is output at the timing synchronized by the SCL, however, the synchronization among
the SDA signals is not performed.
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2.5 Multi-master I 2C-BUS interface
2.5.6 I2C-BUS communication usage example
This clause explains a control example using the I2C-BUS. This is a control example as the master device
and the slave device in the Read Word protocol of I 2C-BUS protocol.
The following is a communication example of E 2PROM (24C0X).
Communication specifications:
•Communication frequency = 100 kHz
•Slave address of communication destination, E 2PROM, = “1010000X 2” (X means the read/write bit)
•Address = E 2PROM internal address
•The communication process is performed in the interrupt process. However, the main process performs
an occurrence of the first START condition and a slave address set.
•A communication buffer is established. Data transfer between the main process and the interrupt process
is performed through the communication buffer.
(1) Initial setting
Figure 2.5.17 shows an initial setting example using I 2C-BUS communication.
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I2C address register (address 1316)
b7
S0D
b0
1 0 1 0 0 0 0 0
Set slave address value A016.
I2C clock control register (address 1616)
b7
S2
b0
1 0 0 0 0 1 0 1
Set clock 100 kHz (XIN = 8MHz)
Standard clock mode
ACK is returned
ACK clock
I2C status register (address 1416)
b7
S1
0 0
b0
1
SCL pin low hold bit: fix to “1”
Slave receive mode
I2C START/STOP condition control register (address 1716)
b7
S2D
b0
1 0 0 1 1 0 1 0
Set setup time hold time to 27 cycles (6.75 µs: XIN = 8 MHz).
SCL/SDA interrupt: Falling edge active
SCL/SDA interrupt: SDA valid
Set Setup/Hold time to “1” (long mode).
I2C control register (address 1516)
b7
S1D
b0
0 1 0 0 1 0 0 0
Set number of transmit/receive bits to “8”.
I2C-BUS interface: enabled
Addressing format
7-bit addressing format
System clock not stopped when WIT instruction is executed
Set CMOS input level.
Fig. 2.5.17 Initial setting example
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2.5 Multi-master I 2C-BUS interface
(2) Communication example in master device
The master device follows the procedures ➀ to ➅ shown by Figure 2.5.18.
Additionally, the shaded area in the figure is a transmission data from the master device and the
white area is a transmission data from the slave device.
➀
➁
➂
➃
➄
➅
Generating of START condition; Transmission of slave address + write bit
Transmission of command
Generating of RESTART condition; Transmission of slave address + read bit
Reception of lower data
Reception of upper data
Generating of STOP condition
Figures 2.5.19 to 2.5.24 show the procedures ➀ to ➅.
➀
S
➁
➂
Slave address R/W A Command A Sr Slave address R/W A
7 bits
“0”
Write
8 bits
Interrupt request
7 bits
Interrupt request
S: START condition
P: STOP condition
A: ACK bit
R/W: Read/Write bit
Sr: RESTART condition
➄
➃
Lower data
“1”
Read
A
➅
Upper data
8 bits
A P
8 bits
Interrupt request Interrupt request
Interrupt request
Master to slave
Slave to master
Fig. 2.5.18 Read Word protocol communication as I2C-BUS master device
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➀ Generating of START condition; Transmission of slave address + write bit
After confirming that other master devices do not use the bus, generate the START condition,
because the I 2C-BUS is a multi-master.
Write “slave address + write bit” to the I2C data shift register (address 0012 16) before performing
to make the START condition generate. It is because the SCL of 1-byte unit is output, following
occurrence of the START condition.
If other master devices start communication until an occurrence of the START condition after
confirming the bus use, it cannot communicate correctly. However in this case, that situation does
not affect other master devices owing to detection of an arbitration lost or the START condition
duplication preventing function.
1
(A) ← 000101102
SEI (Note 1)
• Interrupts disabled
1 (used)
BB (address 1416), bit5 ? (Note 2)
• Bus use confirmation
0 (not used)
S0(address 1216) ← (A)
• Slave address value write
S1(address 1416) ← 111100002
• Start condition occurrence
CLI(Note 1)
• Interrupt enabled
End
Notes 1: In this example, the SEI instruction to disable interrupts need not be executed
because this processing is going to be performed in the interrupt processing.
When the start condition is generated out of the interrupt processing, execute
the SEI instruction to disable interrupts.
2: Use the branch bit instruction to confirm bus busy.
Fig. 2.5.19 Generating of START condition and transmission process of slave address + write bit
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APPLICATION
2.5 Multi-master I 2C-BUS interface
➁ Transmission of command
Confirm correct completion of communication at ➀ before command transmission. When receiving
the STOP condition, a process not to transmit a command is required, because the internal I 2CBUS generates an interrupt request also owing to the STOP condition transmitted to other devices.
After confirming correct completion of communication, write a command to the I 2C data shift
register (address 0012 16).
In case the AL bit (bit 3 of address 001416) is “1”, check the slave address comparison flag (ASS
bit; bit 2 of address 001416) to judge whether the device given a right of master transmission owing
to an arbitration specifies itself as a slave address. When it is “1”, perform the slave reception;
when “0”, wait for a STOP condition occurrence caused by other devices and the communication
completion.
In case the AL bit is “0”, check the last received bit (LRB bit; bit 0 of address 001416). When it is
“1”, make the STOP condition generate and release the bus use, because the specified slave
device does not exist on the I 2C-BUS.
2
1 (error)
PIN (address 1416), bit 4 ?
• Judgment of bus hold
0 (slave address transmitted)
1 (detected)
AL (address 1416), bit 3 ?
• Judgment of arbitration lost detection
0 (not detected)
1 (NACK)
LRB (address 1416), bit 0 ?
• ACK confirmation
0 (ACK)
S0 (address 1216) ← 000011112
• Command data write to I2C data shift register
End
Stop condition output
AAS (address 1416), bit 2 ?
0(address not corresponded)
Re-transmission preparation
• Judgment of slave address comparison
1(address corresponded)
Slave reception
Fig. 2.5.20 Transmission process of command
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APPLICATION
2.5 Multi-master I2C-BUS interface
➂ Generating of RESTART condition; Transmission of slave address + read bit
Confirm correct completion of communication at ➁ before generating the RESTART condition.
After confirming correct completion, generate the RESTART condition and perform the transmission
process of “slave address + read bit”. Note that procedure because that is different from ➀’s
process.
As the same reason as ➀, write “slave address + read bit” to the I2C data shift register (address
001216) before performing to make the START condition generate. However, when writing a slave
address to the I 2C data shift register in this condition, a slave address is output at that time.
Consequently, the RESTART condition cannot be generated. Therefore, follow the slave reception
procedure before those processes.
In case the arbitration lost detecting flag (AL bit, bit 3 of address 0014 16) is “1”, return to the
process ➀, because other master devices will have priority to communicate.
When the last received bit (LRB bit; bit 0 of address 001416) is “1”, generate the STOP condition
and make the bus release, because acknowledgment cannot be done owing to BUSY status of the
slave device specified on the I 2C-BUS or other reasons.
3
1 (stop condition)
PIN (address 1416), bit 4 ?
• Bus judgment during hold
0(command transmission)
1 (detected)
AL (address 1416), bit 3 ?
• Judgment of arbitration lost detection
0(not detected)
1(NACK)
LRB (address 1416), bit 0 ?
• ACK confirmation
0(ACK)
S1(address 1416) ← 000000002 (Note 1)
• Slave receive mode set
(A) ← 000101112
• Slave address read out
SEI (Note 2)
S0(address 001216) ← (A)
S1(address 001416) ← 111100002
CLI(Note 2)
• Interrupt disabled
• Slave address value write
• RESTART condition occurrence
• Interrupt enabled
End
Re-transmission preparation
Stop condition output
Notes 1: Set to the receive mode while the PIN bit is “0”. Do not write “1” to the PIN bit.
2: In this example, the SEI instruction to disable interrupts need not be executed because this
processing is going to be performed in the interrupt processing. When the start condition is
generated out of the interrupt processing, execute the SEI instruction to disable interrupts.
Fig. 2.5.21 Transmission process of RESTART condition and slave address + read bit
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APPLICATION
2.5 Multi-master I 2C-BUS interface
➃ Reception of lower data
Confirm correct completion of communication at ➂ before receiving the lower data. After confirming
correct completion, clear the ACK bit (bit 6 of address 0016 16) to “0”, in which ACK is returned,
and set to the master receive mode. After that, write dummy data to the I 2C data shift register
(address 001216).
When the MST bit (bit 7 of address 001416) is “0”, perform the error process explained as follows
and return to the process ➀.
When the last received bit (LRB bit; bit 0 of address 001416) is “1”, generate the STOP condition
and make the bus release, because the slave device specified on the I 2C-BUS does not exist.
4
1(STOP condition)
• Judgment of bus hold
PIN (address 1416), bit 4 ?
0(transmission of RESTART
condition)
0(slave)
MST (address 1416), bit 7 ?
• Judgment of slave mode detection
1(master)
1(NACK)
LRB (address 1416), bit0 ?
• ACK confirmation
0(ACK)
S2(address 1616) ← 100001012
• “ACK clock is used” select and
“ACK is returned” set
S1(address 1416) ←101000002
• Master receive mode set
S0(address 1216) ← 111111112
• Dummy data to I2C data shift register write
End
Stop condition output
1(detected)
AL (address 1416), bit 3 ?
• Judgment of arbitration lost detection
0(not detected)
Re-transmission preparation
Error processing
Fig. 2.5.22 Reception process of lower data
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APPLICATION
2.5 Multi-master I2C-BUS interface
➄ Transmission of upper data
Confirm correct completion of communication at ➃ before receiving the upper data. After confirming
correct completion, store the received data (lower data).
Set the ACK bit (bit 6 of address 0016 16) to “1”, in which ACK is not returned and write dummy
data to the I 2C data shift register (address 001216).
When the MST bit (bit 7 of address 001416) is “0”, return to the process ➀, because other devices
have priority to communicate.
5
1(stop condition)
PIN (address 1416), bit 4 ?
• Judgment of bus hold
0(lower data transmitted)
0(slave)
MST (address 1416), bit 7 ?
• Judgment of slave mode detection
1(Master)
Receive data buffer ← S0(address 1216)
• Receive data read and save
S2(address 1616) ← 110001012
• “NACK is returned” set
S0(address 1216) ← 111111112
• Dummy data to I2C data shift register write
End
1(detected)
AL (address 1416), bit 3 ?
0(not detected)
Re-transmission preparation
Error processing
Fig. 2.5.23 Reception process of upper data
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• Judgment of arbitration lost detection
APPLICATION
2.5 Multi-master I 2C-BUS interface
➅ Generating of STOP condition
Confirm correct completion of communication at ➄ before generating the STOP condition. After
confirming correct completion, store the received data (upper data).
Clear the ACK bit (bit 6 of address 0016 16) to “0”, in which ACK is returned, and generate the
STOP condition. The communication mode is set to the slave receive mode by the occurrence of
STOP condition.
When the MST bit (bit 7 of address 001416) is “0”, return to the process ➀, because other devices
have priority to communicate.
6
1 (stop condition)
PIN (address 1416), bit 4 ?
• Judgment of bus hold
0 (upper data transmitted)
1 (detected)
AL (address 1416), bit 3 ?
• Judgment of arbitration lost detection
0 (not detected)
Receive data buffer ← S0(address 1216)
S2(address 1616) ← 100001012
• Receive data read and save
• Set “ACK is returned”
S1(address 1416) ← 110100002
• Stop condition occurrence
BB (address 1416), bit5 ? (Note)
• Judgment of bus busy
1 (bus busy)
0 (bus free)
Re-transmission preparation
End
Note: Use the branch bit instruction to check bus busy.
Also, execute the time out processing separately, if neccessary.
Fig. 2.5.24 Generating of STOP condition
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APPLICATION
2.5 Multi-master I2C-BUS interface
(3) Communication example in slave device
The slave device follows the procedures ➀ to ➅ shown by Figure 2.5.25.
The only difference from the master device’s communication is an occurrence of interrupt request
after detection of STOP condition.
➀
➁
➂
➃
➄
➅
Reception of START condition; Transmission of ACK bit due to slave address correspondence
Reception of command
Reception of RESTART condition; Reception of slave address + read bit
Transmission of lower data
Transmission of upper data
Reception of STOP condition
Figures 2.5.26 to 2.5.31 show the procedures ➀ to ➅.
➀
S
➁
➂
Slave address R/W A Command A Sr Slave address R/W A
7 bits
“0”
Write
8 bits
Interrupt request
7 bits
Interrupt request
S: START condition
P: STOP condition
A: ACK bit
R/W: Read/Write bit
Sr: RESTART condition
Lower data
“1”
Read
8 bits
Interrupt request
Master to slave
Slave to master
Fig. 2.5.25 Communication example as slave device
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➄➅
➃
3886 Group User’s Manual
A
Upper data
A P
8 bits
Interrupt request
Interrupt re
Interrupt request
APPLICATION
2.5 Multi-master I 2C-BUS interface
➀ Reception of START condition; Transmission of ACK bit due to slave address correspondence
In the case of operation as the slave, all processes are performed in the interrupt after setting of
the slave reception in the main process, because an interrupt request does not occur until
correspondence of a slave address.
In the first interrupt, after confirming correspondence of the slave address, write dummy data to
receive a command into the I 2C data shift register.
1
1(stop condition)
PIN (address 1416), bit 4 ?
• Judgment of bus hold
0(slave address received)
0(not corresponded)
AAS (address 1416), bit 2 ?
• Judgment of slave address correspondence
1(corresponded)
S0(address 1216) ← 111111112
• Dummy data write to I2C data shift register
End
S1(address 1416) ← 000100002
• Slave receive mode set
Error processing
Fig. 2.5.26 Reception process of START condition and slave address
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APPLICATION
2.5 Multi-master I2C-BUS interface
➁ Reception of command
Confirm correct completion of the command reception in the interrupt after receiving the command.
After confirming correct command from the host, write dummy data to the I 2C data shift register
to wait for reception of the next slave address.
2
1(stop condition)
PIN (address 1416), bit 4 ?
• Judgment of bus hold
0(command received)
Receive data buffer ← S0(address 1216)
• Receive data read and save
Judgment of receive command
S2(address 1616) ← 100001012
• “ACK clock is used” select and “ACK is returned” set
S0(address 1216) ← 111111112
• Dummy data write to I2C data shift register
End
S1(address 1416) ← 000100002
• Slave receive mode set
Error end
Fig. 2.5.27 Reception process of command
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APPLICATION
2.5 Multi-master I 2C-BUS interface
➂ Reception of RESTART condition and slave address
After receiving a slave address, prepare transmission data.
Judgment whether receiving data or transmitting is required, because the mode is automatically
switched between the receive mode and the transmit mode depending on the R/W bit of the
received slave address. Accordingly, judge whether read or write referring the slave address
comparison flag (AAS bit; bit 2 of address 0014 16).
3
1 (stop condition)
PIN (address 1416), bit 4 ?
• Judgment of bus hold
0 (lower data received)
0 (received)
TRX (address 1416), bit 6 ?
• Judgment of transmit/receive mode
1 (transmitted)
S0(address 1216) ← lower data
• Output lower data write to I2C data shift register
End
Slave receive processing, etc.
End
S1(address 1416) ¨ 000100002
• Slave receive mode set
Error end
Fig. 2.5.28 Reception process of RESTART condition and slave address
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APPLICATION
2.5 Multi-master I2C-BUS interface
➃ Transmission of lower data
Before transmitting the upper data, restart to transmit the data at ➃ and confirm correct completion
of transmission of the lower data set in the slave address reception interrupt.
After that, transmit the upper data.
4
1(stop condition)
PIN (address 1416), bit 4 ?
• Judgment of bus hold
0(lower data transmission completed)
1(NACK)
LRB (address 1416), bit 0 ?
• ACK confirmation
0(ACK)
S0(address 1216) ← Upper data
• Output upper data write to I2C data shift register
End
S1(address 1416) ← 000100002
Error end
Fig. 2.5.29 Transmission process of lower data
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3886 Group User’s Manual
• Slave receive mode set
APPLICATION
2.5 Multi-master I 2C-BUS interface
➄ Transmission of upper data
Confirm correct completion of the upper data transmission. The master returns the NACK toward
the transmitted second-byte data, the upper data. Accordingly, confirm that the last received bit
(LRB bit; bit 0 of address 0014 16) is “1”.
After that, write dummy data to the I 2 C data shift register and wait for the interrupt of STOP
condition.
5
1(stop condition)
PIN (address 1416), bit 4 ?
• Judgment of bus hold
0(upper data transmission completed)
0(ACK)
LRB (address 1416), bit 0 ?
• ACK confirmation
1(NACK)
S0(address 1216) ← 111111112
• Dummy data write to I2C data shift register
End
S1(address 1416) ← 000100002
• Slave receive mode set
Error end
Note: Use the branch bit instruction to check bus busy.
Fig. 2.5.30 Transmission process of upper data
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APPLICATION
2.5 Multi-master I2C-BUS interface
➅ Reception of STOP condition
Confirm that the STOP condition is correctly output and the bus is released.
6
0(address or data received)
PIN (address 1416), bit 4 ?
• Judgment of bus hold
1(stop condition)
End processing
S1(address 1416) ← 000100002
• Slave receive mode set
End
S1(address 1416) ← 000100002
Error end
Fig. 2.5.31 Reception of STOP condition
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• Slave receive mode set
APPLICATION
2.5 Multi-master I2C-BUS interface
2.5.7 Notes on multi-master I 2C-BUS interface
(1) Read-modify-write instruction
Precautions for read-modify-write instructions, such as SEB and CLB, when used for any of the
registers of the multi-master I 2C-BUS interface, are described below.
➀ I2C data shift register (S0: address 0012 16)
When executing the read-modify-write instruction for this register during transfer, data may become
an unexpected value.
➁ I2C address register (S0D: address 001316)
When the read-modify-write instruction is executed for this register at detecting the STOP condition,
data may become an unexpected value.
● Reason
Because hardware changes the read/write bit (RWB) at detecting the STOP condition.
➂ I2C status register (S1: address 001416)
Do not execute the read-modify-write instruction for this register because all bits of this register
are changed by hardware.
➃ I2C control register (S1D: address 0015 16)
When the read-modify-write instruction is executed for this register at detecting the START condition
or at completing the byte transfer, data may become an unexpected value.
● Reason
Because hardware changes the bit counter (BC0 to BC2).
➄ I2C clock control register (S2: address 001616)
The read-modify-write instruction can be executed for this register.
➅ I2C START/STOP condition control register (S2D: address 0017 16)
The read-modify-write instruction can be executed for this register.
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APPLICATION
2.5 Multi-master I2C-BUS interface
(2) Procedure for generating START condition using multi-master
➀ Procedure example (The necessary conditions for the procedure are described in Items ➁ to ➄
below).
LDA #SLADR
(Take out slave address value)
SEI
(Disable interrupt)
BBS 5, S1, BUSBUSY (BB flag confirmation and branch process)
BUSFREE:
STA S0
(Write slave address value)
LDM #$F0, S1
(Trigger START condition generation)
CLI
(Enable interrupt)
:
:
BUSBUSY:
CLI
(Enable interrupt)
:
:
➁ Use “Branch on Bit Set” of “BBS 5, S1, –” for the BB flag confirmation and branch process.
➂ Use “STA”, “STX” or “STY” of the zero page addressing instruction for writing the slave address
value to the I 2C data shift register (S0: address 0012 16).
➃ Execute the branch instruction of above ➁ and the store instruction of above ➂ continuously shown
the above procedure example.
➄ Disable interrupts during the following three process steps:
• BB flag confirmation
• Write slave address value
• Trigger START condition generation
When the BB flag is in bus busy state, enable interrupts immediately.
(3) Procedure for generating RESTART condition
This procedure cannot be applied to M38867M8A and M38867E8A when the external memory is
used and the bus cycle is extended by ONW function.
➀ Procedure example (The necessary conditions for the procedure are described in Items ➁ to ➃
below). Execute the following procedure when the PIN bit is “0”.
LDM #$00, S1
(Select slave receive mode)
LDA #SLADR
(Take out slave address value)
SEI
(Disable interrupt)
STA S0
(Write slave address value)
LDM #$F0, S1
(Trigger RESTART condition generation)
CLI
(Enable interrupt)
:
:
➁ Select the slave receive mode when the PIN bit is “0”. Do not write “1” to the PIN bit. Neither “0” nor
“1” is specified as input to the BB bit. The TRX bit becomes “0” and the SDA pin is released.
➂ The SCL pin is released by writing the slave address value to the I 2C data shift register.
➃ Disable interrupts during the following two process steps:
• Write slave address value
• Trigger RESTART condition generation
(4) Writing to I 2C status register
Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and
TRX bits to “0” from “1” simultaneously. Because it may enter the state that the SCL pin is released
and the SDA pin is released after about one machine cycle. Do not execute an instruction to set the
MST and TRX bits to “0” from “1” simultaneously when the PIN bit is “1”. Because it may become
the same as above.
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APPLICATION
2.5 Multi-master I2C-BUS interface
(5) Process of after STOP condition generating
Do not write data in the I2C data shift register (S0) and the I 2C status register (S1) until the bus busy
flag BB becomes “0” after generating the STOP condition in the master mode. Because the STOP
condition waveform might not be normally generated. Reading to the above registers does not have
the problem.
(6) STOP condition input at 7th clock pulse
The SDA line may be held at LOW even if flag BB is set to “0” when all the following conditions are
satisfied:
•The STOP condition is input at the 7th clock pulse while receiving a slave address or data.
•The clock pulse is continuously input.
•In the slave mode
Countermeasure:
Write dummy data to the I2C data shift register or reset the ES0 bit in the S1D register (ES0 = “L”
→ ES0 = “H”) during a stop condition interrupt routine with flag BB = “0”.
Note: Do not use the read-modify-write instruction at this time. Furthermore, when the ES0 bit is
set to “0”, the SDA pin becomes a general-purpose port ; so that the port must be set to input
mode or output “H”.
(7) ES0 bit switch
In standard clock mode when SSC = “00010 2” or in high-speed clock mode, flag BB may switch to
“1” if ES0 bit is set to “1” when SDA is “L”.
Countermeasure:
Set ES0 to “1” when SDA is “H”.
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APPLICATION
2.6 PWM
2.6 PWM
This paragraph explains the registers setting method and the notes relevant to the PWM.
2.6.1 Memory map
002E16 Port control register 1 (PCTL1)
003016 PWM0H register (PWM0H)
003116 PWM0L register (PWM0L)
003216 PWM1H register (PWM1H)
003316 PWM1L register (PWM1L)
003416 AD/DA control register (ADCON)
Fig. 2.6.1 Memory map of registers relevant to PWM
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APPLICATION
2.6 PWM
2.6.2 Relevant registers
Port control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Port control register 1 (PCTL1) [Address 2E 16]
B
Name
P
0
0
–
P
0
3
o
u
t
put structure
0
1
2
3
4
selection bit
P04–P07 output structure
selection bit
P10–P13 output structure
selection bit
P14–P17 output structure
selection bit
P30–P33 pull-up control bit
5 P34–P37 pull-up control bit
6 PWM0 enable bit
7 PWM1 enable bit
Function
0: CMOS
1: N-channel open-drain
0: CMOS
1: N-channel open-drain
0: CMOS
1: N-channel open-drain
0: CMOS
1: N-channel open-drain
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: PWM0 output disabled
1: PWM0 output enabled
0: PWM1 output disabled
1: PWM1 output enabled
At reset
R W
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
Fig. 2.6.2 Structure of Port control register 1
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APPLICATION
2.6 PWM
PWM0H register
b7 b6 b5 b4 b3 b2 b1 b0
PWM0H register (PWM0H) [Address : 3016]
B
Function
0 • The high-order 8 bits of the PWM0H output data are set.
• At writing: A written data is transferred to PWM0 latch at every
1
sub-period (64 µs).
(f(XIN) = 8 MHz)
2 • At reading: The contents of the PWM0H register are read out.
At reset
R W
?
?
?
3
?
4
?
5
?
6
?
7
?
Fig. 2.6.3 Structure of PWM0H register
PWM0L register
b7 b6 b5 b4 b3 b2 b1 b0
PWM0L register (PWM0L) [Address : 3116]
B
Function
0 • The low-order 6 bits of the PWM0L output data are set.
• At writing: A written data is transferred to PWM0 latch at every
1
repetitive period (4096 µs).
(f(XIN) = 8 MHz)
2
• At reading: The low-order 6 bits of PWM0 latch are read out.
?
?
?
4
?
5
6 Nothing is allocated for this bit. This is a write disabled bit.
?
Fig. 2.6.4 Structure of PWM0L register
3886 Group User’s Manual
R W
?
3
When this bit is read out, the value is “0”.
7 • The completion of transfer to the PWM0 latch is indicated.
0: Transfer completed.
1: Not transferred.
• At writing: This bit is set to “1”.
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At reset
?
✕
?
✕
APPLICATION
2.6 PWM
PWM1H register
b7 b6 b5 b4 b3 b2 b1 b0
PWM1H register (PWM1H) [Address : 3216]
B
Function
0 • The high-order 8 bits of the PWM1H output data are set.
• At writing: A written data is transferred to PWM1 latch at every
1
sub-period (64 µs).
(f(XIN) = 8 MHz)
2 • At reading: The contents of the PWM1H register are read out.
At reset
R W
?
?
?
3
?
4
?
5
?
6
?
7
?
Fig. 2.6.5 Structure of PWM1H register
PWM1L register
b7 b6 b5 b4 b3 b2 b1 b0
PWM1L register (PWM1L) [Address : 3316]
B
Function
0 • The low-order 6 bits of the PWM1L output data are set.
• At writing: A written data is transferred to PWM1 latch at every
1
repetitive period (4096 µs).
(f(XIN) = 8 MHz)
2
• At reading: The low-order 6 bits of PWM1 latch are read out.
At reset
?
?
?
3
?
4
?
5
6 Nothing is allocated for this bit. This is a write disabled bit.
?
When this bit is read out, the value is “0”.
7 • The completion of transfer to the PWM1 latch is indicated.
0: Transfer completed.
1: Not transferred.
• At writing: This bit is set to “1”.
R W
?
✕
?
✕
Fig. 2.6.6 Structure of PWM1L register
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APPLICATION
2.6 PWM
AD/DA control register
b7 b6 b5 b4 b3 b2 b1 b0
AD/DA control register (ADCON) [Address : 3416 ]
Name
B
0 Analog input pin selection bits
1
2
Function
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : P60/AN0
1 : P61/AN1
0 : P62/AN2
1 : P63/AN3
0 : P64/AN4
1 : P65/AN5
0 : P66/AN6
1 : P67/AN7
0
3 AD conversion completion bit 0 : Conversion in progress
1
PWM0 output pin selection bit 0: P56/PWM01
1: P30/PWM00
PWM1 output pin selection bit 0: P57/PWM11
1: P31/PWM10
0: DA1 output disabled
DA1 output enable bit
1: DA1 output enabled
DA2 output enable bit
0: DA2 output disabled
1: DA2 output enabled
0
1 : Conversion completed
4
5
6
7
Fig. 2.6.7 Structure of AD/DA control register
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At reset
3886 Group User’s Manual
0
0
0
R W
APPLICATION
2.6 PWM
2.6.3 PWM application example
(1) Control of VS tuner
Figure 2.6.8 shows a connection diagram, and Figure 2.6.9 shows the setting of relevant registers.
VS tuner
A NT
P56/DA1/PWM01
VT
Filter
0 – 32 V
3886 Group
Fig. 2.6.8 Connection diagram
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APPLICATION
2.6 PWM
Outline: • Control of VS tuner by using the 14-bit resolution PWM 0 output function
• f(X IN ) = 8 MHz
AD/DA control register (address 3416)
ADCON
0
Select P56/PWM01 output pin
PWM control register 1 (address 2E16)
PCTL1
1
Enable PWM0 output
Note: The PWM0 output function has priority even when
the bit corresponding to P56 pin of port P5 direction
register is set to the input mode.
PWM0H register (address 3016)
PWM0H
Set high-order 8 bits (N) of 14-bit data to be output
Note: Depending on data (N) of the high-order 8 bits, the period (250
✕ N) of “H” level during the sub-period (64 µs) is determined.
PWM0L register (address 3116)
PWM0L
Set low-order 6 bits (m) of 14-bit data to be output
Note: Depending on data (m) of the low-order 6 bits, the number of
sub-period to which the ADD bit is to be added within the
repetitive cycle consisting of 64 sub-periods is determined.
When output data is written to the PWM0L register, bit 7 of this
register becomes “1”. When completing to transfer data from
the PWM0L register to the PWM0 latch, bit 7 becomes “0”.
Fig. 2.6.9 Relevant registers setting
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APPLICATION
2.6 PWM
Control procedure: PWM waveform is output to the external by setting relevant registers shown
Figure 2.6.9. This PWM0 output is integrated through the low pass filter and
converted into DC signals for control of the VS tuner.
Figure 2.6.10 shows the control procedure.
ADCON (address 003416), bit4
0
P56/DA1/PWM01 pin set as the PWM output pin
PCTL1 (address 002E16), bit6
1
PWM0 enabled
PWM0H (address 003016)
PWM0L (address 003116)
Data to be
output
After setting data, PWM waveform
corresponding to the new data is output from
the next repetitive period.
Fig. 2.6.10 Control procedure
2.6.4 Notes on PWM
●For PWM 0 output, “L” level is output first.
●After data is set to the PWM0L and the PWM0H registers, PWM waveform corresponding to the new data
is output from next repetitive period.
PWM0 output data is Updated data is output from next
updated.
repetitive period.
Fig. 2.6.11 PWM 0 output
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APPLICATION
2.7 A-D converter
2.7 A-D converter
This paragraph explains the registers setting method and the notes relevant to the A-D converter.
2.7.1 Memory map
003416
AD/DA control register (ADCON)
003516
A-D conversion register 1 (AD1)
003816
A-D conversion register 2 (AD2)
003916
Interrupt source selection register (INTSEL)
003D16
Interrupt request register 2 (IREQ2)
003F16
Interrupt control register 2 (ICON2)
Fig. 2.7.1 Memory map of registers relevant to A-D converter
2.7.2 Relevant registers
AD/DA control register
b7 b6 b5 b4 b3 b2 b1 b0
AD/DA control register (ADCON) [Address : 3416 ]
B
Name
0
Analog input pin selection bits
2
4
5
6
7
b2 b1 b0
0
0
0
0
1
1
1
1
1
3
Function
0
0
1
1
0
0
1
1
0 : Conversion in progress
1 : Conversion completed
PWM0 output pin selection bit 0: P56/PWM01
1: P30/PWM00
PWM1 output pin selection bit 0: P57/PWM11
1: P31/PWM10
DA1 output enable bit
0: DA1 output disabled
1: DA1 output enabled
DA2 output enable bit
0: DA2 output disabled
1: DA2 output enabled
AD conversion completion bit
Fig. 2.7.2 Structure of AD/DA control register
2-114
0 : P60/AN0
1 : P61/AN1
0 : P62/AN2
1 : P63/AN3
0 : P64/AN4
1 : P65/AN5
0 : P66/AN6
1 : P67/AN7
3886 Group User’s Manual
At reset
0
1
0
0
0
0
R W
APPLICATION
2.7 A-D converter
A-D conversion register 1
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register 1 (AD1) [Address : 3516]
B
Function
At reset
0 The read-only register in which the A-D conversion’s results are
R W
?
✕
?
✕
b0
?
✕
b9 b8 b7 b6 b5 b4 b3 b2
?
✕
< 10-bit read>
?
✕
?
✕
6
?
✕
7
?
✕
stored.
1
2
b7
3
4
b7
5
< 8-bit read>
b0
b7 b6 b5 b4 b3 b2 b1 b0
Fig. 2.7.3 Structure of A-D conversion register 1
A-D conversion register 2
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register 2 (AD2) [Address : 38 16 ]
B
Name
Function
At reset
R W
?
✕
?
✕
0
✕
3
0
✕
4
0
✕
5
0
✕
6
0
✕
0 The read-only register in which the A-D conversion’s results are
stored.
1
b7
< 10-bit read>
b0
b9 b8
2 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
7 Conversion mode selection bit 0: 10-bit A-D mode
1: 8-bit A-D mode
0
Fig. 2.7.4 Structure of A-D conversion register 2
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APPLICATION
2.7 A-D converter
Interrupt source selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt source selection register (INTSEL) [Address 3916]
B
Name
I
N
T
0
/
i
n
p
u
t
b
u
ffer full interrupt
0
Function
0 : INT0 interrupt
1 : Input buffer full interrupt
source selection bit
0 : INT1 interrupt
1 INT1/output buffer empty
interrupt source selection bit
1 : Output buffer empty interrupt
0 : Serial I/O1 transmit interrupt ✽1
2 Serial I/O1 transmit/SCL,SDA
interrupt source selection bit
1 : SCL,SDA interrupt
✽1
0
: CNTR0 interrupt
C
N
T
R
0
/
S
C
L
,
S
D
A
i
n
t
e
r
r
u
p
t
3
1 : SCL,SDA interrupt
source selection bit
✽2
0 : Serial I/O2 interrupt
4 Serial I/O2/I2C interrupt
1 : I2C interrupt
source selection bit
✽2
0 : INT2 interrupt
5 INT2/I2C interrupt source
1 : I2C interrupt
selection bit
✽3
0 : CNTR1 interrupt
6 CNTR1/key-on wake-up
interrupt source selection bit
1 : Key-on wake-up interrupt
✽3
7 AD converter/key-on wake-up 0 : A-D converter interrupt
interrupt source selection bit
1 : Key-on wake-up interrupt
✽1: Do not write “1” to these bits simultaneously.
✽2: Do not write “1” to these bits simultaneously.
✽3: Do not write “1” to these bits simultaneously.
Fig. 2.7.5 Structure of Interrupt source selection register
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At reset
0
0
0
0
0
0
0
0
R W
APPLICATION
2.7 A-D converter
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2) [Address : 3D16]
B
Name
0 CNTR0/SCL, SDA interrupt
1
2
3
4
5
6
7
Function
At reset
0 : No interrupt request issued
1 : Interrupt request issued
request bit
0 : No interrupt request issued
CNTR1/key-on wake-up
1 : Interrupt request issued
interrupt request bit
0 : No interrupt request issued
Serial I/O2/I2C interrupt
1 : Interrupt request issued
request bit
0 : No interrupt request issued
INT2/I2C interrupt request bit
1 : Interrupt request issued
0 : No interrupt request issued
INT3 interrupt request bit
1 : Interrupt request issued
INT4 interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
AD converter/key-on wake-up 0 : No interrupt request issued
interrupt request bit
1 : Interrupt request issued
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
R W
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✕
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.7.6 Structure of Interrupt request register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2 (ICON2) [Address : 3F16]
B
Name
0 CNTR0/SCL, SDA interrupt
enable bit
1 CNTR1/key-on wake-up
interrupt enable bit
2 Serial I/O2/I2C interrupt
enable bit
3 INT2/I2C interrupt enable bit
4 INT3 interrupt enable bit
5 INT4 interrupt enable bit
6 AD converter/key-on wake-up
interrupt enable bit
7 Fix this bit to “0”.
Function
At reset
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
R W
0
0
0
0
0
0
Fig. 2.7.7 Structure of Interrupt control register 2
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APPLICATION
2.7 A-D converter
2.7.3 A-D converter application examples
(1) Conversion of analog input voltage
Outline : The analog input voltage input from a sensor is converted to digital values.
Figure 2.7.8 shows a connection diagram, and Figure 2.7.9 shows the relevant registers setting.
Sensor
P60/AN0
3886 Group
Fig. 2.7.8 Connection diagram
Specifications : •The analog input voltage input from a sensor is converted to digital values.
•P6 0/AN 0 pin is used as an analog input pin.
AD/DA control register (address 3416)
b7
ADCON
b0
0 0 0 0
Analog input pin : P60/AN0 selected
A-D conversion start
A-D conversion register 2 (address 3816)
b7
b0
(Read-only)
AD2
A-D conversion register 1 (address 3516)
b7
b0
(Read-only)
AD1
A result of A-D conversion is stored (Note).
Note: After bit 3 of ADCON is set to “1”, read out that contents.
When reading 10-bit data, read address 003816 before address 003516;
when reading 8-bit data, read address 003516 only.
When reading 10-bit data, bits 2 to 6 of address 003816 are “0”.
Fig. 2.7.9 Relevant registers setting
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APPLICATION
2.7 A-D converter
An analog input signal from a sensor is converted to the digital value according to the relevant
registers setting shown by Figure 2.7.9. Figure 2.7.10 shows the control procedure for 8-bit read, and
Figure 2.7.11 shows the control procedure for 10-bit read.
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
ADCON (address 3416)
•P60/AN0 pin selected as analog input pin
•A-D conversion start
XXXX00002
0
ADCON (address 3416), bit3 ?
•Judgment of A-D conversion completion
1
•Read out of conversion result
Read out AD1 (address 3516)
Fig. 2.7.10 Control procedure for 8-bit read
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
ADCON (address 3416)
•P60/AN0 pin selected as analog input pin
•A-D conversion start
XXXX00002
0
ADCON (address 3416), bit3 ?
•Judgment of A-D conversion completion
1
Read out AD2 (address 3816)
•Read out of high-order digit (b9, b8) of conversion result
Read out AD1 (address 3516)
•Read out of low-order digit (b7 – b0) of conversion result
Fig. 2.7.11 Control procedure for 10-bit read
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APPLICATION
2.7 A-D converter
2.7.4 Notes on A-D converter
(1) Analog input pin
Make the signal source impedance for analog input low, or equip an analog input pin with an external
capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application products on the
user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A-D conversion precision to be worse.
(2) A-D converter power source pin
The AVSS pin is an A-D converter power source pin. Regardless of using the A-D conversion function
or not, connect them as following :
• AV SS : Connect to the VSS line
● Reason
If the AV SS pin id opened, the microcomputer may have a failure because of noise or others.
(3) Clock frequency during A-D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A-D conversion.
• f(X IN ) is 500 kHz or more
• Do not execute the STP instruction
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APPLICATION
2.8 D-A Converter
2.8 D-A Converter
This paragraph explains the registers setting method and the notes relevant to the D-A converter.
2.8.1 Memory map
000B16
Port P5 direction register (P5D)
003416
AD/DA control register (ADCON)
003616
D-A1 conversion register (DA1)
003716
D-A2 conversion register (DA2)
Fig. 2.8.1 Memory map of registers relevant to D-A converter
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APPLICATION
2.8 D-A Converter
2.8.2 Relevant registers
Port P5 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P5 direction register
(P5D: address 0B16)
b
Name
0 Port P5 direction
register
1
2
3
4
5
6
7
Functions
0 : Port P50 input mode
1 : Port P50 output mode
0 : Port P51 input mode
1 : Port P51 output mode
0 : Port P52 input mode
1 : Port P52 output mode
0 : Port P53 input mode
1 : Port P53 output mode
0 : Port P54 input mode
1 : Port P54 output mode
0 : Port P55 input mode
1 : Port P55 output mode
0 : Port P56 input mode
1 : Port P56 output mode
0 : Port P57 input mode
1 : Port P57 output mode
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.8.2 Structure of Port P5 direction register
AD/DA control register
b7 b6 b5 b4 b3 b2 b1 b0
AD/DA control register
(ADCON: address 3416)
b
Name
0 Analog input pin
selection bits
1
2
3 AD conversion
completion bit
4 PWM0 output pin
selection bit
5 PWM1 output pin
selection bit
6 DA1 output enable
bit
7 DA2 output enable
bit
Functions
b2 b1 b0
0 0 0: P60/AN0
0 0 1: P61/AN1
0 1 0: P62/AN2
0 1 1: P63/AN3
1 0 0: P64/AN4
1 0 1: P65/AN5
1 1 0: P66/AN6
1 1 1: P67/AN7
0: Conversion in progress
1: Conversion completed
0: P56/PWM01
1: P30/PWM00
0: P57/PWM11
1: P31/PWM10
0: DA1 output disabled
1: DA1 output enabled
0: DA2 output disabled
1: DA2 output enabled
Fig. 2.8.3 Structure of AD/DA control register
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At reset R W
0
0
0
1
0
0
0
0
APPLICATION
2.8 D-A Converter
D-Ai conversion register
b7 b6 b5 b4 b3 b2 b1 b0
D-Ai conversion register (i = 1, 2)
(DAi: addresses 3616, 3716)
b
Functions
0 This is D-A output value stored bits. This is write
1 exclusive register.
2
3
4
5
6
7
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.8.4 Structure of D-Ai converter register
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APPLICATION
2.8 D-A Converter
2.8.3 D-A converter application example
(1) Speaker output volume modulation
Outline: The volume of a speaker output is modulated by using D-A converter.
Specifications: •Timer X modulates the period of sound for the pitch interval, so that a fixed pitch
(“la”: approx. 440 Hz) can be output. Modulating the amplitude with the D-A output
value controls the volume.
•Use f(X IN) = 6 MHz.
•Use DA1 (P5 6/DA1 pin) as D-A converter.
Figure 2.8.5 shows a peripheral circuit example and Figure 2.8.6 shows a speaker output example.
Figure 2.8.7 shows the relevant registers setting.
3886 Group
Amplification
circuit
Power
amplifier
P56/DA1
+
Fig. 2.8.5 Peripheral circuit example
Modulation of volume
VREF
(amplitude is set
by D-A1 output)
VSS
Timer X
interrupt
Timer X
interrupt
Timer X
interrupt
Timer X
interrupt
Modulation of pitch interval: 440 Hz
(Cycle is set by timer X)
Fig. 2.8.6 Speaker output example
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Timer X
interrupt
Timer X
interrupt
APPLICATION
2.8 D-A Converter
b7
b0
Port P5 direction register (P5D) (address 0B16)
0
P56/DA1: Input mode
b7
b0
1
AD/DA control register (ADCON) (address 3416)
DA1 output enabled
b7
b0
Timer XY mode register (TM) (address 2316)
0 0 1
Timer X count: Stop
Timer mode
b7
b0
Prescaler X (PREX) (address 2416)
0116
Set division ratio —1
b7
b0
Timer X (TX) (address 2516)
D616
Set division ratio —1
b7
b0
Interrupt request register 1 (IREQ1) (address 3C16)
0
Timer X interrupt request
b7
b0
Interrupt control register 1 (ICON1) (address 3E16)
1
Timer X interrupt: Enabled
b7
b0
D-A1 conversion register (DA1) (address 3616)
Set conversion value (n)
Analog voltage V =
b7
VREF × n
256
(n=0 to 255)
b0
0 0 0
Timer XY mode register (TM) (address 2316 )
Timer X count: Start
Fig. 2.8.7 Relevant registers setting
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APPLICATION
2.8 D-A Converter
When the registers are set as shown in Figure 2.8.7, the speaker output volume is modulated by the
D-A output value. Figure 2.8.8 shows the control procedure.
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SEI
CLT (Note 1)
CLD (Note 2)
•All interrupts disabled
.....
•Timer X interrupt disabled
•Set port P56 to input mode
•DA1 output enabled
•Timer Y: Timer mode, Timer X count: Stop
•Set “division ratio – 1” to Prescaler X
•Set “division ratio – 1” to Timer X
ICON1 (address 3E16), bit4
0
(address 0B16), bit6
P5D
0
ADCON (address 3416)
X1XXXXXX2
(address 2316)
TM
XX001XXX2
2–1
PREX (address 2416)
D616 – 1
(address 2516)
TX
1
WORK flag (Note 3)
0
IREQ1 (address 3C16), bit4
1
ICON1 (address 3E16), bit4
Set outp ut value (volume)
(address 3616)
DA1
CLI
(address 2316)
XX000XXX2
TM
•Timer X interrupt request bit cleared
•Timer X interrupt: Enabled
•D-A converter start
•All interrupts enabled
•Timer X count start
.....
Notes 1: When using Index X mode flag
2: When using Decimal mode flag
3: The WORK flag is a user flag for work. When this flag is
“1”, a value other than Vss is output from the DA output
pin. When this flag is “0”, Vss is output from the DA output
pin.
Main processing
Timer X interrupt process routine
Push registers to stack
•Push registers used in interrupt process routine
“0”
Value of WORK flag ?
“1”
Set value except Vss to D-A1 conversion
register.
Set “0” to WORK flag.
Pop registers
Set value of Vss to D-A1 conversion register.
Set “1” to WORK flag.
•Pop registers pushed to stack
RTI
Fig. 2.8.8 Control procedure
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APPLICATION
2.8 D-A Converter
2.8.4 Notes on D-A converter
(1) Vcc when using D-A converter
The D-A converter accuracy when Vcc is 4.0 V or less differs from that of when Vcc is 4.0 V or more.
When using the D-A converter, we recommend using a Vcc of 4.0 V or more.
(2) D-Ai conversion register when not using D-A converter
When a D-A converter is not used, set all values of the D-Ai conversion registers (i = 1, 2) to “00 16”.
The initial value after reset is “0016”.
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APPLICATION
2.9 Bus interface
2.9 Bus interface
This paragraph explains the registers setting method and the programming examples relevant to the bus
interface.
2.9.1 Memory map
002816
Data bus buffer register 0 (DBB0)
002916
Data bus buffer status register 0 (DBBSTS0)
002A16 Data bus buffer control register (DBBCON)
002B16 Data bus buffer register 1 (DBB1)
002C16 Data bus buffer status register 1 (DBBSTS1)
002F16
Port control register 2 (PCTL2)
003916
Interrupt source selection register (INTSEL)
003C16 Interrupt request register 1 (IREQ1)
003E16 Interrupt control register 1 (ICON1)
Fig. 2.9.1 Memory map of registers relevant to bus interface
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APPLICATION
2.9 Bus interface
2.9.2 Relevant registers
Data bus buffer register i
b7 b6 b5 b4 b3 b2 b1 b0
Data bus buffer register i (DBBi) (i=0, 1) [Address : 2816/2B16]
B
Name
Function
At reset
0 • Buffer register to write output data and read input data.
1
R W
?
• at write: data is written to output data buffer register.
• at read: the contents of input data buffer register are read out.
?
2
?
3
?
4
?
5
?
6
?
7
?
Note: Output data bus buffer and input data bus buffer are assigned to the same address.
The contents of output data bus buffer register cannot be read out.
Writing to input data bus buffer register is disabled.
Fig. 2.9.2 Structure of Data bus buffer register i
Data bus buffer status register i
b7 b6 b5 b4 b3 b2 b1 b0
Data bus buffer status register i (DBBSTSi) (i=0, 1) [Address 2916/2C16]
B
Name
Function
At reset
R W
0 : Buffer empty
1 : Buffer full
0 : Buffer empty
1 Input buffer full flag i
1 : Buffer full
U
s
e
r
d
e
f
i
n
a
b
l
e
f
l
a
g
s
(
T
h
i
s
f
l
a
g
c
a
n be defined by user freely.)
2
0
✕
0
✕
3 A0i flag
This flag indicates the condition of
A0i status when the IBFi flag is set.
4 User definable flags (This flag can be defined by user freely.)
0
5
0
6
0
7
0
0 Output buffer full flag i
0
✕
0
Fig. 2.9.3 Structure of Data bus buffer status register i
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APPLICATION
2.9 Bus interface
Data bus buffer control register
b7 b6 b5 b4 b3 b2 b1 b0
Data bus buffer control register (DBBCON) [Address 2A16]
B
Name
0 Data bus buffer enable bit
Function
At reset
0 : P50–P53, P8 I/O port
1 : Data bus buffer enabled
0
0 : Single data bus buffer mode
(P4 7 functions as I/O port.)
1 : Double data bus buffer mode
(P4 7 functions as S1 input.)
0
2 OBF0 output selection bit
0 : OBF00 valid
1 : OBF01 valid
0
3 OBF00 output enable bit
0 : P42 functions as port I/O pin.
1 : P42 functions as OBF00 output
pin.
0
4 OBF01 output enable bit
0 : P43 functions
1 : P43 functions
pin.
0 : P46 functions
1 : P46 functions
pin.
as port I/O pin.
as OBF01 output
0
as port I/O pin.
as OBF10 output
0
1 Data bus buffer function
selection bit
5 OBF10 output enable bit
6 Input level selection bit
0 : CMOS level input
1 : TTL level input
7 Fix this bit to “0”.
R W
0
0
Fig. 2.9.4 Structure of Data bus buffer control register
Interrupt source selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt source selection register (INTSEL) [Address 3916]
B
Name
0 INT0/input buffer full interrupt
Function
0 : INT0 interrupt
1 : Input buffer full interrupt
0 : INT1 interrupt
1 : Output buffer empty interrupt
0 : Serial I/O1 transmit interrupt ✽1
1 : SCL,SDA interrupt
✽1
0 : CNTR0 interrupt
1 : SCL,SDA interrupt
✽2
0 : Serial I/O2 interrupt
Serial I/O2/I2C interrupt
1 : I2C interrupt
source selection bit
✽2
0 : INT2 interrupt
INT2/I2C interrupt source
1 : I2C interrupt
selection bit
✽3
CNTR1/key-on wake-up
0 : CNTR1 interrupt
interrupt source selection bit
1 : Key-on wake-up interrupt
✽3
AD converter/key-on wake-up 0 : A-D converter interrupt
interrupt source selection bit
1 : Key-on wake-up interrupt
source selection bit
1 INT1/output buffer empty
interrupt source selection bit
2 Serial I/O1 transmit/SCL,SDA
interrupt source selection bit
3 CNTR0/SCL,SDA interrupt
source selection bit
4
5
6
7
✽1: Do not write “1” to these bits simultaneously.
✽2: Do not write “1” to these bits simultaneously.
✽3: Do not write “1” to these bits simultaneously.
Fig. 2.9.5 Structure of Interrupt source selection register
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At reset
0
0
0
0
0
0
0
0
R W
APPLICATION
2.9 Bus interface
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address : 3C16]
Name
B
0 INT0/input buffer full interrupt
request bit
1 INT1/output buffer empty
interrupt request bit
2 Serial I/O1 receive interrupt
request bit
3 Serial I/O1 transmit/SCL, SDA
interrupt request bit
4 Timer X interrupt request bit
5 Timer Y interrupt request bit
6 Timer 1 interrupt request bit
7 Timer 2 interrupt request bit
Function
At reset
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
R W
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.9.6 Structure of Interrupt request register 1
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E16]
B
Name
I
N
T
0
/
i
n
p
u
t
b
u
ffer full interrupt
0
1
2
3
4
enable bit
INT1/output buffer empty
interrupt enable bit
Serial I/O1 receive interrupt
enable bit
Serial I/O1 transmit/SCL, SDA
interrupt enable bit
Timer X interrupt enable bit
5 Timer Y interrupt enable bit
6 Timer 1 interrupt enable bit
7 Timer 2 interrupt enable bit
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset
R W
0
0
0
0
0
0
0
0
Fig. 2.9.7 Structure of Interrupt control register 1
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2.9 Bus interface
Port control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Port control register 2 (PCTL2) [Address 2F 16]
Name
B
0 P4 input level selection bit
At reset
R W
0: CMOS level input
(P42–P46)
1: TTL level input
1 P7 input level selection bit
0: CMOS level input
(P70–P75)
1: TTL level input
2 P4 output structure selection bit 0: CMOS
(P42, P43, P44, P46)
1: N-channel open-drain
0: Port P8/Port P8 direction
3 P8 function selection bit
register
1: Port P4 input register/Port P7
input register
0
✕
0
✕
0
✕
0
✕
4 INT2, INT3, INT4 interrupt
0: INT20, INT30, INT40 interrupt
1: INT21, INT31, INT41 interrupt
0: f(XIN)/16 (f(XCIN)/16 in lowspeed mode)
1: f(XCIN)
6 Oscillation stabilizing time set 0: Automatic set “0116” to timer 1
and “FF16” to prescaler 12
after STP instruction released
1: No automatic set
bit
0: Only software clear
7 Port output P42/P43 clear
1: Software clear and output data
function selection bit
bus buffer 0 reading
(system bus side)
0
✕
switch bit
5 Timer Y count source
selection bit
0
✕
0
✕
0
✕
Fig. 2.9.8 Structure of Port control register 2
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2.9 Bus interface
2.9.3 Bus interface overview
The 3886 group has the built-in bus interface of two bytes to activate itself as a slave microcomputer.
A slave microcomputer is the microcomputer which is operated owing to the host CPU’s indication. Data
is asynchronously transmitted/received between the host CPU and the slave microcomputer, through the
bus interface of these two bytes. Accordingly, the slave microcomputer can be treated as well as two
general peripheral LSIs on the host CPU side. Consequently, it is easy to change its function by updating
the slave’s program.
The performance overview of 3886 group’s built-in bus interface is as follows:
• 8-bit data bus
• Built-in data bus buffer of two levels for input and output each
• Possible externally to output input/output buffer state as status.
Figure 2.9.9 shows the bus interface block diagram.
Data bus
DBB1
Slave
CPU
Host CPU
Data bus
DBB2
3886 Group
Fig. 2.9.9 Bus interface block diagram
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2.9 Bus interface
2.9.4 Input/Output operation
(1) Input operation
The bus interface input operation is explained as the following:
➀ When the logical OR of Si (i = 0, 1) and W is “0”, the data bus status is latched into the data bus
buffer register i (DBBi) at the rising of W input signal.
➁ When the data is latched into the input data bus buffer register i, the IBFi flag of the data bus
buffer status register i is simultaneously set to “1”.
➂ When the IBFi flag is set to “1”, the input buffer full interrupt request occurs and the input buffer
full interrupt request bit is set to “1”.
➃ At the timing ➂, the A0 level is stored into bit 3 of the data bus buffer status register i. Bit 3
indicates that the contents of the input data bus buffer register i are data or a command.
(2) Output operation
The bus interface output operation is explained as the following:
➀ Writing data to the DBBi sets the OBFi flag of the data bus status register i to “1”.
➁ When the logical OR of Si, R and A0 is “0”, the contents of the output data bus buffer register i
are output on the system bus and the OBFi flag is simultaneously cleared to “0”.
➂ At the rising of the R input signal, the output buffer empty interrupt request occurs and the output
buffer empty interrupt request bit is set to “1”.
Table 2.9.1 Bus control signals and data bus status
Si
R
W
A0
0
0
1
0
Read
Output data
0
0
1
1
Read
Status information
0
1
0
0
Write
Input data (Data)
0
1
1
✕
0
✕
1
✕
Write
High impedance
Input data (Command)
—
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Data on data bus
APPLICATION
2.9 Bus interface
2.9.5 Relevant registers setting
Figure 2.9.10 shows the relevant registers setting.
Data bus buffer control register (address 2A16)
b7
DBBCON
b0
1 0 0 1
Enable data bus buffer
Select single data bus buffer mode
Validate OBF00
Set P42 to OBF00 pin
Interrupt source selection register (address 3916)
b7
b0
INTSEL
1 1
Select input buffer full interrupt
Select output buffer empty interrupt
< Input >
< Output >
Data bus buffer status register 0 (address 2916)
Data bus buffer status register 0 (address 2916)
b7
b0
b7
✕
DBBSTS0
DBBSTS0
b0
0
The condition of A00 status
is stored.
Confirm that the buffer is
empty (Note).
Data bus buffer register 0 (address 2816)
b7
Data bus buffer register 0 (address 2816)
b0
b7
DBB0
b0
DBB0
Input data is stored (Note).
Note: When the condition of A00 status is “0”, this is treated as
data.
When the condition is “1”, this is treated as a command.
Write output data.
Note: When using the output buffer empty interrupt, it is
unnecessary to check the output buffer full flag 0.
Fig. 2.9.10 Relevant registers setting
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2.9 Bus interface
Figure 2.9.11 shows the control procedure using the interrupt.
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
DBBCON (address 2A16)
XXXX10012
• Data bus buffer enabled
• Single data bus buffer mode selected
• OBF00 validated (P42 output)
INTSEL (address 3916)
XXXXXX112
• Input buffer full interrupt source selected
• Output buffer empty interrupt source selected
< Input >
< Output >
Read out DBBSTS0 (address 2916)
DBBSTS0 (address 2916), bit3 ?
Write data to DBB0(address 2816)
0
1
Read out DBB0 (address 2816) as command
Read out DBB0 (address 2816) as data
Fig. 2.9.11 Control procedure using interrupt
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2.10 Watchdog timer
2.10 Watchdog timer
This paragraph explains the registers setting method and the notes relevant to the watchdog timer.
2.10.1 Memory map
001E16
Watchdog timer control register (WDTCON)
003B16
CPU mode register (CPUM)
Fig. 2.10.1 Memory map of registers relevant to watchdog timer
2.10.2 Relevant registers
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog timer control register (WDTCON) [Address : 1E16]
Function
B
Name
0 Watchdog timer H (for read-out of high-order 6 bits)
At reset
R W
1
✕
1
1
✕
2
1
✕
3
1
✕
4
1
✕
5
1
✕
6 STP instruction disable bit
7 Watchdog timer H count
source selection bit
0 : STP instruction enabled
1 : STP instruction disabled
0 : Watchdog timer L underflow
1 : f(XIN)/16 or f(XCIN)/16
0
0
Fig. 2.10.2 Structure of Watchdog timer control register
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2.10 Watchdog timer
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
1
CPU mode register
(CPUM: address 3B16)
b
Name
0 Processor mode
bits
1
2 Stack page
selection bit
3 Fix this bit to “1”.
Functions
At reset R W
b1 b0
00 : Single-chip mode
01 : Memory expansion mode (Note)
10 : Microprocessor mode (Note)
11 : Not available
0 : 0 page
1 : 1 page
0
*
0
1
4 Port Xc switch bit
0: I/O port function
(oscillation stopped)
1: XCIN-XCOUT oscillation
function
0
5 Main clock (XINXOUT) stop bit
6 Main clock division
ratio selection bits
0: Oscillating
1: Stopped
0
b7 b6
1
7
0 0: φ=f(XIN)/2
(high-speed mode)
0 1: φ=f(XIN)/8
(middle-speed mode)
1 0: φ=f(XCIN)/2
(low-speed mode)
1 1: Not available
0
*: The initial value of bit 1 depends on the CNVss level.
Note: This mode is not available for M38869M8A/MCA/MFA or the
flash memory version.
Fig. 2.10.3 Structure of CPU mode register
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2.10 Watchdog timer
2.10.3 Watchdog timer application examples
(1) Detection of program runaway
Outline: If program runaway occurs, let the microcomputer reset, using the internal timer for detection
of program runaway.
Specifications: •An underflow of watchdog timer H is judged to be program runaway, and the
microcomputer is returned to the reset status.
•Before the watchdog timer H underflows, “0” is set into bit 7 of the watchdog timer
control register at every cycle in a main routine.
•High-speed mode is used as a main clock division ratio.
•An underflow signal of the watchdog timer L is supplied as the count source of
watchdog timer H.
Figure 2.10.4 shows a watchdog timer connection and division ratio setting; Figure 2.10.5 shows the
relevant registers setting; Figure 2.10.6 shows the control procedure.
Fixed
f(XIN) = 8 MHz
Watchdog timer L Watchdog timer H
1/16
1/256
1/256
Reset
circuit
Internal reset
RESET
STP instruction disable bit
STP instruction
Fig. 2.10.4 Watchdog timer connection and division ratio setting
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2.10 Watchdog timer
CPU mode register (address 3B16)
b7
CPUM
b0
0 0 0
0 0
Processor mode: Single-chip mode
Main clock (XIN-XOUT): Operating
Main clock division ratio: f(XIN)/2 (high-speed mode)
Watchdog timer control register (address 1E16)
WDTCON
b7
b0
0 0
1
Watchdog timer H (for read-out of high-order 6 bits)
Enable STP instruction
Watchdog timer H count source: Watchdog timer L underflow
Fig. 2.10.5 Relevant registers setting
RESET
Initialization
SEI
CLT
CLD
CPUM (address 3B16)
:
:
CLI
•All interrupts disabled
000XXX002
•Processor mode: Single-chip mode
•Main clock f(XIN): Operating
•High-speed mode selected as main clock division ratio
•Interrupts enabled
WDTCON (address 1E16), bit7,bit6
002
•Watchdog timer L underflow selected as Watchdog
timer H count source
•STP instruction enabled
Main processing
:
:
Fig. 2.10.6 Control procedure
2.10.4 Notes on watchdog timer
●Make sure that the watchdog timer does not underflow while waiting Stop release, because the watchdog
timer keeps counting during that term.
●When the STP instruction disable bit has been set to “1”, it is impossible to switch it to “0” by a program.
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2.11 Reset
2.11 Reset
2.11.1 Connection example of reset IC
1
VCC
Power source
M62022L
5 Output
RESET
4 Delay capacity
0.1 µF
GND
3
VSS
3886 Group
Fig. 2.11.1 Example of poweron reset circuit
Figure 2.11.2 shows the system example which switches to the RAM backup mode by detecting a drop of
the system power source voltage with the INT interrupt.
System power
source voltage
+5 V
VCC
+
7
VCC1
RESET
2
VCC2
INT
5
3
RESET
INT
VSS
1
V1 GND Cd
4
6
3886 Group
M62009L, M62009P, M62009FP
Fig. 2.11.2 RAM backup system
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2.11 Reset
2.11.2 Notes on RESET pin
Connecting capacitor
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the V SS pin. Use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
● Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
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2.12 Clock generating circuit
2.12 Clock generating circuit
This paragraph explains how to set the registers relevant to the clock generating circuit and describes an
application example.
2.12.1 Relevant registers
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
1
CPU mode register
(CPUM: address 3B16)
b
Name
0 Processor mode
bits
1
2 Stack page
selection bit
3 Fix this bit to “1”.
Functions
At reset R W
b1 b0
00 : Single-chip mode
01 : Memory expansion mode (Note)
10 : Microprocessor mode (Note)
11 : Not available
0 : 0 page
1 : 1 page
0
*
0
1
4 Port Xc switch bit
0: I/O port function
(oscillation stopped)
1: XCIN-XCOUT oscillation
function
0
5 Main clock (XINXOUT) stop bit
6 Main clock division
ratio selection bits
0: Oscillating
1: Stopped
0
b7 b6
1
7
0 0: φ=f(XIN)/2
(high-speed mode)
0 1: φ=f(XIN)/8
(middle-speed mode)
1 0: φ=f(XCIN)/2
(low-speed mode)
1 1: Not available
0
*: The initial value of bit 1 depends on the CNVss level.
Note: This mode is not available for M38869M8A/MCA/MFA or the
flash memory version.
Fig. 2.12.1 Structure of CPU mode register
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APPLICATION
2.12 Clock generating circuit
2.12.2 Clock generating circuit application example
(1) Status transition during power failure
Outline: The clock counts up every second by using the timer interrupt during a power failure.
Input port
(Note)
Power failure detection signal
3886 Group
Note: A signal is detected when input to input port, interrupt
input pin, or analog input pin.
Fig. 2.12.2 Connection diagram
Specifications: •Reducing power dissipation as low as possible while maintaining clock function
•Clock: f(X IN) = 8 MHz, f(X CIN) = 32.768 kHz
•Port processing
Input port: Fixed to “H” or “L” level externally.
Output port: Fixed to output level that does not cause current flow to the external.
(Example) Fix to “H” for an LED circuit that turns on at “L” output
level.
I/O port: Input port → Fixed to “H” or “L” level externally.
Output port → Output of data that does not consume current
VREF pin: Terminate A-D conversion operation
Stop VREF current dissipation by setting value of D-Ai conversion register
to “00 16”.
Figure 2.12.3 shows the status transition diagram during power failure and Figure 2.12.4 shows the
setting of relevant registers.
Reset released
Power failure detected
XIN
XCIN
Internal system clock
Middle-speed
mode
Low-speed mode
High-speed mode
Change internal system
clock to high-speed mode
After detection, change internal system clock to
low-speed mode and stop oscillating XIN-XOUT
XCIN-XCOUT oscillation function selected
Fig. 2.12.3 Status transition diagram during power failure
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2.12 Clock generating circuit
b7
b0
CPUM 0 0 0 0 1
0 0
CPU mode register (CPUM) (address 3B16)
Main clock: High-speed mode (f(XIN)/2) (Note 1)
b7
b0
CPUM 0 0 0 1 1
0 0
CPU mode register (CPUM) (address 3B16)
(Note 2)
Port XC: XCIN–XCOUT oscillation function
b7
b0
CPUM 1 0 0 1 1
0 0
CPU mode register (CPUM) (address 3B16)
Internal system clock: Low-speed mode (f(XCIN)/2)
b7
b0
CPUM 1 0 1 1 1
0 0
CPU mode register (CPUM) (address 3B16)
Main clock f(XIN): Stopped
Notes 1: This setting is necessary only when selecting the high-speed mode.
2: When selecting the middle-speed mode, bit 6 is “1”.
Fig. 2.12.4 Setting of relevant registers
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2.12 Clock generating circuit
Control procedure: To prepare for a power failure, set the relevant registers in the order shown
below.
●X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
••••
CPUM (address 3B16), bit7, bit 6
CPUM (address 3B16), bit 4
0, 0
1
When selecting main clock f(XIN)/2 (high-speed mode)
Port XC: XCIN-XCOUT oscillation function
••••
N
Detect power failure ?
≈
Y
CPUM (address 3B16), bit7, bit 6
CPUM (address 3B16), bit5
1, 0 (Note)
1 (Note)
Set timer interrupt to occurs every second.
Execute WIT instruction.
N
Internal system clock: f(XCIN)/2 (low-speed mode)
Main clock f(XIN) oscillation stopped
At power failure, clock count is performed during
timer interrupt processing (every second).
Return condition from power failure
completed ?
Y
Return processing from power failure
Note: Do not switch simultaneously.
≈
Fig. 2.12.5 Control procedure
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2.13 Standby function
2.13 Standby function
The 3886 group is provided with standby functions to stop the CPU by software and put the CPU into the
low-power operation.
The following two types of standby functions are available.
•Stop mode using STP instruction
•Wait mode using WIT instruction
2.13.1 Stop mode
The stop mode is set by executing the STP instruction. In the stop mode, the oscillation of both clocks (XIN–
XOUT, X CIN–X COUT) stop and the internal clock φ stops at the “H” level. The CPU stops and peripheral units
stop operating. As a result, power dissipation is reduced.
(1) State in stop mode
Table 2.13.1 shows the state in the stop mode.
Table 2.13.1 State in stop mode
State in stop mode
Item
Oscillation
Stopped.
CPU
Internal clock φ
Stopped.
I/O ports P0–P8
Retains the state at the STP instruction execution.
Stopped. (Timers 1, 2, X, Y)
Timer
Stopped at “H” level.
However, Timers X and Y can be operated in the event counter
mode.
PWM0, PWM1
Stopped.
Watchdog timer
Stopped.
Serial I/O1, Serial I/O2
Stopped.
However, these can be operated only when an external clock
is selected.
I 2C-BUS interface
A-D converter
Stopped.
D-A converter
Retains output voltage.
Comparator
Stopped.
Bus interface
Operating.
Stopped.
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2.13 Standby function
(2) Release of stop mode
The stop mode is released by a reset input or by the occurrence of an interrupt request. Note the
differences in the restoration process according to reset input or interrupt request, as described
below.
■Restoration by reset input
The stop mode is released by holding the RESET pin to the “L” input level during the stop mode.
Oscillation is started when all ports are in the input state and the stop mode of the main clock (X INX OUT) is released.
Oscillation is unstable when restarted. For this reason, time for stabilizing of oscillation (oscillation
stabilizing time) is required. The input of the RESET pin should be held at the “L” level until oscillation
stabilizes.
When the RESET pin is held at the “L” level for 16 cycles or more of X IN after the oscillation has
stabilized, the microcomputer will go to the reset state. After the input level of the RESET pin is
returned to “H”, the reset state is released in approximately 10.5 to 18.5 cycles of the X IN input.
Figure 2.13.1 shows the oscillation stabilizing time at restoration by reset input.
At release of the stop mode by reset input, the internal RAM retains its contents previous to the
reset. However, the previous contents of the CPU register and SFR are not retained.
For more details concerning reset, refer to “2.11 Reset”.
Stop mode
Oscillation
16 cycles or
stabilizing time more of XIN
Operating mode
Vcc
Time to hold internal reset state =
approximately 10.5 to 18.5 cycles of XIN input
RESET
XIN
(Note)
Execute Stop instruction
Note: Some cases may occur in which no waveform is input to XIN (in low-speed mode).
Fig. 2.13.1 Oscillation stabilizing time at restoration by reset input
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2.13 Standby function
■Restoration by interrupt request
The occurrence of an interrupt request in the stop mode releases the stop mode. As a result,
oscillation is resumed. The interrupts available for restoration are:
•INT0–INT 4
•CNTR0, CNTR1
•Serial I/O (1, 2) using an external clock
•Timer X, Y using an external event count
•Key input (key-on wake-up)
•Bus interface
•SCL/S DA
However, when using any of these interrupt requests for restoration from the stop mode, in order to
enable the selected interrupt, you must execute the STP instruction after setting the following conditions.
[Necessary register setting]
➀ Interrupt disable flag I = “0” (interrupt enabled)
➁ Timer 1 interrupt enable bit = “0” (interrupt disabled)
➂ Interrupt request bit of interrupt source to be used for restoration = “0” (no interrupt request
issued)
➃ Interrupt enable bit of interrupt source to be used for restoration = “1” (interrupts enabled)
For more details concerning interrupts, refer to “2.2 Interrupts”.
Oscillation is unstable when restarted. For this reason, time for stabilizing of oscillation (oscillation
stabilizing time) is required. For restoration by an interrupt request, waiting time prior to supplying
internal clock φ to the CPU is automatically generated✽2 by Prescaler 12 and Timer 1✽1. This waiting
time is reserved as the oscillation stabilizing time on the system clock side. The supply of internal
clock φ to the CPU is started at the Timer 1 underflow.
Figure 2.13.2 shows an execution sequence example at restoration by the occurrence of an INT 0
interrupt request.
✽1: If the STP instruction is executed when the oscillation stabilizing time set after STP instruction
released bit is “0”, “FF16” and “0116” are automatically set in the Prescaler 12 counter/latch and
Timer 1 counter/latch, respectively. When the oscillation stabilizing time set after STP instruction
released bit is “1”, nothing is automatically set to either Prescaler 12 or Timer 1. For this reason,
any suitable value can be set to Prescaler 12 and Timer 1 for the oscillation stabilizing time.
✽2: Immediately after the oscillation is started, the count source is supplied to the prescaler 12 so
that a count operation is started.
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2.13 Standby function
●When restoring microcomputer from stop mode by INT0 interrupt (rising edge selected)
Stop mode
XIN or XCIN
(System clock)
Oscillation stabilizing time
XIN; “H”
XCIN; in high-impedance state
INT0 pin
512 counts
“FF16”
Prescaler 12 counter
“0116”
Timer 1 counter
INT0 interrupt request bit
Peripheral device
Operating
CPU
Operating
Operating
Stopped
Execute STP
instruction
Stopped
INT0 interrupt signal
input (INT0 interrupt
request occurs)
Oscillation start
Prescaler 12 count start
Operating
512 counts down by
prescaler 12
Start supplying internal
clock φ to CPU
Accept INT0 interrupt
request
Note: f(XIN)/16 or f(XCIN)/16 is input as the prescaler 12 count source.
Fig. 2.13.2 Execution sequence example at restoration by occurrence of INT0 interrupt request
(3) Notes on using stop mode
■Restarting oscillation
Usually, when the MCU stops the clock oscillation by STP instruction and the STP instruction has
been released by an external interrupt source, the fixed values of Timer 1 and Prescaler 12 (Timer
1 = 0116, Prescaler 12 = FF 16) are automatically reloaded in order for the oscillation to stabilize. The
user can inhibit the automatic setting by writing “1” to bit 6 of the port control register 2 (address
002F16).
However, by setting this bit to “1”, the previous values, set just before the STP instruction was
executed, will remain in Timer 1 and Prescaler 12. Therefore, you will need to set an appropriate
value to each register, in accordance with the oscillation stabilizing time, before executing the STP
instruction.
•Reason
Oscillation will restart when an external interrupt is received. However, internal clock phi is supplied
to the CPU only when Timer 1 underflows. This ensures time for the clock oscillation using the
ceramic resonators to be stabilized.
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2.13 Standby function
■Clock restoration
After restoration from the stop mode to the normal mode by an interrupt request, the contents of
the CPU mode register previous to the STP instruction execution are retained. Accordingly, if both
main clock and sub clock were oscillating before execution of the STP instruction, the oscillation
of both clocks is resumed at restoration.
In the above case, when the main clock side is set as a system clock, the oscillation stabilizing
time for approximately 8,000 cycles of the XIN input is reserved at restoration from the stop mode.
At this time, note that the oscillation on the sub clock side may not be stabilized even after the
lapse of the oscillation stabilizing time of the main clock side.
2.13.2 Wait mode
The wait mode is set by execution of the WIT instruction. In the wait mode, oscillation continues, but the
internal clock φ stops at the “H” level.
The CPU stops, but most of the peripheral units continue operating.
(1) State in wait mode
The continuation of oscillation permits clock supply to the peripheral units except I 2C-BUS interface.
Table 2.13.2 shows the state in the wait mode.
Table 2.13.2 State in wait mode
State in wait mode
Item
Oscillation
Operating.
CPU
Stopped.
Internal clock φ
I/O ports P0–P8
Stopped at “H” level.
Timer
Retains the state at the WIT instruction execution.
Operating.
PWM0, PWM1
Operating.
Watchdog timer
Operating.
Serial I/O1, Serial I/O2
I 2C-BUS interface
Operating.
Stopped.
A-D converter
However, this operates when the system clock stop selection
bit (bit 6 of address 15 16) is “1”.
Operating.
D-A converter
Retains output voltage.
Comparator
Bus interface
Operating.
Operating.
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2.13 Standby function
(2) Release of wait mode
The wait mode is released by reset input or by the occurrence of an interrupt request. Note the
differences in the restoration process according to reset input or interrupt request, as described
below.
In the wait mode, oscillation is continued, so an instruction can be executed immediately after the
wait mode is released.
■Restoration by reset input
The wait mode is released by holding the input level of the RESET pin at “L” in the wait mode.
Upon release of the wait mode, all ports are in the input state, and supply of the internal clock
φ to the CPU is started. To reset the microcomputer, the RESET pin should be held at an “L” level
for 16 cycles or more of XIN. The reset state is released in approximately 10.5 cycles to 18.5 cycles
of the X IN input after the input of the RESET pin is returned to the “H” level.
At release of wait mode, the internal RAM retains its contents previous to the reset. However, the
previous contents of the CPU register and SFR are not retained.
Figure 2.13.3 shows the reset input time.
For more details concerning reset, refer to “2.11 Reset”.
Operating mode
Wait mode
Vcc
16 cycles of XIN
Time to hold internal reset state =
approximately 10.5 to 18.5 cycles of XIN input
RESET
XIN
(Note)
Execute WIT instruction
Note: Some cases may occur in which no waveform is input to XIN (in low-speed mode).
Fig. 2.13.3 Reset input time
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2.13 Standby function
■Restoration by interrupt request
In the wait mode, the occurrence of an interrupt request releases the wait mode and supply of the
internal clock φ to the CPU is started. At the same time, the interrupt request used for restoration
is accepted, so the interrupt processing routine is executed.
However, when using an interrupt request for restoration from the wait mode, in order to enable the
selected interrupt, you must execute the STP instruction after setting the following conditions.
[Necessary register setting]
➀ Interrupt disable flag I = “0” (interrupt enabled)
➁ Interrupt request bit of interrupt source to be used for restoration = “0” (no interrupt request issued)
➂ Interrupt enable bit of interrupt source to be used for restoration = “1” (interrupts enabled)
For more details concerning interrupts, refer to “2.2 Interrupts”.
(3) Notes on wait mode
■Clock restoration
If the wait mode is released by a reset when XCIN is set as the system clock and XIN oscillation is
stopped during execution of the WIT instruction, X CIN oscillation stops, XIN oscillations starts, and
X IN is set as the system clock.
In the above case, the RESET pin should be held at “L” until the oscillation is stabilized.
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2.14 Processor mode
2.14 Processor mode
This paragraph explains usage examples and others relevant to the processor mode.
(Support product: M38867M8A/E8A)
2.14.1 Memory map
003B16 CPU mode register (CPUM)
Fig. 2.14.1 Memory map of registers relevant to processor mode
2.14.2 Relevant registers
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
1
CPU mode register
(CPUM: address 3B16)
b
Name
0 Processor mode
bits
1
2 Stack page
selection bit
3 Fix this bit to “1”.
Functions
At reset R W
b1 b0
00 : Single-chip mode
01 : Memory expansion mode (Note)
10 : Microprocessor mode (Note)
11 : Not available
0 : 0 page
1 : 1 page
0
*
0
1
4 Port Xc switch bit
0: I/O port function
(oscillation stopped)
1: XCIN-XCOUT oscillation
function
0
5 Main clock (XINXOUT) stop bit
6 Main clock division
ratio selection bits
0: Oscillating
1: Stopped
0
b7 b6
1
7
0 0: φ=f(XIN)/2
(high-speed mode)
0 1: φ=f(XIN)/8
(middle-speed mode)
1 0: φ=f(XCIN)/2
(low-speed mode)
1 1: Not available
0
*: The initial value of bit 1 depends on the CNVss level.
Note: This mode is not available for M38869M8A/MCA/MFA or the
flash memory version.
Fig. 2.14.2 Structure of CPU mode register
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2.14 Processor mode
2.14.3 Processor mode usage examples
(1) External memory connection example unusing ONW (one wait) function
Outline: An external memory is accessed, using the microprocessor mode. The RAM which meets
the following conditions can be used at f(X IN) = 8 MHz:
•OE access time: t a(OE) ≤ 50 ns
•Data set up time at write: t su(D) ≤ 65 ns.
For example, the M5M5256BP-10, whose address access time is 100 ns, can be used.
Figure 2.14.3 shows the expansion example of 32-Kbytes ROM and RAM.
3886 group
C N VS S
AD15
ONW
M5M27C256AK-10
2
P30, P31
8
P4
8
P5
AD14
to
AD0
M5M5256BP-10
CE
S
A0 to A14
A0 to A14
74F04
15
EPROM
8
P6
DB0
to
D B7
8
D0 to D7
OE
SRAM
DQ1 to DQ8
OE
W
Memory map
000016
External RAM area
(M5M5256BP)
8
P7
000816
RD
WR
8
SFR area
004016 Internal RAM area
044016
P8
External RAM area
(M5M5256BP)
8 MHz
VCC = 5.0 V ±10 %
800016
External ROM area
(M5M27C256AK)
FFFF16
Fig. 2.14.3 Expansion example of 32-Kbytes ROM and RAM
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2.14 Processor mode
Figures 2.14.4 to 2.14.6 show the basic timing at 8 MHz (no wait) operating.
A0 t o A 7
Low-order address
(Port P0)
A8 t o A 1 4
High-order address
(Port P1)
S
(AD15)
tWL(RD)
td(AL–RD)
OE
125 ns—10 ns (min.)
125ns—40 ns (min.)
(3886 group’s RD)
ta(OE)
50 ns (max.)
Data
DQ1 to DQ8
(Port P2)
tsu(DB—RD)
65 ns (min.)
W
“H” level
(3886 group’s WR)
td(AL—RD)
tWL(RD)
ta(OE)
: RD delay time after address output of 3886 group
: RD pulse width of 3886 group
: Output enable access time of M5M5256BP
tsu(DB—RD) : Data bus set up time before RD of 3886 group
Fig. 2.14.4 Read cycle (OE access, SRAM)
A0 t o A 7
Low-order address
(Port P0)
A8 to A14
High-order address
(Port P1)
tPHL
CE
5.8 ns (max.)
OE
(3886 group’s RD)
tWL(RD)
td(AL—RD)
125 ns—10 ns (min.)
125 ns—40 ns (min.)
ta(OE)
50 ns (max.)
D0 to D7
(Port P2)
Data
tsu(DB—RD)
65 ns (min.)
tPHL
td(AL—RD)
tWL(RD)
: Output delay time of 74F04
: RD delay time after address output of 3886 group
: RD pulse width of 3886 group
ta(OE)
: Output enable access time of M5M27C256AK
tsu(DB—RD) : Data bus set up time before RD of 3886 group
Fig. 2.14.5 Read cycle (OE access, EPROM)
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2.14 Processor mode
A0 t o A 7
Low-order address
(Port P0)
A8 to A14
High-order address
(Port P1)
S
(AD15)
tWL(WR)
td(AL—WR)
W
(3886 group’s WR)
125 ns—10 ns (min.)
125 ns—40 ns (min.)
td(WR—DB)
65 ns (max.)
Data
DQ1 to DQ8
(Port P2)
tsu(D)
35 ns (min.)
OE
(3886 group’s RD)
“H” level
td(AL—WR) : WR delay time after address output of 3886 group
tWL(WR)
: WR pulse width of 3886 group
td(WR—DB) : Data bus delay time after WR of 3886 group
tsu(D)
: Data set up time of M5M5256BP
Fig. 2.14.6 Write cycle (W control, SRAM)
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2.14 Processor mode
(2) External memory connection example using ONW (one wait) function
Outline: When the access time of an external memory is slow, the ONW function is used.
When “L” level is input to the P32/ONW pin in the state that the CPU reads or writes, a read
or write cycle is extended by one cycle of φ. The RD or WR signal retains “L” level during
the extended time.
The ONW function is valid for read or write to addresses 0000 16 to 0007 16 and 044016 to
FFFF16.
Figure 2.14.7 shows the usage example using the ONW function.
3886 group
CNVSS
AD15
2
74F04
M5M27C256AK-10
P30, P31
ONW
8
P4
AD14
to
AD0
CE
15
M5M5256BP-10
S
A0 to A14
A0 to A14
EPROM
8
P5
D B0
to
D B7
8
D0 to D7
OE
SRAM
DQ1 to DQ8
OE
W
Memory map
000016 External RAM area
(M5M5256BP)
8
P6
000816
SFR area
004016 Internal RAM area
044016 External RAM area
RD
WR
(M5M5256BP)
8 M Hz
VCC = 5.0 V ± 10 %
800016
External ROM area
(M5M27C256AK)
FFFF16
Fig. 2.14.7 Usage example of ONW function
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2.14 Processor mode
(3) External memory connection example at f(X IN) = 8 MHz or more
Outline: When the access time of an external memory is fast, it is possible to use at f(X IN) = 8 MHz
or more. The RAM which meets the following conditions can be used at f(X IN) = 9 MHz:
•OE access time: t a(OE) ≤ 35 ns
•Data set up time at write: t su(D) ≤ 50 ns.
For example, the M5M5256BP-70, whose address access time is 70 ns, can be used.
Figure 2.14.8 shows the expansion example of 32-Kbytes ROM and RAM.
3886 group
CNVSS
AD15
ONW
2
M5M27C256AK-85
P30, P31
8
P4
8
P5
AD14
to
AD0
M5M5256BP-70
CE
S
A0 to A14
A0 to A14
74F04
15
EPROM
8
P6
DB0
to
DB7
8
D0 to D7
SRAM
DQ1 to DQ8
OE
OE
W
Memory map
000016
External RAM area
(M5M5256BP)
8
P7
000816
RD
WR
8
SFR area
004016 Internal RAM area
044016
P8
External RAM area
(M5M5256BP)
9MHz
VCC = 5.0 V ±10 %
800016
External ROM area
(M5M27C256AK)
FFFF16
Fig. 2.14.8 Expansion example of 32-Kbytes ROM and RAM at f(XIN) = 8 MHz or more
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2.14 Processor mode
Figures 2.14.9 to 2.14.11 show the basic timing at 9 MHz (no wait) operating.
A0 t o A 7
Low-order address
(Port P0)
A8 t o A 1 4
High-order address
(Port P1)
S
(AD15)
OE
tWL(RD)
td(AL—RD)
(3886 group’s RD)
111 ns—10 ns (min.)
111 ns—40ns (min.)
ta(OE)
35 ns (max.)
Data
DQ1 to DQ8
(Port P2)
tsu(DB—RD)
50 ns (min.)
WR
“H” level
td(AL—RD)
tWL(RD)
: RD delay time after address output of 3886 group
: RD pulse width of 3886 group
: Output enable access time of M5M5256BP
ta(OE)
tsu(DB—RD) : Data bus set up time before RD of 3886 group
Fig. 2.14.9 Read cycle (OE access, SRAM)
A0 t o A 7
Low-order address
(Port P0)
A8 to A14
High-order address
(Port P1)
tPHL
CE
5.8 ns (max.)
tWL(RD)
td(AL—RD)
OE
(3886 group’s RD)
111 ns—10ns (min.)
111 ns—40 ns (min.)
ta(OE)
45 ns (max.)
Data
D0 to D7
(Port P2)
tsu(DB—RD)
50 ns (min.)
WR
“H” level
tPHL
td(AL—RD)
tWL(RD)
ta(OE)
tsu(DB—RD)
: Output delay time of 74F04
: RD delay time after address output of 3886 group
: RD pulse width of 3886 group
: Output enable access time of M5M27C256AK
: Data bus set up time before RD of 3886 group
Fig. 2.14.10 Read cycle (OE access, EPROM)
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2.14 Processor mode
A0 t o A 7
Low-order address
(Port P0)
A8 t o A 1 4
High-order address
(Port P1)
S
(AD15)
tWL(WR)
111 ns—10 ns (min.)
td(AL—WR)
W
(3886 group’s WR)
111 ns—35 ns (min.)
td(WR—DB)
30 ns (max.)
DQ1 to DQ8
Data
(Port P2)
tsu(D)
30 ns (min.)
OE
“H” level
(3886 group’s RD)
td(AL—WR) : WR delay time after address output of 3886 group
tWL(WR)
: WR pulse width of 3886 group
td(WR—DB) : Data bus delay time after WR of 3886 group
tsu(D)
: Data set up time of M5M5256BP
Fig. 2.14.11 Write cycle (W control, SRAM)
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2.15 Flash memory
2.15 Flash memory
This paragraph explains the registers setting method and the notes relevant to the flash memory version.
2.15.1 Overview
The functions of the flash memory version are similar to those of the mask ROM version except that the
flash memory is built-in and some of the SFR area differ from that of the mask ROM version (refer to
“2.15.2 Memory map”).
In the flash memory version, the built-in flash memory can be programmed or erased by using the following
three modes.
• CPU reprogramming mode
• Parallel input/output mode
• Serial input/output mode
2.15.2 Memory map
M38869FFAHP/GP have 60 Kbytes of built-in flash memory.
Figure 2.15.1 shows the memory map of the flash memory version.
000016
SFR area
004016
Internal RAM area
(2 Kbytes)
RAM
083F16
084016
User ROM area
Not used
0FF016
0FFF16
100016
SFR area
28 Kbytes
Not used
100016
7FFF16
800016
Built-in flash memory area
(60 Kbytes)
32 Kbytes
FFFF16
FFFF16
Fig. 2.15.1 Memory map of flash memory version for 3886 Group
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2.15 Flash memory
2.15.3 Relevant registers
0FFE16 Flash memory control register (FCON)
0FFF16
Flash command register (FCMD)
Fig. 2.15.2 Memory map of registers relevant to flash memory
Flash memory control register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Flash memory control register
(FCON : address FFE16)
b
Name
Functions
At reset R W
0 CPU reprogramming 0 : CPU reprogramming
mode select bit
mode is invalid. (Normal
(Note)
operation mode)
1 : When applying 0 V to
CNVSS/VPP pin, CPU
reprogramming mode is
invalid. When applying
VPPH to CNVSS/VPP pin,
CPU reprogramming
mode is valid.
0 : Erase and program are
1 Erase/Program
completed or have not
busy flag
been executed.
1 : Erase/program is being
executed.
CPU
reprogramming
0 : CPU reprogramming
2
mode monitor flag
mode is invalid
1 : CPU reprogramming
mode is valid
0
3 Fix this bit to “0”.
4 Erase/Program
area select bits
0
0
5
b5 b4
0 0: Address 100016 to
FFFF16 (total 60Kbytes)
0 1: Address 100016 to
7FFF16 (total 28Kbytes)
1 0: Address 800016 to
FFFF16 (total 32Kbytes)
1 1: not available
6 Fix this bit to “0”.
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0
0
0
0
Note: Bit 0 can be reprogrammed only when 0 V is applied to the CNVSS/VPP pin.
Fig. 2.15.3 Structure of Flash memory control register
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2.15 Flash memory
Flash command register
b7 b6 b5 b4 b3 b2 b1 b0
Flash command register
(FCMD: address FFF16)
b
Functions
0
1
2
3
4
5
6
7
Writing of software command
<Software command name>
• Read command
• Program command
• Program verify command
• Erase command
• Erase verify command
• Reset command
At reset R W
0
0
0
0
0
0
0
0
Note: The flash command register is a write-only register.
<Command code>
• “0016”
• “4016”
• “C016”
• “2016”+ “2016”
• “A016”
• “FF16” + “FF16”
Fig. 2.15.4 Structure of Flash command register
2.15.4 Parallel I/O mode
In the parallel I/O mode, program/erase to the built-in flash memory can be performed by a general EPROM
programmer.
Set the programming mode of the EPROM programmer to M5M28F101 and set the memory area of
program/erase from 0100016 to 0FFFF16. Be especially careful when erasing; if the memory area is not set
correctly, the products will be damaged eternally.
Table 2.15.1 shows the setting of EPROM programmers when programming in the parallel I/O mode.
Table 2.15.1 Setting of EPROM programmers when parallel programming
Products
M38869FFAHP
Programming adapter
PCA4738HF-80
M38869FFAGP
PCA4738GF-80
2-164
Programming mode
Memory area
M5M28F101
01000 16 to 0FFFF16
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2.15 Flash memory
2.15.5 Serial I/O mode
Table 2.15.2 shows a pin connection example using MSP-I/MSP-II ✼ between the programmer and the
microcomputer when programming in the serial I/O mode.
✼
MSP-I/MSP-II provided by Suisei Electronics System Co., Ltd. (http://www.suisei.co.jp/index_e.htm)
(product available in Asia and Oceania only)
Table 2.15.2 Connection example to programmer when serial programming
MSP-I/MSP-II
Signal name
3886 Group flash memory version
Target connector
Pin name
Pin number
Line number
BUSY
1
P47/SRDY1
18
VPP (Note 1)
2
CNVSS (Note 1)
24
VDD (Note 3)
3
VCC (Note 3)
71
SCL
SDA
4
5
P46/S CLK1
P44/RxD
19
21
PGM/OE
6
P37
55
RESET
7
RESET
25
30, 73
GND (Note 2)
8
VSS, AV SS (Note 2)
Notes 1: Connect an approximate 0.01 µF capacitor between CNVSS/VPP and GND for noise elimination.
2: When connecting a serial programmer, first connect both GNDs to the same GND level.
3: When the VCC power is already supplied to the target board, do not connect the VDD supply pin
of the serial programmer to V CC of the target board.
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2.15 Flash memory
2.15.6 CPU reprogramming mode
In the CPU reprogramming mode, issuing software commands through the Central Processing Unit (CPU)
can reprogram the built-in flash memory. Accordingly, the contents of the built-in flash memory can be
reprogrammed with the microcomputer itself mounted on board, without using the EPROM programmer.
Store the reprogramming control program to the built-in flash memory in advance. The built-in flash memory
cannot be read in the CPU reprogramming mode. Accordingly, after transferring the reprogramming control
program to the internal RAM, execute it on the RAM.
The following commands can be used in the CPU reprogramming mode: read, program, program verify,
erase, erase verify, and reset. For details concerning each command, refer to “CHAPTER 1 Flash memory
mode 3 (CPU reprogramming mode)”.
(1) CPU reprogramming mode beginning/release procedures
Operation procedure in the CPU reprogramming mode for the built-in flash memory is described
below.
As for the control example, refer to “2.15.7 (2) Control example in the CPU reprogramming mode.”
[Beginning procedure]
➀ Apply 0 V to the CNV SS/V PP pin for reset release.
➁ After CPU reprogramming mode control program is transferred to internal RAM, jump to this
control program on RAM. (The following operations are controlled by this control program).
➂ Set “1” to the CPU reprogramming mode select bit (bit 0 of address 0FFE 16).
➃ Apply V PPH to the CNVSS/V PP pin.
➄ Wait until CNV SS/V PP pin becomes 12 V.
➅ Read the CPU reprogramming mode monitor flag (bit 2 of address 0FFE16) to confirm that the
CPU reprogramming mode is valid.
➆ Flash memory operations are executed by writing software-commands to the flash command
register (address 0FFF16).
Note: The following procedures are also necessary.
• Control for data which is input from the external (serial I/O etc.) and to be programmed
to the flash memory.
• Initial setting for ports, etc.
• Writing to the watchdog timer
[Release procedure]
➀ Apply 0 V to the CNV SS/V PP pin.
➁ Wait until CNV SS/VPP pin becomes 0 V.
➂ Set the CPU reprogramming mode select bit (bit 0 of address 0FFE16) to “0”.
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2.15 Flash memory
Also, execute the following processing before the CPU reprogramming mode is selected so that interrupts
will not occur during the CPU reprogramming mode.
• Set the interrupt disable flag (I) to “1”
In the CPU reprogramming mode, write to the watchdog timer control register (address 1E16) periodically
to prevent the generation of a reset by the underflow of the watchdog timer H.
In the program state (programming time: max. 9.5 µs), watchdog timer H and L are set to “FF16”, and the
count stop. The count is started again after the program state or the erase state is completed. Accordingly,
the write period of the watchdog timer control register is calculated except for the program time and erase
time.
When the interrupt request or reset occurs in the CPU reprogramming mode, the microcomputer enters the
following states;
(1) Interrupt
This may cause a program runaway because the flash memory that has an interrupt vector area cannot
be read.
(2) Underflow of watchdog timer H, reset
This may cause a microcomputer reset; the built-in flash memory control circuit and the flash memory
control register are reset.
Also, note that, when the interrupt or reset occurs during program/erase, error data may still exist after
reset release because the reprogramming of the flash memory has not been completed. In this case,
setting the proper program code to the flash memory in the parallel I/O mode or serial I/O mode is required.
2.15.7 Flash memory mode application examples
The control pin processing example on the system board in the serial I/O mode and the control example
in the CPU reprogramming mode are described below.
(1) Control pin connection example on the system board in serial I/O mode
As shown in Figure 2.15.5, in the serial I/O mode, the built-in flash memory can be reprogrammed
with the microcomputer mounted on board. Connection examples of control pins (P37, P44, P46, P47,
CNVSS and RESET pin) in the serial I/O mode are described below.
RS-232C Serial programmer
Master ROM
M3
88
69
FF
Fig. 2.15.5 Reprogramming example of built-in flash memory in serial I/O mode
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2.15 Flash memory
➀ When control signals are not affected to user system circuit
When the control signals in the serial I/O mode are not used or not affected to the user system
circuit, they can be connected as shown in Figure 2.15.6.
Target board
*
Not used or to user system circuit
M38869FF
SDA(P44)
SCLK(P46)
OE(P37)
BUSY(P47)
VCC
AVSS
VPP(CNVSS)
RESET
VSS
XIN XOUT
User reset signal (Low active)
* : When not used, set to input mode and pull up or pull down, or set to output mode and open.
Fig. 2.15.6 Connection example in serial I/O mode (1)
➁ When control signals are affected to user system circuit-1
Figure 2.15.7 shows an example that the jumper switch cut-off the control signals not to supply
to the user system circuit in the serial I/O mode.
Target board
To user system circuit
M38869FF
SDA(P44)
SCLK(P46)
OE(P37)
BUSY(P47)
VCC
AVSS
VSS
VPP(CNVSS)
RESET
User reset signal (Low active)
Fig. 2.15.7 Connection example in serial I/O mode (2)
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3886 Group User’s Manual
XIN XOUT
APPLICATION
2.15 Flash memory
➂ When control signals are affected to user system circuit-2
Figure 2.15.8 shows an example that the analog switch (74HC4066) cut-off the control signals not
to supply to the user system circuit in the serial I/O mode.
Target board
74HC4066
To user system circuit
M38869FF
SDA(P44)
SCLK(P46)
OE(P37)
BUSY(P47)
VCC
AVSS
VSS
VPP(CNVSS)
RESET
XIN XOUT
User reset signal (Low Active)
Fig. 2.15.8 Connection example in serial I/O mode (3)
3886 Group User’s Manual
2-169
APPLICATION
2.15 Flash memory
(2) Control example in CPU reprogramming mode
In this example, the built-in flash memory is reprogrammed in the CPU reprogramming mode by
serial I/O, receiving the reprogramming data (updated data).
Figure 2.15.9 shows an example of the reprogramming system for the built-in flash memory in the
CPU reprogramming mode.
M38869FF
Port for CPU reprogramming mode
switch
(CPU reprogramming mode is
selected/released by port Pi2 input signal)
Pi2
VCC
Pi0
CLK1
Reprogramming data input control
(Updated data is received by serial I/O)
RxD1
VSS
TxD1
VPP circuit control port
ON/OFF of VPP control
circuit is controlled by
port Pi1 output.
0V
VPP *
control
circuit
12V
Pi1
VPP(CNVSS)
RESET
User reset signal
XIN XOUT
10 MHz
(i = 0 to 8)
* Refer to Figure 2.15.14 and Figure 2.15.15.
Fig. 2.15.9 Example of reprogramming system for built-in flash memory in CPU reprogramming
mode
● Specifications
➀ CPU reprogramming mode is selected/released by the input signal to Pi 2.
➁ Updated data is received by serial I/O.
➂ The transfer enable state of serial transmit side is judged by “L” level input to Pi 0.
➃ V PP control circuit is turned ON/OFF by the output from Pi 1 (refer to Figure 2.15.14 and Figure
2.15.15).
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3886 Group User’s Manual
APPLICATION
2.15 Flash memory
Note: In this example, the following program is transferred to and executed on the internal
RAM.
In this program example, the flash memory is reprogrammed by
CPU reprogramming
control program example receiving each 1 byte of data from seri al I/O.
➀ Preparing for transition to CPU
reprogramming mode
Serial I/O initialization
set
Disable the interrupt of built-in
peripheral functions in this processing.
Also, initialize watchdog timer (write to
watchdog timer control register) to
prevent generation of watchdog timer
interrupt.
Interrupt disable processing
CPU reprogramming mode
select bit = “1”
12 V applied circuit
to VPP “ON”
Port Pi1 = “1”
Apply VPP voltage = VPPH
waiting for stabilization *1
➁ Transition to CPU reprogramming mode
NO
Initialize watchdog timer (write to
watchdog timer control register) to prevent
generation of watchdog timer interrupt
during this processing.
CPU reprogramming
mode monitor flag
= “1” ?
YES
Wait 5 ms
NO
*2
Confirmation that CPU
reprogramming mode
is valid.
CPU reprogramming
mode monitor flag
= “1” ?
YES
Continued to “CPU reprogramming control
program example (2)” on the next page.
*1: Waiting by software until VPP input voltage is stabilized at VPPH
is recommended. (Refer to Figures 2.15.14 and 2.15.15 VPP voltage control timing A .)
*2: The waiting time depends on VPP control circuit (Refer to Figures
2.15.14 and 2.15.15 VPP voltage control timing C .)
Fig. 2.15.10 CPU reprogramming control program example (1)
3886 Group User’s Manual
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APPLICATION
2.15 Flash memory
Continued from “CPU
reprogramming control program
example (1)” on previous page.
YES
All addresses
= “0016” ?
NO
Program/program verify
processing
All bytes = “0016”
Refer to “➃ Program/program verify” for
program/program verify flow chart.
Set erase verify
start address
Initialization of software
counter (retry counter) for
erasure retry counter = “0”
➂ Erasure of reprogramming area
From b (next
page)
Retry counter + 1
“2016” is written twice continuously
to flash command register
(address 0FFF16)
Issue erase command
Wait 1 µs *1
NO
Erase/program
busy flag = “0” ?
YES
Issue erase verify command
“A016” is written to flash
command register
(address 0FFF16)
Wait 6 µs *2
To a (next
page)
FAIL
Erase verify
data check
PASS
Erase verify
last address
YES
NO
Erase verify address +1
Continued to “CPU reprogramming control
program example (4)” on the page after next
*1: The wait processing time shown in the flow chart is required
regardless of the external clock input frequency.
*2: The waiting time depends on VPP control circuit (Refer to Figure
2.15.14 and Figure 2.15.15 VPP voltage control timing C.)
Fig. 2.15.11 CPU reprogramming control program example (2)
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3886 Group User’s Manual
Initialize watchdog timer (write to watchdog
timer control register) to prevent generation
of watchdog timer interrupt during this
processing.
APPLICATION
2.15 Flash memory
Continued to “CPU reprogramming
control program example (2)” on
previous page
Continued from “CPU reprogramming
control program example (2)” on
previous page
a
b
Continued from ➂
NO
Retry counter
=1000 ?
YES
Port Pi1 = “0”
Apply VPP voltage = VPPL
waiting for stabilizing *1
NO
CPU reprogramming
mode monitor flag
= “0” ?
YES
Wait 5 ms *2
➄ CPU reprogramming mode release
Initialize watchdog timer (write to
watchdog timer control register) to
prevent generation of watchdog timer
interrupt during this processing.
CPU reprogramming mode
select bit = “0”
NO
CPU reprogramming
mode select bit
= “0”
YES
CPU reprogramming error
*1: Waiting by software until VPP input voltage is stabilized at VPPL
is recommended. (Refer to Figure 2.15.14 and Figure 2.15.15
VPP voltage control timing B.)
*2: The wait time depends on VPP control circuit (Refer to Figure
2.15.14 and Figure 2.15.15 VPP voltage control timing C.)
Fig. 2.15.12 CPU reprogramming control program example (3)
3886 Group User’s Manual
2-173
APPLICATION
2.15 Flash memory
Continued from “CPU reprogramming control
program example (2)” on page before previous
Set program start address
Initialization of software counter
(retry counter) for reprogramming
retry count = “0”
➃ Program/program verify
Initialize watchdog timer (write to
watchdog timer control register) to
prevent generation of watchdog
timer interrupt during this
processing.
Reprogramming data receive
from serial I/O
Retry counter + 1
“4016” is writ ten to fla sh
co m m a n d r e g i st e r
(addres s 0FFF16)
Issue program command
Reprogramming data is written
to program address
Wait 1 µs *1
NO
Erase/program
busy flag = “0” ?
Waiting for program
completed
YES
Issue program verify command
“C016” is written to flash
comma nd register
(addres s 0FFF16)
Wait 6 µs *1
FAIL
NO
Program verify
data check
PASS
Retry counter
= 25?
Program last address
NO
YES
YES
Port Pi1 = “0”
Apply VPP voltage = VPPL
waiting for stabilizing *2
Port Pi1 = “0”
Program address + 1
12 V applied circuit
to VPP “OFF”
Apply VPP voltage = VPPL
waiting for stabilizing *2
NO
CPU reprogramming
mode monitor flag
= “0” ?
YES
NO
Wait 5 ms *3
Wait 5 ms *3
CPU reprogramming mode
select bit = “0”
CPU reprogramming
mode select bit
= “0”
YES
CPU reprogramming error
Initialize watchdog timer (write to
watchdog timer control register) to
prevent generation of watchdog timer
interrupt during this processing.
YES
CPU reprogramming
mode select bit = “0”
NO
➄ CPU reprogramming mode release
CPU reprogramming
mode monitor flag
= “0” ?
Waiting for release of CPU
reprogramming mode
NO
CPU reprogramming
mode select bit
= “0”
YES
END
*1: The wait processing time shown in the flow chart is required regardless of the external clock input frequency.
*2: Waiting by software until VPP input voltage is stabilized at VPPL is recommended. (Refer to Figure 2.15.14 and
Figure 2.15.15 VPP voltage control timing B.)
*3: The waiting time depends on VPP control circuit (Refer to Figure 2.15.14 and Figure 2.15.15 VPP voltage control
timing C.)
Fig. 2.15.13 CPU reprogramming control program example (4)
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3886 Group User’s Manual
APPLICATION
2.15 Flash memory
● When 12 V voltage is supplied to target system
VIN=12V
At Pi1 = L output, VPP = 11.8 V
At Pi1 = H output, VPP = 0 V
2SA1364
System power source
VPP
RT1N144C
30 kΩ
1000 pF
➀ M5237L ➂
➁
220 Ω
47 kΩ
2.7 kΩ
at OFF signal = 3 V
5 kΩ
47 µF
10 kΩ
1 kΩ
Pi1 (VPP circuit control port)
ON/OFF signal
MC2848
4.3 kΩ
0.33 µF
Input ON/OFF signal
so that this point
is 1.5 V or more at OFF
state of VPP output.
VPP voltage control timing
Pi1 = H
Pi1 = L
VPP = 12 V
C
VPP = 0 V
C
A
B
Transition to CPU reprogramming
mode enable cannot be allowed
until VPP = VPPH.
Transition to CPU reprogramming
mode disable cannot be allowed
until VPP = VPPL.
Fig. 2.15.14 V PP control circuit example (1)
● When only 5 V voltage is supplied to target system
VIN=5 V
At Pi1 = L output, VPP = 12 V
At Pi1 = H output, VPP = 0 V
Schottky
Diode
100 µH
RT1P137P
System power source
VPP
100 µF
1 kΩ
22 kΩ
RT1N144C
➆
E OUT ➁
M62212FP
0.1 µF
FB
DTC
GND
➅
➄
➂
RT1N144C
22 kΩ
10 kΩ
100 µF 0.1 µF
2SD1972
1 kΩ
IN
47 kΩ
3.9 kΩ
C OUT
➃ COSC
100 pF
10 kΩ
33 kΩ
➀
➇
VCC
10 kΩ
1 kΩ
Keep VF as
small as
possible.
100 Ω
Set radiation about
0.36 W ✕ 5
0.1 µF
1 kΩ
(VPP circuit control port) Pi
2SC3580
ON/OFF signal
47 kΩ
47 kΩ
VPP voltage control timing
Pi1 = H
Pi1 = L
VPP = 12 V
C
VPP = 0 V
A
Transition to CPU reprogramming
mode enable cannot be allowed
until VPP = VPPH.
C
B
Transition to CPU reprogramming
mode disable cannot be allowed
until VPP = VPPL.
Fig. 2.15.15 VPP control circuit example (2)
3886 Group User’s Manual
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APPLICATION
2.15 Flash memory
2.15.8 Notes on CPU reprogramming mode
(1) Transfer the CPU reprogramming mode control program to the internal RAM before selecting the
CPU reprogramming mode, and then, execute it on the internal RAM. Additionally, when the subroutine
or stack operation instruction is used in the control program, make sure the control program is not
destroyed by the stack operation.
(2) Make sure each instruction description (specified address etc.) is correct, because the CPU reprogramming
mode control program is transferred to the internal RAM and executed on the internal RAM.
(3) In order to avoid generation of a watchdog timer reset, write to the watchdog timer control register
periodically during the CPU reprogramming mode control program (refer to “2.7 Watchdog timer”).
(4) Notes on flash memory version
The CNVSS pin is connected to the internal memory circuit block by a low-ohmic resistance, since it
works as a program power source pin (V PP pin), as well.
To improve the noise margin, connect the CNV SS pin to V SS through 1 to 10 kΩ resistor.
When the CNVSS pin of the mask ROM version is connected to Vss through this resistor, the function
of mask ROM version works well in the same manner as flash memory version.
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3886 Group User’s Manual
CHAPTER 3
APPENDIX
3.1 Electrical characteristics
3.2 Standard characteristics
3.3 Notes on use
3.4 Countermeasures against noise
3.5 List of registers
3.6 Package outline
3.7 List of instruction code
3.8 Machine instructions
3.9 SFR memory map
3.10 Pin configurations
APPENDIX
3.1 Electrical characteristics
3.1 Electrical characteristics
3.1.1 Absolute maximum ratings
Table 3.1.1 Absolute maximum ratings
Symbol
VCC
VCC
VI
VI
VI
VI
VI
VI
VO
VO
Pd
Topr
Tstg
Notes 1:
2:
3:
4:
5:
3-2
Parameter
Power source voltageS (Note 1)
Power source voltageS (Note 2)
Input voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67, P80–P87, VREF
Input voltage P70–P77
Input voltage RESET, XIN
Input voltage CNVSS (Note 3)
Input voltage CNVSS (Note 4)
Input voltage
CNVSS (Note 5)
Output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67, P80–P87, XOUT
Output voltage P70–P77
Power dissipation
Operating temperature
Storage temperature
Conditions
All voltages are based on VSS.
Output transistors are cut off.
Ta = 25 °C
M38867M8A, M38867E8A
M38869M8A, M38869MCA, M38869MFA, M38869FFA
M38867M8A
M38869M8A, M38869MCA, M38869MFA
M38867E8A, M38869FFA
3886 Group User’s Manual
Ratings
–0.3 to 7.0
–0.3 to 6.5
Unit
V
V
–0.3 to VCC +0.3
V
–0.3 to 5.8
–0.3 to VCC +0.3
–0.3 to 7
–0.3 to VCC +0.3
–0.3 to 13
V
V
V
V
V
–0.3 to VCC +0.3
V
–0.3 to 5.8
500
–20 to 85
–40 to 125
V
mW
°C
°C
APPENDIX
3.1 Electrical characteristics
3.1.2 Recommended operating conditions
Table 3.1.2 Recommended operating conditions (1)
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
VCC
VCC
VSS
VREF
AVSS
VIA
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
Parameter
Power source voltage (f(XIN) ≤ 4.1 MHz)
Power source voltage (f(XIN) = 10 MHz)
Power source voltage (flash memory version)
Power source voltage
Analog reference voltage (when A-D converter is used)
Analog reference voltage (when D-A converter is used)
Analog power source voltage
A-D converter input voltage
AN0–AN7
“H” input voltage
P00–P07, P10–P17, P20–P27, P30–P37, P40, P41,
P47, P50–P57, P60–P67, P80–P87
“H” input voltage
P76, P77
“H” input voltage (when I2C-BUS input level is selected)
SDA, SCL
“H” input voltage (when SMBUS input level is selected)
SDA, SCL
“H” input voltage (when CMOS input level is selected)
P42–P46, DQ0–DQ7, W, R, S0, S1, A0
“H” input voltage (when CMOS input level is selected)
P70–P75
“H” input voltage (when TTL input level is selected)
P42–P46, DQ0–DQ7, W, R, S0, S1, A0 (Note)
“H” input voltage (when TTL input level is selected)
P70–P75 (Note)
“H” input voltage
RESET, XIN, XCIN, CNVSS
“L” input voltage
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87
“L” input voltage (when I2C-BUS input level is selected)
SDA, SCL
“L” input voltage (when SMBUS input level is selected)
SDA, SCL
“L” input voltage (when CMOS input level is selected)
P42–P46, P70–P75, DQ0–DQ7, W, R, S0, S1, A0
“L” input voltage (when TTL input level is selected)
P42–P46, P70–P75, DQ0–DQ7, W, R, S0, S1, A0 (Note)
Min.
2.7
4.0
4.0
Limits
Typ.
5.0
5.0
5.0
0
2.0
2.7
Max.
5.5
5.5
5.5
VCC
VCC
Unit
V
V
V
V
AVSS
VCC
V
V
0.8VCC
VCC
V
0.8VCC
5.5
V
0.7VCC
5.5
V
1.4
5.5
V
0.8VCC
VCC
V
0.8VCC
5.5
V
2.0
VCC
V
2.0
5.5
V
0.8VCC
VCC
V
0
0.2VCC
V
0
0.3VCC
V
0
0.6
V
0
0.2VCC
V
0
0.8
V
V
V
0
VIL
“L” input voltage
RESET, CNVSS
0
0.2VCC
VIL
“L” input voltage
XIN, XCIN
0
0.16VCC
Note : When VCC is 4.0 to 5.5 V.
3886 Group User’s Manual
3-3
APPENDIX
3.1 Electrical characteristics
Table 3.1.3 Recommended operating conditions (2)
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
“H” total peak output current
“H” total peak output current
“L” total peak output current
ΣIOL(peak)
“L” total peak output current
P24–P27 (Note)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
“L” total peak output current
P40–P47,P50–P57, P60–P67, P70–P77 (Note)
“H” total average output current P00–P07, P10–P17, P20–P27, P30–P37, P80–P87 (Note)
“H” total average output current P40–P47,P50–P57, P60–P67 (Note)
“L” total average output current P00–P07, P10–P17, P20–P23, P30–P37, P80–P87 (Note)
In single-chip mode
“L” total average output current
In memory expansion mode
P24–P27 (Note)
In microprocessor mode
ΣIOL(avg)
ΣIOL(avg)
Min.
Limits
Typ.
P00–P07, P10–P17, P20–P27, P30–P37, P80–P87 (Note)
P40–P47, P50–P57, P60–P67 (Note)
P00–P07, P10–P17, P20–P23, P30–P37, P80–P87 (Note)
In single-chip mode
In memory expansion mode
In microprocessor mode
“L” total average output current P40–P47,P50–P57, P60–P67, P70–P77 (Note)
Max.
Unit
–80
–80
80
80
mA
mA
mA
mA
40
mA
80
–40
–40
40
40
mA
mA
mA
mA
mA
40
mA
40
mA
Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
Table 3.1.4 Recommended operating conditions (3)
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
IOH(peak)
IOL(peak)
IOL(peak)
Parameter
“H” peak output current
“L” peak output current
“L” peak output current
P24–P27 (Note 1)
IOH(avg)
“H” average output current
IOL(avg)
“L” average output current
IOL(avg)
“L” peak output current
P24–P27 (Note 2)
f(XIN)
f(XCIN)
Min.
Limits
Typ.
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P80–P87 (Note 1)
P00–P07, P10–P17, P20–P23, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87 (Note 1)
In single-chip mode
In memory expansion mode
In microprocessor mode
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P80–P87 (Note 2)
P00–P07, P10–P17, P20–P23, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87 (Note 2)
In single-chip mode
In memory expansion mode
In microprocessor mode
High-speed mode
4.0 V≤ VCC ≤ 5.5 V
High-speed mode
2.7 V≤ VCC ≤ 4.0 V
Main clock input oscillation
Middle-speed mode
frequency (Note 3)
4.0 V≤ VCC ≤ 5.5 V
Middle-speed mode
2.7 V≤ VCC ≤ 4.0 V (Note 5)
Middle-speed mode
2.7 V≤ VCC ≤ 4.0 V (Note 5)
Sub-clock input oscillation frequency (Notes 3, 4)
32.768
Max.
Unit
–10
mA
10
mA
20
mA
10
mA
–5
mA
5
mA
15
mA
5
mA
10
MHz
4.5 VCC–8
MHz
10
MHz
10
MHz
4.5 VCC–8
MHz
50
kHz
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms.
3: When the oscillation frequency has a duty cycle of 50%.
4: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
5: When using the timer X/Y, timer 1/2, serial I/O1, serial I/O2, A-D converter, comparator, and PWM, set the main clock input oscillation frequency to
the max. 4.5VCC–8 (MHz).
3-4
3886 Group User’s Manual
APPENDIX
3.1 Electrical characteristics
3.1.3 Electrical characteristics
Table 3.1.5 Electrical characteristics (1)
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
VOH
VOL
VT+–VT–
VT+–VT–
VT+–VT–
IIH
IIH
IIH
IIL
IIL
IIL
IIL
VRAM
Parameter
Test conditions
“H” output voltage
P00–P07, P10–P17, P20–P27
P30–P37, P40–P47, P50–P57
P60–P67, P80–P87 (Note)
“L” output voltage
P00–P07, P10–P17, P20–P27
P30–P37, P40–P47, P50–P57
P60–P67, P70–P77, P80–P87
Hysteresis
CNTR0, CNTR1, INT0, INT1
INT20–INT40, INT21–INT41
P30–P37
Hysteresis
RxD, SCLK1, SIN2, SCLK2
Hysteresis RESET
“H” input current
P00–P07, P10–P17, P20–P27
P30–P37, P40–P47, P50–P57
P60–P67, P70–P77, P80–P87
“H” input current RESET, CNVSS
“H” input current XIN
“L” input current
P00–P07, P10–P17, P20–P27
P30–P37, P40–P47, P50–P57
P60–P67, P70–P77, P80–P87
“L” input current RESET,CNVSS
“L” input current XIN
“L” input current
P30–P37 (at Pull-up)
RAM hold voltage
IOH = –10 mA
VCC = 4.0 to 5.5 V
IOH = –1.0 mA
VCC = 2.7 to 5.5 V
IOL = 10 mA
VCC = 4.0 to 5.5 V
IOL = 1.6 mA
VCC = 2.7 to 5.5 V
Min.
Typ.
Unit
VCC–2.0
V
VCC–1.0
V
2.0
V
0.4
V
0.4
V
0.5
V
0.5
V
VI = VCC
(Pin floating. Pull-up
transistors “off”)
VI = VCC
5.0
µA
5.0
µA
µA
4
VI = VCC
VI = VSS
(Pin floating. Pull-up
transistors “off”)
VI = VSS
VI = VSS
VI = VSS
VCC = 4.0 to 5.5 V
VI = VSS
VCC = 2.7 to 5.5 V
When clock stopped
Max.
–5.0
–5.0
µA
µA
–120
µA
–4
–20
–60
µA
–10
2.0
µA
5.5
V
Note: P00–P03 are measured when the P00–P03 output structure selection bit of the port control register 1 (bit 0 of address 002E16) is “0”.
P04–P07 are measured when the P04–P07 output structure selection bit of the port control register 1 (bit 1 of address 002E16) is “0”.
P10–P13 are measured when the P10–P13 output structure selection bit of the port control register 1 (bit 2 of address 002E16) is “0”.
P14–P17 are measured when the P14–P17 output structure selection bit of the port control register 1 (bit 3 of address 002E16) is “0”.
P42, P43, P44, and P46 are measured when the P4 output structure selection bit of the port control register 2 (bit 2 of address 002F16) is “0”.
P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
3886 Group User’s Manual
3-5
APPENDIX
3.1 Electrical characteristics
Table 3.1.6 Electrical characteristics (2)
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
ICC
Parameter
Power source current
Test conditions
High-speed mode
f(XIN) = 10 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
High-speed mode
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
High-speed mode
f(XIN) = 10 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
Low-speed mode (VCC = 3 V)
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode (VCC = 3 V)
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
Middle-speed mode
f(XIN) = 10 MHz
f(XCIN) = stopped
Output transistors “off”
Middle-speed mode
f(XIN) = 10 MHz (in WIT state)
f(XCIN) = stopped
Output transistors “off”
Increment when A-D conversion is
executed
f(XIN) = 10 MHz
All oscillation stopped
(in STP state)
Output transistors “off”
3-6
Ta = 25 °C
Ta = 85 °C
3886 Group User’s Manual
Min.
Unit
Typ.
Max.
8.0
15
mA
6.8
13
mA
mA
1.6
60
200
µA
20
40
µA
20
55
µA
8.0
20.0
µA
4.0
7.0
mA
1.5
mA
800
µA
0.1
1.0
µA
10
µA
APPENDIX
3.1 Electrical characteristics
3.1.4 A-D converter characteristics
Table 3.1.7 A-D converter characteristics (1)
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, VREF = 2.0 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
10-bit A-D mode (when conversion mode selection bit (bit 7 of address 003816) is “0”)
Symbol
Parameter
–
–
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
Ladder resistor
at A-D converter operated
Reference power
source input current
at A-D converter stopped
tCONV
RLADDER
IVREF
II(AD)
Test conditions
Limits
Min.
Typ.
VCC = VREF = 5.0 V
VREF = 5.0 V
12
50
35
150
VREF = 5.0 V
A-D port input current
Max.
10
±4
61
100
200
5
5.0
Unit
bit
LSB
2tc(XIN)
kΩ
µA
µA
µA
Table 3.1.8 A-D converter characteristics (2)
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, VREF = 2.0 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
8-bit A-D mode (when conversion mode selection bit (bit 7 of address 003816) is “1”)
Symbol
–
–
tCONV
RLADDER
IVREF
II(AD)
Parameter
Test conditions
Limits
Min.
Typ.
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
Ladder resistor
at A-D converter operated
Reference power
source input current
at A-D converter stopped
VCC = VREF = 5.0 V
VREF = 5.0 V
VREF = 5.0 V
12
50
35
150
A-D port input current
Max.
8
±2
50
100
200
5
5.0
Unit
bit
LSB
2tc(XIN)
kΩ
µA
µA
µA
3.1.5 D-A converter characteristics
Table 3.1.9 D-A converter characteristics
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, VREF = 2.7 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
–
–
tsu
RO
IVREF
Parameter
Test conditions
Limits
Min.
Typ.
Resolution
VCC = 4.0 to 5.5 V
VCC = 2.7 to 4.0 V
Absolute accuracy
Setting time
Output resistor
Reference power source input current (Note 1)
1
2.5
Max.
8
1.0
2.5
3
4
3.2
Unit
Bits
%
%
µs
kΩ
mA
Note 1: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”.
3.1.6 Comparator characteristics
Table 3.1.10 Comparator characteristics
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
–
Parameter
Absolute accuracy
TCONV
Conversion time
VIA
IIA
Analog input voltage
Analog input current
Ladder resistor
RLADDER
CMPREF
Test conditions
Limits
Min.
Typ.
1LSB = VCC/16
at 10 MHz operating
at 8 MHz operating
at 4 MHz operating
0
20
40
Max.
1/2
2.8
3.5
7
VCC
5.0
50
29VCC
/32
Internal reference voltage
VCC/32
External reference input voltage
3886 Group User’s Manual
Unit
LSB
µs
µs
µs
V
µA
kΩ
V
VCC
V
3-7
APPENDIX
3.1 Electrical characteristics
3.1.7 Timing requirements
Table 3.1.11 Timing requirements (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
16
100
40
40
20
5
5
200
80
80
Typ.
Max.
Unit
XIN cycles
ns
ns
ns
µs
µs
µs
ns
ns
ns
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(XCIN)
tWH(XCIN)
tWL(XCIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
Reset input “L” pulse width
Main clock input cycle time
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
tWH(INT)
INT0, INT1, INT20, INT30, INT40, INT21, INT31, INT41
input “H” pulse width
80
ns
tWL(INT)
INT0, INT1, INT20, INT30, INT40, INT21, INT31, INT41
input “L” pulse width
80
ns
800
370
370
220
100
1000
400
400
200
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input setup time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input setup time
Serial I/O2 input hold time
Note : When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
3-8
3886 Group User’s Manual
APPENDIX
3.1 Electrical characteristics
Table 3.1.12 Timing requirements (2)
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
16
1000/(4.5VCC–8)
400/(4.5VCC–8)
400/(4.5VCC–8)
20
5
5
500
230
230
Typ.
Max.
Unit
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(XCIN)
tWH(XCIN)
tWL(XCIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
Reset input “L” pulse width
Main clock input cycle time
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
tWH(INT)
INT0, INT1, INT20, INT30, INT40, INT21, INT31, INT41
input “H” pulse width
230
ns
tWL(INT)
INT0, INT1, INT20, INT30, INT40, INT21, INT31, INT41
input “L” pulse width
230
ns
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input setup time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input setup time
Serial I/O2 input hold time
2000
950
950
400
200
2000
950
950
400
300
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XIN cycles
ns
ns
ns
µs
µs
µs
ns
ns
ns
Note : When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
3886 Group User’s Manual
3-9
APPENDIX
3.1 Electrical characteristics
3.1.8 Timing requirements for system bus interface
Table 3.1.13 Timing requirements for system bus interface (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tsu (S-R)
tsu (S-W)
th (R-S)
th (W-S)
tsu (A-R)
tsu (A-W)
th (R-A)
th (W-A)
tw (R)
tw (W)
tsu (D-W)
th (W-D)
Parameter
S0, S1 setup time
S0, S1 setup time
S0, S1 hold time
S0, S1 hold time
A0 setup time
A0 setup time
A0 hold time
A0 hold time
Read pulse width
Write pulse width
Before write data input setup time
After write data input hold time
Limits
Min.
0
0
0
0
10
10
0
0
120
120
50
0
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 3.1.14 Timing requirements for system bus interface (2)
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tsu (S-R)
tsu (S-W)
th (R-S)
th (W-S)
tsu (A-R)
tsu (A-W)
th (R-A)
th (W-A)
tw (R)
tw (W)
tsu (D-W)
th (W-D)
3-10
Parameter
S0, S1 setup time
S0, S1 setup time
S0, S1 hold time
S0, S1 hold time
A0 setup time
A0 setup time
A0 hold time
A0 hold time
Read pulse width
Write pulse width
Before write data input setup time
After write data input hold time
3886 Group User’s Manual
Limits
Min.
0
0
0
0
30
30
0
0
250
250
130
0
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
APPENDIX
3.1 Electrical characteristics
3.1.9 Switching characteristics
Table 3.1.15 Switching characteristics (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tV (SCLK1-TXD)
tr (SCLK1)
tf (SCLK1)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tV (SCLK2-SOUT2)
tf (SCLK2)
tr (CMOS)
tf (CMOS)
Parameter
Test
conditions
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
Limits
Typ.
Min.
tC(SCLK1)/2–30
tC(SCLK1)/2–30
Max.
140
Fig. 3.1.1
–30
30
30
tC(SCLK2)/2–160
tC(SCLK2)/2–160
200
Fig. 3.1.2
0
10
10
Fig. 3.1.1
30
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: The XOUT pin is excluded.
Table 3.1.16 Switching characteristics (2)
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tV (SCLK1-TXD)
tr (SCLK1)
tf (SCLK1)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tV (SCLK2-SOUT2)
tf (SCLK2)
tr (CMOS)
tf (CMOS)
Parameter
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
Test
conditions
Limits
Typ.
Min.
tC(SCLK1)/2–50
tC(SCLK1)/2–50
Max.
350
Fig. 3.1.1
–30
50
50
tC(SCLK2)/2–240
tC(SCLK2)/2–240
400
Fig. 3.1.2
0
20
20
Fig. 3.1.1
50
50
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: The XOUT pin is excluded.
3.1.10 Switching characteristics for system bus interface
Table 3.1.17 Switching characteristics for system bus interface (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
ta(R-D)
tv(R-D)
tPLH(R-OBF)
Parameter
After read data output enable time
After read data output disable time
After read OBF00, OBF01, OBF10 output propagation time
Limits
Min.
Typ.
Max.
80
30
150
0
Unit
ns
ns
ns
Table 3.1.18 Switching characteristics for system bus interface (2)
(VCC =2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
ta(R-D)
tv(R-D)
tPLH(R-OBF)
Parameter
After read data output enable time
After read data output disable time
After read OBF00, OBF01, OBF10 output propagation time
3886 Group User’s Manual
Min.
0
Typ.
Max.
130
85
300
Unit
ns
ns
ns
3-11
APPENDIX
3.1 Electrical characteristics
3.1.11 Timing requirements in memory expansion mode and microprocessor mode
Table 3.1.19 Timing requirements in memory expansion mode and microprocessor mode
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, in high-speed mode, unless otherwise noted)
Limits
Symbol
Parameter
tsu (ONW-φ)
th (φ-ONW)
tsu (DB-φ)
th (φ-DB)
tsu (ONW-RD), tsu (ONW-WR)
th (RD-ONW), th (WR-ONW)
tsu (DB-RD)
th (RD-DB)
Min.
ONW input setup time
ONW input hold time
Data bus setup time
Data bus hold time
ONW input setup time
ONW input hold time
Data bus setup time
Data bus hold time
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
–20
–20
50
0
–20
–20
50
0
3.1.12 Switching characteristics in memory expansion mode and microprocessor mode
Table 3.1.20 Switching characteristics in memory expansion mode and microprocessor mode
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, in high-speed mode, unless otherwise noted)
Symbol
Limits
Test
conditions
Parameter
tC(φ)
tWH(φ)
tWL(φ)
td(φ-AH)
td(φ-AL)
tV(φ-AH)
tV(φ-AL)
td(φ-SYNC)
tV(φ-SYNC)
td(φ-DB)
tV(φ-DB)
φ clock cycle time
φ clock “H” pulse width
φ clock “L” pulse width
AD15–AD8 delay time
AD7–AD0 delay time
AD15–AD8 valid time
AD7–AD0 valid time
SYNC delay time
SYNC valid time
Data bus delay time
Data bus valid time
tWL(RD), tWL(WR)
RD pulse width, WR pulse width
RD pulse width, WR pulse width
(When one-wait is valid)
td(AH-RD), td(AH-WR)
td(AL-RD), td(AL-WR)
tV(RD-AH), tV(WR-AH)
tV(RD-AL), tV(WR-AL)
td(WR-DB)
tV(WR-DB)
td(RESET-RESETOUT)
tV(φ-RESETOUT)
AD15–AD8 delay time
AD7–AD0 delay time
AD15–AD8 valid time
AD7–AD0 valid time
Data bus delay time
Data bus valid time
RESETOUT output delay time
RESETOUT output valid time (Note)
Min.
Typ.
Max.
2tC(XIN)
tC(XIN)–10
tC(XIN)–10
16
20
5
5
16
5
15
2
2
Fig. 3.1.1
35
40
30
10
tC(XIN)–10
3tC(XIN)–10
tC(XIN)–35
tC(XIN)–40
2
2
tC(XIN)–16
tC(XIN)–20
5
5
15
30
10
200
100
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: The RESETOUT output goes “H” in synchronized with the rise of the φ clock that is anywhere between a few cycles and 10-several cycles after RESET
input goes “H”.
1 kΩ
Measurement output pin
Measurement output pin
100 pF
100 pF
CMOS output
N-channel open-drain output
Fig. 3.1.1 Circuit for measuring output switching characteristics (1)
3-12
Fig. 3.1.2 Circuit for measuring output switching characteristics (2)
3886 Group User’s Manual
APPENDIX
3.1 Electrical characteristics
Timing diagram in single-chip mode
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
0.8VCC
C N TR 0 , C N TR 1
0.2VCC
tWL(INT)
tWH(INT)
INT0,INT1
INT20,INT30,INT40
INT21,INT31,INT41
0.8VCC
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
0.2VCC
tC(XCIN)
tWL(XCIN)
tWH(XCIN)
0.8VCC
XCIN
tC(SCLK1), tC(SCLK2)
tr
tf
SCLK1
SCLK2
0.2VCC
tWL(SCLK1), tWL(SCLK2)
0.8VCC
0.2VCC
tsu(RxD-SCLK1),
tsu(SIN2-SCLK2)
RX D
SIN2
tWH(SCLK1), tWH(SCLK2)
th(SCLK1-RxD),th(SCLK2-SIN2)
0.8VCC
0.2VCC
td(SCLK1-TXD),td(SCLK2-SOUT2)
tv(SCLK1-TXD),
tv(SCLK2-SOUT2)
TX D
SOUT2
Fig. 3.1.3 Timing diagram (1) (in single-chip mode)
3886 Group User’s Manual
3-13
APPENDIX
3.1 Electrical characteristics
Timing diagram in memory expansion mode and microprocessor mode (1)
tC(φ)
tWL(φ)
tWH(φ)
φ
0.5VCC
tv(φ-AH)
td(φ-AH)
AD15–AD8
0.5VCC
td(φ-AL)
AD7–AD0
tv(φ-AL)
0.5VCC
tv(φ-SYNC)
td(φ-SYNC)
0.5VCC
SYNC
td(φ-WR)
RD,WR
tv(φ-WR)
0.5VCC
th(φ-ONW)
tSU(ONW-φ)
0.8VCC
0.2VCC
ONW
tSU(DB-φ)
0.8VCC
0.2VCC
DB0–DB7
(At CPU reading)
td(φ-DB)
DB0–DB7
(At CPU writing)
tv(φ-DB)
0.5VCC
Timing diagram in microprocessor mode
RESET
0.8VCC
0.2VCC
φ
0.5VCC
td(RESET- RESETOUT)
RESETOUT
0.5VCC
Fig. 3.1.4 Timing diagram (2) (in memory expansion mode and microprocessor mode)
3-14
th(φ-DB)
3886 Group User’s Manual
tv(φ- RESETOUT)
APPENDIX
3.1 Electrical characteristics
Timing diagram in memory expansion mode and microprocessor mode (2)
tWL(RD)
tWL(WR)
RD,WR
0.5VCC
td(AH-RD)
td(AH-WR)
AD15–AD8
tv(RD-AH)
tv(WR-AH)
0.5VCC
td(AL-RD)
td(AL-WR)
AD7–AD0
tv(RD-AL)
tv(WR-AL)
0.5VCC
th(RD-ONW)
th(WR-ONW)
tsu(ONW-RD)
tsu(ONW-WR)
ONW
0.8VCC
0.2VCC
(At CPU reading)
RD
0.5VCC
tSU(DB-RD)
th(RD-DB)
0.8VCC
0.2VCC
DB0–DB7
(At CPU writing)
WR
0.5VCC
tv(WR-DB)
td(WR-DB)
DB0–DB7
0.5VCC
Fig. 3.1.5 Timing diagram (3) (in memory expansion mode and microprocessor mode)
3886 Group User’s Manual
3-15
APPENDIX
3.1 Electrical characteristics
System bus interface timing diagram
Read operation
tsu(A-R)
A0
th(R-A)
2.4 (0.8VCC)
0.45 (0.2VCC)
2.4 (0.8VCC)
0.45 (0.2VCC)
tsu(S-R)
S 0 ,S 1
th(R-S)
0.45 (0.2VCC)
0.45 (0.2VCC)
tw(R)
R
2.4 (0.8VCC)
2.4 (0.8VCC)
0.45 (0.2VCC)
0.45 (0.2VCC)
2.0 (0.8VCC)
0.8 (0.2VCC)
2.0 (0.8VCC)
0.8 (0.2VCC)
DQ0–DQ7
ta(R-D)
tv(R-D)
tPLH(R-OBF)
OBF00,OBF01,OBF10
0.8 (0.2VCC)
Write operation
tsu(A-W)
A0
th(W-A)
2.4 (0.8VCC)
0.45 (0.2VCC)
2.4 (0.8VCC)
0.45 (0.2VCC)
tsu(S-W)
S 0 ,S 1
th(W-S)
0.45 (0.2VCC)
0.45 (0.2VCC)
tw(W)
W
2.4 (0.8VCC)
2.4 (0.8VCC)
0.45 (0.2VCC)
0.45 (0.2VCC)
th(W-D)
2.4 (0.8VCC)
0.45 (0.2VCC)
DQ0–DQ7
tsu(D-W)
Outside of parenthesis : TTL I/O
Inside of parenthesis : CMOS I/O
Fig. 3.1.6 Timing diagram (4) (system bus interface)
3-16
3886 Group User’s Manual
2.4 (0.8VCC)
0.45 (0.2VCC)
APPENDIX
3.1 Electrical characteristics
3.1.13 Multi-master I2C-BUS bus line characteristics
Table 3.1.21 Multi-master I2C-BUS bus line characteristics
Standard clock mode High-speed clock mode
Symbol
Parameter
Min.
Max.
Max.
Unit
tBUF
Bus free time
4.7
Min.
1.3
tHD;STA
Hold time for START condition
4.0
0.6
µs
tLOW
Hold time for SCL clock = “0”
4.7
1.3
µs
µs
tR
Rising time of both SCL and SDA signals
tHD;DAT
Data hold time
tHIGH
Hold time for SCL clock = “1”
tF
Falling time of both SCL and SDA signals
tSU;DAT
Data setup time
250
100
ns
tSU;STA
Setup time for repeated START condition
4.7
0.6
µs
tSU;STO
Setup time for STOP condition
4.0
0.6
µs
1000
20+0.1Cb
0
0
4.0
0.6
300
300
ns
0.9
µs
µs
20+0.1Cb
300
ns
Note: Cb = total capacitance of 1 bus line
SDA
tHD:STA
tBUF
tLOW
SCL
P
tR
tF
S
tHD:STA
Sr
tHD:DAT
tsu:STO
tHIGH
tsu:DAT
P
tsu:STA
S : START condition
Sr: RESTART condition
P : STOP condition
Fig. 3.1.7 Timing diagram of multi-master I2C-BUS
3886 Group User’s Manual
3-17
APPENDIX
3.2 Standard characteristics
3.2 Standard characteristics
3.2.1 Power source current characteristic examples
Figure 3.2.1, Figure 3.2.2, Figure 3.2.3, Figure 3.2.4, Figure 3.2.5, Figure 3.2.6 and Figure 3.2.7 show
power source current characteristic examples.
[Measuring condition: 25 °C, in high-speed mode, A-D conversion and comparator operating]
16.0
14.0
12.0
10.0
ICC [mA]
: 10MHz
: 8MHz
: 4MHz
: 2MHz
: 500kHz
Note: External clock input
8.0
6.0
4.0
2.0
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD [V]
Fig. 3.2.1 Power source current characteristic examples (in high-speed mode, A-D conversion and
comparator operating)
[Measuring condition: 25 °C, in high-speed mode]
8.0
7.0
6.0
: 10MHz
: 8MHz
: 4MHz
: 2MHz
: 500kHz
Note: External clock input
5.0
ICC [mA]
4.0
3.0
2.0
1.0
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD [V]
Fig. 3.2.2 Power source current characteristic examples (in high-speed mode)
3-18
3886 Group User’s Manual
APPENDIX
3.2 Standard characteristics
[Measuring condition: 25 °C, in high-speed mode, WAIT execution]
2.00
1.75
1.50
1.25
ICC [mA]
: 10MHz
: 8MHz
: 4MHz
: 2MHz
: 500kHz
Note: External clock input
1.00
0.75
0.50
0.25
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD [V]
Fig. 3.2.3 Power source current characteristic examples (in high-speed mode, WAIT execution)
[Measuring condition: 25 °C, in middle-speed mode]
4.0
3.5
3.0
2.5
ICC [mA]
: 10MHz
: 8MHz
: 4MHz
: 2MHz
: 500kHz
Note: External clock input
2.0
1.5
1.0
0.5
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD [V]
Fig. 3.2.4 Power source current characteristic examples (in middle-speed mode)
3886 Group User’s Manual
3-19
APPENDIX
3.2 Standard characteristics
[Measuring condition: 25 °C, in middle-speed mode, WAIT execution]
1.000
0.875
0.750
0.625
: 10MHz
: 8MHz
: 4MHz
: 2MHz
: 500kHz
Note: External clock input
ICC [mA] 0.500
0.375
0.250
0.125
0.0
2.5
3.0
3.5
4.0
4.5
5.0
6.0
5.5
VDD [V]
Fig. 3.2.5 Power source current characteristic examples (in middle-speed mode, WAIT execution)
[Measuring condition: 25 °C, in low-speed mode]
80.0
70.0
: Normal operation
: Wait instruction
: Normal operation (oscillator)
: Wait instruction (oscillator)
60.0
50.0
ICC [µA]
40.0
30.0
20.0
10.0
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD [V]
Fig. 3.2.6 Power source current characteristic examples (in low-speed mode)
3-20
3886 Group User’s Manual
APPENDIX
3.2 Standard characteristics
[Measuring condition: 25 °C, at reset]
4.0
3.5
3.0
2.5
ICC [mA]
: 10MHz
: 8MHz
: 4MHz
: 2MHz
: 500kHz
Note: External clock input
2.0
1.5
1.0
0.5
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD [V]
Fig. 3.2.7 Power source current characteristic examples (at reset)
3886 Group User’s Manual
3-21
APPENDIX
3.2 Standard characteristics
3.2.2 Port standard characteristic examples
Figures 3.2.8, Figures 3.2.9, Figures 3.2.10, Figures 3.2.11, Figure 3.2.12, and Figure 3.2.13 show port
standard characteristic examples.
Port P00 IOH-VOH characteristics (P-channel drive) [Ta=25 °C]
(Pins with same characteristic: P0, P1, P2, P3, P4, P5, P6, P8)
–50
–45
–40
–35
Vcc=5V
IOH –30
[mA]
–25
Vcc=4.0V
–20
–15
Vcc=2.7V
–10
–5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VOH [V]
Fig. 3.2.8 Standard characteristic examples of CMOS output port at P-channel drive (Ta=25 °C)
Port P00 IOH-VOH characteristics (P-channel drive) [Ta=90 °C]
(Pins with same characteristic: P0, P1, P2, P3, P4, P5, P6, P8)
–50
–45
–40
–35
IOH –30
[mA]
Vcc=5V
–25
–20
Vcc=4.0V
–15
–10
–5
Vcc=2.7V
0
0
0 .5
1.0
1 .5
2 .0
2.5
3 .0
3 .5
4 .0
4 .5
5 .0
5 .5
VOH [V]
Fig. 3.2.9 Standard characteristic examples of CMOS output port at P-channel drive (Ta=90 °C)
3-22
3886 Group User’s Manual
APPENDIX
3.2 Standard characteristics
Port P00 IOL-VOL characteristics (N-channel drive) [Ta=25 °C]
(Pins with same characteristic: P0, P1, P20–P23, P3, P4, P5,
P6, P7, P8, and P24–P27 except at single-chip mode)
50
Vcc=5V
45
40
35
IO L
[mA]
Vcc=4.0V
30
25
20
Vcc=2.7V
15
10
5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VOL[V]
Fig. 3.2.10 Standard characteristic examples of CMOS output port at N-channel drive (Ta=25 °C)
Port P00 IOL-VOL characteristics (N-channel drive) [Ta=90 °C]
(Pins with same characteristic: P0, P1, P20–P23, P3, P4, P5,
P6, P7, P8, and P24–P27 except at single-chip mode)
50
Vcc=5V
45
40
35
IOL
[mA]
Vcc=4.0V
30
25
20
15
Vcc=2.7V
10
5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VOL[V]
Fig. 3.2.11 Standard characteristic examples of CMOS output port at N-channel drive (Ta=90 °C)
3886 Group User’s Manual
3-23
APPENDIX
3.2 Standard characteristics
Port P24 IOL-VOL characteristics (N-channel drive) [Ta=25 °C]
(Pins with same characteristic: P24–P27 at single-chip mode)
Vcc=5V
100
90
80
Vcc=4.0V
70
IOL
[mA]
60
50
40
Vcc=2.7V
30
20
10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VOL[V]
Fig. 3.2.12 Standard characteristic examples of CMOS large current output port at N-channel drive (Ta=25 °C)
Port P24 IOL-VOL characteristics (N-channel drive) [Ta=90 °C]
(Pins with same characteristic: P24–P27 at single-chip mode)
Vcc=5V
100
90
80
70
IOL
[mA]
Vcc=4.0V
60
50
40
30
Vcc=2.7V
20
10
0
0
0 .5
1 .0
1.5
2.0
2 .5
3 .0
3 .5
4.0
4 .5
5 .0
5.5
VOL[V]
Fig. 3.2.13 Standard characteristic examples of CMOS large current output port at N-channel drive (Ta=90 °C)
3-24
3886 Group User’s Manual
APPENDIX
3.2 Standard characteristics
3.2.3 Input port standard characteristic examples
Figures 3.2.14 and Figure 3.2.15 show port standard characteristic examples.
Port P30 IIL-VIL characteristics (at pull-up) [Ta=25 °C]
(Pins with same characteristic: P3)
–100
–90
–80
Vcc=5V
–70
IIL –60
[µA]
–50
Vcc=4.0V
–40
–30
–20
Vcc=2.7V
–10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VIL [V]
Fig. 3.2.14 Standard characteristic examples of CMOS input port at pull-up (Ta=25 °C)
Port P30 IIL-VIL characteristics (at pull-up) [Ta=90 °C]
(Pins with same characteristic: P3)
–100
–90
–80
–70
Vcc=5V
IIL –60
[µA]
–50
Vcc=4.0V
–40
–30
Vcc=2.7V
–20
–10
0
0
0 .5
1.0
1.5
2 .0
2.5
3 .0
3 .5
4 .0
4 .5
5 .0
5.5
VIL [V]
Fig. 3.2.15 Standard characteristic examples of CMOS input port at pull-up (Ta=90 °C)
3886 Group User’s Manual
3-25
APPENDIX
3.2 Standard characteristics
3.2.4 A-D conversion standard characteristics
Figure 3.2.16 shows the A-D conversion standard characteristics.
3886 Group A-D CONVERTER ERROR & STEP WIDTH MEASUREMENT
1LSB WIDTH
15
15.0
10
10.0
5
5.0
0
0.0
-5
1L SB WIDTH [mV]
ERR OR [mV]
Vcc = 5.12 [V], VREF = 5.12 [V]
XIN = 8 [MHz], Temp = 25 [deg.]
-1 0
0
16
32
48
64
80
96
112
ERR OR [mV]
128
144
160
176
192
208
224
240
256
STEP No.
ERROR (absolute precision error)
15
15.0
10
10.0
5
5.0
0
0.0
-5
1L SB WIDTH [mV]
-1 5
-10
-15
256
272
288
304
320
336
352
368
384
400
416
432
448
464
480
496
512
15
15.0
10
10.0
5
5.0
0
0.0
-5
1L SB WIDTH [mV]
ERR OR [mV]
STEP No.
-1 0
-15
512
528
544
560
576
592
606
624
640
656
672
688
704
720
736
752
768
15
15.0
10
10.0
5
5.0
0
0.0
-5
-1 0
-1 5
768
784
800
816
832
848
864
880
896
912
928
STEP No.
Fig. 3.2.16 A-D conversion standard characteristics
3-26
3886 Group User’s Manual
944
960
976
992
1008
1024
1L SB WIDTH [mV]
ERR OR [mV]
STEP No.
APPENDIX
3.2 Standard characteristics
3.2.5 D-A conversion standard characteristics
Figure 3.2.17 shows the D-A conversion standard characteristics.
3886 Group D-A CONVERTER ERROR & STEP WIDTH MEASUREMENT
Vcc = 5.12 [V], VREF = 5.12 [V]
XIN = 8 [MHz], Temp = 25 [deg.]
30
ERROR [mV]
20
10
0
-10
-20
-30
0
16
32
48
64
80
96
112
128
208
224
240
256
STEP No.
30
ERROR [mV]
20
10
0
-10
-20
-30
128
144
160
176
192
STEP No.
Fig. 3.2.17 D-A conversion standard characteristics
3886 Group User’s Manual
3-27
APPENDIX
3.3 Notes on use
3.3 Notes on use
3.3.1 Notes on input and output pins
(1) Notes in stand-by state
In stand-by state*1 for low-power dissipation, do not make input levels of an input port and an I/O
port “undefined”, especially for I/O ports of the N-channel open-drain.
Pull-up (connect the port to V CC ) or pull-down (connect the port to V SS ) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using built-in pull-up or pull-down resistor, note on varied current values:
• When setting as an input port : Fix its input level
• When setting as an output port : Prevent current from flowing out to external
■ Reason
In I/O ports of the N-channel open-drain, in spite of setting as an output port with its direction
register, when the content of the port latch is “1”, the transistor becomes the OFF state, which
causes the ports to be the high-impedance state. Note that the level becomes “undefined” depending
on external circuits.
Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the
state that input levels of an input port and an I/O port are “undefined”. This may cause power
source current.
* 1 stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
(2) Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction*2, the value of the
unspecified bit may be changed.
■ Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
• As for a bit which is set for an input port :
The pin state is read in the CPU, and is written to this bit after bit managing.
• As for a bit which is set for an output port :
The bit value of the port latch is read in the CPU, and is written to this bit after bit managing.
Note the following :
• Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
• As for a bit of the port latch which is set for an input port, its value may be changed even when
not specified with a bit managing instruction in case where the pin state differs from its port latch
contents.
* 2 bit managing instructions : SEB, and CLB instructions
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3886 Group User’s Manual
APPENDIX
3.3 Notes on use
3.3.2 Termination of unused pins
(1) Terminate unused pins
➀ Output ports : Open
➁ Input ports :
Connect each pin to VCC or VSS through each resistor of 1 kΩ to 10 kΩ. With regard to ports which
can select the built-in pull-up resistor, the built-in pull-up resistor can be used.
As for pins whose potential affects to operation modes such as the CNV SS pin or others, select
the V CC pin or the V SS pin according to their operation mode.
➂ I/O ports :
• Set the I/O ports for the input mode and connect them to V CC or V SS through each resistor of
1 kΩ to 10 kΩ. With regard to ports which can select the built-in pull-up resistor, the built-in pullup resistor can be used.
Set the I/O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input mode.
With regard to an effects on the system, thoroughly perform system evaluation on the user side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
➃ The AVss pin when not using the A-D/D-A converter :
• When not using the A-D/D-A converter, handle a power source pin for the A-D/D-A converter, AVss pin
as follows:
• AVss: Connect to the Vss pin
(2) Termination remarks
➀ Input ports and I/O ports :
Do not open in the input mode.
■ Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➁ and
➂ shown on the above.
➁ I/O ports :
When setting for the input mode, do not connect to V CC or V SS directly.
■ Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and V CC (or V SS).
3886 Group User’s Manual
3-29
APPENDIX
3.3 Notes on use
➂ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through a resistor.
■ Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
3.3.3 Notes on interrupts
(1) Switching external interrupt detection edge
When switching the external interrupt detection edge, switch it in the following sequence.
Clear an interrupt enable bit to “0” (interrupt disabled)
↓
Switch the detection edge
↓
Clear an interrupt request bit to “0”
(no interrupt request issued)
↓
Set the interrupt enable bit to “1” (interrupt enabled)
Fig. 3.3.1 Sequence of switching the detection edge
■ Reason
The interrupt circuit recognizes the switching of the detection edge as the change of external input
signals. This may cause an unnecessary interrupt.
(2) Check of interrupt request bit
● When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request
register immediately after this bit is set to “0” by using a data transfer instruction, execute one or
more instructions before executing the BBC or BBS instruction.
Clear the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Data transfer instruction:
LDM, LDA, STA, STX, and STY instructions
Fig. 3.3.2 Sequence of check of interrupt request bit
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3886 Group User’s Manual
APPENDIX
3.3 Notes on use
■ Reason
If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt
request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0”
is read.
(3) Change of relevant register setting
When the setting of the following register or bit is changed, the interrupt request bit may be set to
“1”.
•Interrupt edge selection register (address 3A 16)
•Interrupt source selection register (address 39 16)
•INT2, INT3, INT4 interrupt switch bit of port control register 2 (bit 4 of address 2F 16)
Set the above listed registers or bits as the following sequence.
Clear an interrupt enable bit to “0” (interrupt disabled)
↓
Set the above listed registers or bits
↓
Clear an interrupt request bit to “0”
(no interrupt request issued)
↓
Set the interrupt enable bit to “1” (interrupt enabled)
Fig. 3.3.3 Sequence of changing relevant register
3.3.4 Notes on timer
● If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
● When switching the count source by the timer Y count source selection bit, the value of timer count
is altered in unconsiderable amount owing to generating of a thin pulses in the count input signals.
Therefore, select the timer count source before set the value to the timer.
3886 Group User’s Manual
3-31
APPENDIX
3.3 Notes on use
3.3.5 Notes on serial I/O
(1) Notes when selecting clock synchronous serial I/O (Serial I/O1)
➀ Stop of transmission operation
Clear the serial I/O1 enable bit and the transmit enable bit to “0” (Serial I/O1 and transmit disabled).
■ Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O1 enable bit is cleared to “0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and S RDY1 function as I/O ports, the transmission data
is not output). When data is written to the transmit buffer register in this state, data starts to be
shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O1 enable bit to “0”
(Serial I/O1 disabled).
➂ Stop of transmit/receive operation
Clear both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled).
(when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
■ Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.
If any one of transmission and reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,
the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clearing the serial I/O1 enable bit to
“0” (Serial I/O1 disabled) (refer to (1) ➀).
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APPENDIX
3.3 Notes on use
(2) Notes when selecting clock asynchronous serial I/O (Serial I/O1)
➀ Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled).
■ Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O1 enable bit is cleared to “0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O ports, the transmission data
is not output). When data is written to the transmit buffer register in this state, data starts to be
shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
➂ Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled).
■ Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O1 enable bit is cleared to “0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O ports, the transmission data
is not output). When data is written to the transmit buffer register in this state, data starts to be
shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TxD pin and an operation failure occurs.
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
(3) S RDY1 output of reception side (Serial I/O1)
When signals are output from the S RDY1 pin on the reception side by using an external clock in the
clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY1 output enable bit, and
the transmit enable bit to “1” (transmit enabled).
(4) Setting serial I/O1 control register again (Serial I/O1)
Set the serial I/O1 control register again after the transmission and the reception circuits are reset
by clearing both the transmit enable bit and the receive enable bit to “0.”
Clear both the transmit enable
bit (TE) and the receive enable
bit (RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O control register
↓
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to “1”
Can be set with the
LDM instruction at
the same time
Fig. 3.3.4 Sequence of setting serial I/O1 control register again
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APPENDIX
3.3 Notes on use
(5) Data transmission control with referring to transmit shift register completion flag (Serial I/O1)
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks after writing the data to the transmit buffer register. When data transmission is controlled with
referring to the flag after writing the data to the transmit buffer register, note the delay.
(6) Transmission control when external clock is selected (Serial I/O1)
When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the S CLK input level. Also, write the transmit data to the transmit buffer
register (serial I/O shift register) at “H” of the S CLK input level.
(7) Transmit interrupt request when transmit enable bit is set (Serial I/O1)
When the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as shown
in the following sequence.
➀ Set the interrupt enable bit to “0” (disabled) with CLB instruction.
➁ Prepare serial I/O for transmission/reception.
➂ Set the interrupt request bit to “0” with CLB instruction after 1 or more instruction has been
executed.
➃ Set the interrupt enable bit to “1” (enabled).
■ Reason
When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift
register completion flag are set to “1”. The interrupt request is generated and the transmission
interrupt bit is set regardless of which of the two timings listed below is selected as the timing for
the transmission interrupt to be generated.
• Transmit buffer empty flag is set to “1”
• Transmit shift register completion flag is set to “1”
(8) Transmit data writing (Serial I/O2)
In the clock synchronous serial I/O, when selecting an external clock as synchronous clock, write the
transmit data to the serial I/O2 register (serial I/O shift register) at “H” of the transfer clock input level.
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APPENDIX
3.3 Notes on use
3.3.6 Notes on multi-master I 2C-BUS interface
(1) Read-modify-write instruction
Precautions for read-modify-write instructions, such as SEB and CLB, when used for any of the
registers of the multi-master I 2C-BUS interface, are described below.
➀ I2C data shift register (S0: address 0012 16)
When executing the read-modify-write instruction for this register during transfer, data may become
an unexpected value.
➁ I2C address register (S0D: address 001316)
When the read-modify-write instruction is executed for this register at detecting the STOP condition,
data may become an unexpected value.
■ Reason
Because hardware changes the read/write bit (RWB) at detecting the STOP condition.
➂ I2C status register (S1: address 001416)
Do not execute the read-modify-write instruction for this register because all bits of this register
are changed by hardware.
➃ I2C control register (S1D: address 0015 16)
When the read-modify-write instruction is executed for this register at detecting the START condition
or at completing the byte transfer, data may become an unexpected value.
■ Reason
Because hardware changes the bit counter (BC0 to BC2).
➄ I2C clock control register (S2: address 001616)
The read-modify-write instruction can be executed for this register.
➅ I2C START/STOP condition control register (S2D: address 0017 16)
The read-modify-write instruction can be executed for this register.
(2) Procedure for generating START condition using multi-master
➀ Procedure example (The necessary conditions for the procedure are described in Items ➁ to ➄
below).
LDA #SLADR
(Take out slave address value)
SEI
(Disable interrupt)
BBS 5, S1, BUSBUSY (BB flag confirmation and branch process)
BUSFREE:
STA S0
(Write slave address value)
LDM #$F0, S1
(Trigger START condition generation)
CLI
(Enable interrupt)
:
:
BUSBUSY:
CLI
(Enable interrupt)
:
:
➁ Use “Branch on Bit Set” of “BBS 5, S1, –” for the BB flag confirmation and branch process.
➂ Use “STA”, “STX” or “STY” of the zero page addressing instruction for writing the slave address
value to the I 2C data shift register (S0: address 0012 16).
➃ Execute the branch instruction of above ➁ and the store instruction of above ➂ continuously shown
the above procedure example.
➄ Disable interrupts during the following three process steps:
• BB flag confirmation
• Write slave address value
• Trigger START condition generation
When the BB flag is in bus busy state, enable interrupts immediately.
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APPENDIX
3.3 Notes on use
(3) Procedure for generating RESTART condition
This procedure cannot be applied to M38867M8A and M38867E8A when the external memory is
used and the bus cycle is extended by ONW function.
➀ Procedure example (The necessary conditions for the procedure are described in Items ➁ to ➃
below). Execute the following procedure when the PIN bit is “0”.
LDM #$00, S1
(Select slave receive mode)
LDA #SLADR
(Take out slave address value)
SEI
(Disable interrupt)
STA S0
(Write slave address value)
LDM #$F0, S1
(Trigger RESTART condition generation)
CLI
(Enable interrupt)
:
:
➁ Select the slave receive mode when the PIN bit is “0”. Do not write “1” to the PIN bit. Neither “0” nor
“1” is specified as input to the BB bit. The TRX bit becomes “0” and the SDA pin is released.
➂ The SCL pin is released by writing the slave address value to the I 2C data shift register.
➃ Disable interrupts during the following two process steps:
• Write slave address value
• Trigger RESTART condition generation
(4) Writing to I 2C status register
Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and
TRX bits to “0” from “1” simultaneously. Because it may enter the state that the SCL pin is released
and the SDA pin is released after about one machine cycle. Do not execute an instruction to set the
MST and TRX bits to “0” from “1” simultaneously when the PIN bit is “1”. Because it may become
the same as above.
(5) Process of after STOP condition generating
Do not write data in the I2C data shift register (S0) and the I2C status register (S1) until the bus busy
flag BB becomes “0” after generating the STOP condition in the master mode. Because the STOP
condition waveform might not be normally generated. Reading to the above registers does not have
the problem.
(6) STOP condition input at 7th clock pulse
The SDA line may be held at LOW even if flag BB is set to “0” when all the following conditions are
satisfied:
•The STOP condition is input at the 7th clock pulse while receiving a slave address or data.
•The clock pulse is continuously input.
•In the slave mode
Countermeasure:
Write dummy data to the I2C shift register or reset the ES0 bit in the S1D register (ES0 = “L” →
ES0 = “H”) during a stop condition interrupt routine with flag PIN = “1”.
Note: Do not use the read-modify-write instruction at this time. Furthermore, when the ES0 bit is
set to “0”, the SDA pin becomes a general-purpose port ; so that the port must be set to input
mode or output “H”.
(7) ES0 bit switch
In standard clock mode when SSC = “00010 2” or in high-speed clock mode, flag BB may switch to
“1” if ES0 bit is set to “1” when SDA is “L”.
Countermeasure:
Set ES0 to “1” when SDA is “H”.
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APPENDIX
3.3 Notes on use
3.3.7 Notes on PWM
●For PWM 0 output, “L” level is output first.
●After data is set to the PWM0L and the PWM0H
registers, PWM waveform corresponding to the
new data is output from next repetitive period.
PWM0 output data is Updated data is output from next
updated.
repetitive period.
Fig. 3.3.5 PWM 0 output
3.3.8 Notes on A-D converter
(1) Analog input pin
Make the signal source impedance for analog input low, or equip an analog input pin with an external
capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application products on the
user side.
■ Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A-D conversion precision to be worse.
(2) A-D converter power source pin
The AVSS pin is an A-D converter power source pin. Regardless of using the A-D conversion function
or not, connect them as following :
• AV SS : Connect to the V SS line
■ Reason
If the AV SS pin is opened, the microcomputer may have a failure because of noise or others.
(3) Clock frequency during A-D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A-D conversion.
• f(X IN) is 500 kHz or more
• Do not execute the STP instruction
3.3.9 Notes on D-A converter
(1) Vcc when using D-A converter
The D-A converter accuracy when Vcc is 4.0 V or less differs from that of when Vcc is 4.0 V or more.
When using the D-A converter, we recommend using a Vcc of 4.0 V or more.
(2) D-Ai conversion register when not using D-A converter
When a D-A converter is not used, set all values of the D-Ai conversion registers (i = 1, 2) to “00 16”.
The initial value after reset is “00 16”.
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APPENDIX
3.3 Notes on use
3.3.10 Notes on watchdog timer
● Make sure that the watchdog timer does not underflow while waiting Stop release, because the
watchdog timer keeps counting during that term.
● When the STP instruction disable bit has been set to “1”, it is impossible to switch it to “0” by a
program.
3.3.11 Notes on RESET pin
(1) Connecting capacitor
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the V SS pin. Use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
■ Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
3.3.12 Notes on CPU reprogramming mode
(1) Transfer the CPU reprogramming mode control program to the internal RAM before selecting the
CPU reprogramming mode, and then, execute it on the internal RAM. Additionally, when the subroutine
or stack operation instruction is used in the control program, make sure the control program is not
destroyed by the stack operation.
(2) Make sure each instruction description (specified address etc.) is correct, because the CPU reprogramming
mode control program is transferred to the internal RAM and executed on the internal RAM.
(3) In order to avoid generation of a watchdog timer reset, write to the watchdog timer control register
periodically during the CPU reprogramming mode control program (refer to “2.7 Watchdog timer”).
(4) Notes on flash memory version
The CNVSS pin is connected to the internal memory circuit block by a low-ohmic resistance, since it
works as a program power source pin (V PP pin), as well.
To improve the noise margin, connect the CNV SS pin to V SS through 1 to 10 kΩ resistor.
When the CNVSS pin of the mask ROM version is connected to Vss through this resistor, the function
of mask ROM version works well in the same manner as flash memory version.
3.3.13 Notes on using stop mode
■Clock restoration
After restoration to the normal mode from the stop mode by an interrupt request, the contents of
the CPU mode register previous to the STP instruction execution are retained. Accordingly, if both
main clock and sub clock were oscillating before execution of the STP instruction, the oscillation
of both clocks is resumed at restoration.
In the above case, when the main clock side is set as a system clock, the oscillation stabilizing
time for approximately 8,000 cycles of the XIN input is reserved at restoration from the stop mode.
At this time, note that the oscillation on the sub clock side may not be stabilized even after the
lapse of the oscillation stabilizing time of the main clock side.
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APPENDIX
3.3 Notes on use
3.3.14 Notes on wait mode
■Clock restoration
If the wait mode is released by a reset when X CIN is set as the system clock and X IN oscillation is
stopped during execution of the WIT instruction, XCIN oscillation stops, XIN oscillation starts, and XIN
is set as the system clock.
In the above case, the RESET pin should be held at “L” until the oscillation is stabilized.
3.3.15 Notes on low-speed operation mode
(1) Using sub-clock
To use a sub-clock, fix bit 3 of the CPU mode register to “1” and control the Rd (refer to Figure 3.3.6)
resistance value to a certain level to stabilize an oscillation. For resistance value of Rd, consult the
oscillator manufacturer.
XCIN
XCOUT
Rf
CCIN
Rd
CCOUT
Fig. 3.3.6 Ceramic resonator circuit
■ Reason
When the bit 3 of the CPU mode register is set to “0”, the sub-clock oscillation may stop.
3.3.16 Notes on restarting oscillation
(1) Restarting oscillation
Usually, when the MCU stops the clock oscillation by STP instruction and the STP instruction has
been released by an external interrupt source, the fixed values of Timer 1 and Prescaler 12 (Timer
1 = 0116, Prescaler 12 = FF16) are automatically reloaded in order for the oscillation to stabilize. The
user can inhibit the automatic setting by writing “1” to bit 6 of the port control register 2 (address
002F16).
However, by setting this bit to “1”, the previous values, set just before the STP instruction was
executed, will remain in Timer 1 and Prescaler 12. Therefore, you will need to set an appropriate
value to each register, in accordance with the oscillation stabilizing time, before executing the STP
instruction.
■ Reason
Oscillation will restart when an external interrupt is received. However, internal clock phi is supplied
to the CPU only when Timer 1 underflows. This ensures time for the clock oscillation using the
ceramic resonators to be stabilized.
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APPENDIX
3.3 Notes on use
3.3.17 Notes on programming
(1) Processor status register
➀ Initializing of processor status register
Flags which affect program execution must be initialized after a reset.
In particular, it is essential to initialize the T and D flags because they have an important effect
on calculations.
■ Reason
After a reset, the contents of the processor status register (PS) are undefined except for the I
flag which is “1”.
Reset
↓
Initializing of flags
↓
Main program
Fig. 3.3.7 Initialization of processor status register
➁ How to reference the processor status register
To reference the contents of the processor status register (PS), execute the PHP instruction once
then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its
original status.
A NOP instruction should be executed after every PLP instruction.
PLP instruction execution
↓
NOP
(S)
(S)+1
Fig. 3.3.8 Sequence of PLP instruction execution
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Stored PS
Fig. 3.3.9 Stack memory contents after PHP
instruction execution
3886 Group User’s Manual
APPENDIX
3.3 Notes on use
(2) BRK instruction
➀ Detection of interrupt source
It can be detected that the BRK instruction interrupt event or the least priority interrupt event by
referring the stored B flag state. Refer to the stored B flag state in the interrupt routine.
(S) 7
4
(S)+1
1
0
=B flag
PS
(S)+2 PCL (Low-order of program counter)
(S)+3 PCH (High-order of program counter)
Fig. 3.3.10 Interrupt routine
➁ Interrupt priority level
When the BRK instruction is executed with the following conditions satisfied, the interrupt execution
is started from the address of interrupt vector which has the highest priority.
• Interrupt request bit and interrupt enable bit are set to “1”.
• Interrupt disable flag (I) is set to “1” to disable interrupt.
(3) Decimal calculations
➀ Execution of decimal calculations
The ADC and SBC are the only instructions which will yield proper decimal notation, set the
decimal mode flag (D) to “1” with the SED instruction. After executing the ADC or SBC instruction,
execute another instruction before executing the SEC, CLC, or CLD instruction.
➁ Notes on status flag in decimal mode
When decimal mode is selected, the values of three of the flags in the status register (the N, V,
and Z flags) are invalid after a ADC or SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared
to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C
flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be
initialized to “1” before each calculation.
Set D flag to “1”
↓
ADC or SBC instruction
↓
NOP instruction
↓
SEC, CLC, or CLD instruction
Fig. 3.3.11 Status flag at decimal calculations
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APPENDIX
3.3 Notes on use
(4) JMP instruction
When using the JMP instruction in indirect addressing mode, do not specify the last address on a
page as an indirect address.
3.3.18 Programming and test of built-in PROM version
As for in the One Time PROM version (shipped in blank) and the built-in EPROM version, their built-in
PROM can be read or programmed with a general-purpose PROM programmer using a special programming
adapter.
The built-in EPROM version is available only for program development and on-chip program evaluation.
The programming test and screening for PROM of the One Time PROM version (shipped in blank) are not
performed in the assembly process and the following processes. To ensure reliability after programming,
performing programming and test according to the Figure 3.3.12 before actual use are recommended.
Programming with PROM programmer
Screening (Caution)
(Leave at 150 °C for 40 hours)
Verification with PROM programmer
Functional check in target device
Caution: The screening temperature is far higher than the
storage temperature. Never expose to 150 °C
exceeding 100 hours.
Fig. 3.3.12 Programming and testing of One Time PROM version
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APPENDIX
3.3 Notes on use
3.3.19 Notes on built-in PROM version
(1) Programming adapter
Use a special programming adapter shown in Table 3.3.1 and a general-purpose PROM programmer
when reading from or programming to the built-in PROM in the built-in PROM version.
Table 3.3.1 Programming adapters
Microcomputer
M38867E8AFS
Programming adapter
PCA4738L-80A
M38867E8AHP (One Time PROM version shipped in blank)
PCA4738H-80A
(2) Programming/reading
In PROM mode, operation is the same as that of the M5M27C101AK, but programming conditions
of PROM programmer are not set automatically because there are no internal device ID codes.
Accurately set the following conditions for data programming/reading. Take care not to apply 21 V
to V PP pin (is also used as the CNVSS pin), or the product may be permanently damaged.
• Programming voltage: 12.5 V
• Setting of PROM programmer switch: refer to Table 3.3.2.
Table 3.3.2 PROM programmer address setting
PROM programmer
Product name format
start address
PROM programmer
end address
M38867E8AFS
Address 08080 16
Address 0FFFD 16
M38867E8AHP
Note: Addresses 8080 16 to FFFD16 in the built-in PROM corresponds to addresses 0808016 to 0FFFD16 in
the PROM programmer.
(3) Erasing
Contents of the windowed EPROM are erased through an ultraviolet light source of the wavelength
2537 Ångstrom. At least 15 W • sec/cm 2 are required to erase EPROM contents.
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APPENDIX
3.4 Countermeasures against noise
3.4 Countermeasures against noise
Countermeasures against noise are described below. The following countermeasures are effective against
noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use.
3.4.1 Shortest wiring length
(1) Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin as short as possible. Especially,
connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within
20mm).
● Reason
The width of a pulse input into the RESET pin is determined by the timing necessary conditions.
If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is completely initialized. This may cause
a program runaway.
Noise
Reset
circuit
Reset
circuit
RESET
VSS
VSS
VSS
RESET
VSS
N.G.
O.K.
Fig. 3.4.1 Wiring for the RESET pin
(2) Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected
to an oscillator and the V SS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS patterns.
● Reason
If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program
failure or program runaway. Also, if a potential difference is caused by the noise between the V SS
level of a microcomputer and the V SS level of an oscillator, the correct clock will not be input in
the microcomputer.
Noise
XIN
XOUT
VSS
N.G.
XIN
XOUT
VSS
O.K.
Fig. 3.4.2 Wiring for clock I/O pins
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APPENDIX
3.4 Countermeasures against noise
(3) Wiring to CNVSS pin
Connect the CNV SS pin to the V SS pin with the shortest possible wiring.
● Reason
The processor mode of a microcomputer is influenced by a potential at the CNV SS pin. If a
potential difference is caused by the noise between pins CNVSS and VSS, the processor mode may
become unstable. This may cause a microcomputer malfunction or a program runaway.
Noise
CNVSS
CNVSS
VSS
VSS
O.K.
N.G.
Fig. 3.4.3 Wiring for CNV SS pin
(4) Wiring to V PP pin of One Time PROM version and EPROM version
Connect an approximately 5 kΩ resistor to the VPP pin the shortest possible in series and also to the
VSS pin. When not connecting the resistor, make the length of wiring between the V PP pin and the
VSS pin the shortest possible.
Note: Even when a circuit which included an approximately 5 kΩ resistor is used in the Mask ROM
version, the microcomputer operates correctly.
● Reason
The VPP pin of the One Time PROM and the EPROM version is the power source input pin for
the built-in PROM. When programming in the built-in PROM, the impedance of the VPP pin is low
to allow the electric current for writing flow into the PROM. Because of this, noise can enter easily.
If noise enters the V PP pin, abnormal instruction codes or data are read from the built-in PROM,
which may cause a program runaway.
Approximately
5kΩ
CNVSS/VPP
VSS
In the shortest
distance
Fig. 3.4.4 Wiring for the V PP pin of the One Time PROM version and the EPROM version
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APPENDIX
3.4 Countermeasures against noise
3.4.2 Connection of bypass capacitor across V SS line and V CC line
Connect an approximately 0.1 µF bypass capacitor across the V SS line and the V CC line as follows:
• Connect a bypass capacitor across the V SS pin and the V CC pin at equal length.
• Connect a bypass capacitor across the V SS pin and the V CC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for V SS line and V CC line.
• Connect the power source wiring via a bypass capacitor to the V SS pin and the V CC pin.
VCC
VCC
VSS
VSS
N.G.
O.K.
Fig. 3.4.5 Bypass capacitor across the V SS line and the VCC line
3.4.3 Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog
input pin in series. Besides, connect the resistor to the microcomputer as close as possible.
• Connect an approximately 1000 pF capacitor across the V SS pin and the analog input pin. Besides,
connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog
input pin and the V SS pin at equal length.
● Reason
Signals which is input in an analog input pin (such as an A-D converter/comparator input pin) are
usually output signals from sensor. The sensor which detects a change of event is installed far
from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer
necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer,
which causes noise to an analog input pin.
If a capacitor between an analog input pin and the VSS pin is grounded at a position far away from
the V SS pin, noise on the GND line may enter a microcomputer through the capacitor.
Noise
(Note)
Microcomputer
Analog
input pin
Thermistor
N.G.
O.K.
VSS
Note : The resistor is used for dividing
resistance with a thermistor.
Fig. 3.4.6 Analog signal line and a resistor and a capacitor
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APPENDIX
3.4 Countermeasures against noise
3.4.4 Oscillator concerns
Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected
by other signals.
(1) Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a
current larger than the tolerance of current value flows.
● Reason
In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and
thermal heads or others. When a large current flows through those signal lines, strong noise
occurs because of mutual inductance.
Microcomputer
Mutual inductance
M
XIN
XOUT
VSS
Large
current
GND
Fig. 3.4.7 Wiring for a large current signal line
(2) Installing oscillator away from signal lines where potential levels change frequently
Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential
levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines
which are sensitive to noise.
● Reason
Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect
other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms
may be deformed, which causes a microcomputer failure or a program runaway.
N.G.
Do not cross
CNTR
XIN
XOUT
VSS
Fig. 3.4.8 Wiring of RESET pin
3886 Group User’s Manual
3-47
APPENDIX
3.4 Countermeasures against noise
(3) Oscillator protection using VSS pattern
As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the
position (on the component side) where an oscillator is mounted.
Connect the V SS pattern to the microcomputer V SS pin with the shortest possible wiring. Besides,
separate this V SS pattern from other V SS patterns.
An example of VSS patterns on the
underside of a printed circuit board
Oscillator wiring
pattern example
XIN
XOUT
VSS
Separate the VSS line for oscillation from other VSS lines
Fig. 3.4.9 V SS pattern on the underside of an oscillator
3.4.5 Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an I/O port in series.
<Software>
• As for an input port, read data several times by a program for checking whether input levels are
equal or not.
• As for an output port, since the output data may reverse because of noise, rewrite data to its port
latch at fixed periods.
• Rewrite data to direction registers at fixed periods.
Note: When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse
may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise
pulse.
O.K.
Noise
Data bus
Noise
Direction register
N.G.
Port latch
I/O port
pins
Fig. 3.4.10 Setup for I/O ports
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3886 Group User’s Manual
APPENDIX
3.4 Countermeasures against noise
3.4.6 Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer
and the microcomputer can be reset to normal operation. This is equal to or more effective than program
runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer
provided by software.
In the following example, to reset a microcomputer to normal operation, the main routine detects errors of
the interrupt processing routine and the interrupt processing routine detects errors of the main routine.
This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
<The main routine>
• Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value
N in the SWDT once at each execution of the main routine. The initial value N should satisfy the
following condition:
N+1 ≥ ( Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others,
the initial value N should have a margin.
• Watches the operation of the interrupt processing routine by comparing the SWDT contents with
counts of interrupt processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and determines to branch to the program
initialization routine for recovery processing in the following case:
If the SWDT contents do not change after interrupt processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt processing.
• Determines that the main routine operates normally when the SWDT contents are reset to the
initial value N at almost fixed cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch to the program initialization
routine for recovery processing in the following case:
If the SWDT contents are not initialized to the initial value N but continued to decrement and if
they reach 0 or less.
≠N
Main routine
Interrupt processing routine
(SWDT)← N
(SWDT) ← (SWDT)—1
CLI
Interrupt processing
Main processing
(SWDT)
≤0?
(SWDT)
=N?
N
Interrupt processing
routine errors
≤0
>0
RTI
Return
Main routine
errors
Fig. 3.4.11 Watchdog timer by software
3886 Group User’s Manual
3-49
APPENDIX
3.5 List of registers
3.5 List of registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)
[Address : 0016, 0216, 0416, 0616, 0816, 0A16, 0C16, 0E16, 1016]
B
Name
0 Port Pi0
Function
●
In output mode
Write
Port latch
Read
●
In input mode
Write : Port latch
Read : Value of pins
1 Port Pi1
2 Port Pi2
At reset
R W
Undefined
Undefined
Undefined
3 Port Pi3
Undefined
4 Port Pi4
Undefined
5 Port Pi5
Undefined
6 Port Pi6
Undefined
7 Port Pi7
Undefined
Fig. 3.5.1 Structure of Port Pi
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)
[Address : 01 16, 03 16, 05 16, 0716, 0916, 0B16, 0D 16, 0F16, 1116]
B
Function
Name
0 Port Pi direction register
1
2
3
4
5
6
7
0 : Port Pi 0 input mode
1 : Port Pi 0 output mode
0 : Port Pi 1 input mode
1 : Port Pi 1 output mode
0 : Port Pi 2 input mode
1 : Port Pi 2 output mode
0 : Port Pi 3 input mode
1 : Port Pi 3 output mode
0 : Port Pi 4 input mode
1 : Port Pi 4 output mode
0 : Port Pi 5 input mode
1 : Port Pi 5 output mode
0 : Port Pi 6 input mode
1 : Port Pi 6 output mode
0 : Port Pi 7 input mode
1 : Port Pi 7 output mode
Fig. 3.5.2 Structure of Port Pi direction register
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3886 Group User’s Manual
At reset
R W
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
APPENDIX
3.5 List of registers
I2C data shift register
b7 b6 b5 b4 b3 b2 b1 b0
I2C data shift register (S0) [Address : 1216]
B
Function
0 This register is an 8-bit shift register to store receive data or write
At reset
R W
?
transmit data.
1
?
2
?
3
?
4
?
5
?
6
?
7
?
Note: Secure 8 machine cycles from clearing MST bit to “0” (slave mode) until writing
data to I2C data shift register.
If executing the read-modify-write instruction(SEB, CLB etc.) for this register
during transfer, data may become a value not intended.
Fig. 3.5.3 Structure of I 2C data shift register
I2C address register
b7 b6 b5 b4 b3 b2 b1 b0
I2C address register (S0D) [Address : 1316]
B
Name
0 Read / write bit (RWB)
Function
At reset
0 : Write bit
1 : Read bit
These bits are compared with the
1 Slave address
(SAD0, SAD1, SAD2, SAD3, address data transmitted from the
master.
SAD4, SAD5, SAD6)
2
0
3
0
4
0
5
0
6
0
7
0
R W
0
0
Note: If the read-modify-write instruction(SEB, CLB, etc.) is executed for this register
at detecting the stop condition, data may become a value not to intend.
Fig. 3.5.4 Structure of I 2C address register
3886 Group User’s Manual
3-51
APPENDIX
3.5 List of registers
I2C status register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address : 1416]
Name
B
L
a
s
t
r
e
c
e
i
v
e
bit (LRB)
0
1
2
3
4
5
6
7
Function
0 : Last bit = “0”
1 : Last bit = “1”
(Note1)
General call detecting
0 : No general call detected
1 : General call detected(Note1, 2)
flag(AD0)
Slave address comparison
0 : Address disagreement
1 : Address agreement (Note1, 2)
flag (AAS)
Arbitration lost detecting flag 0 : Not detected
(AL)
1 : Detected
(Note1)
SCL pin low hold bit (PIN)
0 : SCL pin low hold
1 : SCL pin low release
Bus busy flag (BB)
0 : Bus free
1 : Bus busy
Communication mode
00 : Slave receive mode
specification bits (TRX, MST) 01 : Slave transmit mode
10 : Master receive mode
11 : Master transmit mode
At reset
R W
?
✕
0
✕
0
✕
0
✕
1
✽
0
0
0
Notes 1: These bits and flags can be read out, but cannot be written.
2
2: These bits can be detected when data format selection bit (ALS) of I C control
register is “0”.
3: Do not execute the read-modify-write instruction (SEB, CLB) for this register
because all bits of this register are changed by hardware.
✽: “1” can be written to this bit, but “0” cannot be written by program.
Fig. 3.5.5 Structure of I 2C status register
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3886 Group User’s Manual
APPENDIX
3.5 List of registers
I2C control register
b7 b6 b5 b4 b3 b2 b1 b0
I2C control register (S1D) [Address :1516]
Name
B
B
i
t
c
o
u
n
t
e
r
(
Number of
0
1
transmit/receive bits)
(BC0, BC1, BC2)
2
3 I2C-BUS interface enable bit
(ES0)
4 Data format selection bit
(ALS)
5 Addressing format selection
bit (10 BIT SAD)
Function
b2 b1 b0
0 0 0:8
0 0 1:7
0 1 0:6
0 1 1:5
1 0 0:4
1 0 1:3
1 1 0:2
1 1 1:1
0 : Disabled
1 : Enabled
0 : 7-bit addressing format
1 : 10-bit addressing format
0
7 I2C-BUS interface pin input
0 : CMOS input
1 : SMBUS input
level selection bit (TISS)
0
0
0 : System clock stop when
executing WIT or STP
instruction
1 : Not system clock stop when
executing WIT instruction
(Do not use the STP
instruction.)
R W
0
0 : Addressing format
1 : Free data format
6 System clock stop selection
bit (CLKSTP)
At reset
0
0
Notes : When the read-modify-write instruction is executed for this register at detecting
the START condition or at completing the byte transfer, data may become a
value not intended.
Fig. 3.5.6 Structure of I 2C control register
3886 Group User’s Manual
3-53
APPENDIX
3.5 List of registers
I2C clock control register
b7 b6 b5 b4 b3 b2 b1 b0
I2C clock control register (S2) [Address : 1616]
B
Name
0 SCL frequency control bits
Function
At reset
Refer to Table 3.5.1
0
0 : Standard clock mode
1 : High-speed clock mode
0 : ACK is returned
1 : ACK is not returned
0 : No ACK clock
1 : ACK clock
0
(CCR0, CCR1, CCR2, CCR3,
CCR4)
1
2
3
4
5 SCL mode specification bit
(FAST MODE)
6 ACK bit (ACK BIT)
7 ACK clock bit (ACK)
Fig. 3.5.7 Structure of I 2C clock control register
Table 3.5.1 Set value of I 2C clock control register and SCL frequency
Setting value of
CCR4–CCR0
CCR4 CCR3 CCR2 CCR1 CCR0
1
1
1
1
1
1
1
1
1
0
1
1
0
1
0
1
0
1
0
…
…
0
0
1
1
0
0
1
…
0
0
0
0
1
1
1
…
0
0
0
0
0
0
0
…
0
0
0
0
0
0
0
1
0
1
SCL frequency
(at φ = 4 MHz, unit : kHz) (Note 3)
Standard clck
High-speed
mode
clock mode
Setting disabled
Setting disabled
Setting disabled
Setting disabled
Setting disabled
Setting disabled
– (Note 1)
333
– (Note 1)
250
400 (Note 2)
100
166
83.3
500/CCR value
1000/CCR value
34.5
33.3
32.3
17.2
16.6
16.1
Notes 1: Each value of S CL frequency exceeds the limit at φ = 4 MHz or more. When using these setting value, use φ of
4 MHz or less.
2: The data formula of SCL frequency is described below:
φ/(8 ✕ CCR value) Standard clock mode
φ/(4 ✕ CCR value) High-speed clock mode (CCR value ≠ 5)
φ/(2 ✕ CCR value) High-speed clock mode (CCR value = 5)
Do not set 0 to 2 as CCR value regardless of φ frequency.
Set 100 kHz (max.) in the standard clock mode and 400 kHz (max.) in the high-speed clock mode to the S CL
frequency by setting the SCL frequency control bits CCR4 to CCR0.
3: Duty of SCL clock output is 50 %. The duty becomes 35 to 45 % only when the high-speed clock mode is selected
and CCR value = 5 (400 kHz, at φ = 4 MHz). “H” duration of the clock fluctuates from –4 to +2 machine cycles in
the standard clock mode, and fluctuates from –2 to +2 machine cycles in the high-speed clock mode. In the case of
negative fluctuation, the frequency does not increase because “L” duration is extended instead of “H” duration
reduction.
These are value when S CL clock synchronization by the synchronous function is not performed. CCR value is the
decimal notation value of the SCL frequency control bits CCR4 to CCR0.
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3886 Group User’s Manual
0
0
R W
APPENDIX
3.5 List of registers
I2C START/STOP condition control register
b7 b6 b5 b4 b3 b2 b1 b0
I2C START/STOP condition control register (S2D) [Address : 1716]
Function
B
Name
0 START/STOP condition set bit SCL release time=
(SSC0, SSC1, SSC2, SSC3,
SSC4)
(Note)
1
φ(µs) ✕ (SSC+1)
At reset
R W
?
Set up time=
φ(µs) ✕ (SSC+1)/2
2
Hold time=
φ(µs) ✕ (SSC+1)/2
3
4
5 SCL/SDA interrupt pin polarity
selection bit(SIP)
6 SCL/SDA interrupt pin selection
bit (SIS)
7 START/STOP condition
generating selection bit
(STSPSEL)
0 : Falling edge active
1 : Rising edge active
0
0 : SDA valid
1 : SCL valid
0 : Setup/Hold time short mode
1 : Setup/Hold time long mode
0
0
Note: Do not set “000002” or an odd number to the START/STOP condition set bit
(SSC4 to SSC0).
Fig. 3.5.8 Structure of I 2C START/STOP condition control register
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB) [Address : 1816]
B
Name
Function
0 The transmission data is written to or the receive data is read out
from this buffer register.
1 • At writing: A data is written to the transmit buffer register.
• At reading: The contents of the receive buffer register are read
out.
2
At reset
R W
?
?
?
3
?
4
?
5
?
6
?
7
?
Note: The contents of transmit buffer register cannot be read out.
The data cannot be written to the receive buffer register.
Fig. 3.5.9 Structure of Transmit/Receive buffer register
3886 Group User’s Manual
3-55
APPENDIX
3.5 List of registers
Serial I/O1 status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 status register (SIO1STS) [Address : 1916]
Name
B
0 Transmit buffer empty flag
(TBE)
1 Receive buffer full flag (RBF)
2 Transmit shift register shift
completion flag (TSC)
3 Overrun error flag (OE)
4 Parity error flag (PE)
5 Framing error flag (FE)
Function
At reset
R W
0 : Buffer full
1 : Buffer empty
0 : Buffer empty
1 : Buffer full
0 : Transmit shift in progress
1 : Transmit shift completed
0 : No error
1 : Overrun error
0
✕
0
✕
0
✕
0
✕
0 : No error
1 : Parity error
0 : No error
1 : Framing error
0
✕
0
✕
0
✕
1
✕
0 : (OE) U (PE) U (FE) = 0
1 : (OE) U (PE) U (FE) = 1
7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “1”.
6 Summing error flag (SE)
Fig. 3.5.10 Structure of Serial I/O1 status register
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register (SIO1CON) [Address : 1A16]
B
Name
0 BRG count source
selection bit (CSS)
1 Serial I/O1 synchronous
clock selection bit (SCS)
2 SRDY1 output enable bit
(SRDY)
3 Transmit interrupt
source selection bit (TIC)
4 Transmit enable bit (TE)
5 Receive enable bit (RE)
6 Serial I/O1 mode selection bit
(SIOM)
7 Serial I/O1 enable bit
(SIOE)
Function
0 : f(XIN) (f(XCIN) in Low Speed Mode)
1 : f(XIN)/4 (f(XCIN)/4 in Low Speed Mode)
• In clock synchronous serial I/O
0 : BRG output devided by 4
1 : External clock input
• In UART
0 : BRG output devided by 16
1 : External clock input devided by 16
0
0 : P47 pin operates as ordinary I/O pin
1 : P47 pin operates as SRDY1 output pin
0
0 : Interrupt when transmit buffer has emptied
1 : Interrupt when transmit shift operation is
completed
0 : Transmit disabled
1 : Transmit enabled
0 : Receive disabled
1 : Receive enabled
0 : Clock asynchronous(UART) serial I/O
1 : Clock synchronous serial I/O
0
0 : Serial I/O1 disabled
(pins P44 to P47 operate as ordinary I/O pins)
1 : Serial I/O1 enabled
(pins P44 to P47 operate as serial I/O pins)
0
Fig. 3.5.11 Structure of Serial I/O1 control register
3-56
At reset
3886 Group User’s Manual
0
0
0
0
R W
APPENDIX
3.5 List of registers
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register (UARTCON) [Address : 1B16]
B
Name
Function
0 : 8 bits
1 : 7 bits
(CHAS)
0 : Parity checking disabled
Parity enable bit
1 : Parity checking enabled
(PARE)
0 : Even parity
Parity selection bit
1 : Odd parity
(PARS)
0 : 1 stop bit
Stop bit length selection bit
1 : 2 stop bits
(STPS)
In output mode
P45/TxD P-channel output
0
: CMOS output
disable bit (POFF)
1 : N-channel open-drain output
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “1”.
At reset
0 Character length selection bit
0
1
0
2
3
4
5
R W
0
0
0
1
✕
6
1
✕
7
1
✕
Fig. 3.5.12 Structure of UART control register
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator (BRG) [Address : 1C16]
B
Function
Set
a
count
value
of
baud
rate
generator.
0
At reset
R W
?
1
?
2
?
3
?
4
?
5
?
6
?
7
?
Fig. 3.5.13 Structure of Baud rate generator
3886 Group User’s Manual
3-57
APPENDIX
3.5 List of registers
Serial I/O2 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register (SIO2CON) [Address : 1D16 ]
B
Name
0
Function
b2 b1 b0
Internal synchronous clock
selection bits
0 0 0: f(XIN)/8
0 0 1: f(XIN)/16
0 1 0: f(XIN)/32
0 1 1: f(XIN)/64
1 1 0: f(XIN)/128
1 1 1: f(XIN)/256
1
2
0: I/O port (P71, P72)
1: SOUT2,SCLK2 signal output
0
: I/O port (P73)
SRDY2 output enable bit
1: SRDY2 signal output
Transfer direction selection bit 0: LSB first
1: MSB first
Serial I/O2 synchronous clock 0: External clock
selection bit
1: Internal clock
Comparator reference input
0: P00/P3REF input
selection bit
1: Reference input fixed
Serial I/O2 port selection bit
3
4
5
6
7
At reset
R W
0
0
0
0
0
0
0
0
Fig. 3.5.14 Structure of Serial I/O2 control register
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog timer control register (WDTCON) [Address : 1E16]
Function
B
Name
0 Watchdog timer H (for read-out of high-order 6 bits)
R W
1
✕
1
1
✕
2
1
✕
3
1
✕
4
1
✕
5
1
✕
6 STP instruction disable bit
7 Watchdog timer H count
source selection bit
0 : STP instruction enabled
1 : STP instruction disabled
0 : Watchdog timer L underflow
1 : f(XIN)/16 or f(XCIN)/16
Fig. 3.5.15 Structure of Watchdog timer control register
3-58
At reset
3886 Group User’s Manual
0
0
APPENDIX
3.5 List of registers
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 register (SIO2) [Address : 1F16]
B
Name
Function
At reset
0 •Serial I/O2 register is the shift register for serial transfer.
?
•At transmit: transmit data is set.
1 •At receive: receive data is set.
?
2
?
3
?
4
?
5
?
6
?
7
?
R W
Fig. 3.5.16 Structure of Serial I/O2 register
Prescaler 12, Prescaler X, Prescaler Y
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 12 (PRE12) [Address : 20 16]
Prescaler X (PREX) [Address : 24 16]
Prescaler Y (PREY) [Address : 26 16]
B
Name
Function
0 •Set a count value of each prescaler.
•The value set in this register is written to both each prescaler
1 and the corresponding prescaler latch at the same time.
•When this register is read out, the count value of the corres2 ponding prescaler is read out.
At reset
R W
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 3.5.17 Structure of Prescaler 12, Prescaler X, Prescaler Y
3886 Group User’s Manual
3-59
APPENDIX
3.5 List of registers
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1 (T1) [Address : 21 16]
B
Name
Function
0 •Set a count value of timer 1.
At reset
R W
1
•The value set in this register is written to both timer 1 and timer 1
latch at the same time.
•When this register is read out, the timer 1’s count value is read
2 out.
1
0
0
3
0
4
0
5
0
6
0
7
0
Fig. 3.5.18 Structure of Timer 1
Timer 2, Timer X, Timer Y
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2 (T2) [Address : 22 16]
Timer X (TX) [Address : 25 16]
Timer Y (TY) [Address : 27 16]
B
Name
Function
0 •Set a count value of each timer.
•The value set in this register is written to both each timer and
1 each timer latch at the same time.
•When this register is read out, each timer’s count value is read
2 out.
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 3.5.19 Structure of Timer 2, Timer X, Timer Y
3-60
At reset
3886 Group User’s Manual
R W
APPENDIX
3.5 List of registers
Timer XY mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer XY mode register (TM) [Address : 23 16]
B
Function
Name
0 Timer X operating mode bits
1
At reset
b1 b0
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement
mode
0
0
The function depends on the
operating mode of Timer X.
(Refer to Table 3.5.2)
0
3 Timer X count stop bit
0 : Count start
1 : Count stop
0
4 Timer Y operating mode bits
b5 b4
0
2 CNTR 0 active edge selection
bit
5
6 CNTR 1 active edge selection
bit
7 Timer Y count stop bit
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement
mode
The function depends on the
operating mode of Timer Y.
(Refer to Table 3.5.2)
0 : Count start
1 : Count stop
R W
0
0
0
Fig. 3.5.20 Structure of Timer XY mode register
Table 3.5.2 CNTR 0 /CNTR 1 active edge selection bit function
Timer X /Timer Y operation
modes
Timer mode
CNTR0 / CNTR1 active edge selection bit
(bits 2, 6 of address 2316) contents
“0” CNTR 0 / CNTR 1 interrupt request occurrence: Falling edge
; No influence to timer count
“1” CNTR 0 / CNTR 1 interrupt request occurrence: Rising edge
; No influence to timer count
Pulse output mode
“0” Pulse output start: Beginning at “H” level
CNTR 0 / CNTR 1 interrupt request occurrence: Falling edge
“1” Pulse output start: Beginning at “L” level
Event counter mode
CNTR 0 / CNTR 1 interrupt request occurrence: Rising edge
“0” Timer X / Timer Y: Rising edge count
CNTR 0 / CNTR 1 interrupt request occurrence: Falling edge
“1” Timer X / Timer Y: Falling edge count
CNTR 0 / CNTR 1 interrupt request occurrence: Rising edge
Pulse width measurement mode
“0” Timer X / Timer Y: “H” level width measurement
CNTR 0 / CNTR 1 interrupt request occurrence: Falling edge
“1” Timer X / Timer Y: “L” level width measurement
CNTR 0 / CNTR 1 interrupt request occurrence: Rising edge
3886 Group User’s Manual
3-61
APPENDIX
3.5 List of registers
Data bus buffer register i
b7 b6 b5 b4 b3 b2 b1 b0
Data bus buffer register i (DBBi) (i=0, 1) [Address : 2816/2B16]
B
Name
Function
At reset
0 • Buffer register to write output data and read input data.
1
R W
?
• at write: data is written to output data buffer register.
• at read: the contents of input data buffer register are read out.
?
2
?
3
?
4
?
5
?
6
?
7
?
Note: Output data bus buffer and input data bus buffer are ssigned to the same address.
The contents of output data bus buffer register cannot be read out.
Writing to input data bus buffer register is disabled.
Fig. 3.5.21 Structure of Data bus buffer register
Data bus buffer status register i
b7 b6 b5 b4 b3 b2 b1 b0
Data bus buffer status register i (DBBSTSi) (i=0, 1) [Address 2916/2C16]
B
Name
Function
R W
0
✕
0
✕
3 A0i flag
This flag indicates the condition of
A0i status when the IBFi flag is set.
4 User definable flags (This flag can be defined by user freely.)
0
5
0
6
0
7
0
Fig. 3.5.22 Structure of Data bus buffer status register
3-62
At reset
0 : Buffer empty
1 : Buffer full
0 : Buffer empty
1 Input buffer full flag i
1 : Buffer full
2 User definable flags (This flag can be defined by user freely.)
0 Output buffer full flag i
3886 Group User’s Manual
0
0
✕
APPENDIX
3.5 List of registers
Data bus buffer control register
b7 b6 b5 b4 b3 b2 b1 b0
Data bus buffer control register (DBBCON) [Address 2A16]
B
Name
0 Data bus buffer enable bit
Function
At reset
0 : P50–P53, P8 I/O port
1 : Data bus buffer enabled
0
0 : Single data bus buffer mode
(P47 functions as I/O port.)
1 : Double data bus buffer mode
(P47 functions as S1 input.)
0
2 OBF0 output selection bit
0 : OBF00 valid
1 : OBF01 valid
0
3 OBF00 output enable bit
0 : P42 functions as port I/O pin.
1 : P42 functions as OBF00 output
pin.
0
4 OBF01 output enable bit
0 : P43 functions
1 : P43 functions
pin.
0 : P46 functions
1 : P46 functions
pin.
as port I/O pin.
as OBF01 output
0
as port I/O pin.
as OBF10 output
0
1 Data bus buffer function
selection bit
5 OBF10 output enable bit
6 Input level selection bit
0 : CMOS level input
1 : TTL level input
7 Fix this bit to “0”.
R W
0
0
Fig. 3.5.23 Structure of Data bus buffer control register
Comparator data register
b7 b6 b5 b4 b3 b2 b1 b0
Comparator data register (CMPD) [Address : 2D 16]
B
Name
Function
At reset
0 • At writing: The voltage comparison is immediately performed by
?
writing operation.
1 • At reading: The comparison result is read out.
?
2
?
3
?
4
?
5
?
6
?
7
?
R W
Fig. 3.5.24 Structure of Comparator data register
3886 Group User’s Manual
3-63
APPENDIX
3.5 List of registers
Port control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Port control register 1 (PCTL1) [Address 2E16]
B
Name
0 P00–P03 output structure
1
2
3
4
selection bit
P04–P07 output structure
selection bit
P10–P13 output structure
selection bit
P14–P17 output structure
selection bit
P30–P33 pull-up control bit
5 P34–P37 pull-up control bit
6 PWM0 enable bit
7 PWM1 enable bit
Function
0: CMOS
1: N-channel open-drain
0: CMOS
1: N-channel open-drain
0: CMOS
1: N-channel open-drain
0: CMOS
1: N-channel open-drain
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: PWM0 output disabled
1: PWM0 output enabled
0: PWM1 output disabled
1: PWM1 output enabled
At reset
R W
0
0
0
0
0
0
0
0
Fig. 3.5.25 Structure of Port control register 1
Port control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Port control register 2 (PCTL2) [Address 2F16]
Name
B
0 P4 input level selection bit
(P42–P46)
P
1 7 input level selection bit
(P70–P75)
2 P4 output structure selection bit
(P42, P43, P44, P46)
3 P8 function selection bit
4
5
6
7
Function
0: CMOS level input
1: TTL level input
0: CMOS level input
1: TTL level input
0: CMOS
1: N-channel open-drain
0: Port P8/Port P8 direction
register
1: Port P4 input register/Port P7
input register
INT2, INT3, INT4 interrupt
0: INT20, INT30, INT40 interrupt
switch bit
1: INT21, INT31, INT41 interrupt
Timer Y count source
0: f(XIN)/16 (f(XCIN)/16 in lowselection bit
speed mode)
1: f(XCIN)
Oscillation stabilizing time set 0: Automatic set “0116” to timer 1
after STP instruction released
and “FF16” to prescaler 12
bit
1: No automatic set
0: Only software clear
Port output P42/P43 clear
1: Software clear and output data
function selection bit
bus buffer 0 reading
(system bus side)
Fig. 3.5.26 Structure of Port control register 2
3-64
3886 Group User’s Manual
At reset
0
0
0
0
0
0
0
0
R W
APPENDIX
3.5 List of registers
PWM0H register
b7 b6 b5 b4 b3 b2 b1 b0
PWM0H register (PWM0H) [Address : 3016]
B
Function
0 • The high-order 8 bits of the PWM0H output data are set.
• At writing: A written data is transferred to PWM0 latch at every
1
sub-period (64 µs).
(f(XIN) = 8 MHz)
2 • At reading: The contents of the PWM0H register are read out.
At reset
R W
?
?
?
3
?
4
?
5
?
6
?
7
?
Fig. 3.5.27 Structure of PWM0H register
PWM0L register
b7 b6 b5 b4 b3 b2 b1 b0
PWM0L register (PWM0L) [Address : 3116]
Function
B
0 • The low-order 6 bits of the PWM0L output data are set.
• At writing: A written data is transferred to PWM0 latch at every
repetitive period (4096 µs).
(f(XIN) = 8 MHz)
2
• At reading: The low-order 6 bits of PWM0 latch are read out.
1
At reset
R W
?
?
?
3
?
4
?
5
?
6 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
7 • The completion of transfer to the PWM0 latch is indicated.
0: Transfer completed.
1: Not transferred.
• At writing: This bit is set to “1”.
?
✕
?
✕
Fig. 3.5.28 Structure of PWM0L register
3886 Group User’s Manual
3-65
APPENDIX
3.5 List of registers
PWM1H register
b7 b6 b5 b4 b3 b2 b1 b0
PWM1H register (PWM1H) [Address : 3216]
B
Function
0 • The high-order 8 bits of the PWM1H output data are set.
• At writing: A written data is transferred to PWM1 latch at every
1
sub-period (64 µs).
(f(XIN) = 8 MHz)
2 • At reading: The contents of the PWM1H register are read out.
At reset
R W
?
?
?
3
?
4
?
5
?
6
?
7
?
Fig. 3.5.29 Structure of PWM1H register
PWM1L register
b7 b6 b5 b4 b3 b2 b1 b0
PWM1L register (PWM1L) [Address : 3316]
Function
B
0 • The low-order 6 bits of the PWM1L output data are set.
• At writing: A written data is transferred to PWM1 latch at every
repetitive period (4096 µs).
(f(XIN) = 8 MHz)
2
• At reading: The low-order 6 bits of PWM1 latch are read out.
1
R W
?
?
?
3
?
4
?
5
?
6 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
?
✕
7 • The completion of transfer to the PWM1 latch is indicated.
?
✕
0: Transfer completed.
1: Not transferred.
• At writing: This bit is set to “1”.
Fig. 3.5.30 Structure of PWM1L register
3-66
At reset
3886 Group User’s Manual
APPENDIX
3.5 List of registers
AD/DA control register
b7 b6 b5 b4 b3 b2 b1 b0
AD/DA control register
(ADCON: address 3416)
b
Name
Functions
0 Analog input pin
selection bits
1
2
3 AD conversion
completion bit
4 PWM0 output pin
selection bit
5 PWM1 output pin
selection bit
6 DA1 output enable
bit
7 DA2 output enable
bit
At reset R W
0
b2 b1 b0
0 0 0: P60/AN0
0 0 1: P61/AN1
0 1 0: P62/AN2
0 1 1: P63/AN3
1 0 0: P64/AN4
1 0 1: P65/AN5
1 1 0: P66/AN6
1 1 1: P67/AN7
0
0
0: Conversion in progress
1: Conversion completed
0: P56/PWM01
1: P30/PWM00
0: P57/PWM11
1: P31/PWM10
0: DA1 output disabled
1: DA1 output enabled
0: DA2 output disabled
1: DA2 output enabled
1
0
0
0
0
Fig. 3.5.31 Structure of AD/DA control register
A-D conversion register 1
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register 1 (AD1) [Address : 3516]
Function
B
0 The read-only register in which the A-D conversion’s results are
At reset
R W
?
✕
?
✕
b0
?
✕
b9 b8 b7 b6 b5 b4 b3 b2
?
✕
< 10-bit read>
?
✕
?
✕
6
?
✕
7
?
✕
stored.
1
2
3
b7
4
b7
5
< 8-bit read>
b0
b7 b6 b5 b4 b3 b2 b1 b0
Fig. 3.5.32 Structure of AD conversion register 1
3886 Group User’s Manual
3-67
APPENDIX
3.5 List of registers
D-Ai conversion register
b7 b6 b5 b4 b3 b2 b1 b0
D-Ai conversion register (DAi) (i = 1, 2)
[Address: 3616, 3716]
b
Functions
At reset R W
0 This is D-A output value stored bits. This is write
1 exclusive register.
2
3
4
5
6
7
0
0
0
0
0
0
0
0
Fig. 3.5.33 Structure of D-Ai conversion register
A-D conversion register 2
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register 2 (AD2) [Address : 38 16 ]
B
Name
Function
At reset
R W
?
✕
?
✕
?
✕
3
?
✕
4
?
✕
5
?
✕
6
?
✕
0 The read-only register in which the A-D conversion’s results are
stored.
1
b7
< 10-bit read>
b0
b9 b8
2 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
7 Conversion mode selection bit 0: 10-bit A-D mode
1: 8-bit A-D mode
Fig. 3.5.34 Structure of A-D convesion register 2
3-68
3886 Group User’s Manual
?
APPENDIX
3.5 List of registers
Interrupt source selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt source selection register [INTSEL: address 003916]
B
Name
Function
0 INT0/input buffer full interrupt 0 : INT0 interrupt
source selection bit
1 : Input buffer full interrupt
0 : INT1 interrupt
1 INT1/output buffer empty
interrupt source selection bit 1 : Output buffer empty interrupt
0 : Serial I/O1 transmit interrupt ✽1
2 Serial I/O1 transmit/SCL,SDA
interrupt source selection bit 1 : SCL,SDA interrupt
✽1
0 : CNTR0 interrupt
3 CNTR0/SCL,SDA interrupt
source selection bit
1 : SCL,SDA interrupt
✽2
0 : Serial I/O2 interrupt
4 Serial I/O2/I2C interrupt
source selection bit
1 : I2C interrupt
✽2
0 : INT2 interrupt
5 INT2/I2C interrupt source
selection bit
1 : I2C interrupt
✽3
0 : CNTR1 interrupt
6 CNTR1/key-on wake-up
interrupt source selection bit 1 : Key-on wake-up interrupt
✽3
7 AD converter/key-on wake-up 0 : A-D converter interrupt
interrupt source selection bit 1 : Key-on wake-up interrupt
✽1: Do not write “1” to these bits simultaneously.
✽2: Do not write “1” to these bits simultaneously.
✽3: Do not write “1” to these bits simultaneously.
At reset
R W
0
0
0
0
0
0
0
0
Fig. 3.5.35 Structure of Interrupt source selection register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A16]
B
Name
0 INT0 interrupt edge
1
2
3
4
5
Function
0 : Falling edge active
1 : Rising edge active
selection bit
INT1 interrupt edge
0 : Falling edge active
selection bit
1 : Rising edge active
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
0 : Falling edge active
INT2 interrupt edge
1 : Rising edge active
selection bit
0 : Falling edge active
INT3 interrupt edge
1 : Rising edge active
selection bit
0 : Falling edge active
INT4 interrupt edge
1 : Rising edge active
selection bit
6 Nothing is allocated for these bits. These are write disabled bits.
At reset
R W
0
0
0
✕
0
0
0
0
✕
0
✕
When these bits are read out, the values are “0”.
7
Fig. 3.5.36 Structure of Interrupt edge selection register
3886 Group User’s Manual
3-69
APPENDIX
3.5 List of registers
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
1
CPU mode register
(CPUM: address 3B16)
b
Name
0 Processor mode
bits
1
2 Stack page
selection bit
3 Fix this bit to “1”.
Functions
At reset R W
b1 b0
00 : Single-chip mode
01 : Memory expansion mode (Note)
10 : Microprocessor mode (Note)
11 : Not available
0 : 0 page
1 : 1 page
0
*
0
1
4 Port Xc switch bit
0: I/O port function
(oscillation stopped)
1: XCIN-XCOUT oscillation
function
0
5 Main clock (XINXOUT) stop bit
6 Main clock division
ratio selection bits
0: Oscillating
1: Stopped
0
b7 b6
1
7
0 0: φ=f(XIN)/2
(high-speed mode)
0 1: φ=f(XIN)/8
(middle-speed mode)
1 0: φ=f(XCIN)/2
(low-speed mode)
1 1: not available
0
*: The initial value of bit 1 depends on the CNVss level.
Note: This mode is not available for M38869M8A/MCA/MFA or the
flash memory version.
Fig. 3.5.37 Structure of CPU mode register
3-70
3886 Group User’s Manual
APPENDIX
3.5 List of registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address : 3C16]
Name
B
0 INT0/input buffer full interrupt
request bit
1 INT1/output buffer empty
interrupt request bit
2 Serial I/O1 receive interrupt
request bit
3 Serial I/O1 transmit/SCL, SDA
interrupt request bit
4 Timer X interrupt request bit
5 Timer Y interrupt request bit
6 Timer 1 interrupt request bit
7 Timer 2 interrupt request bit
Function
At reset
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
R W
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 3.5.38 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2) [Address : 3D16]
Name
B
0 CNTR0/SCL, SDA interrupt
Function
At reset
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
INT3 interrupt request bit
1 : Interrupt request issued
0 : No interrupt request issued
INT4 interrupt request bit
1 : Interrupt request issued
AD converter/key-on wake-up 0 : No interrupt request issued
interrupt request bit
1 : Interrupt request issued
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
request bit
1 CNTR1/key-on wake-up
interrupt request bit
2 Serial I/O2/I2C interrupt
request bit
3 INT2/I2C interrupt request bit
4
5
6
7
R W
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✕
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 3.5.39 Structure of Interrupt request register 2
3886 Group User’s Manual
3-71
APPENDIX
3.5 List of registers
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E16]
B
Name
I
N
T
0
/
i
n
p
u
t
b
uffer full interrupt
0
enable bit
1 INT1/output buffer empty
interrupt enable bit
2 Serial I/O1 receive interrupt
enable bit
3 Serial I/O1 transmit/SCL, SDA
interrupt enable bit
4 Timer X interrupt enable bit
5 Timer Y interrupt enable bit
6 Timer 1 interrupt enable bit
7 Timer 2 interrupt enable bit
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset
R W
0
0
0
0
0
0
0
0
Fig. 3.5.40 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2 (ICON2) [Address : 3F16]
Name
B
0 CNTR0/SCL, SDA interrupt
1
2
3
4
5
6
7
0 : Interrupt disabled
1 : Interrupt enabled
enable bit
0 : Interrupt disabled
CNTR1/key-on wake-up
1 : Interrupt enabled
interrupt enable bit
Serial I/O2/I2C interrupt enable 0 : Interrupt disabled
bit
1 : Interrupt enabled
INT2/I2C interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
INT3 interrupt enable bit
1 : Interrupt enabled
INT4 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
AD converter/key-on wake-up 0 : Interrupt disabled
interrupt enable bit
1 : Interrupt enabled
Fix this bit to “0”.
Fig. 3.5.41 Structure of Interrupt control register 2
3-72
Function
3886 Group User’s Manual
At reset
0
0
0
0
0
0
0
0
R W
APPENDIX
3.5 List of registers
Flash memory control register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Flash memory control register
(FCON : address FFE16)
b
Name
Functions
At reset R W
0 CPU reprogramming 0 : CPU reprogramming
mode select bit
mode is invalid. (Normal
(Note)
operation mode)
1 : When applying 0 V to
CNVSS/VPP pin, CPU
reprogramming mode is
invalid. When applying
VPPH to CNVSS/VPP pin,
CPU reprogramming
mode is valid.
0 : Erase and program are
1 Erase/Program
completed or have not
busy flag
been executed.
1 : Erase/program is being
executed.
2 CPU reprogramming 0 : CPU reprogramming
mode monitor flag
mode is invalid
1 : CPU reprogramming
mode is valid
0
3 Fix this bit to “0”.
4 Erase/Program
area select bits
0
0
5
b5 b4
0 0: Address 100016 to
FFFF16 (total 60Kbytes)
0 1: Address 100016 to
7FFF16 (total 28Kbytes)
1 0: Address 800016 to
FFFF16 (total 32Kbytes)
1 1: not available
6 Fix this bit to “0”.
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0
0
0
0
Note: Bit 0 can be reprogrammed only when 0 V is applied to the CNVSS/VPP pin.
Fig. 3.5.42 Structure of Flash memory control register
3886 Group User’s Manual
3-73
APPENDIX
3.5 List of registers
Flash command register
b7 b6 b5 b4 b3 b2 b1 b0
Flash command register
(FCMD: address FFF16)
b
Functions
0
1
2
3
4
5
6
7
Writing of software command
<Software command name>
• Read command
• Program command
• Program verify command
• Erase command
• Erase verify command
• Reset command
At reset R W
0
0
0
0
0
0
0
0
Note: The flash command register is a write-only register.
<Command code>
• “0016”
• “4016”
• “C016”
• “2016”+ “2016”
• “A016”
• “FF16” + “FF16”
Fig. 3.5.43 Structure of Flash command register
3-74
3886 Group User’s Manual
APPENDIX
3.6 Package outline
3.6 Package outline
MMP
EIAJ Package Code
LQFP80-P-1212-0.5
Plastic 80pin 12✕12mm body LQFP
Weight(g)
0.47
JEDEC Code
–
Lead Material
Cu Alloy
MD
e
80P6Q-A
b2
D
ME
HD
80
61
1
l2
Recommended Mount Pad
60
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Lp
HE
E
Symbol
41
20
21
40
A
L1
F
y
M
L
Detail F
x
y
c
x
A1
b
A3
A3
A2
e
b2
I2
MD
ME
Lp
80D0
Dimension in Millimeters
Min
Nom
Max
–
–
1.7
0.1
0.2
0
–
–
1.4
0.13
0.18
0.28
0.105
0.125
0.175
11.9
12.0
12.1
11.9
12.0
12.1
–
0.5
–
13.8
14.0
14.2
13.8
14.0
14.2
0.3
0.5
0.7
1.0
–
–
0.45
0.6
0.75
–
0.25
–
–
–
0.08
–
–
0.1
–
0°
10°
–
–
0.225
0.9
–
–
–
–
12.4
–
–
12.4
Glass seal 80pin QFN
EIAJ Package Code
–
JEDEC Code
–
21.0±0.2
Weight(g)
18.4±0.15
3.32MAX
0.8TYP
1.78TYP
0.6TYP
41
64
65
INDEX
0.5TYP
3886 Group User’s Manual
0.8TYP
12.0±0.15
1.2TYP
15.6±0.2
0.8TYP
40
25
80
24
1.2TYP
1
3-75
APPENDIX
APPENDIX
3.7 Machine instructions
3.7 Machine instructions
3.7 Machine instructions
Addressing mode
Addressing mode
Symbol
Function
Details
IMP
OP n
ADC
(Note 1)
(Note 5)
When T = 0
A←A+M+C
When T = 1
M(X) ← M(X) + M + C
AND
(Note 1)
When TV= 0
A←A M
When T = 1 V
M(X) ← M(X) M
7
ASL
C←
0
←0
IMM
# OP n
BIT,
BIT,A,AR
A
# OP n
# OP n
BIT,
BIT,ZP,
ZPR
ZP
# OP n
# OP n
#
ZP, X
ZP, Y
OP n
# OP n
ABS
ABS, X
ABS, Y
IND
# OP n
# OP n
# OP n
# OP n
Processor status register
ZP, IND
# OP n
IND, X
IND, Y
REL
# OP n
# OP n
# OP n
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
When T = 0, this instruction adds the contents
M, C, and A; and stores the results in A and C.
When T = 1, this instruction adds the contents
of M(X), M and C; and stores the results in
M(X) and C. When T=1, the contents of A remain unchanged, but the contents of status
flags are changed.
M(X) represents the contents of memory
where is indicated by X.
69 2
2
65 3
2
75 4
2
6D 4
3 7D 5
3 79 5
3
61 6
2 71 6
2
N
V
•
•
•
•
Z
C
When T = 0, this instruction transfers the contents of A and M to the ALU which performs a
bit-wise AND operation and stores the result
back in A.
When T = 1, this instruction transfers the contents M(X) and M to the ALU which performs a
bit-wise AND operation and stores the results
back in M(X). When T = 1 the contents of A remain unchanged, but status flags are
changed.
M(X) represents the contents of memory
where is indicated by X.
29 2
2
25 3
2
35 4
2
2D 4
3 3D 5
3 39 5
3
21 6
2 31 6
2
N
•
•
•
•
•
Z
•
06 5
2
16 6
2
0E 6
3 1E 7
3
N
•
•
•
•
•
Z
C
This instruction shifts the content of A or M by
one bit to the left, with bit 0 always being set to
0 and bit 7 of A or M always being contained in
C.
0A 2
1
BBC
(Note 4)
Ai or Mi = 0?
This instruction tests the designated bit i of M
or A and takes a branch if the bit is 0. The
branch address is specified by a relative address. If the bit is 1, next instruction is
executed.
13
+
20i
4
2
17
+
20i
5
3
•
•
•
•
•
•
•
•
BBS
(Note 4)
Ai or Mi = 1?
This instruction tests the designated bit i of the
M or A and takes a branch if the bit is 1. The
branch address is specified by a relative address. If the bit is 0, next instruction is
executed.
03 4
+
20i
2
07 5
+
20i
3
•
•
•
•
•
•
•
•
BCC
(Note 4)
C = 0?
This instruction takes a branch to the appointed address if C is 0. The branch address
is specified by a relative address. If C is 1, the
next instruction is executed.
90 2
2
•
•
•
•
•
•
•
•
BCS
(Note 4)
C = 1?
This instruction takes a branch to the appointed address if C is 1. The branch address
is specified by a relative address. If C is 0, the
next instruction is executed.
B0 2
2
•
•
•
•
•
•
•
•
BEQ
(Note 4)
Z = 1?
This instruction takes a branch to the appointed address when Z is 1. The branch
address is specified by a relative address.
If Z is 0, the next instruction is executed.
F0 2
2
•
•
•
•
•
•
•
•
BIT
A
M7 M6 •
•
•
•
Z
•
BMI
(Note 4)
N = 1?
This instruction takes a branch to the appointed address when N is 1. The branch
address is specified by a relative address.
If N is 0, the next instruction is executed.
30 2
2
•
•
•
•
•
•
•
•
BNE
(Note 4)
Z = 0?
This instruction takes a branch to the appointed address if Z is 0. The branch address
is specified by a relative address. If Z is 1, the
next instruction is executed.
D0 2
2
•
•
•
•
•
•
•
•
3-76
V
M
This instruction takes a bit-wise logical AND of
A and M contents; however, the contents of A
and M are not modified.
The contents of N, V, Z are changed, but the
contents of A, M remain unchanged.
3886 Group User’s Manual
24 3
2
2C 4
3
3886 Group User’s Manual
3-77
APPENDIX
APPENDIX
3.7 Machine instructions
3.7 Machine instructions
Addressing mode
Addressing mode
Symbol
Function
Details
IMP
OP n
IMM
# OP n
A
# OP n
BIT, A
# OP n
ZP
# OP n
BIT, ZP
# OP n
#
ZP, X
OP n
ZP, Y
# OP n
ABS
# OP n
ABS, X
# OP n
ABS, Y
# OP n
IND
# OP n
Processor status register
ZP, IND
# OP n
IND, X
# OP n
IND, Y
# OP n
REL
# OP n
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
BPL
(Note 4)
N = 0?
This instruction takes a branch to the appointed address if N is 0. The branch address
is specified by a relative address. If N is 1, the
next instruction is executed.
10 2
2
•
•
•
•
•
•
•
•
BRA
PC ← PC ± offset
This instruction branches to the appointed address. The branch address is specified by a
relative address.
80 4
2
•
•
•
•
•
•
•
•
BRK
B←1
(PC) ← (PC) + 2
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
M(S) ← PS
S←S–1
I← 1
PCL ← ADL
PCH ← AD H
When the BRK instruction is executed, the
CPU pushes the current PC contents onto the
stack. The BADRS designated in the interrupt
vector table is stored into the PC.
•
•
•
1
•
1
•
•
BVC
(Note 4)
V = 0?
This instruction takes a branch to the appointed address if V is 0. The branch address
is specified by a relative address. If V is 1, the
next instruction is executed.
50 2
2
•
•
•
•
•
•
•
•
BVS
(Note 4)
V = 1?
This instruction takes a branch to the appointed address when V is 1. The branch
address is specified by a relative address.
When V is 0, the next instruction is executed.
70 2
2
•
•
•
•
•
•
•
•
CLB
Ai or Mi ← 0
This instruction clears the designated bit i of A
or M.
•
•
•
•
•
•
•
•
CLC
C←0
This instruction clears C.
18 2
1
•
•
•
•
•
•
•
0
CLD
D←0
This instruction clears D.
D8 2
1
•
•
•
•
0
•
•
•
CLI
I←0
This instruction clears I.
58 2
1
•
•
•
•
•
0
•
•
CLT
T←0
This instruction clears T.
12 2
1
•
•
0
•
•
•
•
•
CLV
V←0
This instruction clears V.
B8 2
1
•
0
•
•
•
•
•
•
CMP
(Note 3)
When T = 0
A–M
When T = 1
M(X) – M
When T = 0, this instruction subtracts the contents of M from the contents of A. The result is
not stored and the contents of A or M are not
modified.
When T = 1, the CMP subtracts the contents
of M from the contents of M(X). The result is
not stored and the contents of X, M, and A are
not modified.
M(X) represents the contents of memory
where is indicated by X.
N
•
•
•
•
•
Z
C
COM
M←M
This instruction takes the one’s complement of
the contents of M and stores the result in M.
N
•
•
•
•
•
Z
•
CPX
X–M
This instruction subtracts the contents of M
from the contents of X. The result is not stored
and the contents of X and M are not modified.
E0 2
CPY
Y–M
This instruction subtracts the contents of M
from the contents of Y. The result is not stored
and the contents of Y and M are not modified.
C0 2
DEC
A ← A – 1 or
M←M–1
This instruction subtracts 1 from the contents
of A or M.
3-78
__
00 7
1
1B
+
20i
3886 Group User’s Manual
C9 2
2
1
1F
+
20i
5
2
C5 3
2
44 5
2
2
E4 3
2
EC 4
3
N
•
•
•
•
•
Z
C
2
C4 3
2
CC 4
3
N
•
•
•
•
•
Z
C
C6 5
2
CE 6
3 DE 7
N
•
•
•
•
•
Z
•
2
1A 2
1
D5 4
D6 6
2
2
CD 4
3 DD 5
3 D9 5
3
C1 6
2 D1 6
3
3886 Group User’s Manual
2
3-79
APPENDIX
APPENDIX
3.7 Machine instructions
3.7 Machine instructions
Addressing mode
Addressing mode
Symbol
Function
Details
IMP
OP n
IMM
# OP n
A
# OP n
BIT, A
# OP n
ZP
# OP n
BIT, ZP
# OP n
#
ZP, X
OP n
ZP, Y
# OP n
ABS
# OP n
ABS, X
# OP n
ABS, Y
# OP n
IND
# OP n
Processor status register
ZP, IND
# OP n
IND, X
# OP n
IND, Y
# OP n
REL
# OP n
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
DEX
X←X–1
This instruction subtracts one from the current CA 2
contents of X.
1
N
•
•
•
•
•
Z
•
DEY
Y←Y–1
This instruction subtracts one from the current
contents of Y.
88 2
1
N
•
•
•
•
•
Z
•
DIV
A ← (M(zz + X + 1),
M(zz + X )) / A
M(S) ← one's complement of Remainder
S←S–1
Divides the 16-bit data in M(zz+(X)) (low-order
byte) and M(zz+(X)+1) (high-order byte) by the
contents of A. The quotient is stored in A and
the one's complement of the remainder is
pushed onto the stack.
•
•
•
•
•
•
•
•
EOR
(Note 1)
When T = 0
–M
A←AV
When T = 0, this instruction transfers the contents of the M and A to the ALU which
performs a bit-wise Exclusive OR, and stores
the result in A.
When T = 1, the contents of M(X) and M are
transferred to the ALU, which performs a bitwise Exclusive OR and stores the results in
M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
When T = 1
–M
M(X) ← M(X) V
E2 16 2
49 2
2
45 3
2
55 4
2
4D 4
3 5D 5
3 59 5
E6 5
2
F6 6
2
EE 6
3 FE 7
3
INC
A ← A + 1 or
M←M+1
This instruction adds one to the contents of A
or M.
INX
X←X+1
This instruction adds one to the contents of X.
E8 2
1
INY
Y←Y+1
This instruction adds one to the contents of Y.
C8 2
1
JMP
If addressing mode is ABS
PCL ← ADL
PCH ← AD H
If addressing mode is IND
PCL ← M (ADH, AD L)
PCH ← M (ADH, ADL + 1)
If addressing mode is ZP, IND
PCL ← M(00, ADL)
PCH ← M(00, AD L + 1)
This instruction jumps to the address designated by the following three addressing
modes:
Absolute
Indirect Absolute
Zero Page Indirect Absolute
4C 3
3
JSR
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
After executing the above,
if addressing mode is ABS,
PCL ← ADL
PCH ← AD H
if addressing mode is SP,
PCL ← ADL
PCH ← FF
If addressing mode is ZP, IND,
PCL ← M(00, ADL)
PCH ← M(00, AD L + 1)
This instruction stores the contents of the PC
in the stack, then jumps to the address designated by the following addressing modes:
Absolute
Special Page
Zero Page Indirect Absolute
20 6
3
LDA
(Note 2)
When T = 0
A←M
When T = 1
M(X) ← M
When T = 0, this instruction transfers the contents of M to A.
When T = 1, this instruction transfers the contents of M to (M(X)). The contents of A remain
unchanged, but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
AD 4
3 BD 5
LDM
M ← nn
This instruction loads the immediate value in
M.
LDX
X←M
This instruction loads the contents of M in X.
A2 2
LDY
Y←M
This instruction loads the contents of M in Y.
A0 2
3-80
3A 2
3886 Group User’s Manual
A9 2
2
1
A5 3
2
3C 4
3
2
A6 3
2
2
A4 3
2
B5 4
2
B6 4
B4 4
2
2 AE 4
AC 4
41 6
6C 5
3 B9 5
BE 5
3
3 BC 5
3
3
3 B2 4
2
02 7
2
2 51 6
2
22 5
A1 6
2 B1 6
3
3
3886 Group User’s Manual
2
2
3-81
APPENDIX
APPENDIX
3.7 Machine instructions
3.7 Machine instructions
Addressing mode
Addressing mode
Symbol
Function
Details
IMP
OP n
LSR
7
0→
0
→C
Multiplies Accumulator with the memory specified by the Zero Page X address mode and
stores the high-order byte of the result on the
Stack and the low-order byte in A.
NOP
PC ← PC + 1
This instruction adds one to the PC but does EA 2
no otheroperation.
ORA
(Note 1)
When T = 0
A←AVM
When T = 0, this instruction transfers the contents of A and M to the ALU which performs a
bit-wise “OR”, and stores the result in A.
When T = 1, this instruction transfers the contents of M(X) and the M to the ALU which
performs a bit-wise OR, and stores the result
in M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
PHP
PLA
PLP
ROL
S←S–1
1
# OP n
46 5
BIT, ZP
# OP n
2
#
ZP, X
ZP, Y
OP n
# OP n
56 6
2
ABS
ABS, X
ABS, Y
# OP n
# OP n
# OP n
4E 6
3 5E 7
3
IND
# OP n
Processor status register
ZP, IND
# OP n
IND, X
# OP n
IND, Y
# OP n
# OP n
62 15 2
1
09 2
2
05 3
2
15 4
2
0D 4
3 1D 5
3 19 5
3
01 6
2 11 6
REL
2
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
0
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
1
M(S) ← PS
S←S–1
This instruction pushes the contents of PS to
the memory location designated by S and decrements the contents of S by one.
08 3
1
S←S+1
A ← M(S)
This instruction increments S by one and
stores the contents of the memory designated
by S in A.
68 4
1
S←S+1
PS ← M(S)
This instruction increments S by one and
stores the contents of the memory location
designated by S in PS.
28 4
1
7
←
This instruction shifts either A or M one bit left
through C. C is stored in bit 0 and bit 7 is
stored in C.
2A 2
1
26 5
2
36 6
2
2E 6
3 3E 7
3
N
•
•
•
•
•
Z
C
This instruction shifts either A or M one bit
right through C. C is stored in bit 7 and bit 0 is
stored in C.
6A 2
1
66 5
2
76 6
2
6E 6
3 7E 7
3
N
•
•
•
•
•
Z
C
82 8
2
•
•
•
•
•
•
•
•
0
←C ←
RRF
7
→
3-82
# OP n
ZP
48 3
7
C→
RTS
BIT, A
This instruction pushes the contents of A to
the memory location designated by S, and
decrements the contents of S by one.
ROR
RTI
# OP n
4A 2
M(S) • A ← A ✽ M(zz + X)
S←S–1
PHA
# OP n
A
This instruction shifts either A or M one bit to
the right such that bit 7 of the result always is
set to 0, and the bit 0 is stored in C.
MUL
When T = 1
M(X) ← M(X) V M
IMM
0
→
0
→
This instruction rotates 4 bits of the M content
to the right.
S←S+1
PS ← M(S)
S←S+1
PCL ← M(S)
S←S+1
PCH ← M(S)
This instruction increments S by one, and
stores the contents of the memory location
designated by S in PS. S is again incremented
by one and stores the contents of the memory
location designated by S in PC L. S is again
incremented by one and stores the contents of
memory location designated by S in PCH.
S←S+1
PCL ← M(S)
S←S+1
PCH ← M(S)
(PC) ← (PC) + 1
This instruction increments S by one and
stores the contents of the memory location
designated by S in PCL. S is again
incremented by one and the contents of the
memory location is stored in PC H . PC is
incremented by 1.
(Value saved in stack)
(Value saved in stack)
40 6
1
60 6
1
•
3886 Group User’s Manual
3886 Group User’s Manual
•
•
•
•
•
•
•
3-83
APPENDIX
APPENDIX
3.7 Machine instructions
3.7 Machine instructions
Addressing mode
Addressing mode
Symbol
Function
Details
IMP
OP n
SBC
(Note 1)
(Note 5)
When T = 0 _
A←A–M–C
When T = 1
_
M(X) ← M(X) – M – C
IMM
# OP n
When T = 0, this instruction subtracts the
value of M and the complement of C from A,
and stores the results in A and C.
When T = 1, the instruction subtracts the contents of M and the complement of C from the
contents of M(X), and stores the results in
M(X) and C.
A remain unchanged, but status flag are
changed.
M(X) represents the contents of memory
where is indicated by X.
E9 2
A
# OP n
BIT, A
# OP n
ZP
# OP n
2
E5 3
BIT, ZP
# OP n
#
2
ZP, X
ZP, Y
OP n
# OP n
F5 4
2
ABS
ABS, X
ABS, Y
IND
# OP n
# OP n
# OP n
# OP n
ED 4
3 FD 5
3 F9 5
3
Processor status register
ZP, IND
# OP n
IND, X
IND, Y
REL
# OP n
# OP n
# OP n
E1 6
2 F1 6
2
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
N
V
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
SEB
Ai or Mi ← 1
This instruction sets the designated bit i of A
or M.
SEC
C←1
This instruction sets C.
38 2
1
•
•
•
•
•
•
•
1
SED
D←1
This instruction set D.
F8 2
1
•
•
•
•
1
•
•
•
SEI
I←1
This instruction set I.
78 2
1
•
•
•
•
•
1
•
•
SET
T←1
This instruction set T.
32 2
1
•
•
1
•
•
•
•
•
STA
M←A
This instruction stores the contents of A in M.
The contents of A does not change.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
STP
This instruction resets the oscillation control F/
F and the oscillation stops. Reset or interrupt
input is needed to wake up from this mode.
0B
+
20i
2
1
0F
+
20i
85 4
42 2
2
M←X
This instruction stores the contents of X in M.
The contents of X does not change.
86 4
2
STY
M←Y
This instruction stores the contents of Y in M.
The contents of Y does not change.
84 4
2
TAX
X←A
This instruction stores the contents of A in X. AA 2
The contents of A does not change.
TAY
Y←A
This instruction stores the contents of A in Y.
The contents of A does not change.
TST
M = 0?
This instruction tests whether the contents of
M are “0” or not and modifies the N and Z.
TSX
X←S
This instruction transfers the contents of S in BA 2
X.
TXA
A←X
This instruction stores the contents of X in A.
TXS
S←X
TYA
A←Y
Notes 1
2
3
4
5
3-84
:
:
:
:
:
2
95 5
8D 5
2
3 9D 6
3 99 6
3
81 7
2 91 7
1
STX
WIT
5
2 8E 5
3
•
•
•
•
•
•
•
•
8C 5
3
•
•
•
•
•
•
•
•
1
N
•
•
•
•
•
Z
•
1
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
1
N
•
•
•
•
•
Z
•
8A 2
1
N
•
•
•
•
•
Z
•
This instruction stores the contents of X in S.
9A 2
1
•
•
•
•
•
•
•
•
This instruction stores the contents of Y in A.
98 2
1
N
•
•
•
•
•
Z
•
The WIT instruction stops the internal clock
but not the oscillation of the oscillation circuit
is not stopped.
CPU starts its function after the Timer X over
flows (comes to the terminal count). All registers or internal memory contents except Timer
X will not change during this mode. (Of course
needs VDD).
C2 2
1
•
•
•
•
•
•
•
•
A8 2
64 3
96 5
2
94 5
2
2
The number of cycles “n” is increased by 3 when T is 1.
The number of cycles “n” is increased by 2 when T is 1.
The number of cycles “n” is increased by 1 when T is 1.
The number of cycles “n” is increased by 2 when branching has occurred.
N, V, and Z flags are invalid in decimal operation mode.
3886 Group User’s Manual
3886 Group User’s Manual
3-85
APPENDIX
3.7 Machine instructions
Symbol
Contents
Symbol
IMP
IMM
A
BIT, A
BIT, A, R
ZP
BIT, ZP
BIT, ZP, R
ZP, X
ZP, Y
ABS
ABS, X
ABS, Y
IND
Implied addressing mode
Immediate addressing mode
Accumulator or Accumulator addressing mode
Accumulator bit addressing mode
Accumulator bit relative addressing mode
Zero page addressing mode
Zero page bit addressing mode
Zero page bit relative addressing mode
Zero page X addressing mode
Zero page Y addressing mode
Absolute addressing mode
Absolute X addressing mode
Absolute Y addressing mode
Indirect absolute addressing mode
ZP, IND
Zero page indirect absolute addressing mode
IND, X
IND, Y
REL
SP
C
Z
I
D
B
T
V
N
Indirect X addressing mode
Indirect Y addressing mode
Relative addressing mode
Special page addressing mode
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
X-modified arithmetic mode flag
Overflow flag
Negative flag
+
–
✽
/
V
V
–
V
–
←
X
Y
S
PC
PS
PCH
PCL
ADH
ADL
FF
nn
zz
M
M(X)
M(S)
M(ADH, ADL)
M(00, ADL)
Ai
Mi
OP
n
#
3-86
3886 Group User’s Manual
Contents
Addition
Subtraction
Multiplication
Division
Logical OR
Logical AND
Logical exclusive OR
Negation
Shows direction of data flow
Index register X
Index register Y
Stack pointer
Program counter
Processor status register
8 high-order bits of program counter
8 low-order bits of program counter
8 high-order bits of address
8 low-order bits of address
FF in Hexadecimal notation
Immediate value
Zero page address
Memory specified by address designation of any addressing mode
Memory of address indicated by contents of index
register X
Memory of address indicated by contents of stack
pointer
Contents of memory at address indicated by ADH and
ADL, in ADH is 8 high-order bits and ADL is 8 low-order bits.
Contents of address indicated by zero page ADL
Bit i (i = 0 to 7) of accumulator
Bit i (i = 0 to 7) of memory
Opcode
Number of cycles
Number of bytes
APPENDIX
3.8 List of instruction code
3.8 List of instruction code
D7 – D4
D3 – D0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Hexadecimal
notation
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ORA
ABS
ASL
ABS
SEB
0, ZP
0000
0
BRK
BBS
ORA
JSR
IND, X ZP, IND 0, A
—
ORA
ZP
ASL
ZP
BBS
0, ZP
PHP
ORA
IMM
ASL
A
SEB
0, A
—
0001
1
BPL
ORA
IND, Y
CLT
BBC
0, A
—
ORA
ZP, X
ASL
ZP, X
BBC
0, ZP
CLC
ORA
ABS, Y
DEC
A
CLB
0, A
—
0010
2
JSR
ABS
AND
IND, X
JSR
SP
BBS
1, A
BIT
ZP
AND
ZP
ROL
ZP
BBS
1, ZP
PLP
AND
IMM
ROL
A
SEB
1, A
BIT
ABS
0011
3
BMI
AND
IND, Y
SET
BBC
1, A
—
AND
ZP, X
ROL
ZP, X
BBC
1, ZP
SEC
AND
ABS, Y
INC
A
CLB
1, A
ROL
CLB
LDM
AND
ZP ABS, X ABS, X 1, ZP
0100
4
RTI
EOR
IND, X
STP
BBS
2, A
COM
ZP
EOR
ZP
LSR
ZP
BBS
2, ZP
PHA
EOR
IMM
LSR
A
SEB
2, A
JMP
ABS
0101
5
BVC
EOR
IND, Y
—
BBC
2, A
—
EOR
ZP, X
LSR
ZP, X
BBC
2, ZP
CLI
EOR
ABS, Y
—
CLB
2, A
—
0110
6
RTS
MUL
ADC
IND, X ZP, X
BBS
3, A
TST
ZP
ADC
ZP
ROR
ZP
BBS
3, ZP
PLA
ADC
IMM
ROR
A
SEB
3, A
JMP
IND
0111
7
BVS
ADC
IND, Y
—
BBC
3, A
—
ADC
ZP, X
ROR
ZP, X
BBC
3, ZP
SEI
ADC
ABS, Y
—
CLB
3, A
—
1000
8
BRA
STA
IND, X
RRF
ZP
BBS
4, A
STY
ZP
STA
ZP
STX
ZP
BBS
4, ZP
DEY
—
TXA
SEB
4, A
STY
ABS
STA
ABS
STX
ABS
SEB
4, ZP
1001
9
BCC
STA
IND, Y
—
BBC
4, A
STY
ZP, X
STA
ZP, X
STX
ZP, Y
BBC
4, ZP
TYA
STA
ABS, Y
TXS
CLB
4, A
—
STA
ABS, X
—
CLB
4, ZP
1010
A
LDY
IMM
LDA
IND, X
LDX
IMM
BBS
5, A
LDY
ZP
LDA
ZP
LDX
ZP
BBS
5, ZP
TAY
LDA
IMM
TAX
SEB
5, A
LDY
ABS
LDA
ABS
LDX
ABS
SEB
5, ZP
1011
B
BCS
JMP
BBC
LDA
IND, Y ZP, IND 5, A
LDY
ZP, X
LDA
ZP, X
LDX
ZP, Y
BBC
5, ZP
CLV
LDA
ABS, Y
TSX
CLB
5, A
1100
C
CPY
IMM
CMP
IND, X
WIT
BBS
6, A
CPY
ZP
CMP
ZP
DEC
ZP
BBS
6, ZP
INY
CMP
IMM
DEX
SEB
6, A
CPY
ABS
1101
D
BNE
CMP
IND, Y
—
BBC
6, A
—
CMP
ZP, X
DEC
ZP, X
BBC
6, ZP
CLD
CMP
ABS, Y
—
CLB
6, A
—
1110
E
CPX
IMM
DIV
SBC
IND, X ZP, X
BBS
7, A
CPX
ZP
SBC
ZP
INC
ZP
BBS
7, ZP
INX
SBC
IMM
NOP
SEB
7, A
CPX
ABS
1111
F
BEQ
SBC
IND, Y
BBC
7, A
—
SBC
ZP, X
INC
ZP, X
BBC
7, ZP
SED
SBC
ABS, Y
—
CLB
7, A
—
—
ASL
CLB
ORA
ABS, X ABS, X 0, ZP
AND
ABS
EOR
ABS
ROL
ABS
LSR
ABS
SEB
1, ZP
SEB
2, ZP
LSR
CLB
EOR
ABS, X ABS, X 2, ZP
ADC
ABS
ROR
ABS
SEB
3, ZP
ROR
CLB
ADC
ABS, X ABS, X 3, ZP
LDX
CLB
LDY
LDA
ABS, X ABS, X ABS, Y 5, ZP
CMP
ABS
DEC
ABS
SEB
6, ZP
DEC
CLB
CMP
ABS, X ABS, X 6, ZP
SBC
ABS
INC
ABS
SEB
7, ZP
INC
CLB
SBC
ABS, X ABS, X 7, ZP
: 3-byte instruction
: 2-byte instruction
: 1-byte instruction
3886 Group User’s Manual
3-87
APPENDIX
3.9 SFR memory map
3.9 SFR memory map
000016
Port P0 (P0)
002016
Prescaler 12 (PRE12)
000116
Port P0 direction register (P0D)
002116
Timer 1 (T1)
000216
Port P1 (P1)
002216
Timer 2 (T2)
000316
Port P1 direction register (P1D)
002316
Timer XY mode register (TM)
000416
Port P2 (P2)
002416
Prescaler X (PREX)
000516
Port P2 direction register (P2D)
002516
Timer X (TX)
000616
Port P3 (P3)
002616
Prescaler Y (PREY)
000716
Port P3 direction register (P3D)
002716
Timer Y (TY)
000816
Port P4 (P4)
002816
Data bas buffer register 0 (DBB0)
000916
Port P4 direction register (P4D)
002916
Data bas buffer status register 0 (DBBSTS0)
000A16
Port P5 (P5)
002A16
Data bas buffer control register (DBBCON)
000B16
Port P5 direction register (P5D)
002B16
Data bas buffer register 1 (DBB1)
000C16
Port P6 (P6)
002C16
Data bas buffer status register 1 (DBBSTS1)
000D16
Port P6 direction register (P6D)
002D16
Comparator data register (CMPD)
000E16
Port P7 (P7)
002E16
Port control register 1 (PCTL1)
000F16
Port P7 direction register (P7D)
002F16
Port control register 2 (PCTL2)
001016
Port P8 (P8)/Port P4 input register (P4I)
003016
PWM0H register (PWM0H)
001116
Port P8 direction register (P8D)/Port P7 input register (P7I)
003116
PWM0L register (PWM0L)
001216
I2C data shift register (S0)
003216
PWM1H register (PWM1H)
001316
I2C address register (S0D)
003316
PWM1L register (PWM1L)
001416
I2C status register (S1)
003416
AD/DA control register (ADCON)
001516
I2 C
control register (S1D)
003516
A-D conversion register 1 (AD1)
001616
I2 C
clock control register (S2)
003616
D-A1 conversion register (DA1)
001716
I2C start/stop condition control register (S2D)
003716
D-A2 conversion register (DA2)
001816
Transmit/Receive buffer register (TB/RB)
003816
A-D conversion register 2 (AD2)
001916
Serial I/O1 status register (SIO1STS)
003916
Interrupt source selection register (INTSEL)
001A16
Serial I/O1 control register (SIO1CON)
003A16
Interrupt edge selection register (INTEDGE)
001B16
UART control register (UARTCON)
003B16
CPU mode register (CPUM)
001C16
Baud rate generator (BRG)
003C16
Interrupt request register 1 (IREQ1)
001D16
Serial I/O2 control register (SIO2CON)
003D16
Interrupt request register 2 (IREQ2)
001E16
Watchdog timer control register (WDTCON)
003E16
Interrupt control register 1 (ICON1)
001F16
Serial I/O2 register (SIO2)
003F16
Interrupt control register 2 (ICON2)
0FFE16
Flash memory control register (FCON)
(Note)
0FFF16
Flash command register (FCMD)
(Note)
Note: Flash memory version only
3-88
3886 Group User’s Manual
APPENDIX
3.10 Pin configurations
61
40
62
39
38
37
63
64
P16/AD14
P17/AD15
P20/DB0
P21/DB1
P22/DB2
P23/DB3
P24/DB4
P25/DB5
P26/DB6
P27/DB7
VSS
XOUT
XIN
P40/XCOUT
P41/XCIN
RESET
VPP
CNVSS
P42/INT0/OBF00
P43/INT1/OBF01
P44/RXD
36
65
66
35
34
67
68
69
70
71
72
73
74
75
76
77
78
79
80
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
17
18
14
15
16
11
12
13
7
8
9
10
6
4
5
P60/AN0
P77/SCL
P76/SDA
P75/INT41
P74/INT31
P73/SRDY2/INT21
P72/SCLK2
P71/SOUT2
P70/SIN2
P57/DA2/PWM11
P56/DA1/PWM01
P55/CNTR1
P54/CNTR0
P53/INT40/W
P52/INT30/R
P51/INT20/S0
P50/A0
P47/SRDY1/S1
P46/SCLK1/OBF10
P45/TXD
2
3
M38867M8A-XXXHP
M38867E8AHP
1
P31/PWM10
P30/PWM00
P87/DQ7
P86/DQ6
P85/DQ5
P84/DQ4
P83/DQ3
P82/DQ2
P81/DQ1
P80/DQ0
VCC
VREF
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
50
49
48
47
46
45
44
43
42
41
60
59
58
57
56
55
54
53
52
51
PIN CONFIGURATION (TOP VIEW)
P32/ONW
P33/RESETOUT
P34/φ
P35/SYNC
P36/WR
P37/RD
P00/P3REF/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/AD8
P11/AD9
P12/AD10
P13/AD11
P14/AD12
P15/AD13
3.10 Pin configurations
: PROM version
Note: The pin number and the position of
the function pin may change by the
kind of package.
Package type : 80P6Q-A
Fig. 3.10.1 M38867M8A-XXXHP, M38867E8AHP pin configuration
41
44
43
42
47
46
45
49
48
52
51
50
40
39
38
37
36
35
M38867E8AFS
65
66
67
68
73
74
75
20
21
18
19
17
14
15
16
11
12
13
27
26
25
P62/AN2
P61/AN1
P60/AN0
P77/SCL
P76/SDA
P75/INT41
P74/INT31
P73/SRDY2/INT21
P72/SCLK2
P71/SOUT2
P70/SIN2
P57/DA2/PWM11
P56/DA1/PWM01
P55/CNTR1
P54/CNTR0
P53/INT40/W
P52/INT30/R
P51/INT20/S0
P50/A0
P47/SRDY1/S1
P46/SCLK1/OBF10
P45/TXD
P44/RXD
P43/INT1/OBF01
8
9
10
76
77
78
79
80
34
33
32
31
30
29
28
Package type : 80D0
P20/DB0
P21/DB1
P22/DB2
P23/DB3
P24/DB4
P25/DB5
P26/DB6
P27/DB7
VSS
XOUT
XIN
P40/XCOUT
P41/XCIN
RESET
VPP
CNVSS
P42/INT0/OBF00
22
23
24
69
70
71
72
1
2
3
4
5
6
7
P87/DQ7
P86/DQ6
P85/DQ5
P84/DQ4
P83/DQ3
P82/DQ2
P81/DQ1
P80/DQ0
VCC
VREF
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
55
54
53
64
63
62
61
60
59
58
57
56
P30/PWM00
P31/PWM10
P32/ONW
P33/RESETOUT
P34/φ
P35/SYNC
P36/WR
P37/RD
P00/P3REF/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/AD8
P11/AD9
P12/AD10
P13/AD11
P14/AD12
P15/AD13
P16/AD14
P17/AD15
PIN CONFIGURATION (TOP VIEW)
: PROM version
Note: The pin number and the position of
the function pin may change by the
kind of package.
Fig. 3.10.2 M38867E8AFS pin configuration
3886 Group User’s Manual
3-89
APPENDIX
3.10 Pin configurations
41
44
43
42
46
45
50
49
48
47
40
39
38
37
36
35
34
33
61
Package type : 80P6S-A/80P6Q-A
: Flash memory version
Note: The pin number and the position of the
function pin may change by the kind of
package.
Fig. 3.10.3 M38869MFA-XXXGP/HP, M38869FFAGP/HP pin configuration
3-90
3886 Group User’s Manual
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
VSS
XOUT
XIN
P40/XCOUT
P41/XCIN
RESET
CNVSS
VPP
P42/INT0/OBF00
P43/INT1/OBF01
P44/RXD
20
19
17
18
16
15
14
13
12
11
9
10
7
8
6
3
32
31
30
29
28
27
26
25
24
23
22
21
P60/AN0
P77/SCL
P76/SDA
P75/INT41
P74/INT31
P73/SRDY2/INT21
P72/SCLK2
P71/SOUT2
P70/SIN2
P57/DA2/PWM11
P56/DA1/PWM01
P55/CNTR1
P54/CNTR0
P53/INT40/W
P52/INT30/R
P51/INT20/S0
P50/A0
P47/SRDY1/S1
P46/SCLK1/OBF10
P45/TXD
4
5
M38869MFA-XXXGP/HP
M38869FFAGP/HP
2
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1
P31/PWM10
P30/PWM00
P87/DQ7
P86/DQ6
P85/DQ5
P84/DQ4
P83/DQ3
P82/DQ2
P81/DQ1
P80/DQ0
VCC
VREF
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
57
56
55
54
53
52
51
60
59
58
P32
P33
P34
P35
P36
P37
P00/P3REF
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
PIN CONFIGURATION (TOP VIEW)
MITSUBISHI SEMICONDUCTORS
USER’S MANUAL
3886 Group
Sep. Second Edition 2000
Editioned by
Committee of editing of Mitsubishi Semiconductor USER’S MANUAL
Published by
Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission
of Mitsubishi Electric Corporation.
©2000 MITSUBISHI ELECTRIC CORPORATION
User’s Manual
3886 Group
© 2000 MITSUBISHI ELECTRIC CORPORATION.
New publication, effective Sep. 2000.
Specifications subject to change without notice.