CYPRESS CY9C6264

PRELIMINARY
CY9C6264
8K x 8 Magnetic Nonvolatile CMOS RAM
Features
• 100% form, fit, function compatible with 8K × 8
micropower SRAM CY6264
— Fast Read and Write access: 70 ns
— Voltage range: 4.5V–5.5V operation
— Low active power: 330 mW (max.)
— Low standby power, CMOS: 495 µW (max.)
— Easy memory expansion with CE and OE features
— TTL-compatible inputs and outputs
— Automatic power-down when deselected
• Replaces 8K × 8 Battery Backed (BB) SRAM, SRAM,
EEPROM, FeRAM, or Flash memory
• Data is automatically Write protected during power loss
• Write cycle endurance: >1015 cycles
• Data Retention: >10 Years
• Shielded from external magnetic fields
• Extra 64-bytes for device identification and tracking
• Temperature ranges
— Commercial: 0°C to 70°C
• JEDEC STD 28-pin DIP (600-mil), 28-pin (300-mil) SOIC
and 28-pin TSOP-1 packages. Also available in 450-mil
wide (300-mil body width) 28-pin narrow SOIC.
Functional Description
The CY9C6264 is a high-performance CMOS nonvolatile
RAM employing an advanced magnetic RAM (MRAM)
process. An MRAM is nonvolatile memory that operates as a
fast read and write RAM. It provides data retention for more
than ten years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM, EEPROM, Flash and FeRAM. Its fast
writes and high write cycle endurance makes it superior to
other types of nonvolatile memory.
The CY9C6264 operates very similarly to SRAM devices.
Memory read and write cycles require equal times. The MRAM
memory is nonvolatile due to its unique magnetic process.
Unlike BBSRAM, the CY9C6264 is truly a monolithic nonvolatile memory. It provides the same functional benefits of a fast
write without the serious disadvantages associated with
modules and batteries or hybrid memory solutions.
These capabilities make the CY9C6264 ideal for nonvolatile
memory applications requiring frequent or rapid writes in a
byte wide environment.
The CY9C6264 is offered in both commercial and industrial
temperature ranges.
— Industrial: –40°C to +85°C
Logic Block Diagram
Pin Configurations
SOIC/DIP
Top View
I/O0
INPUTBUFFER
CE 2
CE 1
WE
Silicon Sig.
512 × 128
ARRAY
SENSE AMPS
I/O1
ROW DECODER
A9
A8
A7
A6
A5
A4
A3
A2
A1
NC
A4
A5
A6
A7
A8
A9
A10
A11
A12
I/O0
I/O1
I/O2
GND
I/O2
I/O4
DOWN &
WRITE
PROTECT
I/O6
I/O7
A 12
A 11
A10
A0
OE
POWER
Cypress Semiconductor Corporation
Document #: 38-15003 Rev. *D
•
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
CE 2
A3
A2
A1
OE
A0
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
I/O3
I/O5
COLUMN
DECODER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
3901 North First Street
OE
A1
A2
A3
CE2
WE
VCC
NC
A4
A5
A6
A7
A8
A9
•
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
TSOP I
Top View
(not to scale)
20
19
18
17
16
15
14
13
12
11
10
9
8
A0
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A12
A11
A10
San Jose, CA 95134
•
408-943-2600
Revised January 25, 2005
PRELIMINARY
Overview
The CY9C6264 is a byte-wide MRAM memory. The memory
array is logically organized as 8,192 × 8 and is accessed using
an industry standard parallel asynchronous SRAM-like
interface. The CY9C6264 is inherently nonvolatile and offers
write protect during sudden power loss. Functional operation
of the MRAM is otherwise similar to SRAM-type devices.
Memory Architecture
Users access 8,192 memory locations each with eight data
bits through a parallel interface. Internally, the memory array
is organized into 8 blocks of 128 rows x 64 columns each.
The access and cycle time are the same for Read and Write
memory operations. Unlike an EEPROM or Flash, it is not
necessary to poll the device for a ready condition since writes
occur at bus speed.
Memory Operation
The CY9C6264 is designed to operate in a manner similar to
other bytewide memory products. For users familiar with
BBSRAM, the MRAM performance is superior. For users
familiar with EEPROM, Flash, and FeRAM, the obvious differences result from higher write performance of MRAM
technology and much higher write endurance.
All memory array bits are set to logic “1” at the time of
shipment.
Read Operation
CY9C6264
Write Inhibit and Data Retention Mode
This feature protects against the inadvertent Write. The
CY9C6264 provides full functional capability for VCC greater
than 4.5V and Write-protects the device below 4.0V. Data is
maintained in the absence of VCC. During the power-up,
normal operation can resume 20 µs after VPFD is reached.
Refer to page 8 for details.
Sudden Power Loss—“Brown out”
The nonvolatile RAM constantly monitors VCC. Should the
supply voltage decay below the operating range, the
CY9C6264 automatically write-protects itself, all inputs
become “don’t care,” and all outputs become high impedance.
Refer to page 8 for details.
Silicon Signature/Device ID
An extra 64 bytes of MRAM are available to the user for Device
ID. By raising A7 to VCC + 2.0V and by using address locations
00 (Hex) to 3F (Hex) on address pins A6, A5, A4, A12, A11, and
A10 (MSB to LSB) respectively, the additional bytes may be
accessed in the same manner as the regular memory array
with 140ns read access time and 140ns write cycle time.
Writing the extra bytes of MRAM requires a longer address
setup to write start of 70 ns vs. the normal operating specification of 0ns. Dropping A7 from input high (VCC + 2.0V) to <
VCC + 0.5V max. returns the device to normal operation after
140-ns delay.
Address (MSB to LSB)
A6 A5 A4 A12 A11 A10
Description
ID
00h
Manufacturer ID
34h
A read cycle begins whenever WE (Write Enable) is inactive
(HIGH) and CE1 (Chip Enable) and OE (Output Enable) are
active LOW while CE2 is active HIGH. The unique address
specified by the 13 address inputs (A0–A12) defines which of
the 8,192 bytes of data is to be accessed. Valid data will be
available at the eight output pins within tAA (access time) after
the last address input is stable, providing that CE1 or CE2 and
OE access times are also satisfied. If CE1 or CE2 and OE
access times are not satisfied, the data access must be
measured from the later-occurring signal (CE1, CE2 or OE)
and the limiting parameter is either tACE1 for CE1, tACE2 for
CE2, or tDOE for the OE rather than address access.
All User Space bits are set to logic “1” at the time of shipment.
Write Cycle
Applications
The CY9C6264 initiates a Write cycle whenever the WE and
CE1 signals are active (LOW) or WE is LOW and CE2 is HIGH,
after address inputs are stable. The later occurring falling edge
of CE1 (rising in case of CE2) or WE will determine the start of
the Write cycle. The Write cycle is terminated by the earlier
rising edge of CE1 (falling edge in case of CE2) or WE. All
address inputs must be kept valid throughout the Write cycle.
The OE control signal should be kept inactive (HIGH) during
Write cycles to avoid bus contention. However, if the output
drivers are enabled (CE1 or CE2 and OE active), WE will
disable the outputs in tHZWE from the WE falling edge.
Battery-backed SRAM (BBSRAM) Replacement
Unlike other nonvolatile memory technologies, there is no
Write delay with MRAM. The entire memory operation occurs
in a single bus cycle. Therefore, any operation including Read
or Write can occur immediately following a Write. Data Polling,
a technique used with EEPROMs to determine if the Write is
complete, is unnecessary. Page Write, a technique used to
enhance EEPROM Write performance, is also unnecessary
because of inherently fast Write cycle time for MRAM. The
total write time for the entire array is 0.575 ms.
Document#: 38-15003 Rev. *D
01h
Device ID
41h
02h–3Fh
User Space
62 bytes
Magnetic Shielding
CY9C6264 is protected from external magnetic fields through
the application of a “magnetic shield” that covers the entire
memory array.
CY9C6264 is designed to replace (plug and play) existing
BBSRAM while eliminating the need for battery and VCC
monitor IC, reducing cost and board space and improving
system reliability.
The cost associated with multiple components, assemblies,
and manufacturing overhead associated with battery-backed
SRAM is eliminated by using monolithic MRAM. CY9C6264
eliminates multiple assemblies, connectors, modules, field
maintenance, and environmental issues common with BB
SRAM. MRAM is a true nonvolatile RAM with high performance, high endurance, and data retention.
Battery-backed SRAMs are forced to monitor VCC in order to
switch to the backup battery. Users that are modifying existing
designs to use MRAM in place of BBSRAM, can eliminate the
VCC controller IC along with the battery. MRAM performs this
function on-chip.
Page 2 of 12
PRELIMINARY
Cost
The cost of both the component and manufacturing overhead
of battery-backed SRAM is high. In addition, there is a built-in
rework step required for battery attachment in case of surface
mount assembly. This can be eliminated with MRAM. In the
case of DIP battery-backed modules, the assembly
techniques are constrained to through-hole assembly and
board wash using no water.
System Reliability
Battery-backed SRAM is inherently vulnerable to shock and
vibration. In addition, a negative voltage on any pin of a
battery-backed SRAM, even a momentary undershoot, can
cause data loss. The negative voltage causes current to be
drawn directly from the battery, weakens the battery, and
reduces its capacity over time. In general, there is no way to
monitor the lost battery capacity. MRAM guarantees reliable
operation across the voltage range with inherent nonvolatility.
Space
Battery-backed SRAM in DIP modules takes up board space
height and dictates through-hole assembly. MRAM is offered
in surface mount as well as DIP packages.
Field Maintenance
Batteries must eventually be replaced, which creates an
inherent maintenance problem. Despite projections of long
life, it is difficult to know how long a battery will last, considering
all the factors that degrade them.
Environmental
Lithium batteries are a potential disposal burden and are
considered a fire hazard. MRAM eliminates all such issues
through a truly monolithic nonvolatile solution.
Users replacing battery-backed SRAMs with an integrated
Real-time Clock (RTC) in the same package may need to
Document#: 38-15003 Rev. *D
CY9C6264
move the RTC function to a different location within the
system.
EEPROM Replacement
CY9C6264 can also replace EEPROM in current applications.
CY9C6264 is pinout- and functionally-compatible to byte-wide
EEPROM, but it does not need data-bar polling, page Write,
and hardware Write protect due to its fast Write and
inadvertent Write-protect features.
Users replacing EEPROMs with MRAM can eliminate the
page mode operation and simplify to standard asynchronous
write. Additionally, data-bar polling can be eliminated, since
every byte Write is completed within same cycle. All Writes are
completed within 70 ns.
FeRAM Replacement
FeRAM requires addresses to be latched on falling edge of
CE, which adds to system overhead in managing the CE and
latching function. MRAM eliminates this overhead by offering
a simple asynchronous SRAM interface.
Users replacing FeRAM can simplify their address decoding
since you do not need to drive CE active and then inactive for
each address. This overhead is eliminated when using MRAM.
Secondly, MRAM Read is nondestructive and no precharge
cycle is required like the one used with FeRAM. This has no
apparent impact to the design, but the Read cycle time can
now see immediate improvement equal to the precharge time.
Boot Up PROM (EPROM, PROM) Function Replacement
The CY9C6264 can be accessed like an EPROM or PROM.
When CE1 and OE are LOW and CE2 and WE are HIGH, the
data stored at the memory location determined by the address
pins is asserted on the outputs. MRAM may be used to accomplish system boot up function using this condition.
Page 3 of 12
PRELIMINARY
Maximum Ratings
CY9C6264
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................... –40°C to +85°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ........................................... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State[1] ....................................–0.5V to VCC + 0.5V
[1]
DC Input Voltage .................................–0.5V to VCC + 0.5V
except in case of super voltage pin (A7) while accessing 16
device ID and silicon signature bytes. ... −0.5V to VCC + 2.5V
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Maximum Exposure to Magnetic Field
@ Device Package[2, 3] ............................................ < 20 Oe
Operating Range
Range
Ambient Temperature
VCC
0°C to +70°C
5V ± 10%
–40°C to +85°C
5V ± 10%
Commercial
Industrial
Electrical Characteristics Over the Operating Range
CY9C62256-70
Parameter
Description
Test Conditions
Typ.[5]
Min.
Max.
Unit
VOH
Output HIGH Voltage
VCC = Min., IOH = −1.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 2.1 mA
0.4
V
VIH
Input HIGH Voltage
2.2
VCC + 0.5V
V
VIL
Input LOW Voltage
−0.5[1]
0.8
V
IIX[4]
Input Leakage Current
GND < VI < VCC
−0.5
+0.5
µA
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
−0.5
+0.5
µA
2.4
V
ICC
VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC
60
mA
ISB1
Automatic CE Power-down
Current— TTL Inputs
Max. VCC, CE1 > VIH or CE2 < VIL
VIN > VIH or VIN < VIL, f = fMAX
500
µA
ISB2
Automatic CE Power-down
Current— CMOS Inputs
Max. VCC,
CE1 > VCC − 0.3V or CE2 < 0.3V
VIN > VCC − 0.3V or VIN < 0.3V, f = 0
90
µA
Capacitance[6]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Unit
6
pF
8
pF
AC Test Loads and Waveforms
R1 1800 Ω
5V
OUTPUT
R1 1800 Ω
5V
ALL INPUT PULSES
OUTPUT
R2
990Ω
100 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
OUTPUT
(a)
3.0V
R2
990Ω
5 pF
INCLUDING
JIG AND
SCOPE
GND
10%
< 5 ns
90%
90%
10%
< 5 ns
(b)
THEVENIN EQUIVALENT
639Ω
1.77V
Notes:
1. VIL(min) = –2.0V for pulse duration of 20 ns.
2. Magnetic field exposure is highly dependent on the distance from the magnetic field source. The magnetic field falls of as 1/R squared, where R is the distance
from the magnetic source.
3. Exposure beyond this level may cause loss of data.
4. IIX during access to 16 device ID and silicon signature bytes w/ super voltage pin at VCC + 2.0V will be 100 µA max., VIL (min.) = –2.0V for pulse duration of less
than 20 ns.
5. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions
(TA = 25°C, VCC). Parameters are guaranteed by design and characterization and not 100% tested.
6. Tested initially and after any design or process changes that may affect these parameters.
Document#: 38-15003 Rev. *D
Page 4 of 12
PRELIMINARY
CY9C6264
Switching Characteristics Over the Operating Range[7]
CY9C6264-70
Parameter
Description
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
70
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE1
CE1 LOW to Data Valid
70
ns
tACE2
CE2 HIGH to Data Valid
70
ns
tDOE
OE LOW to Data Valid
35
ns
25
ns
[8]
ns
70
5
ns
ns
tLZOE
OE LOW to Low-Z
tHZOE
OE HIGH to High-Z[8, 9]
5
ns
tLZCE1
CE1 LOW to Low-Z[8]
5
ns
tLZCE2
CE2 HIGH to Low-Z[8]
5
ns
tHZCE
CE1 HIGH to High-Z[8, 9]
CE2 LOW to High-Z[8, 9]
tPU
CE1 LOW to Power-up
CE2 HIGH to Power-up
tPD
CE1 HIGH to Power-down
CE2 LOW to Power-down
25
0
ns
ns
70
ns
Write Cycle[10, 11]
tWC
Write Cycle Time
70
ns
tSCE1
CE1 LOW to Write End
60
ns
tSCE2
CE2 HIGH to Write End
60
ns
tAW
Address Set-up to Write End
60
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-up to Write Start
0
ns
tPWE
WE Pulse Width
50
ns
tSD
Data Set-up to Write End
30
ns
tHD
Data Hold from Write End
0
ns
tHZWE
WE LOW to High-Z[8, 9]
tLZWE
WE HIGH to
Low-Z[8]
25
5
ns
ns
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100-pF load capacitance.
8. At any given temperature and voltage condition, tHZCE1 is less than tLZCE1, tHZCE2 is less than tLZCE2, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for
any given device.
9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
10. The internal Write time of the memory is defined by the overlap of CE1 LOW or CE2 HIGH and WE LOW. Both signals must be LOW to initiate a Write and either
signal can terminate a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write.
11. The minimum write pulse width for Write cycle #3 (WE-controlled, OE LOW) is the sum of tHZWE and tSD.
Document#: 38-15003 Rev. *D
Page 5 of 12
PRELIMINARY
CY9C6264
Switching Waveforms
Read Cycle No. 1[12, 13]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2[13, 14]
tRC
CE1
CE2
tACE
OE
DATA OUT
tHZOE
tHZCE
tDOE
tLZOE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
ICC
50%
50%
ISB
Write Cycle No. 1 (WE Controlled)[10, 15, 16]
tWC
ADDRESS
tSCE1
CE1
CE2
tSCE2
tAW
tSA
WE
tHA
tPWE
OE
tSD
DATA I/O
NOTE 17
tHD
DATA IN VALID
t HZOE
Notes:
12. Device is continuously selected. OE = VIL CE1 = VIL or OE = VIL CE2 = VIH.
13. WE is HIGH for Read cycle.
14. Address valid prior to or coincident with CE1 transition LOW or CE2 transition to HIGH.
15. Data I/O is high impedance if OE = VIH.
16. If CE1 goes HIGH Or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Document#: 38-15003 Rev. *D
Page 6 of 12
PRELIMINARY
CY9C6264
Switching Waveforms (continued)
Write Cycle No. 2 (CE1 Or CE2 Controlled)[10, 15, 16]
tWC
ADDRESS
tSCE1
CE1
CE2
tSCE2
tSA
tAW
tHA
WE
tSD
DATA I/O
tHD
DATA IN VALID
Write Cycle No. 3 (WE Controlled, OE LOW)[10, 15, 16, 18]
tWC
ADDRESS
t SCE1
CE1
tSCE2
CE2
tAW
tHA
tSA
WE
tSD
DATA I/O
tHD
DATA IN VALID
NOTE 17
tLZWE
tHZWE
Truth Table
CE1
CE2
WE
OE
H
L
X
X
4.5–5.5V High-Z
VCC
Inputs/Outputs
Deselect/Power-down
Standby (ISB)
H
H
X
X
4.5–5.5V High-Z
Deselect/Power-down
Standby (ISB)
L
L
X
X
4.5–5.5V High-Z
Deselect/Power-down
Standby (ISB)
L
H
H
L
4.5–5.5V Data Out
Read
Active (ICC)
L
H
L
X
4.5–5.5V Data In
Write
Active (ICC)
L
H
H
H
4.5–5.5V High-Z
Deselect, Output Disabled
Active (ICC)
X
X
X
X
< 4.0V
Write Inhibit
Active (ICC)
Inputs = X, Outputs = High-Z
Mode
Power
Note:
18. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE HIGH, the outputs remain in high-impedance state.
Document#: 38-15003 Rev. *D
Page 7 of 12
PRELIMINARY
CY9C6264
Power-down/Power-up Mode AC Waveforms
Parameter
Description
Min.
Typ.
Max.
4.35
4.5
Unit
VPFD
Power-fail Deselect Voltage
4.2
tF[19]
VPFD (max.) to VPFD (min.) VCC Fall Time
100
tFB
VPFD (min.) to VSS VCC Fall Time
50
µs
tR
VSS to VPFD (max.) Rise Time
20
µs
V
µs
tWP
Write Protect Time On VCC = VPFD
20
µs
tREC
VPFD (max.) to Inputs Recognized
500
µs
tF
VCC
VPFD (max.)
VPFD (min.)
VPFD (typ)
tWP
tR
tFB
tREC
INPUTS
DON’T CARE
RECOGNIZED
OUTPUTS
HIGH-Z
VALID
RECOGNIZED
VALID
Ordering Information
Speed (ns)
70
Ordering Code
CY9C6264−70SC
CY9C6264-70SI
Package Name
S21
S21
Package Type
Operating Range
28-pin (300-mil) Molded SOIC
Commercial
28-pin (300-mil) Molded SOIC
Industrial
CY9C6264-70SNC
SN28
28-lead (300-mil) Narrow Body SOIC
Commercial
CY9C6264-70SNI
SN28
28-lead (300-mil) Narrow Body SOIC
Industrial
CY9C6264−70ZC
Z28
28-pin Thin Small Outline Package
Commercial
CY9C6264−70ZI
Z28
28-pin Thin Small Outline Package
Industrial
CY9C6264−70PC
P15
28-pin (600-mil) Molded DIP
Commercial
CY9C6264-70PI
P15
28-pin (600-mil) Molded DIP
Industrial
Note:
19. VPFD (max.) to VPFD (min.) fall time of less than tF may result in deselection/write protection not occurring until 20 µs after VCC passes VPFD (min.).
Document#: 38-15003 Rev. *D
Page 8 of 12
PRELIMINARY
CY9C6264
Package Diagrams
28-pin
(600-Mil) Molded DIP P15
51-85017-*A
28 Lead (300 Mil) SOIC - S21
28-Lead (300-Mil) Molded SOIC S21
PIN 1 ID
14
1
MIN.
MAX.
DIMENSIONS IN INCHES[MM]
0.394[10.01]
*
0.419[10.64]
0.291[7.39]
PACKAGE WEIGHT 0.85gms
0.300[7.62]
15
28
REFERENCE JEDEC MO-119
PART #
S28.3 STANDARD PKG.
SZ28.3 LEAD FREE PKG.
0.026[0.66]
0.032[0.81]
SEATING PLANE
0.697[17.70]
0.713[18.11]
0.092[2.33]
0.105[2.67]
0.004[0.10]
0.050[1.27]
TYP.
0.013[0.33]
0.004[0.10]
0.019[0.48]
0.0118[0.30]
*
0.015[0.38]
0.050[1.27]
0.0091[0.23]
0.0125[3.17]
*
51-85026-*C
Document#: 38-15003 Rev. *D
Page 9 of 12
PRELIMINARY
CY9C6264
Package Diagrams (continued)
450-mil Wide (300-mil Body Width) 28 Pin Narrow SOIC (SN28)
PIN 1 ID
DIMENSIONS IN INCHES
OMEDATA
0.291
0.300
MIN.
MAX.
MIN.
MAX.
CSPI
0.390
0.420
0.463
0.477
0.026
0.032
DETAIL "B"
0.015
0.020
0.014
0.020
DETAIL "A"
SEATING PLANE
0.702
0.710
0.390
0.420
B
0.094
0.110
0.004
A
0.050
TYP.
Document#: 38-15003 Rev. *D
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51-85092-*B
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PRELIMINARY
CY9C6264
Package Diagrams (continued)
28-pin Thin Small Outline Package Type 1 (8 × 13.4 mm) Z28
51-85071-*G
All product and company names mentioned in this document are the trademarks of their respective holders.
Document#: 38-15003 Rev. *D
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© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
CY9C6264
Document History Page
Document Title: CY9C6264 8K x 8 Magnetic Nonvolatile CMOS RAM
Document Number: 38-15003
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
116317
06/11/02
NBP
New Data Sheet
*A
116771
07/25/02
NBP
Add state of memory bits at the time of shipment
*B
208424
SEE ECN
NBP
Icc, Isb1, Isb2, Shielding Specification, Condition to emulate Boot PROM
functionality
*C
227582
SEE ECN
NBP
Changed Magnetic Shielding Specification
*D
309663
SEE ECN
NBP
Changed VPFD & tWP Specification, added SNC package & Silicon Signature
ID address bits.
Document#: 38-15003 Rev. *D
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