CY62158E MoBL® 8-Mbit (1M x 8) Static RAM is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption. Placing the device into standby mode reduces power consumption significantly when deselected (CE1 HIGH or CE2 LOW). Features ■ Very high speed: 45 ns ❐ Wide voltage range: 4.5V – 5.5V ■ Ultra low active power ❐ Typical active current:1.8 mA @ f = 1 MHz ❐ Typical active current: 18 mA @ f = fmax ■ To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A19). Ultra low standby power ❐ Typical standby current: 2 μA ❐ Maximum standby current: 8 μA ■ Easy memory expansion with CE1, CE2 and OE features ■ Automatic power down when deselected ■ CMOS for optimum speed and power ■ Offered in Pb-free 44-Pin TSOP II package To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and OE LOW while forcing the WE HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the IO pins. The eight input and output pins (IO0 through IO7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a write operation is in progress (CE1 LOW and CE2 HIGH and WE LOW). See the Truth Table on page 8 for a complete description of read and write modes. Functional Description The CY62158E MoBL® is a high performance CMOS static RAM organized as 1024K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Logic Block Diagram SENSE AMPS ROW DECODER IO1 1024K x 8 ARRAY IO2 IO3 IO4 IO5 IO6 COLUMN DECODER WE POWER DOWN IO7 A15 A16 A17 A13 A14 OE Cypress Semiconductor Corporation Document #: 38-05684 Rev. *D IO0 DATA IN DRIVERS • A18 A19 CE1 CE2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 16, 2008 [+] Feedback CY62158E MoBL® Pin Configuration Figure 1. 44-Pin TSOP II (Top View) [1] A4 A3 A2 A1 A0 CE1 NC NC IO0 IO1 VCC VSS IO2 IO3 NC NC WE A19 A18 A17 A16 A15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 A5 A6 A7 OE CE2 A8 NC NC IO7 IO6 VSS 33 32 31 30 29 28 27 26 25 24 23 VCC IO5 IO4 NC NC A9 A10 A11 A12 A13 A14 Product Portfolio Power Dissipation Product Speed (ns) VCC Range (V) Operating ICC (mA) f = 1 MHz CY62158ELL Min Typ [2] Max 4.5 5.0 5.5 45 Standby ISB2 (μA) f = fmax Typ [2] Max Typ [2] Max Typ [2] Max 1.8 3 18 25 2 8 Notes 1. NC pins are not connected on the die. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. Document #: 38-05684 Rev. *D Page 2 of 10 [+] Feedback CY62158E MoBL® DC Input Voltage [3, 4] .....................–0.5V to VCC(max) + 0.5V Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static Discharge Voltage............................................ >2001V (MIL-STD-883, Method 3015) Storage Temperature .................................. –65°C to +150°C Latch up Current...................................................... >200 mA Ambient Temperature with Power Applied ............................................ –55°C to +125°C Operating Range Supply Voltage to Ground Potential –0.5V to VCC(max) + 0.5V Device DC Voltage Applied to Outputs in High-Z State [3, 4] ........................–0.5V to VCC(max) + 0.5V CY62158ELL Range Ambient Temperature VCC [5] Industrial –40°C to +85°C 4.5V – 5.5V Electrical Characteristics Over the Operating Range -45 Parameter Description Test Conditions Min Typ [2] Max Unit 0.4 V VOH Output HIGH Voltage IOH = –1 mA VOL Output LOW Voltage IOL = 2.1 mA 2.4 V VIH Input HIGH Voltage VCC = 4.5V to 5.5V 2.2 VCC + 0.5V V VIIL Input LOW Voltage VCC = 4.5V to 5.5V –0.5 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 μA IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 μA ICC VCC Operating Supply Current f = fMAX = 1/tRC ISB1 Automatic CE Power down Current — CMOS Inputs ISB2 [6] Automatic CE Power-down Current — CMOS Inputs 18 25 mA 1.8 3 mA CE1 > VCC− 0.2V, CE2 < 0.2V VIN > VCC – 0.2V, VIN < 0.2V) f = fMAX (Address and Data Only), f = 0 (OE, and WE), VCC = VCCmax 2 8 μA CE1 > VCC – 0.2V or CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = VCCmax 2 8 μA VCC = VCCmax IOUT = 0 mA CMOS levels f = 1 MHz Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max Unit 10 pF 10 pF Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board TSOP II Unit 75.13 °C/W 8.95 °C/W Notes 3. VIL(min) = –2.0V for pulse durations less than 20 ns. 4. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 5. Full Device AC operation assumes a 100 μs ramp time from 0 to VCC (min) and 200 μs wait time after VCC stabilization. 6. Only chip enables (CE1 and CE2), must be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. Document #: 38-05684 Rev. *D Page 3 of 10 [+] Feedback CY62158E MoBL® Figure 2. AC Test Loads and Waveforms R1 VCC OUTPUT 3V 100 pF GND R2 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Rise Time = 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V Parameters 5.0V Unit R1 1838 Ω R2 994 Ω RTH 645 Ω VTH 1.75 V Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR Description Conditions VCC for Data Retention [6] Min Typ [2] Max 2 Data Retention Current tCDR [7] Chip Deselect to Data Retention Time tR [8] Operation Recovery Time V 8 VCC = VDR CE1 > VCC − 0.2V, CE2 < 0.2V, VIN > VCC − 0.2V or VIN < 0.2V Unit μA 0 ns tRC ns Figure 3. Data Retention Waveform VCC VCC(min) tCDR DATA RETENTION MODE VDR > 2.0 V VCC(min) tR CE1 or CE2 Notes 7. Tested initially and after any design or process changes that may affect these parameters. 8. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs. Document #: 38-05684 Rev. *D Page 4 of 10 [+] Feedback CY62158E MoBL® Switching Characteristics Over the Operating Range [9] Parameter Description 45 ns Min Max Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW and CE2 HIGH to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z [10] OE HIGH to High Z tHZOE 45 10 [10, 11] CE1 HIGH or CE2 LOW to High Z tPU CE1 LOW and CE2 HIGH to Power Up Write Cycle ns 22 ns ns 10 [10, 11] tHZCE tPD 45 18 [10] ns ns 18 0 CE1 HIGH or CE2 LOW to Power Down ns ns 5 CE1 LOW and CE2 HIGH to Low Z tLZCE ns 45 ns ns 45 ns [12] tWC Write Cycle Time 45 ns tSCE CE1 LOW and CE2 HIGH to Write End 35 ns tAW Address Setup to Write End 35 ns tHA Address Hold from Write End 0 ns tSA Address Setup to Write Start 0 ns tPWE WE Pulse Width 35 ns tSD Data Setup to Write End 25 ns tHD Data Hold from Write End 0 ns [10, 11] tHZWE WE LOW to High Z tLZWE WE HIGH to Low Z [10] 18 10 ns ns Notes 9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 4. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 11. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 12. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05684 Rev. *D Page 5 of 10 [+] Feedback CY62158E MoBL® Switching Waveforms Figure 4 shows address transition controlled read cycle waveforms.[13, 14] Figure 4. Read Cycle No. 1 tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5 shows OE controlled read cycle waveforms.[14, 15] Figure 5. Read Cycle No. 2 ADDRESS tRC CE1 CE2 tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC HIGH IMPEDANCE DATA VALID tPD tPU SUPPLY CURRENT tHZCE 50% ICC 50% ISB Notes 13. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 14. WE is HIGH for read cycle. 15. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH. Document #: 38-05684 Rev. *D Page 6 of 10 [+] Feedback CY62158E MoBL® Switching Waveforms (continued) Figure 6 shows WE controlled write cycle waveforms.[12, 16, 17] Figure 6. Write Cycle No. 1 tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA tPWE WE OE tSD DATA IO tHD VALID DATA NOTE 18 tHZOE Figure 7 shows CE1 or CE2 controlled write cycle waveforms.[12, 16, 17] Figure 7. Write Cycle No. 2 tWC ADDRESS tSCE CE1 tSA CE2 tAW tHA tPWE WE OE tSD DATA IO tHD VALID DATA Notes 16. Data IO is high impedance if OE = VIH. 17. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 18. During this period, the IOs are in output state. Do not apply input signals. Document #: 38-05684 Rev. *D Page 7 of 10 [+] Feedback CY62158E MoBL® Switching Waveforms (continued) Figure 8 shows WE controlled, OE LOW write cycle waveforms.[17] Figure 8. Write Cycle No. 3 tWC ADDRESS tSCE CE1 CE2 tAW tSA tHA tPWE WE tSD DATA IO NOTE 18 tHD VALID DATA tLZWE tHZWE Truth Table CE1 CE2 WE OE Inputs/Outputs Mode Power H X X X High Z Deselect/Power Down Standby (ISB) X L X X High Z Deselect/Power Down Standby (ISB) L H H L Data Out Read Active (ICC) L H H H High Z Output Disabled Active (ICC) L H L X Data in Write Active (ICC) Ordering Information Speed (ns) 45 Ordering Code CY62158ELL-45ZSXI Document #: 38-05684 Rev. *D Package Diagram Package Type 51-85087 44-Pin TSOP II (Pb-free) Operating Range Industrial Page 8 of 10 [+] Feedback CY62158E MoBL® Package Diagrams Figure 9. 44-Pin TSOP II, 51-85087 51-85087-*A Document #: 38-05684 Rev. *D Page 9 of 10 [+] Feedback CY62158E MoBL® Document History Page Document Title: CY62158E MoBL® 8-Mbit (1M x 8) Static RAM Document Number: 38-05684 REV. ECN NO. Issue Date Orig. of Change ** 270350 See ECN PCI New Data Sheet *A 291271 See ECN SYT Converted from Advance Information to Preliminary Changed input pulse level from VCC to 3V in the AC Test Loads and Waveforms Modified footnote #9 to include timing reference level of 1.5V and input pulse level of 3V *B 1462592 See ECN VKN/AESA Converted from preliminary to final Removed 35 ns speed bin Removed “L” parts Removed 48-Ball VFBGA package Changed ICC(max) spec from 2.3 mA to 3 mA at f=1 MHz Changed ICC(typ) spec from 16 mA to 18 mA at f=fMAX Changed ICC(max) spec from 28 mA to 25 mA at f=fMAX Changed ISB1(typ) and ISB2(typ) spec from 0.9 μA to 2 μA Changed ISB1(max) and ISB2(max) spec from 4.5 μA to 8 μA Changed ICCDR(max) spec from 4.5 μA to 8 μA Changed tLZOE spec from 3 ns to 5 ns Changed tLZCE spec from 6 ns to 10 ns Changed tHZCE spec from 22 ns to 18 ns Changed tPWE spec from 30 ns to 35 ns Changed tSD spec from 22 ns to 25 ns Changed tLZWE spec from 6 ns to 10 ns Added footnote# 6 related to ISB2 and ICCDR Updated Ordering information table VKN/PYRS Corrected typo in the Ordering Information table *C 2428708 See ECN *D 2516494 See ECN PYRS Description of Change Corrected ECN number © Cypress Semiconductor Corporation, 2008. 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Document #: 38-05684 Rev. *D Revised June 16, 2008 Page 10 of 10 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback