FemtoClock NG® Clock Synthesizer ICS843N571I DATA SHEET General Description Features • • • The ICS843N571I is a PLL based clock synthesizer for use in Ethernet applications. The device uses IDT’s fourth generation FemtoCLock® NG technology for optimal high clock frequency and low phase noise performance, combined with a low power consumption and high power supply noise rejection. Using IDT’s latest FemtoClock NG PLL technology, the ICS843N571I achieves <0.3ps RMS phase jitter performance. ICS843N571I can synthesize 100MHz, 125MHz, 156.25MHz and a low frequency 33.33MHz CPU clock from a single device. Six LVCMOS outputs also serve as additional buffering of the 25MHz crystal reference. Fourth generation FemtoClock® Next Generation (NG) technology Seven single-ended LVCMOS outputs, 30Ω output impedance Three LVPECL output pairs One differential LVPECL (QA, nQA) output pair: 156.25MHz Two selectable differential LVPECL output pairs (QB, nQB and QC, nQC): 100MHz and 125MHz • • • One single-ended LVCMOS (QD0) 33.33MHz CPU clock • FemtoClock NG frequency multiplier provides low jitter, high frequency output • • FemtoClock NG VCO frequency: 2.5GHz • • • • Power supply noise rejection PSNR: -80dB Selectable external crystal or single-ended input source Crystal oscillator interface designed for 25MHz, parallel resonant crystal RMS phase jitter @ 125MHz, using a 25MHz crystal (12kHz – 20MHz): 0.283ps (typical) 3.3V supply voltage -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) packages QREF4 QREF5 VCC VEE VCC FORCE_LOW nc nc VCC VCC Pin Assignment 40 39 38 37 36 35 34 33 32 31 VCC 2 29 QREF3 QREF2 QREF0 QREF1 3 ICS843N571I 28 VCC 4 27 FREQSEL VCC 5 40-Lead VFQFN 6mm x 6mm x 0.925mm package body K Package Top View 26 VCC 25 VCC 24 VCC QD0 QC VEE 1 XTAL_IN 30 REFCLK 6 7 8 REFSEL 9 23 22 10 21 XTAL_OUT VEE nQC ICS843N571AKI REVISION A SEPTEMBER 29, 2011 1 nQB QB nQA QA VCC VCC nc nc nc VCC 11 12 13 14 15 16 17 18 19 20 ©2011 Integrated Device Technology, Inc. ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER Block Diagram REFSEL Pullup QREF 0 XTAL_IN QREF 1 OSC 25MHz XTAL_OUT REFCLK Pulldown 1 QREF 2 0 QREF 3 25MHz QREF 4 QREF 5 PF + CP FemtoClock NG VCO ÷100 QA nQA ÷16 ÷25 0 1 FREQSEL Pullup/Pulldown QB nQB 3 -State Decoder 0 ÷20 1 ÷75 FORCE_LOW ICS843N571AKI REVISION A SEPTEMBER 29, 2011 2 QC nQC QD0 Pulldown ©2011 Integrated Device Technology, Inc. ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER Table 1. Pin Descriptions Number Name 1, 10, 34 VEE Type Description Power Negative supply pins. 2, 5, 11, 15, 16, 24, 25, 26, 28, 33, 35, 39, 40 VCC Power Power supply pins. Pins 2, 28, 33 – power supply connection for the 25MHz LVCMOS outputs Pin 5 – power supply connection for the crystal oscillator Pins 11, 15, 26, 35 – power supply connection for the dividers and other core circuitry Pin 16 (vposO) – power supply connection for the differential LVPECL outputs Pin 24, 25 – power supply connection for the 33MHz LVCMOS output Pin 39 – power supply connection for the digital logic Pin 40 – power supply connection for the PLL 3, 4, 29, 30, 31, 32 QREF0, QREF1, QREF2, QREF3, QREF4, QREF5 Output Single-ended outputs. 3.3V LVCMOS/LVTTL reference levels. 6, 7 XTAL_IN, XTAL_OUT Input 8 REFCLK Input Pulldown 9 REFSEL Input Pullup 12, 13, 14, 36, 38 nc 17, 18 QA, nQA Output Differential output pair. LVPECL interface levels. 19, 20 QB, nQB Output Differential output pair. LVPECL interface levels. 21, 22 QC, nQC Output Differential output pair. LVPECL interface levels. 23 QD0 Output Single-ended output. 3.3V LVCMOS/LVTTL reference levels. 27 FREQSEL Input Pullup/ Pulldown Frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels. 37 FORCE_LOW Input Pulldown Forces the QD0 output into a low state. See Table 3C. LVCMOS/LVTTL interface levels. Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. Single-ended LVCMOS/LVTTL reference clock input. Reference select pin. When HIGH, selects crystal. When LOW, selects REFCLK. See Table 3A. LVCMOS/LVTTL interface levels. No connect. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance (per output) RPULLUP Test Conditions Minimum Typical Maximum Units 2 pF 6 pF Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ROUT Output Impedance 30 Ω ICS843N571AKI REVISION A SEPTEMBER 29, 2011 QD0, QREF[0:5] VCC = 3.6V QD0, QREF[0:5] 3 ©2011 Integrated Device Technology, Inc. ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER Function Tables Table 3A. REFSEL Function Table Inputs Input Source REFSEL 0 REFCLK 1 (default) XTAL_IN, XTAL_OUT Table 3B. FREQSEL Function Table Inputs Output Frequency (MHz) FREQSEL QB, nQB QC, nQC 0 125 125 1 100 100 Float (default) 125 100 Table 3C. FORCE_LOW Function Table Inputs Output Frequency (MHz) FORCE_LOW QD0 0 (default) 33.33 1 Disabled ICS843N571AKI REVISION A SEPTEMBER 29, 2011 4 ©2011 Integrated Device Technology, Inc. ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 3.63V Inputs, VI XTAL_IN Other Inputs 0V to VCC -0.5V to VCC + 0.5V Outputs, IO (LVCMOS) -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 37.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 0.3V, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions VCC Power Supply Voltage IEE Power Supply Current Minimum Typical Maximum Units 3.0 3.3 3.6 V 250 mA No Load Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage VIM Input Medium Voltage IIH Input High Current Test Conditions REFSEL, FORCE_LOW Minimum 2 Typical Maximum Units VCC + 0.3 V 0.8 V 0.4 V VCC/2 + 0.1 V VCC - 0.4 FREQSEL REFSEL, FORCE_LOW -0.3 FREQSEL FREQSEL VCC/2 - 0.1 REFCLK, FREQSEL, FORCE_LOW VCC = VIN = 3.6V 150 µA REFSEL VCC = VIN = 3.6V 5 µA REFCLK, FORCE_LOW VCC = 3.6V, VIN = 0V -5 µA REFSEL, FREQSEL VCC = 3.6V, VIN = 0V -150 µA Output High Voltage; NOTE 1 VCC = 3.3V ± 0.3V 2.3 V Output Low Voltage; NOTE 1 VCC = 3.3V ± 0.3V IIL Input Low Current VOH VOL 0.8 V NOTE 1: Outputs terminated with 50Ω to VCC/2. See Parameter Measurement Information, Output Load Test Circuit diagrams. ICS843N571AKI REVISION A SEPTEMBER 29, 2011 5 ©2011 Integrated Device Technology, Inc. ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER Table 4C. LVPECL DC Characteristics, VCC = 3.3V ± 0.3V, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Minimum Typical Maximum Units VCC – 1.4 VCC – 0.8 V VCC – 2.0 VCC – 1.6 V 0.6 1.0 V NOTE 1: Outputs teerminated with 50Ω to VCC – 2V. Table 5. Crystal Characteristics Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF AC Electrical Characteristics Table 6A. LVPECL AC Characteristics, VCC = 3.3V ± 0.3V, VEE = 0V, TA = -40°C to 85°C Symbol Parameter fIN Input Frequency fOUT Output Frequency tjit(θ) Test Conditions Minimum Typical Maximum 25 25 RMS Phase Jitter (Random) NOTE 1 tsk(o) Output Skew; NOTE 2, 3 PSNR Power Supply Noise Reduction Units MHz 156.25 MHz 156.25MHz fOUT, 25MHz crystal Integration Range: 12kHz – 20MHz 0.233 ps 125MHz fOUT, 25MHz crystal Integration Range: 12kHz – 20MHz 0.283 ps 100MHz fOUT, 25MHz crystal Integration Range: 12kHz – 20MHz 0.299 ps Measured on the Rising Edge 40 ps Pin 40 (VCC) From DC to 8MHz, FORCE_LOW = HIGH -75 dB Pin 40 (VCC) From DC to 3MHz, FORCE_LOW = LOW -80 dB tR / tF Output Rise/Fall Time odc Output Duty Cycle 20% to 80% 150 550 ps 48 52 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions NOTE 1: Refer to the Phase Noise Plot. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. ICS843N571AKI REVISION A SEPTEMBER 29, 2011 6 ©2011 Integrated Device Technology, Inc. ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER Table 6B. AC Characteristics for Single Side Band Power Levels (LVPECL Outputs), VCC = 3.3V ± 0.3V, VEE = 0V, TA = -25°C Symbol Parameter Test Conditions ΦN(1k) Single-side band phase noise, 1kHz from Carrier -120 dBc/Hz ΦN(10k) Single-side band phase noise, 10kHz from Carrier -132 dBc/Hz ΦN(100k) Single-side band phase noise, 100kHz from Carrier -135 dBc/Hz ΦN(1M) Single-side band phase noise, 1MHz from Carrier -140 dBc/Hz ΦN(10M) Single-side band phase noise, 10MHz from Carrier -156 dBc/Hz ΦN(20M) Single-side band phase noise, 20MHz from Carrier -157 dBc/Hz ΦN(1k) Single-side band phase noise, 1kHz from Carrier -121 dBc/Hz ΦN(10k) Single-side band phase noise, 10kHz from Carrier -133 dBc/Hz ΦN(100k) Single-side band phase noise, 100kHz from Carrier -137 dBc/Hz ΦN(1M) Single-side band phase noise, 1MHz from Carrier -143 dBc/Hz ΦN(10M) Single-side band phase noise, 10MHz from Carrier -153 dBc/Hz ΦN(20M) Single-side band phase noise, 20MHz from Carrier -153 dBc/Hz ΦN(1k) Single-side band phase noise, 1kHz from Carrier -123 dBc/Hz ΦN(10k) Single-side band phase noise, 10kHz from Carrier -135 dBc/Hz ΦN(100k) Single-side band phase noise, 100kHz from Carrier -139 dBc/Hz ΦN(1M) Single-side band phase noise, 1MHz from Carrier -145 dBc/Hz ΦN(10M) Single-side band phase noise, 10MHz from Carrier -154 dBc/Hz ΦN(20M) Single-side band phase noise, 20MHz from Carrier -154 dBc/Hz 156.25MHz, 33.33MHz Output disabled 125MHz, 33.33MHz Output disabled 100MHz, 33.33MHz Output disabled Minimum Typical Maximum Units NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. ICS843N571AKI REVISION A SEPTEMBER 29, 2011 7 ©2011 Integrated Device Technology, Inc. ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER Table 6C. LVCMOS AC Characteristics, VCC = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol Parameter fIN Input Frequency fOUT Output Frequency tjit(θ) Test Conditions Minimum Typical Maximum Units 33.33 MHz 25 25 RMS Phase Jitter (Random) NOTE 1 tsk(o) Output Skew; NOTE 2, 3 QREF[0:5] PSNR Power Supply Noise Reduction Pin 40, (VCC) tR / tF Output Rise/Fall Time odc Output Duty Cycle MHz 33.33MHz fOUT, 25MHz crystal Integration Range: 12kHz – 5MHz 0.266 ps 25MHz fOUT, 25MHz crystal Integration Range: 12kHz – 5MHz 0.212 ps Measured on the Rising Edge 50 From DC to 6.25MHz 20% to 80% -80 ps dB 200 600 ps 48 52 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions NOTE 1: Refer to the Phase Noise Plot. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VCC/2. Table 6D. AC Characteristics for Single Side Band Power Levels (LVCMOS Outputs), VCC = 3.3V ± 0.3V, VEE = 0V, TA = -25°C Symbol Parameter Test Conditions ΦN(1k) Single-side band phase noise, 1kHz from Carrier -134 dBc/Hz ΦN(10k) Single-side band phase noise, 10kHz from Carrier -144 dBc/Hz ΦN(100k) Single-side band phase noise, 100kHz from Carrier -149 dBc/Hz ΦN(1M) Single-side band phase noise, 1MHz from Carrier -153 dBc/Hz ΦN(5M) Single-side band phase noise, 5MHz from Carrier -159 dBc/Hz ΦN(1k) Single-side band phase noise, 1kHz from Carrier -137 dBc/Hz ΦN(10k) Single-side band phase noise, 10kHz from Carrier -152 dBc/Hz ΦN(100k) Single-side band phase noise, 100kHz from Carrier -158 dBc/Hz ΦN(1M) Single-side band phase noise, 1MHz from Carrier -160 dBc/Hz ΦN(5M) Single-side band phase noise, 5MHz from Carrier -160 dBc/Hz 33.33MHz 25MHz Minimum Typical Maximum Units NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. ICS843N571AKI REVISION A SEPTEMBER 29, 2011 8 ©2011 Integrated Device Technology, Inc. ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER Noise Power dBc Hz Typical Phase Noise at 25MHz (LVCMOS Output) Offset Frequency (Hz) Noise Power dBc Hz Typical Phase Noise at 33.33MHz (LVCMOS Output) Offset Frequency (Hz) ICS843N571AKI REVISION A SEPTEMBER 29, 2011 9 ©2011 Integrated Device Technology, Inc. ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER Noise Power dBc Hz Typical Phase Noise at 100MHz (LVPECL Output) Offset Frequency (Hz) Noise Power dBc Hz Typical Phase Noise at 125MHz (LVPECL Output) Offset Frequency (Hz) ICS843N571AKI REVISION A SEPTEMBER 29, 2011 10 ©2011 Integrated Device Technology, Inc. ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER Noise Power dBc Hz Typical Phase Noise at 156.25MHz (LVPECL Output) Offset Frequency (Hz) ICS843N571AKI REVISION A SEPTEMBER 29, 2011 11 ©2011 Integrated Device Technology, Inc. ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER Parameter Measurement Information 2V 1.65V ± 0.15V VCC Qx SCOPE SCOPE VCC Qx nQx VEE VEE -1.65V ± 0.15V -1.3V ± 0.3V LVCMOS Output Load AC Test Circuit LVPECL Output Load AC Test Circuit Phase Noise Plot Noise Power V CC QREFx 2 V CC QREFy f1 Offset Frequency 2 tsk(o) f2 RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers Phase Jitter LVCMOS Output Skew nQx Qx 80% 80% nQy 20% 20% QD0, QREF[0:5] Qy tR tF tsk(o) LVCMOS Output Rise/Fall Time LVPECL Output Skew ICS843N571AKI REVISION A SEPTEMBER 29, 2011 12 ©2011 Integrated Device Technology, Inc. ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER Parameter Measurement Information, continued V CC nQ[A:C] QD0, QREF[0:5] 80% 80% 2 t PW VSW I N G Q[A:C] t PERIOD 20% 20% tF tR odc = t PW x 100% t PERIOD LVCMOS Output Duty Cycle/Pulse Width/Period LVPECL Output Rise/Fall Time nQ[A:C] Q[A:C] t PW t odc = PERIOD t PW x 100% t PERIOD LVPECL Output Duty Cycle/Pulse Width/Period ICS843N571AKI REVISION A SEPTEMBER 29, 2011 13 ©2011 Integrated Device Technology, Inc. ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER Applications Information Overdriving the XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 1A. The XTAL_OUT pin can be left floating. The maximum amplitude of the input signal should not exceed 2V and the input edge rate can be as slow as 10ns. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. 3.3V 3.3V R1 100 Ro ~ 7 Ohm C1 Zo = 50 Ohm XTAL_IN RS 43 R2 100 Driv er_LVCMOS 0.1uF XTAL_OUT Cry stal Input Interf ace Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface VCC=3.3V C1 Zo = 50 Ohm XTAL_IN R1 50 Zo = 50 Ohm 0.1uF XTAL_OUT LVPECL Cry stal Input Interf ace R2 50 R3 50 Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface ICS843N571AKI REVISION A SEPTEMBER 29, 2011 14 ©2011 Integrated Device Technology, Inc. ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 2. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 2. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ICS843N571AKI REVISION A SEPTEMBER 29, 2011 15 ©2011 Integrated Device Technology, Inc. ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω R3 125Ω 3.3V 3.3V Zo = 50Ω 3.3V R4 125Ω 3.3V 3.3V + Zo = 50Ω + _ LVPECL Input Zo = 50Ω R1 50Ω _ LVPECL R2 50Ω R1 84Ω VCC - 2V RTT = 1 * Zo ((VOH + VOL) / (VCC – 2)) – 2 Input Zo = 50Ω R2 84Ω RTT Figure 3A. 3.3V LVPECL Output Termination Figure 3B. 3.3V LVPECL Output Termination Recommendations for Unused Input and Output Pins Inputs: Outputs: REFCLK Input LVCMOS Outputs For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REFCLK to ground. All unused LVCMOS output can be left floating. There should be no trace attached. LVPECL Outputs: Crystal Inputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. ICS843N571AKI REVISION A SEPTEMBER 29, 2011 16 ©2011 Integrated Device Technology, Inc. ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER Application Schematic Example Figure 4 shows an example of ICS843N571I application schematic. In this example, the device is operated at VCC = 3.3V. An 18pF parallel resonant 25MHz crystal is used. The load capacitance C1 = 15pF and C2 = 15pF are recommended for frequency accuracy. Depending on the parasitics of the printed circuit board layout, these values might required slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used. This will require adjusting C1 and C2. For this device, the crystal load capacitors are required for proper operation. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for wide range of noise frequency. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component with high amplitude interference is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally general design practice for power plane voltage stability suggests adding bulk capacitances in the general area of all devices. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uf capacitor in each power pin filter should be placed on the device side. The other components can be on the opposite side of the PCB. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. R1 QRE F0 Z o = 50 VC C F p 8 1 VC C V CC nc 1 2 3 4 5 6 7 8 9 10 QR EF0 QR EF1 C2 XTAL_I N XTAL_OU T 15pF R EFSE L R5 Zo = 50 QR EF5 R ec eiv er QR EF3 QR EF2 30 29 28 27 26 25 24 23 22 21 QR EF 3 QR EF 2 VCC F REQSE L VCC VCC VCC QD 0 nQC QC 3. 3V FR EQSEL R3 133 QD 0 nQC QC QC 41 11 12 13 14 15 16 17 18 19 20 Set Logic Input to '0' R6 82. 5 VCC= 3.3V VC C R7 82.5 LVPECL Termination QB nQB VC C - PAD VC C nc nc nc V CC VCC QA nQA QB nQB Z o = 50 Ohm Logic Control Input Examples RU1 1K + nQC D riv er_LVC MOS Set Logic Input to '1' R4 133 Z o = 50 Ohm 33 VC C Z o = 50 20 VC C VEE VC C QRE F0 QRE F1 VC C XTAL_IN XTAL_OU T R EFC LK R EFSEL VEE R2 VC C FOR CE_LOW X1 Q1 nc VCC VEE VC C QR EF5 QR EF4 U1 VCC 25MHz R ec eiv er 40 39 38 37 36 35 34 33 32 31 VC C V CC C1 15pF 20 QR EF5 QRE F4 FOR CE_LOW RU2 N ot Ins tall To Logic Input pins RD1 N ot Ins tall To Logic Input pins Zo = 50 Ohm QA RD2 1K + Zo = 50 Ohm nQA 3. 3V - muR at a, BLM18BB221SN 1 1 F B1 2 (U1:2) (U1:5) (U1:11) (U1:15) (U1:16) C4 C5 C6 C7 C8 C9 10uF 0. 1uF 0.1uF 0.1uF 0.1uF 0.1uF C3 0. 1uF 3. 3V R8 50 V CC Optional Y-Termination R9 50 R 10 50 muRat a, BLM18BB 221SN1 1 C10 0.1uF (U1:24) 2 FB2 C 11 10uF (U1:25) (U1:26) (U1:28) (U1:33) (U1:35) (U1:39) (U1:40)VC C C 12 C 13 C14 C15 C16 C 17 C 18 C 19 0. 1uF 0.1uF 0. 1uF 0. 1uF 0. 1uF 0. 1uF 0. 1uF 0.1uF Figure 4. ICS843S571I Application Schematic ICS843N571AKI REVISION A SEPTEMBER 29, 2011 17 ©2011 Integrated Device Technology, Inc. ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER Power Considerations This section provides information on power dissipation and junction temperature for the ICS843N571I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843N571I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.6V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Core and LVPECL Output Power Dissipation • Power (core)MAX = VCC_MAX * IEE_MAX = 3.6V * 250mA = 900mW • Power (outputs)MAX = 32mW/Loaded Output pair If all outputs are loaded, the total power is 3 * 32mW = 96mW Dynamic Power Dissipation at 33.3333MHz and 25MHz Power (33.33MHz) = CPD * Frequency * (VCC)2 * # of outputs = 6pF * 33.3333MHz * (3.6V)2 * 1= 2.592mW Power (25MHz) = CPD * Frequency * (VCC)2 * # of outputs = 6pF * 25MHz * (3.6V)2 * 6 = 11.664mW Total Power Dissipation • Total Power = Power (Core) + Power (Output) + Dynamic Power (33.3333MHz) + Dynamic Power (25MHz) = 900mW + 2.592mW + 11.66mW = 1010.252mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37.7°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 1.010W * 37.7°C/W = 123.1°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance θJA for 40 Lead VFQFN Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS843N571AKI REVISION A SEPTEMBER 29, 2011 0 1 2.5 37.7°C/W 31.6°C/W 28.8°C/W 18 ©2011 Integrated Device Technology, Inc. ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pairs. LVPECL output driver circuit and termination are shown in Figure 5. VCC Q1 VOUT RL 50Ω VCC - 2V Figure 5. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCC – 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX –0.8V (VCC_MAX – VOH_MAX) = 0.8V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.6V (VCC_MAX – VOL_MAX) = 1.6V • Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = [(2V – 0.8V)/50Ω] * 0.8V = 19.2mW Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) = [(2V – 1.6V)/50Ω] * 1.6V = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW ICS843N571AKI REVISION A SEPTEMBER 29, 2011 19 ©2011 Integrated Device Technology, Inc. ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER Reliability Information Table 8. θJA vs. Air Flow Table for a 40 Lead VFQFN θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 37.7°C/W 31.6°C/W 28.8°C/W Transistor Count The transistor count for ICS843N571I is: 22,466 ICS843N571AKI REVISION A SEPTEMBER 29, 2011 20 ©2011 Integrated Device Technology, Inc. ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER Package Outline and Package Dimensions Package Outline - K Suffix for 40 Lead VFQFN (Ref.) S eating Plan e N &N Even (N -1)x e (R ef.) A1 Ind ex Area A3 N To p View Anvil Anvil Singulation Singula tion or OR Sawn Singulation L N e (Ty p.) 2 If N & N 1 are Even 2 E2 (N -1)x e (Re f.) E2 2 b A (Ref.) D e N &N Odd Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C Bottom View w/Type A ID D2 C Bottom View w/Type C ID 2 1 2 1 CHAMFER 4 Th er mal Ba se D2 2 N N-1 RADIUS 4 N N-1 There are 2 methods of indicating pin 1 corner at the back of the VFQFN package are: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type C: Mouse bite on the paddle (near pin 1) Table 9. Package Dimensions NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 9. JEDEC Variation: VJJD-2/-5 All Dimensions in Millimeters Symbol Minimum Maximum N 40 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.30 10 ND & NE D&E 6.00 Basic D2 & E2 2.75 3.05 e 0.50 Basic L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 ICS843N571AKI REVISION A SEPTEMBER 29, 2011 21 ©2011 Integrated Device Technology, Inc. ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER Ordering Information Table 10. Ordering Information Part/Order Number 843N571AKILF 843N571AKILFT Marking ICS43N571AIL ICS43N571AIL Package “Lead-Free” 40 Lead VFQFN “Lead-Free” 40 Lead VFQFN Shipping Packaging Tray 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS843N571AKI REVISION A SEPTEMBER 29, 2011 22 ©2011 Integrated Device Technology, Inc. ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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